3D memory with hollow epitaxial channels

Abstract

Approaches for fabricating a 3D NAND flash memory structure including a hollow epitaxial channel are disclosed. One approach for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate, etching a channel hole through the plurality of alternating material layers to the substrate, and forming a tunnel layer around the channel hole contacting the plurality of alternating material layers. The method may further include forming a channel liner along the tunnel layer, forming a core gap material in the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole between the tunnel layer and the core gap material.

Description

[Technical Field]

[0001]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 429,867, filed December 2, 2022, entitled "3D Memory Including Hollow Epitaxial Channels," the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present disclosure relates to processing of NAND devices, and more particularly to approaches for fabricating 3D NAND flash memory structures that include hollow epitaxial channels. [Background technology]

[0003]

[0003] The memory design known as NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain stored data. NAND flash memory is used in many products, including solid-state devices and portable electronics. To improve the density and reduce the size of NAND memory, the traditional two-dimensional NAND architecture has transitioned to a three-dimensional NAND stack. Unlike 2D planar NAND technology, in which individual memory cells are stacked on separate horizontal substrates, 3D NAND is stacked vertically using multiple layers of alternating conductive and dielectric materials and intersecting vertical channels.

[0004]

[0004] Polysilicon is commonly used as the channel material for 3D NAND. However, as channel lengths increase, the mobility limitations imposed by polysilicon adversely affect device performance. It is with respect to these and other considerations that the present disclosure is provided. Summary of the Invention

[0005]

[0005] In light of the above, in some approaches, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers arranged in a vertical stack on the silicon substrate, wherein a channel hole extends through the plurality of alternating material layers to the silicon substrate, and the channel hole is perpendicular to the plurality of alternating material layers. The 3D NAND memory structure may further include a channel inside the channel hole, wherein the channel includes a tunnel layer around the interior of the channel hole, which contacts the plurality of alternating material layers, and a hollow epitaxial silicon core inside the tunnel layer, which contacts the silicon substrate.

[0006] In some approaches, a method may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate and etching a channel hole through the plurality of alternating material layers to the substrate. The method may further include forming a tunnel layer around the channel hole in contact with the plurality of alternating material layers and forming a channel liner along the tunnel layer. The method may further include forming a core gap material in the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole between the tunnel layer and the core gap material.

[0007] In some approaches, a method for fabricating a hollow epitaxial silicon core of a three-dimensional (3D) NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate, etching a channel hole through the plurality of alternating material layers to the silicon substrate, and forming a tunnel layer around the channel hole, where the tunnel layer contacts the plurality of alternating material layers. In some embodiments, the method may further include forming a channel liner around the tunnel layer, forming a core gap material in the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the silicon substrate through the channel hole between the tunnel layer and the core gap material.

[0008] The nature and advantages of various embodiments may be further understood by reference to the remaining portions of the specification and the drawings, wherein like reference numerals are used throughout the several views to refer to like components. In some instances, a subscript is associated with the reference numeral to indicate one of multiple similar components. When a reference numeral is made without specifying an existing subscript, reference to all such multiple similar components is intended. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a top view of a processing system according to some embodiments. [Figure 2A-2B]

[0010] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 2C-2D] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 2E-2F]1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 2G-2H] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 2I-2J] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 2K-2L] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 2M-2N] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 2O-2P] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 2Q-2R] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 3A]

[0011] 1 is a portion of a memory array according to some embodiments. [Figure 3B]

[0012] ] In some embodiments, a portion of the channel is part of the memory array when used as a support structure to facilitate a hollow epitaxial channel core. [Figure 4A-4B]

[0013] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 4C-4D]1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 4E-4F] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 4G-4H] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 4I-4J] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 4K-4L] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 4M-4N] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 5A-5B]

[0014] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 5C-5D] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figures 5E-5F] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 5G-5H] 1A-1C illustrate progressive steps for producing an array of 3D NAND flash memory cells with hollow epitaxial channels, according to some embodiments. [Figure 6]

[0015] FIG. 1 is a flow diagram of a method for manufacturing a 3D NAND memory structure, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0016] The drawings are not necessarily to scale. The drawings are merely representational and are not intended to portray specific parameters of the present disclosure. The drawings are intended to illustrate exemplary embodiments of the present disclosure and therefore should not be considered limiting in scope.

[0011]

[0017] Additionally, certain elements in some of the figures may be omitted or not drawn to scale for clarity of illustration. The cross-sectional views may be in the form of "slices" or "near-sighted" cross-sections, and certain background lines that would be visible in a "true" cross-section have been omitted for clarity of illustration. Additionally, some reference numbers may be omitted in certain figures for clarity of illustration.

[0012]

[0018] The methods, systems, and devices according to the present disclosure will now be described more fully with reference to the accompanying drawings, in which various embodiments are shown. The methods, systems, and devices may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0013]

[0019] Embodiments described herein are directed to 3D NAND devices including hollow epitaxially grown silicon channels formed according to a bottom punch method that opens access to the substrate. More specifically, embodiments herein provide an approach for punching a stack of alternating layers to provide a reference for hollow or "macaroni"-shaped epitaxial channel growth. In some embodiments, this bottom punch is performed in conjunction with a lateral etching technique to overcome deck-to-deck alignment challenges due to high channel aspect ratios. Advantageously, the macaroni-shaped epitaxial channel growth of the present disclosure can be used to reduce the volume of epitaxial silicon, making threshold voltage less sensitive to variations in trap density. Embodiments herein further prevent stack collapse during lateral etching using support structures, thus providing a low-cost solution for providing an epitaxial reference for crystalline channel growth.

[0014]

[0020] 1 illustrates a top view of one embodiment of a processing system 100 comprising a deposition chamber, an etch chamber, a bake chamber, and a cure chamber, in accordance with some embodiments. As shown, a pair of front-opening integrated pods 102 deliver substrates of various sizes that are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-f positioned in tandem sections 109a-c. A second robotic arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and vice versa. Each substrate processing chamber 108a-f can be equipped to perform several substrate processing operations, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processes, as well as the etching processes described herein.

[0015]

[0021] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to both deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the fabrication system shown in different embodiments. It will be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films are contemplated by the processing system 100. Additionally, any number of other processing systems capable of incorporating chambers for performing any of the specific operations may be utilized with the present technology. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections (e.g., the holding area and transfer area described above) can enable operations to be performed in multiple chambers while maintaining a particular vacuum environment between separate processes.

[0016]

[0022] The processing system 100, and more particularly, the chambers incorporated into the processing system 100 or other processing systems, may be used to fabricate structures according to some embodiments of the present disclosure. For example, the processing system 100 may be used to fabricate memory arrays by performing operations such as deposition, etching, sputtering, polishing, cleaning, etc. in the various substrate processing chambers 108.

[0017]

[0023] FIG. 2A shows a cross-sectional side view of a memory device (hereinafter “device”) 200 at an early stage of processing, according to one or more embodiments described herein. Device 200 may be, for example, a partial stack of alternating oxide-nitride layers formed for a 3D NAND flash array. Each layer shown in FIG. 2A may be formed incrementally, one layer on top of the previous layer, using any deposition or layer formation technique. In this example, the layers may be formed on a substrate 201 of silicon material, such as an epitaxial silicon or single-crystal silicon wafer. A silicon oxide layer 202 may be formed on the substrate 201, followed by a silicon nitride layer 204. In some embodiments, silicon oxide layer 202 and silicon nitride layer 204 may represent initial layers on substrate 201, which may be thicker than the alternating oxide-nitride layers formed thereon. Alternating layers of silicon oxide 206 and silicon nitride 208 may then be formed in the stack.

[0018]

[0024] The progressive formation of substrate 201, silicon oxide layer 206, silicon nitride layer 208, and other materials described below in FIGS. 2A-2R may be collectively referred to as stack 224. As shown in FIG. 2A, stack 224 may initially be limited in height. For example, completed stack 224 may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, forming all of these layers initially may result in stack 224 with an aspect ratio that is too high to reliably form narrow channel holes and other vias throughout stack 224. Therefore, stack 224 may be formed in a series of stages, with alternating silicon oxide layers 206 and silicon nitride layers 208 corresponding to first stage 205.

[0019]

[0025] As further shown in FIG. 2A , the stack 224 can be etched to form a plurality of channel holes 203 through the alternating silicon oxide layers 206 and silicon nitride layers 208. The channel holes 203 can be formed by depositing a mask (not shown) over the partial stack and performing an etching process that removes the material exposed by the mask. Any etching process can be used, and in some embodiments, a dielectric etch can be used. Etching through the alternating silicon oxide layers 206 and silicon nitride layers 208 can benefit from a dielectric etch because the desired aspect ratio of the channel holes 203 for the device channels is relatively high (i.e., the vertical depth of the channel holes 203 is relatively large compared to the horizontal width of the channel holes 203). In general, the depth of the channel holes 203 can be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the time for which the etching process is performed can be determined by the number of silicon oxide layers 206 and the number of silicon nitride layers 208, along with the thickness of these layers. For example, some embodiments may etch the channel holes 203 down to the silicon nitride layer 204. Other embodiments may etch the channel holes 203 down to the silicon oxide layer 202 or down to the top of the substrate 201. The non-limiting example shown in Figure 2A stops the etch at the top of the silicon nitride layer 204.

[0020]

[0026] FIG. 2B illustrates how a bottom punch etch can be used to penetrate the substrate 201 and expose the silicon of the substrate 201, according to some embodiments. The dielectric etch used in FIG. 2B can stop the channel hole etch before it penetrates the substrate 201. Some embodiments can then perform a second etching process such that the channel hole 203 extends below the substrate 201. This additional etch can be a directional etch directed vertically toward the bottom of the channel hole 203 and may be referred to herein as a “bottom punch” etch. The bottom punch etch can allow the silicon material of the substrate 201 to be exposed at the bottom of the channel hole 203. In some embodiments, the bottom punch etch can represent a separate etch from the etch used to form the channel hole 203. For example, the bottom punch etch can be performed in a conductor etch chamber instead of a dielectric etch chamber, which may have better critical dimension uniformity and profile tuning than the dielectric etch used to initially form the channel hole 203 for the device channel. Thus, the bottom punch can extend the channel hole 203 into the substrate 201 to expose the silicon material. For example, the bottom punch etch can extend to the top surface of the substrate 201 or penetrate the substrate 201 below the top surface of the substrate 201. Alternatively, other embodiments can etch the entire length of the channel hole 203 all the way into the substrate 201 using a single etching process, thus combining the results of FIGS. 2A-2B into a single processing step. The exposed silicon material of the substrate 201 can be used in a later step to epitaxially grow silicon through the channel that forms the 3D NAND flash memory cell.

[0021]

[0027] 2C illustrates how the stack 224 can be expanded by adding a second level 213 above the first level 205, which can include additional silicon oxide and silicon nitride layers 207 and 209. These additional layers can be gradually formed above the first level 205. After adding the additional silicon oxide and silicon nitride layers 207 and 209 of the second level 213, multiple holes 211, 219 can be etched in the second level 213, as shown. Note that these holes 211, 219 can be formed using a mask similar to that previously used to etch the channel hole 203 in the first level 205. By gradually etching these layer sets, a very high aspect ratio can be achieved despite the depth of the holes 211, 219 in the full stack 224.

[0022]

[0028] In reality, stack 224 may include many layers, many channel holes, and may be used to form hundreds of 3D NAND flash memory cells. However, these illustrations are simplified to show the formation of a single epi-silicon channel and adjacent support structures or slits in the memory array. For example, an actual stack may include thousands of channels, over 100 alternating oxide and nitride layers, and multiple slits and support structures. These layers may be formed in multiple processes, with incremental etching operations performed on each batch of layers added to the partial stack. Thus, while FIG. 2B shows only two partial stacks being combined, it should be understood that many additional partial stacks may be deposited and etched to form channel hole 203 through stack 224. For example, some embodiments may include a combination of two partial stacks, each having approximately 128 alternating oxide-nitride layers, for a total of 256 alternating oxide-nitride layers.

[0023]

[0029] FIG. 2D illustrates a support feature 210 that may be formed in one of the holes, such as hole 211, to provide support to stack 224 during subsequent steps of the process, according to some embodiments. Support feature 210 may be selectively deposited in one of the holes to form a rigid structure through first level 205 and second level 213. For example, some embodiments may form support feature 210 using a metal such as tungsten. Some embodiments may use a dielectric fill for support feature 210, such as SiO or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack. Any deposition process may be used to form support feature 210. Note that support feature 210 may extend all the way down to substrate 201 by the etching process described above past the final silicon oxide layer 202. As will become clear later in this disclosure, support feature 210 prevents the layers of stack 224 from collapsing when silicon nitride layer 204 is removed. Additionally, extending support features 210 all the way down to substrate 201 prevents the upper layers of stack 224 from shifting when silicon nitride layer 204 is later removed.

[0024]

[0030] FIG. 2E shows an initial layer of epitaxial silicon 212 formed in one of the holes 219, according to some embodiments. As described above, as the depth of the bottom punch etch into the substrate 201 increases, the silicon material of the substrate 201 becomes exposed in the channel hole 219. Because the single-crystal silicon of the substrate 201 is exposed, the epitaxial silicon layer 212 can be grown in the channel hole using a process such as silicon epitaxial deposition or epitaxy, which grows a thin layer of single-crystal silicon on the single-crystal silicon substrate 201. For example, some embodiments can perform the epitaxy process by chemical vapor deposition. Materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other chemical sources of silicon can be provided to a deposition chamber to gradually form the epitaxial silicon 212 growing on the substrate 201. The height of the epitaxial silicon 212 can be above the silicon oxide layer 202 but below the next silicon oxide layer 206 in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204 .

[0025]

[0031] 2F illustrates the deposition of tunnel layer 214 of holes 219, according to some embodiments. Holes 219 may now be used to form channels of vertical columns of a 3D NAND memory cell, and therefore may also be referred to herein as channel holes 219. Tunnel layer 214 may be formed by depositing a blocking dielectric or oxide, a charge trapping nitride (e.g., silicon nitride), and a tunnel dielectric or oxide. These three layers may be collectively referred to as "tunnel layer" 214 in this disclosure. The oxide layer of tunnel layer 214 may provide a conduction and valence band offset for the transistor device of the memory cell.

[0026]

[0032] In some embodiments, the silicon nitride layer may be encapsulated within inner and outer layers of silicon oxide. The various layers of the tunnel layer 214 may be formed using atomic layer deposition, and therefore the layers of the tunnel layer 214 may be relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process allows the tunnel layer 214 to grow on the sidewalls of the channel hole 219, on top of the epitaxial silicon 212, and along the bottom of the channel hole. Because the epitaxial silicon 212 stops before the alternating silicon oxide layer 206 and silicon nitride layer 208, the inside of the channel of the 3D NAND memory cell may be covered with the tunnel layer 214.

[0027]

[0033] 2G shows the deposition of a channel liner 217 formed on the tunnel layer 214 in the channel hole 219. The channel liner 217 may be aluminum oxide (AlO) formed using atomic layer deposition and may therefore be relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process allows the channel liner 217 to be grown on the tunnel layer 214.

[0028]

[0034] 2H illustrates how the channel holes 219 may be filled with a core gap fill material 216, according to some embodiments. To protect the tunnel layer 214 and the channel liner 217 during subsequent etching processes, the channel holes 219 may be filled with the core gap fill material 216, which may be SiO. As shown, the core gap fill material 216 may be formed directly on the channel liner 217.

[0029]

[0035] 2I shows a slit 218 that may be etched in stack 224, according to some embodiments. Slit 218 may represent a relatively long trench etched in stack 224 such that it is adjacent to channel holes 219, 211 along the length of slit 218. In contrast to the etching processes used to form channel holes 211 and 219, slit 218 may be etched using a single process that penetrates all layers of stack 224. More specifically, slit 218 may extend into silicon nitride layer 204. Because slit 218 may be wider than the channel holes, a single process may be used. Thus, the aspect ratio may be smaller and achievable in a single process.

[0030]

[0036] 2J shows a slit liner 220 deposited inside the slit 218 to protect the internal silicon oxide layer 206 and silicon nitride layer 208 of the first level 205 and to protect the additional silicon oxide layer 207 and silicon nitride layer 209 of the second level 213 from a subsequent chemical etching process using the slit 218. For example, the slit liner 220 can be deposited on the sidewalls and bottom of the slit 218, and a subsequent etch can be used to remove the slit liner 220 from the bottom of the slit 218, exposing the silicon nitride layer 204. The slit 218 can be used in memory arrays of two different memory blocks. In later processes, the slit 218 also provides access to all of the nitride layers in the stack 224 so that these nitride layers can be removed and replaced with tungsten (or any other conductive material) to form conductive paths for each memory cell. These conductive paths can later form the word lines or gate electrodes of the memory cells. For example, the slit 218 can provide access for a precursor to remove a nitride layer from the stack 224 using a wet etch with hot phosphoric acid and then grow tungsten into the voids left from the removed nitride layer using an atomic layer deposition process. In some embodiments, the slit liner 220 can be amorphous silicon (a-Si).

[0031]

[0037] FIG. 2K illustrates selective removal of the silicon nitride layer 204 (FIG. 2J) of the stack 224, according to some embodiments. The silicon nitride layer 204 is removed to expose portions of the tunnel layer 214 and channel liner 217 that need to be removed to grow the epitaxial silicon 212 in the channel hole, so that the epitaxial silicon 212 can once again be exposed in the channel hole. In this example, a wet etch such as a hot phosphoric acid chemical etch may be used. The wet etch may access the silicon nitride layer 204 through the slits 218 and selectively remove the silicon nitride layer 204. The slit liner 220 may protect the inner nitride layer from the etching process. Other embodiments may use a dry etch or other process configured to selectively remove the silicon nitride layer 204.

[0032]

[0038] 2L shows a masking layer 232 formed over stack 224, including over core gap fill material 216 in channel holes 219 and over support features 210 in channel holes 211. As shown, openings 233 can be provided through masking layer 232, with openings 233 aligned with slits 218.

[0033]

[0039] 2M illustrates selectively removing the tunnel layer 214 and channel liner 217 from the bottom of the channel hole 219 to form a gap 230 between the epitaxial silicon 212 and the bottom silicon oxide layer 206. A lateral wet etching process may be used to selectively remove the tunnel layer 214 and channel liner 217. As shown, the channel liner 217 may be partially recessed into the channel hole 219. After the channel liner 217 is partially removed, the channel hole 219 is covered by the tunnel layer 214 and exposed to the epitaxial silicon 212.

[0034]

[0040] Note that the gap 230 left by the removal of the nitride layer, tunnel layer 214, and channel liner 217 is lined above and below by oxide layers (e.g., oxide layer 202 and bottom silicon oxide layer 206). These oxide layers may be formed to be slightly thicker than the other oxide layers in stack 224. However, because the oxide and nitride layers of tunnel layer 214 and channel liner 217 may be formed as atomic layer deposition layers, these layers are relatively thin so that they can be removed without removing significant portions of other oxide layers that may be exposed to the etching process.

[0035]

[0041] 2N illustrates the growth of epitaxial silicon 212, according to some embodiments. The epitaxy process may be performed as described above. However, because the slits 218 and channel holes 219 are exposed to the epitaxial silicon 212, a layer of epitaxial silicon 236 may be grown to fill the gaps 230 (FIG. 2M) and begin to fill the channel holes 219. More specifically, the epitaxial silicon layer 236 may extend along the tunnel layer 214 to form an epitaxial core layer 242 in the lower part of the channel holes 219. The growth of the layer of epitaxial silicon 236 may stop upon reaching the channel liner 217 to prevent the slits 218 from also being filled with the layer of epitaxial silicon 236.

[0036]

[0042] 2O illustrates the selective removal of portion 243 of layer of epitaxial silicon 236 at the bottom of slit 218. Portion 243 of layer of epitaxial silicon 236 may be removed using an etching process that performs a bottom "punch," as described above. This etch may remove portion 243 of epitaxial silicon layer 236 until bottom oxide layer 202 is exposed. Alternatively, the etch may penetrate through bottom oxide layer 202 into substrate 201.

[0037]

[0043] 2P shows the deposition of a sacrificial gap-fill material 240 in the slit 218, according to some embodiments. The sacrificial gap-fill material 240 may be deposited in the slit 218, including in the portion 243 of the epitaxial silicon layer 236, which allows the epitaxial silicon 236 to grow in the channel hole 219 without filling the slit 218. In some embodiments, the sacrificial gap-fill material 240 is formed directly on the bottom oxide layer 202.

[0038]

[0044] 2Q illustrates the removal of the remainder of the channel liner 217 (FIG. 2P) from the channel hole 219. As shown, the channel liner 217 is removed along with the tunnel layer 214 in the area above the epitaxial core layer 242. In some embodiments, the core gap fill material 216 remains in place and the channel liner 217 is removed from the top of the channel hole 219.

[0039]

[0045] 2R illustrates epitaxial growth of epitaxial silicon 236 through channel hole 219, according to some embodiments. An epitaxy process may be performed as described above to further grow epitaxial core layer 242 through channel hole 219, for example, in the area vacated by channel liner 217. The resulting structure may include stack 224 having channel hole 219 filled with hollow epitaxial silicon core 244 having a "macaroni" structure. Hollow epitaxial silicon core (hereinafter "epicore") 244 may be formed between tunnel layer 214 and core gap-fill material 216. As shown, epicore 244 may be physically connected to substrate 201, epitaxial silicon 212, and tunnel layer 214.

[0040]

[0046] Still referring to FIG. 2R, device 200 (e.g., a 3D NAND memory structure) may include a silicon substrate 201, which may be formed of single crystal silicon. The device may also include multiple alternating material layers 275 arranged in a vertical stack on silicon substrate 201. Alternating material layers 275 may include alternating layers of oxide and nitride materials (e.g., silicon oxide and silicon nitride). At later stages in the fabrication process, alternating material layers 275 may instead include alternating layers of oxide and metal (e.g., tungsten). For example, the nitride material may be selectively removed and replaced with a metal to form gate electrodes of individual memory cells in the memory structure.

[0041]

[0047] The channel hole 219 may extend through the multiple alternating material layers 275 to the silicon substrate 201. This channel hole 219 may be formed using any of the processes described throughout this disclosure. As shown, the channel hole 219 may be approximately perpendicular to the multiple alternating material layers 275. The device 200 may also include a channel 248 inside the channel hole 219. The channel may include a tunnel layer 214 around the interior of the channel hole 219 (and consequently around the exterior of the channel) using the layers described above. The channel 248 may also include a hollow epicore 244 inside the tunnel layer 214 that contacts the silicon substrate 201. In some cases, the epicore 244 may extend into the silicon substrate 201, such that the epicore 244 may initiate epitaxial growth below the top level of the silicon substrate 201. In some embodiments, the channel 248 may further include a core gap fill material 216 within the epicore 244.

[0042]

[0048] Device 200 may also include an epitaxial silicon layer 236 that extends beyond channel hole 219, with epitaxial silicon layer 236 being parallel to multiple alternating material layers 275. While FIG. 2R shows only one channel of many in device 200, the layer of epitaxial silicon 236 may connect the epicore 244 of the illustrated channel 248 to multiple other channels in device 200. For example, the epicores of each channel connected by the layer of epitaxial silicon 236 may be grown simultaneously from the layer of epitaxial silicon 236 during the same epitaxy process.

[0043]

[0049] The process described above can be used to selectively grow epicore 244 using the single crystal silicon of substrate 201. 3D NAND flash memory cells using hollow "macaroni" type epicore 244 advantageously reduce the volume of epitaxial Si and make threshold voltage less sensitive to variations in trap density.

[0044]

[0050] Further processing may later be performed on stack 224 to complete the memory array. These operations are beyond the scope of this disclosure, but may include removing sacrificial gap fill material 240 from the slits, removing the nitride layer of stack 224, depositing a conductive metal (e.g., tungsten) in place of the nitride layer to form gate electrodes, performing a step etch on stack 224, etc.

[0045]

[0051] FIG. 3A shows a portion of a memory array 300, according to some embodiments. This portion of the memory array 300 may represent a single memory block having offset rows of channels 256. Slits 250, 252 may be used to separate this memory block from other memory blocks. This example uses 24 channels arranged in offset columns between the slits 250, 252. This portion of the memory array 300 may use conventional oxide or polysilicon cores for the channels. Therefore, no support structures are required, and each channel hole may be used to implement a memory cell.

[0046]

[0052] In comparison, FIG. 3B illustrates a portion of a memory array 301 where portions of the channel holes are used for support structures to facilitate epitaxial silicon channel cores, according to some embodiments. As described above, processes for growing epitaxial silicon channels for memory cells in the memory array 301 may use processes in which portions of the channel holes are used for support structures 254 to prevent the memory array 301 from collapsing when a sacrificial nitride layer is removed to make room for the epitaxial silicon layer. These support structures 254 may be spaced apart throughout the memory array to provide adequate support for the layer stack in the array during the fabrication process. Note that the spacing shown in FIG. 3B is provided for illustrative purposes only and is not intended to be limiting. In this example, the support structures 254 are spaced approximately every fourth channel hole and every other column. In this configuration, using some of the channel holes that would otherwise be used for memory cells for support structures 254 slightly reduces the bit density per area in the memory array 301.

[0047]

[0053] As described above, some embodiments may use channel holes to provide support structures during the manufacturing process. Advantages of using channel holes for the support structures include the ability to increase or decrease the spacing between the support structures as needed. However, some embodiments may instead form the same epitaxial silicon channel by using slits instead of channel holes to provide the support structures. These embodiments trade off the amount of support provided across the memory block for increased channel density.

[0048]

[0054] 4A-4N illustrate incremental steps in a manufacturing process for a memory structure that uses slits to separate memory blocks for supporting structures when growing epitaxial silicon channels for individual memory cells, according to some embodiments. FIG. 4A illustrates a channel hole 401 in a stack 400 with epitaxial silicon 406 grown from a substrate 404, according to some embodiments. The channel hole 401 and epitaxial silicon 406 can be formed using the process described above with respect to FIGS. 2A-2E. In some embodiments, the epitaxial silicon 406 can be formed after the channel hole 401 is formed in a first set of oxide / nitride layers and before an upper set of oxide / nitride layers is formed and etched to extend the channel hole 401. For example, returning to FIG. 2B, after the channel hole 203 is etched and a bottom punch etch is used to extend the channel hole 203 into the substrate 201, the epitaxial silicon 406 can be grown in the channel hole 203 from the exposed substrate 201 at this stage. After epitaxial silicon 406 is formed in hole 203, upper alternating layers of oxide 207 and nitride 209 can be added and etched to increase the number of device layers and the depth of channel hole 203, ultimately forming the structure shown in Figure 4A. Alternatively, epitaxial silicon 406 can be grown at any stage after channel hole 401 is fully formed or after the silicon of substrate 404 is exposed.

[0049]

[0055] Figure 4B shows the channel hole 401 after it has been covered with a tunnel layer 408. The tunnel layer 408 may be formed as described in detail above with respect to Figure 2H. Figure 4C shows the channel hole 401 after it has been further covered with a channel liner 417. The channel liner 417 may be formed as described in detail above with respect to Figure 2G. Figure 4D shows the channel hole 401 filled with a sacrificial gap-fill material 410, which may be formed as described in detail above with respect to Figure 2H.

[0050]

[0056] FIG. 4E illustrates slits 412, 413 formed on opposite sides of a memory block, according to some embodiments. While only two channel holes are shown, it should be understood that there could be many more channels between the slits 412, 413. For example, the slits 412, 413 could surround a memory block having a block width of 24 channels. These channels could be arranged in a honeycomb pattern of two offset rows of 12 channels each. Multiple pairs of these offset rows of 24 channels could be present within a block. As shown, the slits 413 are etched to a depth below the first oxide layer 427 and into the sacrificial nitride layer 415. However, the slits may undergo an additional or extended etching process to increase their depth in order to provide a support structure for later fabrication of the epitaxial silicon layer and channel cores. For example, the slits 412 could be etched to a depth below the top of the substrate 404 using a bottom punch etch. This allows the slits 412 to act as support structures that are fixed to the substrate 404 instead of floating above it.

[0051]

[0057] 4F shows slits 412 filled with gap-fill material 414, according to some embodiments. In this example, alternating slits can be used as support structures for a memory array. Thus, slits 413 remain at a shallower depth, and slits 412 are etched to a depth below substrate 404 and filled with gap-fill material 414, which can act as support structures during the growth of subsequent epitaxial silicon layers.

[0052]

[0058] 4G illustrates a slit liner 418 that may be deposited inside the slit 413 and a subsequent etch that may be used to remove the slit liner 418 from the bottom of the slit 413 to expose the sacrificial nitride layer 415. The slit liner 418 may be formed as described in detail above with respect to FIG.

[0053]

[0059] 4H illustrates the removal of the sacrificial nitride layer 415, according to some embodiments. As described above with respect to FIG. 2K, the sacrificial nitride layer 415 may be exposed to an etching process through the slits 413 to selectively remove the sacrificial nitride layer 415. Removal of the sacrificial nitride layer 415 exposes a lower portion 419 of the tunnel layer 408 in an area above the epitaxial silicon 406 grown from the substrate 404.

[0054]

[0060] 4I illustrates the formation of a masking layer 432 over the device 400 and the removal of the sacrificial nitride layer 415. In some embodiments, the channel liner 417 may be partially recessed into the channel hole 401. The sacrificial nitride layer 415 and the channel liner 417 may be removed as described in detail above with respect to FIG. 2M. After removing the exposed portion 419 of the tunnel layer 408 (FIG. 4H) and the channel liner 417 at the bottom of the channel hole 401, the gap fill material 414 may provide a support structure for the stack 400 to prevent it from collapsing after exposing the gap 416 between the substrate 404 and the first oxide layer 427.

[0055]

[0061] 4J illustrates the epitaxial growth of an epitaxial silicon layer 420 in the gap 416. As described above, the epitaxial silicon layer 420 can be grown, for example, in the area where the channel liner 417 was removed, until it begins to fill the channel hole 401. More specifically, the epitaxial silicon layer 420 can extend along the tunnel layer 408 to form an epitaxial core layer 442 in the lower portion of the channel hole 401.

[0056]

[0062] Figure 4K shows using a bottom punch etch process to form holes 422 in epitaxial silicon layer 420 to extend slits 413, and Figure 4L shows slits 413 filled with gap-fill material 424. These steps may be performed as described in detail above with respect to Figures 2O and 2P.

[0057]

[0063] FIG. 4M illustrates further removal of the channel liner 417 from the channel hole 401, and FIG. 4N illustrates epitaxial growth of an epitaxial silicon layer 420 through the channel hole 401, according to some embodiments. An epitaxy process may be performed as described above to further grow an epitaxial core layer 442 through the channel hole 401, for example, in the area vacated by the channel liner 417. The resulting structure may include a hollow epitaxial silicon core 444 having a “macaroni” structure. The hollow epitaxial silicon core (hereinafter “epicore”) 444 may be formed between the tunnel layer 408 and the sacrificial gap-fill material 410. As shown, the epicore 444 may be physically connected to the substrate 404 and the tunnel layer 408.

[0058]

[0064] The channels in the resulting stack 400 shown in FIG. 4N may be substantially similar to the channels in the resulting stack 224 of FIG. 2R, comprising alternating material layers 475 and channel holes 401, each capped with a tunnel layer 408 and filled with an epicore 444. As further shown, sacrificial gap-fill material 410 may be present in the epicore 444. However, in a memory structure including this stack 400, it is not necessary to reserve any channels as support structures. Instead, maximum channel density can be achieved by using slits as support structures during the fabrication process. As mentioned above, additional process steps beyond the scope of this disclosure may then be performed on the stack 400 to complete fabrication of the memory structure, such as removing alternating nitride layers, forming a conductive layer (e.g., a tungsten layer) to form a gate electrode, and performing a step etch.

[0059]

[0065] 5A-5H illustrate progressive steps in a manufacturing process for a memory structure that uses slits to separate memory blocks for support structures when growing epitaxial silicon channels for individual memory cells, according to some embodiments. FIG. 5A shows a stack 500 formed using the process described above with respect to FIGS. 4A-4F. As further shown, a first channel hole 501 may be formed through the layers of stack 500 and then filled with support structures 509. A second channel hole 501 may be filled with gap fill material 510, a tunnel layer 508, and a channel liner 517 that separates gap fill material 510 from epitaxial silicon 511 grown from substrate 504. Stack 500 may further include slits 513 and 523. Note that there may also be more channel holes in stack 500 that are not visible in FIG. 5A.

[0060]

[0066] 5B, within slit 513 is slit liner 520, which may be etched to a level above substrate 504 to contact sacrificial nitride layer 518. Slit 523 may be filled with gap-fill material 588 and extend below substrate 504 to act as a support structure.

[0061]

[0067] The remaining steps for growing epitaxial silicon into the channels of stack 500 may be performed as described in detail above. For example, FIG. 5C illustrates the removal of sacrificial nitride layer 518 to expose gap 539, allowing stack 500 to be supported by a support structure. FIG. 5D illustrates the removal of the portions of tunnel layer 508 and channel liner 517 exposed in gap 539. Channel liner 517 may be recessed into second channel hole 501. FIG. 5E illustrates the growth of epitaxial silicon layer 516 in gap 539, and FIG. 5F illustrates the result of forming gap-fill material 520 in slit 513 after bottom-punching through epitaxial silicon layer 516. FIG. 5F also illustrates partial growth of epitaxial core layer 542 in first channel hole 501. FIG. 5G shows the removal of the channel liner 517, and FIG. 5H shows the further growth of the epitaxial core layer 542 to form a hollow epitaxial silicon core 544.

[0062]

[0068] 6 shows a flow diagram 600 of a method for fabricating a 3D NAND memory structure, according to some embodiments. The method may be performed in various processing chambers within a semiconductor processing system, such as that shown in FIG.

[0063]

[0069] In block 601, the method may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate. In some embodiments, the alternating material layers include alternating layers of oxide and nitride materials. In some embodiments, the alternating material layers include alternating layers of oxide and metal, where the metal forms the gate electrodes of individual memory cells.

[0064]

[0070] At block 602, the method may include etching a channel hole that extends through multiple alternating material layers to a substrate.

[0065]

[0071] At block 603, the method may include forming a tunnel layer around the channel hole that contacts the plurality of alternating material layers. In some embodiments, the tunnel layer may include a blocking dielectric or oxide layer, a charge trapping nitride layer, and a dielectric or oxide layer.

[0066]

[0072] At block 604, the method may include forming a channel liner along the tunnel layer. In some embodiments, the channel liner may be AlO deposited via ALD.

[0067]

[0073] At block 605, the method may include forming a core gap material in the channel liner. In some embodiments, the core gap material may be SiO, which fills the channel hole.

[0068]

[0074] At block 606, the method may include removing the channel liner from the channel hole. In some embodiments, removing the channel liner from the channel hole includes recessing a first portion of the channel liner from a lower section of the channel hole.

[0069]

[0075] At block 607, the method may include epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole between the tunnel layer and the core gap material. In some embodiments, after removing a first portion of the channel liner from the lower section of the channel hole, the epitaxial core layer is first grown in the lower section of the channel hole.

[0070]

[0076] It should be understood that the specific steps illustrated in FIG. 6 provide a particular method for fabricating a 3D NAND memory structure according to various embodiments. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, individual steps illustrated in FIG. 6 may include multiple sub-steps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed according to a particular application. Many variations, modifications, and alternatives are also within the scope of the present disclosure.

[0071]

[0077] In various embodiments, a design tool may be provided and may be configured to create a dataset used, for example, to pattern a semiconductor layer of a device described herein. For example, a dataset may be generated to generate a photomask for use during a lithography process to pattern a layer for a structure described herein. Such a design tool may include a collection of one or more modules and may be configured as hardware, software, or a combination thereof. Thus, for example, a tool may be a collection of one or more software modules, hardware modules, software / hardware modules, or any combination or permutation thereof. As another example, a tool may be a computing device or other apparatus that executes software, or may be implemented in hardware.

[0072]

[0078] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," and "longitudinal" are used herein to describe the relative locations and orientations of various components and their constituent parts as seen in the figures. Such terms include the specifically mentioned words, derivatives thereof, and words of similar importance.

[0073]

[0079] Furthermore, it should be noted that the particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While a flowchart may describe steps as a sequential process, many of the steps may be performed in parallel or simultaneously. Additionally, the order of steps may be rearranged. A process ends when the steps are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to a calling function or to a main function.

[0074]

[0080] As used herein, elements or steps described in the singular, preceded by the words "a" or "an," are to be understood to include a plurality of such elements or steps, unless the exclusion of a plurality of elements or steps is expressly stated. Furthermore, references to "one embodiment" of the present disclosure are not intended to be limiting. Additional embodiments may incorporate the described features.

[0075]

[0081] Furthermore, the terms "substantial" or "substantially," as well as "approximate" or "approximately," may be used interchangeably in some embodiments and may be described using any relative measure acceptable to one of ordinary skill in the art. For example, these terms may serve as a comparison to a reference parameter and indicate a tolerance that may provide the intended function. The amount of deviation from such a reference parameter may be, but is not limited to, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0076]

[0082] Furthermore, those skilled in the art will understand that when an element, such as a layer, region, or substrate, is referred to as being formed, deposited, or positioned "on / atop" or "over" another element, the element may be directly adjacent to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on, directly over, or directly atop" another element, there may be no intervening elements present. The present disclosure is not limited in scope by the specific embodiments described herein. Indeed, various other embodiments and modifications of the present disclosure in addition to those described herein will be apparent to those skilled in the art from the foregoing specification and accompanying drawings. Accordingly, such other embodiments and modifications are intended to be included within the scope of the present disclosure. Furthermore, the present disclosure has been described herein in the context of particular implementations in particular environments for particular purposes. Those skilled in the art will recognize that these particular implementations are not the only useful embodiments, and that the present disclosure may be advantageously implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in light of the full scope and spirit of the present disclosure as described herein.

Claims

1. 1. A three-dimensional (3D) NAND memory structure, comprising: A silicon substrate; a plurality of alternating material layers arranged in a vertical stack on the silicon substrate, wherein a channel hole extends through the plurality of alternating material layers to the silicon substrate, the channel hole being perpendicular to the plurality of alternating material layers; A channel inside the channel hole, the channel comprising: a tunnel layer around the interior of the channel hole, contacting the plurality of alternating material layers; and a hollow epitaxial silicon core inside the tunnel layer in contact with the silicon substrate; a channel; 1. A three-dimensional (3D) NAND memory structure comprising:

2. 10. The 3D NAND memory structure of claim 1, wherein the silicon substrate comprises single crystal silicon from which the hollow epitaxial silicon core is grown through the channel hole.

3. 10. The 3D NAND memory structure of claim 1, wherein the plurality of alternating layers of material comprise alternating layers of oxide and nitride materials.

4. 10. The 3D NAND memory structure of claim 1, wherein the plurality of alternating layers of material comprise alternating layers of oxide material and metal, the metal forming gate electrodes of individual memory cells.

5. 10. The 3D NAND memory structure of claim 1, wherein the hollow epitaxial silicon core extends into the silicon substrate.

6. 10. The 3D NAND memory structure of claim 1, further comprising: a layer of epitaxial silicon extending beyond the channel hole, the layer of epitaxial silicon being between the silicon substrate and the plurality of alternating material layers, the layer of epitaxial silicon connecting the hollow epitaxial silicon core to a plurality of other channels.

7. 7. The 3D NAND memory structure of claim 6, further comprising support structures through the plurality of alternating layers of material and the layer of epitaxial silicon, the support structures extending into the silicon substrate.

8. 1. A method for fabricating a three-dimensional (3D) NAND memory structure, comprising: forming a plurality of alternating layers of material arranged in a vertical stack on a substrate; etching a channel hole through the plurality of alternating layers of material to the substrate; forming a tunnel layer around the channel hole, the tunnel layer contacting the plurality of alternating material layers; forming a channel liner along the tunnel layer; forming a core gap material within the channel liner; removing the channel liner from the channel hole; epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole between the tunnel layer and the core gap material; A method comprising:

9. 10. The method of claim 8, further comprising etching a slit in the memory structure, the slit extending through the plurality of alternating material layers and into a sacrificial nitride layer, the sacrificial nitride layer overlying the substrate.

10. 10. The method of claim 9, further comprising selectively etching the sacrificial nitride layer to expose portions of the tunnel layer and the channel liner.

11. The method of claim 10 further comprising removing the portions of the tunnel layer and the channel liner.

12. The method of claim 10 , further comprising epitaxially growing an epitaxial silicon layer over the substrate after the tunnel layer and the portions of the channel liner are removed.

13. Etching a second channel hole through the plurality of alternating material layers, the second channel hole extending into the substrate; filling the second channel holes with a gap-filling material to support the vertical stack; The method of claim 8 further comprising:

14. 9. The method of claim 8, wherein removing the channel liner from the channel hole comprises recessing a first portion of the channel liner from a lower section of the channel hole, and wherein an epitaxial core layer is epitaxially grown in the lower section of the channel hole.

15. 1. A method for fabricating a hollow epitaxial silicon core of a three-dimensional (3D) NAND memory structure, comprising: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate; Etching a channel hole through the plurality of alternating material layers to the silicon substrate; forming a tunnel layer around the channel hole, the tunnel layer contacting the plurality of alternating material layers; forming a channel liner around the tunnel layer; forming a core gap material within the channel liner; removing the channel liner from the channel hole; epitaxially growing the hollow epitaxial silicon core from the silicon substrate through the channel hole between the tunnel layer and the core gap material; A method comprising:

16. 16. The method of claim 15, further comprising etching slits in the memory structure through the plurality of alternating material layers, the slits extending into a sacrificial nitride layer, the sacrificial nitride layer overlying the silicon substrate.

17. 17. The method of claim 16, further comprising selectively etching the sacrificial nitride layer to expose portions of the tunnel layer and the channel liner.

18. 18. The method of claim 17, further comprising removing the portions of the tunnel layer and the channel liner to form a gap between the silicon substrate and the channel liner.

19. 20. The method of claim 18, further comprising epitaxially growing an epitaxial silicon layer from the silicon substrate, the epitaxial silicon layer extending into the gap.

20. 16. The method of claim 15, wherein removing the channel liner from the channel hole comprises recessing a first portion of the channel liner from a lower section of the channel hole, and wherein an epitaxial core layer is epitaxially grown in the lower section of the channel hole.

Images