Methods of forming vanadium nitride-containing layers and structures including vanadium nitride-containing layers

Abstract

The present disclosure relates to methods of forming vanadium nitride-containing layers.SOLUTION: The method comprises providing a substrate in a reaction chamber of a reactor and depositing a vanadium nitride containing layer on a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The present disclosure further relates to structures and devices including vanadium nitride-containing layers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates generally to methods and systems suitable for manufacturing thin films. More specifically, the present disclosure relates to methods and systems for producing vanadium nitride-containing layers by deposition processes, and structures including vanadium nitride-containing layers. [Background technology]

[0002] The scaling of semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in the speed and density of integrated circuits. However, traditional device scaling techniques face significant challenges for future technology nodes.

[0003] For example, one challenge has been finding a suitable conductive material for use as the gate electrode in CMOS devices. Traditionally, n-type doped polysilicon has been used as the gate electrode material in CMOS devices. However, doped polysilicon may not be the ideal gate electrode material for advanced node applications. Although doped polysilicon is conductive, there may still be a surface region that may lack carriers under bias conditions. This region can manifest as additional gate insulator thickness, commonly referred to as gate depletion, and can contribute to the equivalent oxide thickness. While the gate depletion region may be thin, it can become significant as the gate oxide thickness decreases in advanced node applications, by several angstroms (Å). As a further example, polysilicon does not exhibit an ideal effective work function (eWF) for both NMOS and PMOS devices. To overcome the nonideal effective work function of doped polysilicon, threshold voltage adjust implants can be utilized. However, as device geometries decrease in advanced node applications, the threshold voltage adjust implant process becomes increasingly complex and may become infeasible.

[0004] To overcome the problems associated with doped polysilicon gate electrodes, polysilicon gate materials can be replaced with alternative materials, such as metals, such as titanium nitride layers. Titanium nitride layers can provide a more ideal effective work function for CMOS applications. However, in some cases, such as in the PMOS region of a CMOS device, where a higher work function value than that available with titanium nitride layers is desired, improved materials are desirable. Such materials may be suitable for electrode / capacitor applications, such as gate electrodes, threshold voltage adjustment, p-dipole shifters, or dynamic random access memory (DRAM) applications.

[0005] All descriptions, including descriptions of the problems and solutions described in this section, are included in this disclosure solely for the purpose of providing a context for the disclosure, and such descriptions should not be construed as an admission that any or all of the information was known at the time the invention was made or constitutes prior art. Summary of the Invention [Means for solving the problem]

[0006] This Summary may introduce selected concepts in a simplified form that may be described in more detail below. This Summary is not necessarily intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] Various embodiments of the present disclosure relate to methods for forming vanadium nitride-containing layers, structures and devices formed using the methods, and apparatus for carrying out the methods and / or for forming the structures and / or devices. While the manner in which various embodiments of the present disclosure address the shortcomings of previous methods and systems is described in more detail below, generally, various embodiments of the present disclosure provide improved methods for forming vanadium nitride-containing layers that exhibit relatively high work function values. Additionally or alternatively, vanadium nitride-containing layers can be formed using one or more vanadium precursors. Furthermore, exemplary vanadium nitride-containing layers can be formed using a thermal cyclic deposition process. They can also be formed using plasma or plasma-activated species.

[0008] In this disclosure, "gas" can include materials that are gases at ambient temperature and pressure (NTP), vaporized solids, and / or vaporized liquids, and can consist of a single gas or a mixture of gases, depending on the circumstances. Gases other than process gases, i.e., gases introduced without passing through a gas distribution assembly, other gas distribution devices, etc., can be used, for example, to seal the reaction space and can include seal gases, e.g., noble gases.

[0009] The term "precursor" can refer to a compound that participates in a chemical reaction that produces another compound. The term reactant can be used interchangeably with the term precursor. The term "inert gas" can refer to a gas that does not participate in a chemical reaction and / or does not become part of the layer to any significant extent. Exemplary inert gases include He and Ar, and any combination thereof. In some cases, molecular nitrogen and / or hydrogen can be inert gases.

[0010] As used herein, the term "purging" may refer to a procedure in which an inert or substantially inert gas is supplied to a reaction chamber between two pulses of reacting gases. For example, a purge or purging (e.g., using nitrogen gas) may be provided between pulses of two precursors, thus avoiding or at least minimizing gas-phase interactions between the two precursors. Of course, purging can be accomplished either temporally or spatially, or both. For example, in the case of a temporal purge, the purge steps can be used in a time sequence, for example, by supplying a first precursor to the reaction chamber, supplying a purge gas to the reaction chamber, and supplying a second precursor to the reaction chamber, without moving the substrate on which the layer is deposited. For example, in the case of a spatial purge, the purge step can take the form of moving the substrate from a first location where the first precursor is continuously supplied to a second location where the second precursor is continuously supplied through a purge gas curtain.

[0011] As used herein, the term "substrate" can refer to any underlying material or materials that can be used to form a structure, device, circuit, or layer, or any underlying material or materials on which a structure, device, circuit, or layer can be formed. The substrate can include bulk materials such as silicon (e.g., monocrystalline silicon), other Group IV materials such as germanium, or other semiconductor materials such as Group II-VI or Group III-V semiconductor materials, and can include one or more layers overlying or underlying the bulk material. Additionally, the substrate can include various features (such as recesses, protrusions, and the like) formed in or on at least a portion of the layers of the substrate. For example, the substrate can include a bulk semiconductor material and an insulating or dielectric material layer overlying at least a portion of the bulk semiconductor material.

[0012] As used herein, the terms "film" and / or "layer" can refer to any continuous or discontinuous structure and material, such as materials deposited by the methods disclosed herein. For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or partial or complete molecular layers, or partial or complete atomic layers, or even clusters of atoms and / or molecules. A film or layer may include a material or layer with pinholes and may be at least partially continuous. A seed layer may be a discontinuous layer that serves to increase the nucleation rate of another material. However, a seed layer may also be substantially or completely continuous.

[0013] As used herein, a "structure" can be or include a substrate as described herein. The structure can include one or more layers overlying the substrate, such as one or more layers formed according to a method according to the present disclosure.

[0014] The term cyclic deposition process or cyclical deposition process can refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit layers on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclical deposition processes that include ALD and cyclical CVD components. The process may include a purge step between introducing precursors.

[0015] The term "atomic layer deposition" can refer to a vapor deposition process in which deposition cycles, typically multiple consecutive deposition cycles, are performed in a process chamber. As used herein, the term atomic layer deposition is also meant to include processes denoted by related terms, such as chemical vapor deposition (CVD) atomic layer deposition, when performed with alternating pulses of precursor / reactive gases and purge (e.g., inert carrier) gases.

[0016] Generally, in an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface, which may contain previously deposited material or other materials from a previous ALD cycle) to form a monolayer or submonolayer of material that does not readily react with additional precursors (i.e., a self-limiting reaction). In some cases, a reactant (e.g., another precursor or reactant gas) can then be introduced into the process chamber for use in converting the chemisorbed precursor to the desired material on the deposition surface. The reactant can further react with the precursor. A purge step can be utilized between one or more cycles, e.g., between each step of each cycle, to remove excess precursor from the process chamber and / or remove excess reactants and / or reaction by-products from the reaction chamber.

[0017] As used herein, a "vanadium nitride-containing layer" can be a material layer that can be represented by a chemical formula containing vanadium and nitrogen. The vanadium nitride layer can include additional elements such as oxygen (e.g., a vanadium oxynitride layer). In some embodiments, the vanadium nitride-containing layer can include a significant proportion of elements other than vanadium and nitride. In some embodiments, the vanadium nitride-containing layer comprises vanadium nitride (VN). In some embodiments, the vanadium nitride-containing layer can include, for example, 80, 90, 95, or 99 atomic percent (at%) of VN. In some embodiments, the vanadium nitride-containing layer can consist essentially of vanadium nitride. In some embodiments, the vanadium nitride-containing layer can consist of vanadium nitride. A layer comprised of vanadium nitride can contain acceptable amounts of impurities, such as oxygen, carbon, chlorine or other halogens, and / or hydrogen, which can result from one or more precursors used to deposit the vanadium nitride-containing layer.

[0018] In some embodiments, the vanadium content of the vanadium nitride-containing layer is at least 1.0 atomic percent to at most 99.0 atomic percent, or at least 3.0 atomic percent to at most 97.0 atomic percent, or at least 5.0 atomic percent to at most 95.0 atomic percent, or at least 10.0 atomic percent to at most 90.0 atomic percent, or at least 20.0 atomic percent to at most 80.0 atomic percent, or at least 30.0 atomic percent to at most 70.0 atomic percent, or at least 40.0 atomic percent to at most 60.0 atomic percent.

[0019] In some embodiments, the nitrogen content of the vanadium nitride-containing layer is at least 1.0 atomic percent to at most 99.0 atomic percent, or at least 3.0 atomic percent to at most 97.0 atomic percent, or at least 5.0 atomic percent to at most 95.0 atomic percent, or at least 10.0 atomic percent to at most 90.0 atomic percent, or at least 20.0 atomic percent to at most 80.0 atomic percent, or at least 30.0 atomic percent to at most 70.0 atomic percent, or at least 40.0 atomic percent to at most 60.0 atomic percent.

[0020] As used herein, vanadium precursors include gases or materials that can be in gaseous form and can be represented by a chemical formula that includes vanadium, such as one or more of vanadium halides, vanadium alkylamide compounds, and vanadium amidinate compounds. The vanadium precursors can be organic or inorganic molecules.

[0021] The term nitrogen precursor can refer to a gas or material that can be gaseous and can be represented by a chemical formula that includes nitrogen. In some cases, the chemical formula includes nitrogen and hydrogen. In some cases, the nitrogen precursor does not include diatomic nitrogen.

[0022] Deposition is generally per surface area or volume (e.g., per cm²) on the first facing.2 in or / cm 3 A surface is defined as selective if the amount of material deposited on the first surface (at 1000 nm) is greater than the amount of material deposited per surface area or volume on the second surface. The amount of material deposited on the surface can be determined by measuring the thickness of each layer. In some cases, thickness measurements may not be possible due to discontinuous films. In some cases, selectivity can be determined by measuring the atoms deposited per surface area or volume. As noted above, selectivity can be expressed as the ratio of the amount of material formed on the first surface to the amount of material formed on the first and second surfaces combined.

[0023] The selectivity of deposition on a first surface relative to a second surface can be given as a percentage calculated by [(deposition on the first surface) - (deposition on the second surface)] / (deposition on the first surface). Deposition can be measured in any of a variety of ways. For example, deposition can be expressed as a measured thickness of deposited material or a measured amount of deposited material. In the embodiments described herein, selective deposition of a vanadium nitride-containing layer can be performed on a first surface relative to a second surface.

[0024] Preferably, the selectivity is greater than about 70%, greater than about 80%, more preferably greater than 90%, even more preferably greater than 95%, and most preferably about 100%. In some cases, a selectivity of greater than 80% may be acceptable for a particular application. In some cases, a selectivity of greater than 50% may be acceptable for a particular application.

[0025] Furthermore, in this disclosure, any two variables can constitute a workable range for that variable, and any stated range may include or exclude the endpoints. Furthermore, any value of a stated variable (whether or not it is indicated as "about") refers to an exact or approximate value, including equivalents, and may refer to an average, median, representative value, or majority, etc. Furthermore, in this disclosure, the terms "comprise," "comprised of," and "having" independently refer, in some embodiments, to "typically or broadly include," "comprise," "consist essentially of," or "consist." In this disclosure, any defined meaning does not necessarily exclude, in some embodiments, the ordinary and customary meaning.

[0026] The accompanying drawings, which are included to provide a further understanding of the disclosure and constitute a part of this specification, illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0027] [Figure 1] 1 illustrates a method according to the present disclosure. [Figure 2] 1 illustrates one embodiment of a method according to the present disclosure. [Figure 3] 1 shows a structure including a vanadium nitride-containing layer according to the present disclosure. [Figure 4] 1 illustrates another exemplary structure according to the present disclosure. [Figure 5] 1 illustrates yet another exemplary structure according to the present disclosure. [Figure 6] 1 illustrates a schematic representation of a deposition apparatus according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] The descriptions of exemplary embodiments of methods, structures, devices, and apparatus provided below are merely exemplary and intended for illustrative purposes only. The following descriptions are not intended to limit the scope of the present disclosure or the claims. Moreover, the recitation of multiple embodiments having described features is not intended to exclude other embodiments having additional features or other embodiments incorporating different combinations of the described features. For example, various embodiments may be described as exemplary embodiments and recited in dependent claims. Unless otherwise stated, the exemplary embodiments or components thereof may be combined or applied separately from each other.

[0029] The present disclosure relates to a method for forming a vanadium nitride-containing layer, the method including providing a substrate in a reaction chamber of a reactor and depositing a vanadium nitride-containing layer on the surface of the substrate. In the method according to the present disclosure, the deposition process includes providing a vanadium precursor to the reaction chamber (e.g., sequentially and separately) and providing a nitrogen precursor to the reaction chamber.

[0030] The methods according to the present disclosure can be used to fabricate structures including vanadium nitride-containing layers and devices including vanadium nitride-containing layers. The vanadium nitride-containing layers and structures according to the present disclosure can be used as metal gates, liners / barriers, metal electrodes (DRAM, logic, 3D NAND), and also as work function metals in p-metal gates for logic, and also as dipole (p) tuning layers for logic and other applications.

[0031] The method according to the present disclosure may be carried out in a batch processing tool such as a vertical furnace, in a mini-batch, single wafer or spatial reactor.

[0032] In one embodiment, the vanadium precursor may comprise an organic compound. In another embodiment, the vanadium precursor may comprise an inorganic compound.

[0033] The organic vanadium precursor may include one or more of a vanadium alkylamide precursor, a vanadium dialkylamide precursor, a vanadium amidinate precursor, a vanadium alkoxide precursor, a vanadyl alkoxide precursor, a vanadium beta-diketonate precursor, and a vanadium cyclopentadienyl precursor.

[0034] The following abbreviations will be used throughout this disclosure: Me is methyl (CH3), Et is ethyl (C2H5), n Pr is n-propyl, i Pr is isopropyl, n Bu is n-butyl, t Bu is tert-butyl, n Pn is n-pentyl, and t Pn stands for tert-pentyl, AMD stands for acetamidinate, and FMD stands for formamidinate.

[0035] Examples of Vanadium Alkylamide Precursors V(NMe2)4, V(NEt2)4, and V(NEtMe)4. Exemplary vanadium dialkylamide precursors include V(NMe2)4, V(NEt2)4, and V(NEtMe)4, (designated tetrakis(dimethylamido)vanadium(IV), tetrakis(diethylamido)vanadium(IV), and tetrakis(ethylmethylamido)vanadium(IV), respectively).

[0036] Examples of vanadium amidinate precursors include V( i PrAMD)3, V( t BuAMD)3, V( i PrFMD)3, and V( t Examples of vanadium alkoxide precursors are V(OMe)4, V(OEt)4, V(OnPr)4, V(OiPr)4, V(OiBu)4, V(OtBu)4, V(OtPn)4, and V(OnPn)4. Additionally, examples of vanadyl alkoxide precursors are VO(OMe)3, VO(OEt)3, VO(O n Pr)3, VO(O i Pr)3, VO(O iBu)3, VO(O t Bu)3, VO(O t Pn)3, and VO(O n Pn)3.

[0037] Examples of vanadium beta-diketonate precursors are V(acac)3 (tris-(2,4-pentanedionato)vanadium(IV)), V(thd)3 (tris-(2,2,6,6-tetramethyl-3,5-heptanedione)vanadium(IV)), V(hfac)3 (tris-(1,1,1,5,5,5-hexafluoro-2,4-pentanedionato)vanadium(IV)), V(thd)3 (tris-(2,2,6,6-tetramethyl-3,5-heptanedione ... IV)), VO(acac)2 (oxobis(2,4-pentanedionato)vanadium(IV)), VO(thd)2 (oxobis(2,2,6,6-tetramethyl-3,5-heptanedione)vanadium(IV)), and VO(hfac)2 (oxobis(1,1,1,5,5,5-hexafluoro-2,4-pentanedionato)vanadium(IV)).

[0038] Vanadium cyclopentadienyl precursors include VCp2Cl2, VCp2, and VCp2(CO)4 (named bischlorobis(cyclopentdienyl)vanadium(IV), bis(cyclopentadienyl)vanadium(II), and cyclopentadienylvanadium tetracarbonyl, respectively. Additional exemplary vanadium cyclopentadienyl compounds include variations of these compounds, where Cp is unsubstituted or contains one or more alkyl groups, such as MeCp, EtCp, iPrCp, etc.

[0039] Examples of inorganic vanadium precursors are vanadium halide precursors and vanadium oxyhalide precursors. The vanadium halide precursors can be selected from the group consisting of vanadium fluoride, vanadium chloride, vanadium bromide, vanadium iodide, etc. The vanadium oxyhalide precursors can be selected from the group consisting of vanadium oxyfluoride, vanadium oxychloride, vanadium oxybromide, vanadium oxyiodide, etc.

[0040] Additionally, exemplary vanadium precursors can include "heteroleptic" or mixed-ligand precursors, where any combination of exemplary ligand types can be attached to the vanadium atom in any achievable number (typically 3-5 ligands, but there are exceptions). Examples include V(Cl). x (NMe) 4-x and V(Cl) x (iPrAMD) x could be included.

[0041] The nitrogen precursor may be selected from one or more of ammonia (NH), hydrazine (NH), and other compounds containing or consisting of nitrogen and hydrogen. For example, a mixture of nitrogen gas and hydrogen gas may be used. In one embodiment, the nitrogen precursor does not contain diatomic nitrogen, i.e., the nitrogen precursor is a non-diatomic precursor.

[0042] The use of vanadium halide precursors may be advantageous compared to methods using other precursors, such as vanadium organometallic precursors, because vanadium halide precursors may be relatively inexpensive, may result in vanadium layers with lower concentrations of impurities such as carbon, and / or processes using such precursors may be more controllable compared to processes using organometallic or other vanadium precursors. Furthermore, such reactants may be used to form excited species without the aid of a plasma. Also, processes using vanadium halide precursors may be easier to scale up compared to methods using organometallic vanadium precursors.

[0043] In one embodiment, the deposition process includes a continuous flow of at least one precursor. In another embodiment, the flow of both precursors may be continuous. In another embodiment, the flow of the two precursors may be at least partially simultaneous.

[0044] The cyclic deposition process can include one or more of an atomic layer deposition process and a cyclic chemical vapor deposition process. The cyclic deposition process can also include a thermal process, i.e., a process that does not use plasma activated species. In some cases, reactants can be exposed to a plasma to form activated reactant species. In some embodiments, the cyclic deposition process can include only one or more thermal processes.

[0045] In one embodiment, the temperature of the substrate in the reaction chamber during the cyclic deposition process is from about 20°C to about 800°C. For example, the cyclic deposition process may include heating the substrate to a desired deposition temperature in the reaction chamber. The temperature may be less than 800°C. For example, heating the substrate to the deposition temperature may include heating the substrate to a temperature of from about 20°C to about 800°C. In some embodiments, the substrate temperature may be from about 100°C to about 400°C, or from about 200°C to about 500°C, e.g., 250°C, 300°C, or 450°C, or from about 20°C to about 200°C.

[0046] In the case of a thermal cyclic deposition process, the period of time for supplying a precursor to the reaction chamber may be relatively long to allow the precursor to react with another precursor or its derivative. For example, the period can be 5 seconds or more, or 10 seconds or more, or between about 5 and 10 seconds. In one embodiment, the period of time for supplying the nitrogen precursor to the reaction chamber is 5 seconds or more, or 10 seconds or more, or between about 5 and about 10 seconds.

[0047] In addition to controlling the temperature of the substrate, the pressure within the reaction chamber can also be adjusted. For example, in some embodiments of the present disclosure, the pressure within the reaction chamber can be less than 760 Torr, or between 0.2 Torr and 760 Torr, between 1 Torr and 100 Torr, or between 1 Torr and 10 Torr.

[0048] In one embodiment, the surface of the substrate comprises a first surface material and a second surface material, and the cyclic deposition process results in the deposition of a vanadium nitride-containing layer selectively on the first surface material relative to the second surface material.

[0049] In some embodiments, the vanadium nitride-containing layer is selectively deposited on a first metal or metallic surface of the substrate relative to a second dielectric surface of the substrate. In some embodiments, the second surface comprises —OH groups, such as a SiO2-based surface. In some embodiments, the vanadium nitride is selectively deposited on a first metal, metallic, metal oxide, or dielectric surface of the substrate relative to a second, different SiO2 surface.

[0050] Unless otherwise indicated, when a surface is referred to herein as a metal surface, the surface may be a metallic surface or a metallic surface. In some embodiments, the metal or metallic surface may include a metal such as, for example, an elemental metal, a metal nitride, a metal silicide, a metal carbide, and / or a mixture thereof. In some embodiments, the metal or metallic surface may include a surface oxidation, e.g., a surface layer of a native metal oxide. In some embodiments, the metallic material of the metal or metallic surface is conductive with or without surface oxidation. In some embodiments, the metal or metallic surface includes silicon, such as H-terminated silicon. In some embodiments, the metal or metallic surface is a silicon surface, such as an H-terminated silicon surface. In some embodiments, the metal or metallic surface is not a silicon surface, such as an H-terminated silicon surface. A first metal or metallic surface may also be referred to herein as a first surface.

[0051] In some embodiments, the metal or metallic surface comprises one or more transition metals. In some embodiments, the metal or metallic surface comprises aluminum. In some embodiments, the metal or metallic surface comprises one or more of Al, Cu, Co, Ni, and W. In some embodiments, the metallic surface comprises titanium nitride. In some embodiments, the metal or metallic surface comprises one or more noble metals, such as Ru. In some embodiments, the metal or metallic surface comprises a conductive metal oxide, such as a noble metal oxide, such as RuO.

[0052] In some embodiments, the material is selectively deposited on a first metal surface, which comprises a metal oxide surface. The metal oxide surface may be, for example, WO x , HfO2, TiO2, Al2O3, or ZrO2 surfaces. In some embodiments, the metal oxide surface is an oxidized surface of a metallic material. In some embodiments, the metal oxide surface is created by oxidizing at least the surface of the metallic material using an oxygen compound, such as a compound comprising O3, HO, HO, O2, O2, oxygen atoms, oxygen plasma, or oxygen radicals, or a mixture thereof. In some embodiments, the metal oxide surface is a native oxide formed on the metallic material.

[0053] In some embodiments, the vanadium nitride-containing layer is selectively deposited on a first surface comprising a dielectric surface relative to a second SiO2 surface. The term dielectric is used herein for simplicity when distinguishing from other surfaces, i.e., metal or metallic surfaces. Unless otherwise indicated for a particular embodiment, the term dielectric in the context of this application may be understood to cover all surfaces that are electrically non-conductive or have very high resistivity. As used herein, the term "dielectric surface" may refer to the surface of a dielectric material, including, but not limited to, silicon-containing dielectric materials, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and mixtures thereof. Furthermore, the term "dielectric surface" may also refer to the surface of a metal oxide material or the oxidized surface of a metal nitride material.

[0054] In some embodiments, the dielectric surface may be referred to herein as the second surface. In some embodiments, the second surface may include any dielectric surface. In some embodiments, a substrate is provided that includes a first metal or metallic surface and a second dielectric surface. In some embodiments, a substrate is provided that includes a first metal surface, including a metal oxide surface. In some embodiments, the second surface may include —OH groups. In some embodiments, the second surface may be a SiO2-based surface. In some embodiments, the second surface may include Si—O bonds. In some embodiments, the second surface may include a SiO2-based low-k material. In some embodiments, the second surface may include greater than about 30%, preferably greater than about 50%, of SiO2. In some embodiments, the second surface may include GeO2. In some embodiments, the second surface may include Ge—O bonds.

[0055] In one embodiment, the first surface may comprise a metal and the second surface may comprise a metal. In another embodiment, the first surface may comprise a metal and the second surface may comprise a dielectric material. In another embodiment, the first surface may comprise a dielectric material and the second surface may comprise a metal. In yet another embodiment, the first surface and the second surface comprise a dielectric material.

[0056] In one embodiment, the deposition selectivity is at least 50%, or at least 80%, or at least 90%. In another embodiment, the deposition selectivity may be at least 95%, at least 98%, or at least 99%. The deposition selectivity may be at least 99.5% or even about 100%. The deposition selectivity may alternatively be evaluated based on the nucleation rate on a given surface material under given conditions. For example, a vanadium nitride-containing layer may begin to grow on a first surface material after one, two, or three deposition cycles. Alternatively, a vanadium nitride-containing layer may begin to grow on a first surface material after 10 deposition cycles. A vanadium nitride-containing layer may begin to grow on a second surface material after 50 deposition cycles or 100 deposition cycles.

[0057] In one embodiment, deposition selectivity is adjusted via etch-back between cyclic depositions. By etch-back, as used herein, is meant the process of removing a portion of a layer already deposited between deposition cycles. Etch-back can increase selectivity by slowing layer growth on a second surface material relative to a first surface material. Methods according to the present disclosure may include one or more etch-back phases, and the spacing, duration, and other characteristics of the etch-back phases may be selected independently of the deposition cycles. This allows the process to be tailored to achieve desired layer selectivity, thickness, etc.

[0058] In one embodiment, the vanadium nitride-containing layer is a seed layer. The seed layer can increase the nucleation rate of another deposited material. This, in turn, can result in achieving a substantially or completely continuous layer with fewer deposition cycles and improving layer integrity. This allows for thinner layers to be deposited. Alternatively, or in addition, the resulting layer may have a smoother surface. This can be advantageous, for example, in avoiding defects in sensitive applications and applications involving high aspect ratio structures. In one embodiment, the vanadium nitride-containing layer can be deposited as a seed layer prior to depositing the titanium nitride layer. The titanium nitride layer can be deposited from TiCl4 and NH3 using a cyclic deposition process.

[0059] It may be advantageous to use the vanadium nitride-containing layer as a seed layer before depositing a metal layer. Examples of metals that can be deposited on the vanadium nitride-containing seed layer include molybdenum, tungsten, copper, and cobalt. The metal layer may function, for example, as a barrier metal, a work function metal for logic, or a DRAM electrode.

[0060] In one embodiment, the seed layer has a thickness of 0.6 nm or less, for example 0.4 nm. It may be possible to deposit a thin vanadium nitride-containing layer that is substantially continuous. Such a layer may have advantages in space-limited structures. The seed layer may be substantially continuous. In one embodiment, the seed layer may be discontinuous. The rate of nucleation may also be improved by a discontinuous seed layer. This may be desirable, for example, to reduce the effect of the seed layer on the properties of the fabricated structure.

[0061] In further embodiments, the vanadium nitride-containing layer may be deposited on a seed layer, referred to herein as an underlayer. The use of an underlayer between the substrate and the vanadium nitride-containing layer may enable the deposition of a vanadium nitride-containing layer with reduced resistivity. Thus, the use of an underlayer may enable the deposition of a substantially or completely continuous vanadium-containing layer with fewer deposition cycles, as described above, and may improve layer integrity and / or surface smoothness. In some embodiments, the underlayer is deposited on a substrate that includes, consists essentially of, or consists of a dielectric material. In some embodiments, the dielectric material is a thermal oxide. In some embodiments, the dielectric material is a thermal oxide.

[0062] The use of an underlayer beneath a vanadium nitride-containing layer can be advantageous in applications where a vanadium nitride-containing layer having a thickness of less than 10 nm, or less than 5 nm, or less than 3 nm, or less than 2 nm, or less than 1.5 nm is used. In some embodiments, the thickness of the underlayer can be, for example, from about 0.05 nm to about 0.4 nm, or from about 0.1 nm to about 0.3 nm, e.g., about 0.15 nm, about 0.2 nm, about 0.25 nm, or about 0.35 nm.

[0063] The underlayer may be substantially continuous. In some embodiments, the underlayer may be discontinuous. The underlayer may comprise various chemistries, such as silicon oxide or deposited carbon-containing metal oxides known in the art. In some embodiments, the underlayer is deposited in 1 to 5 deposition cycles, e.g., 1, 2, or 3 deposition cycles.

[0064] As a non-limiting example of a method according to the present disclosure, when a vanadium nitride-containing layer according to the present disclosure substantially contains only vanadium and nitride and has a layer thickness of approximately 50 Å, the film resistivity may be 200 μOhm·cm or less. When the vanadium nitride-containing layer has a thickness of approximately 40 Å, the resistivity may be less than 300 μOhm·cm, and when the layer thickness is approximately 30 Å, the resistivity may be less than 350 μOhm·cm. Furthermore, when the vanadium nitride-containing film has a thickness of approximately 20 Å, the resistivity may be less than 500 μOhm·cm. The increase in resistivity of the vanadium nitride-containing layer may be slower than that of a TiN layer of similar thickness.

[0065] The method according to the present disclosure may be performed in a single wafer tool or a batch reactor. The reaction chamber may be a stand-alone reaction chamber or part of a cluster tool.

[0066] It may be possible to obtain good within-wafer thickness uniformity and good down-boat thickness and resistivity performance for vanadium nitride-containing layers in batch deposition. In some embodiments, the wafers are rotated during processing. In some embodiments, the batch reactor comprises a reactor configured to accommodate 25 or more, 50 or more, 75 or more, 100 or more, or 150 or more wafers stacked vertically on a boat. In other embodiments, the batch reactor may comprise a mini-batch reactor configured to accommodate 10 or fewer wafers, 8 or fewer wafers, 6 or fewer wafers, 4 or fewer wafers, or 2 wafers. In some embodiments using a batch reactor, when the vanadium nitride-containing layer has a thickness of less than 20 nm, less than 15 nm, less than 10 nm, less than 7 nm, less than 5 nm, less than 4 nm, or less than 3 nm, the wafer-to-wafer thickness non-uniformity, or resistivity, may be less than 20% (1 sigma), less than 10%, less than 5%, less than 3%, less than 2%, or even less than 1%.

[0067] Within-wafer thickness non-uniformity or resistivity is less than 30% (1 sigma), less than 20%, less than 15%, less than 10%, less than 5%, less than 3%, less than 2%, less than 1%, or even less than 0.5%.

[0068] In one embodiment, the vanadium nitride-containing layer is used as an etch stop layer. In another embodiment, the vanadium nitride-containing layer may be used as an etch stop layer for a dielectric metal oxide, such as aluminum oxide.

[0069] In one embodiment, the cyclic deposition process includes annealing in the presence of SiH4. The annealing can be used to reduce stress in the layer. The annealing can be performed during the cyclic deposition process. Alternatively, the annealing can be performed after the cyclic deposition process. The annealing can be performed once. Alternatively, the annealing can be performed several times at predetermined intervals during the cyclic deposition process. The annealing can affect layer properties by reducing intrinsic and / or thermal stress in the layer. Reducing stress in the deposited layer can have a positive effect on the properties of the final device.

[0070] In one embodiment, silane (SiH), disilane (SiH), trisilane (SiH), or tetrasilane (SiH) 10 Silane compounds such as chlorosilanes (OCTS), octochlorotrisilane (OCTS), HCDS (hexachlorodisilane), and DCS (dichlorosilane) can be used for annealing.

[0071] Without limiting the present disclosure to any particular theory, annealing in the presence of silicon-containing compounds such as silanes, some silicon may be incorporated into the layer, and the amount of silicon incorporated may be varied and tunable by appropriate selection of the annealing regime.

[0072] In one embodiment, annealing may be carried out at a temperature between 300°C and 500°C, for example, at a temperature of approximately 350°C, 370°C, or 400°C.

[0073] The present disclosure is further explained by the following exemplary embodiments shown in the drawings. The figures shown herein are not meant to be actual drawings of any particular materials, structures, or devices, but are merely schematic representations for describing embodiments of the present disclosure. It should be understood that elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of the illustrated embodiments of the present disclosure.

[0074] 1 illustrates a method 100 in an exemplary embodiment of the present disclosure. The method 100 may be used to form a layer including vanadium nitride, i.e., a vanadium nitride-containing layer. The vanadium nitride-containing layer may be used during the formation of devices, such as those described herein. However, unless otherwise noted, the method is not limited to such applications.

[0075] The method 100 includes providing a substrate in a reaction chamber of a reactor (102) and depositing a layer comprising vanadium nitride on a surface of the substrate (104).

[0076] During step 102, a substrate is provided into a reaction chamber. The reaction chamber used during step 102 may be or include a reaction chamber of a chemical vapor deposition reactor system configured to perform a deposition process. The deposition process may be a cyclic deposition process. The reaction chamber may be a stand-alone reaction chamber or part of a cluster tool. The reaction chamber may be a batch processing tool.

[0077] Step 102 may include heating the substrate to a desired deposition temperature in a reaction chamber. In some embodiments of the present disclosure, step 102 includes heating the substrate to a temperature less than 800°C. For example, in some embodiments of the present disclosure, heating the substrate to the deposition temperature may include heating the substrate to a temperature between about 100°C and about 500°C, about 250°C and about 450°C, about 250°C and about 400°C, or about 200°C and about 350°C.

[0078] In addition to controlling the temperature of the substrate, the pressure within the reaction chamber can also be adjusted. For example, in some embodiments of the present disclosure, the pressure within the reaction chamber during step 102 can be less than 760 Torr, or between 0.5 Torr and 760 Torr, about 1 Torr and 100 Torr, for example, or between about 1 Torr and 10 Torr. The pressure can be, for example, 10 Torr or less, 5 Torr or less, 3 Torr or less, 2 Torr or less, 1 Torr or less, 0.1 Torr or less, or 0.001 Torr or less.

[0079] During step 104, a layer comprising vanadium nitride is deposited on the surface of the substrate using a deposition process. As mentioned above, the deposition process may be a cyclic deposition process and may include a cyclic CVD, ALD, or hybrid cyclic CVD / ALD process. For example, in some embodiments, the growth rate of a particular ALD process may be low compared to a CVD process. One approach to increasing the growth rate may be to operate at a higher deposition temperature than that typically used in an ALD process, resulting in a chemical vapor deposition process but still with the benefits of sequential introduction of precursors. Such a process may be referred to as cyclic CVD. In some embodiments, a cyclic CVD process may include the introduction of two or more precursors into the reaction chamber, with a period of overlap between the two or more precursors in the reaction chamber, resulting in both an ALD component of the deposition and a CVD component of the deposition. This is referred to as a hybrid process. By further example, a cyclic deposition process may include a continuous flow of one reactant / precursor and periodic pulses of a second precursor into the reaction chamber. The temperature and / or pressure within the reaction chamber during step 104 may be the same as or similar to any of the pressures and temperatures described above in connection with step 102 .

[0080] According to some embodiments of the present disclosure, the deposition process is a thermal deposition process. In these cases, the deposition process does not involve the use of a plasma to form activated species for use in the deposition process. For example, the deposition process may not involve the formation or use of a plasma, may not involve the formation or use of excited species, and / or may not involve the formation or use of radicals. In the case of a thermal cyclic deposition process, the duration of the step of supplying a precursor to the reaction chamber may be relatively long to allow the precursor to react with another precursor or its derivative. For example, the duration may be 5 seconds or more, or 10 seconds or more, or between about 5 and 10 seconds.

[0081] In other cases, a plasma can be used to excite one or more precursors, one or more precursors, and / or one or more inert gases.

[0082] The cyclic deposition process may include (e.g., separately and sequentially) supplying a vanadium precursor to a reaction chamber and supplying a nitrogen precursor to the reaction chamber. In some cases, a hydrogen reactant may be supplied to the reaction chamber with the vanadium precursor or the nitrogen precursor. The hydrogen reactant may include, for example, H or excited hydrogen species, atomic hydrogen species, hydrogen plasma species, or radical hydrogen species.

[0083] 2 illustrates an exemplary cyclical method 200 suitable for step 104 of method 100. Method 200 includes delivering a vanadium precursor to a reaction chamber (step 202) and delivering a nitrogen precursor to the reaction chamber (step 204). According to an embodiment of the present disclosure, a vanadium nitride-containing layer is formed during the step of delivering the nitrogen precursor to the reaction chamber (step 204).

[0084] In some embodiments of the present disclosure, method 100 includes repeating a unit deposition cycle including steps 202 and 204, with an optional purge or transfer step after step 202 and / or step 204. The deposition cycle can be repeated one or more times based on, for example, the desired thickness of the vanadium nitride-containing layer. For example, if the thickness of the vanadium nitride-containing layer is thinner than desired for a particular application, steps 202 and 204 can be repeated one or more times. In some embodiments, the method includes at least 1 cycle and up to 100 cycles, or at least 2 cycles and up to 80 cycles, or at least 3 cycles and up to 70 cycles, or at least 4 cycles and up to 60 cycles, or at least 5 cycles and up to 50 cycles, or at least 10 cycles and up to 40 cycles, or at least 20 cycles and up to 30 cycles. In some embodiments, the method comprises up to 100 cycles, or up to 90 cycles, or up to 80 cycles, or up to 70 cycles, or up to 60 cycles, or up to 50 cycles, or up to 40 cycles, or up to 30 cycles, or up to 20 cycles, or up to 10 cycles, or up to 5 cycles, or up to 4 cycles, or up to 3 cycles, or up to 2 cycles, or a single cycle.

[0085] The vanadium precursor can include any of the precursors set forth in this disclosure.

[0086] The reaction chamber can be purged using vacuum and / or inert gas before or after one or more steps, for example, to mitigate gas-phase reactions between precursors and enable self-saturating surface reactions (e.g., in the case of ALD). For example, the reaction chamber can be purged after one or more of steps 202 and 204. Additionally or alternatively, the substrate can be moved to be contacted separately with a first gas-phase precursor and a second gas-phase precursor. Excess chemicals and reaction by-products, if any, can be removed from the surface of the substrate or the reaction chamber before contacting the substrate with the next reactive chemical, for example, by purging the reaction space or by moving the substrate. The reaction chamber can be purged after a step of supplying precursors to the reaction chamber and / or after a step of supplying precursors to the reaction chamber.

[0087] In some embodiments, the step coverage of the vanadium nitride-comprising layer is about 50% or greater, or about 80% or greater, or about 90% or greater, or about 95%, or about 98%, or about 99% or greater, in / on structures with aspect ratios (height / width) greater than about 2, greater than about 5, greater than about 10, greater than about 25, greater than about 50, greater than about 100, or between about 10-100, or about 5-25.

[0088] In some embodiments, the growth rate of the vanadium nitride-containing layer can be relatively low, for example, less than 3 Å / cycle, about 0.2 to 3 Å / cycle, or about 0.1 to about 1 Å / cycle. Alternatively, the growth rate of the vanadium nitride-containing layer can be less than 10 Å / cycle, less than 5 Å / cycle, or less than 4 Å / cycle. A relatively low growth rate can facilitate the desired precision of film thickness and / or film thickness uniformity. However, with appropriate selection of process conditions, faster growth rates can be obtained. The preferred layer growth rate depends on the application and can be selected as needed by one skilled in the art.

[0089] 3 shows a structure / portion of a device 300 according to an additional embodiment of the present disclosure. The device or structure 300 includes a substrate 302, a dielectric or insulating material 305, and a layer 308 including vanadium nitride. In the illustrated embodiment, the structure 300 also includes an additional conductive layer 310.

[0090] Substrate 302 can be or can include any of the substrate materials described herein.

[0091] The dielectric or insulating material 305 may include one or more dielectric or insulating material layers. For example, the dielectric or insulating material 305 may include an interface layer 304 and a high-k material 306 deposited overlying the interface layer 304. In some cases, the interface layer 304 may be absent or absent to a significant extent. The interface layer 304 may include an oxide, such as silicon oxide, which may be formed on the surface of the substrate 302 using, for example, a chemical oxidation process or an oxide deposition process. The high-k material 306 may be or include, for example, a metal oxide having a dielectric constant greater than about 7. In some embodiments, the high-k material has a dielectric constant higher than that of silicon oxide. Exemplary high-k materials include hafnium oxide (HfO), tantalum oxide (TaO), zirconium oxide (ZrO), titanium oxide (TiO), hafnium silicate (HfSiO), and the like. x ), aluminum oxide (Al2O3), lanthanum oxide (La2O3), and mixtures / laminates comprising one or more such layers.

[0092] The vanadium nitride-containing layer 308 can be formed according to the methods described herein. When the vanadium nitride-containing layer 308 is formed using a cyclic deposition process, the concentrations of vanadium, nitrogen, and / or other components within the vanadium nitride-containing layer 308 can be varied from the bottom of the vanadium nitride-containing layer 308 to the top of the vanadium nitride-containing layer 308, for example, by controlling the amount of vanadium precursor and / or reactant and / or the respective pulse time or number of pulses during one or more deposition cycles. In some cases, the vanadium nitride-containing layer 308 can have a stoichiometric composition. The work function and other properties of the vanadium nitride-containing layer 308 can be modified by varying the amounts of vanadium, nitrogen, and / or other compounds within the layer or deposition cycle.

[0093] The vanadium nitride containing layer 308 may contain halides, hydrogen, or similar impurities, alone or in combination, in amounts less than 1 atomic percent, less than 0.2 atomic percent, or less than 0.1 atomic percent, or less than 0.05 atomic percent.

[0094] The thickness of the vanadium nitride-containing layer 308 can vary depending on the application. For example, the thickness of the vanadium nitride-containing layer 308 can be less than 5 nm, or between about 0.1 nm and about 10 nm, or between about 0.1 nm and about 5 nm, or between about 0.2 nm and about 5 nm, or between about 0.3 nm and about 3 nm, or between about 0.3 nm and about 1 nm. When used to replace a layer that may contain aluminum rather than vanadium, the vanadium nitride-containing layer 308 can be relatively thin, which may be desirable for many applications, including work function and / or voltage threshold adjustment layers. In some cases, the thickness of the vanadium nitride-containing layer 308 can be greater than 2 nm, for example, when the vanadium nitride-containing layer 308 is used as a barrier layer or liner.

[0095] The shifted work function of the vanadium nitride-containing layer 308 can be greater than 4.6 eV, greater than 4.7 eV, greater than 4.8 eV, greater than 4.9 eV, greater than 4.95 eV, or greater than 5.0 eV. The work function value of the device can be shifted by about 30 meV to about 300 meV, or about 30 meV to about 200 meV, or about 50 meV to about 100 meV using the vanadium nitride-containing layers described herein. The thickness and / or composition of the vanadium nitride-containing layer can be manipulated to obtain a desired shift in work function and / or threshold voltage.

[0096] Additionally or alternatively, the vanadium nitride-containing layer 308 can be formed into a continuous film with a thickness of less than 5 nm, less than 4 nm, less than 3 nm, less than 2 nm, less than 1.5 nm, less than 1.2 nm, less than 1.0 nm, or less than 0.9 nm using, for example, method 100. The vanadium nitride-containing layer 308 can be relatively smooth and have relatively low grain boundary formation. In some cases, the vanadium nitride-containing layer 308 can be amorphous, with a relatively low columnar crystal structure (compared to TiN). The RMS roughness of exemplary vanadium nitride-containing layers 308 can be less than 1.0 nm, less than 0.7 nm, less than 0.5 nm, less than 0.4 nm, less than 0.35 nm, or less than 0.3 nm at a thickness of less than 10 nm.

[0097] The additional conductive layer 310 may include, for example, a metal, such as a refractory metal, etc. By way of example, the conductive layer 310 may be or include one or more of titanium nitride, vanadium nitride, titanium nitride and a metal (e.g., W, Co, Ru, Mo) or a metal stack including titanium nitride, titanium aluminum carbon, and titanium nitride, tungsten, tungsten carbonitride, cobalt, copper, molybdenum, ruthenium, or the like.

[0098] Although illustrated with vanadium nitride-containing layer 308 overlying dielectric or insulating material 305, in some cases vanadium nitride-containing layer 308 may additionally or alternatively be formed directly on substrate 302 (which may include various layers and / or topologies) and / or beneath dielectric or insulating material 305, between interface layer 304 and high-k material 306, and / or between layers of high-k material 306. Furthermore, vanadium nitride-containing layer 308 may be deposited and at least partially removed such that the resulting structure may no longer include vanadium nitride-containing layer 308 or may include fewer layers comprising vanadium nitride than were originally formed on the structure.

[0099] 4 illustrates another exemplary structure 400 according to an embodiment of the present disclosure. The device or structure 400 includes a substrate 402, a dielectric or insulating material 404, and a vanadium nitride-containing layer 406. In the illustrated embodiment, the structure 400 also includes an additional conductive layer 412. The substrate 402, the dielectric or insulating material 404, the vanadium nitride-containing layer 406, and the additional conductive layer 412 may be the same as or similar to the substrate 402, the dielectric or insulating material 404, the vanadium and / or vanadium nitride-containing layer 408, and the conductive layer 410. As above, the vanadium nitride-containing layer 406 may additionally or alternatively be formed on the substrate 402 (which may include various layers and / or topologies) and / or below the insulating material 404, between the interface layer 408 and the high-k material 410, and / or between layers of the high-k material 410. Additionally, the vanadium nitride-containing layer 406 may be deposited and at least partially removed such that the resulting structure may no longer include the vanadium nitride-containing layer 406 or may include fewer vanadium nitride-containing layers 406 than were originally formed on the structure.

[0100] In the illustrated embodiment, the substrate 402 includes a source region 414, a drain region 416, and a channel region 418. Although illustrated as a horizontal structure, structures and devices according to embodiments of the present disclosure can include vertical and / or three-dimensional structures and devices, such as FinFET devices, gate-all-around devices, and nanosheet devices.

[0101] 5 illustrates another structure 500 according to an embodiment of the present disclosure. The structure 500 is suitable for devices such as gate-all-around field-effect transistor (GAA FET) (also called lateral nanowire FET).

[0102] In the illustrated example, structure 500 includes a semiconductor material 502, a dielectric material 504, a vanadium nitride-containing layer 506, and a conductive layer 508. Structure 500 may include and be formed overlying a substrate material described herein.

[0103] Semiconductor material 502 may include any suitable semiconductor material. For example, semiconductor material 502 may include a Group IV, Group III-V, or Group II-VI semiconductor material. By way of example, semiconductor material 502 may include silicon.

[0104] As mentioned above, the dielectric material 504, the vanadium nitride-containing layer 506, and the conductive layer 508 can be the same as or similar to the dielectric or insulating material 305, the vanadium nitride-containing layer 308, and the conductive layer 310. The vanadium nitride-containing layer 506 can be formed over the semiconductor material 502 and / or under the dielectric material 504 according to further embodiments of the present disclosure.

[0105] 6 is an illustration of a deposition apparatus 600 according to yet an additional exemplary embodiment of the present disclosure. Apparatus 600 can be used to perform methods described herein and / or to form structures or device portions described herein.

[0106] In the illustrated embodiment, the apparatus 600 includes one or more reaction chambers 602 , a first precursor gas source 604 , a second precursor gas source 606 , a purge gas source 608 , an exhaust source 610 , and a controller 612 .

[0107] Reaction chamber 602 can include any suitable reaction chamber, for example, an ALD or CVD reaction chamber.

[0108] The first precursor gas source 604 can include a container and one or more vanadium precursors described herein, alone or mixed with one or more carrier (e.g., inert) gases. The second precursor gas source 606 can include a container and one or more precursors described herein (e.g., nitrogen precursors), alone or mixed with one or more carrier gases. The purge gas source 608 can include one or more inert gases described herein. Although illustrated with three gas sources 604-608, the apparatus 600 can include any suitable number of gas sources. The gas sources 604-608 can be connected to the reaction chamber 602 via lines 614-618, which can each include flow controllers, valves, heaters, and the like.

[0109] The exhaust source 610 may include one or more vacuum pumps.

[0110] The controller 612 includes electronic circuitry and software that selectively operates the valves, manifolds, heaters, pumps, and other components included in the apparatus 600. Such circuitry and components operate to introduce precursor, reactant, and purge gases from their respective sources 604-608. The controller 612 controls the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to properly operate the apparatus 600. The controller 612 may include control software that electrically or pneumatically controls valves to control the flow of precursor, reactant, and purge gases into and out of the reaction chamber 602. The controller 612 may include software or hardware components, such as modules, e.g., FPGAs or ASICs, that perform specific tasks. The modules are advantageously configured to reside on addressable storage media in the control system and may be configured to perform one or more processes.

[0111] Other configurations of the apparatus 600 are possible, including different numbers and types of precursor and reactant sources and purge gas sources. It will be appreciated that there are numerous arrangements of valves, conduits, precursor sources, and purge gas sources that can be used to achieve the goal of selectively delivering gases into the reaction chamber 602. Furthermore, as a schematic representation of the apparatus, many components have been omitted for ease of illustration. Such components may include, for example, various valves, manifolds, purifiers, heaters, reservoirs, vents, and / or bypasses.

[0112] During operation of deposition apparatus 600, a substrate, e.g., a semiconductor wafer (not shown), is transferred, e.g., from a substrate handling system, to reaction chamber 602. Once the substrate is transferred to reaction chamber 602, one or more gases, e.g., precursors, reactants, carrier gases, and / or purge gases, from gas sources 604-608 are introduced into reaction chamber 602.

[0113] The exemplary embodiments of the present disclosure described above are merely examples of embodiments of the present invention, as defined by the appended claims and their legal equivalents, and therefore do not limit the scope of the present invention. Any equivalent embodiments are intended to be within the scope of the present invention. Indeed, various modifications of the present disclosure in addition to those shown and described herein may become apparent to those skilled in the art from the description, including alternative useful combinations of the described elements. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims

1. A method for forming a vanadium nitride-containing layer and a conductive layer on the vanadium nitride-containing layer, comprising: providing a substrate into a reaction chamber of a reactor; depositing the vanadium nitride-containing layer on the surface of the substrate by a first cyclic deposition step to form a seed layer; the first cyclical deposition step comprising: providing a vanadium precursor to the reaction chamber; providing a nitrogen precursor to the reaction chamber; The method further comprises, after the first cyclical deposition step, depositing the conductive layer on the seed layer by a second cyclical deposition step.

2. The method of claim 1, wherein the conductive layer comprises a heat-resistant metal.

3. The conductive layer Titanium nitride, Vanadium nitride, a first metal stack comprising titanium nitride and one or more of tungsten, cobalt, ruthenium, and molybdenum; a second metal stack comprising titanium nitride, titanium aluminum carbon, and titanium nitride; Tungsten and tungsten carbonitride; Cobalt and Copper and Molybdenum and ruthenium.

4. The method of claim 1, wherein the reaction chamber is purged between supplying the vanadium precursor to the reaction chamber and supplying the nitrogen precursor to the reaction chamber.

5. The method of claim 1, wherein the nitrogen precursor is selected from one or more of ammonia (NH 3 ), hydrazine (N 2 H 4 ), and compounds containing or consisting of nitrogen and hydrogen.

6. The method of claim 1, wherein the nitrogen precursor does not contain diatomic nitrogen.

7. The method of claim 1, wherein the conductive layer comprises titanium nitride.

8. The method described in claim 1, wherein the thickness of the seed layer is 0.6 nm or less.

9. The method of claim 1, wherein the seed layer is discontinuous.

10. The method of claim 1, wherein the first cyclic deposition step includes annealing in the presence of a silane compound.

11. The method of claim 10, wherein the silane compound is SiH 4 .

12. A method for forming a structure, comprising: providing a substrate into a reaction chamber of a reactor; depositing a vanadium nitride-containing layer on the surface of the substrate using a first cyclic deposition step to form a seed layer; the first cyclical deposition step comprising: providing a vanadium precursor to the reaction chamber; providing a nitrogen precursor to the reaction chamber; The method further includes, after the seed layer is formed by the first cyclical deposition process, depositing a conductive layer on the seed layer using a second cyclical deposition process.

13. The method of claim 12, wherein the conductive layer comprises a heat-resistant metal.

14. The conductive layer Titanium nitride, Vanadium nitride, a first metal stack comprising titanium nitride and one or more of tungsten, cobalt, ruthenium, and molybdenum; a second metal stack comprising titanium nitride, titanium aluminum carbon, and titanium nitride; Tungsten and tungsten carbonitride; Cobalt and Copper and Molybdenum and ruthenium.

15. The method of claim 12, wherein the structure is configured to be used as a metal gate, a liner or barrier, a metal electrode, a p-metal gate, or a work function metal for a dipole (p) tuning layer.

16. The method of claim 12, wherein the structure is configured for use during the formation of a gate-all-around field effect transistor device.

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