Doped semiconductor film
By incorporating dopants into silicon and boron-containing films, the method addresses transparency and etch selectivity challenges in semiconductor manufacturing, producing films with reduced stress and improved processing capabilities.
Patent Information
- Application Number
- JP2025154885
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2020-09-18
- Filing Date
- 2025-09-18
- Publication Date
- 2026-01-14
AI Technical Summary
Conventional semiconductor manufacturing processes face challenges in achieving high transparency and etch selectivity in hard mask materials due to increased hydrogen content, leading to film cracking and reduced effectiveness during subsequent thermal processing.
A deposition method incorporating dopants like carbon, nitrogen, oxygen, or sulfur into silicon and boron-containing films to reduce the extinction coefficient and maintain etch selectivity, using controlled plasma conditions and thermal annealing to minimize hydrogen content and stress.
The method produces films with reduced surface roughness and improved mask materials that facilitate processing steps, maintaining transparency and integrity during thermal annealing, reducing cracking and stress-related issues.
Smart Images
Figure 2026004353000001_ABST
Abstract
Description
[Technical Field]
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 025,009, filed Sep. 18, 2020, entitled "DOPING SEMICONDUCTOR FILMS," the entire contents of which are incorporated herein by reference.
[0002]
[0002] The present technology relates to semiconductor integration processes. More specifically, the present technology relates to methods for depositing materials having dopants that affect the transparency of the film. [Background technology]
[0003]
[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods for forming and removing exposed material. As device sizes continue to shrink, material properties can affect subsequent operation. For example, the transparency of masking materials can affect subsequent etching processes.
[0004]
[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technique addresses these and other needs. Summary of the Invention
[0005] An exemplary deposition method may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may include delivering a dopant-containing precursor along with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The method may include forming a plasma of all the precursors in the processing region of the semiconductor processing chamber. The method may include depositing a silicon-and-boron material on a substrate disposed in the processing region of the semiconductor processing chamber. The silicon-and-boron material may include about 1 atomic % (at. %) or more of the dopant from the dopant-containing precursor.
[0006] In some embodiments, the silicon and boron material may be characterized by an extinction coefficient of about 0.3 or less at 633 nm. The hydrogen concentration in the film may be maintained at about 3 atomic % or less. The method may include providing a germanium-containing precursor along with a silicon-containing precursor and a boron-containing precursor. The method may include performing a thermal anneal of the silicon and boron material after depositing. The thermal anneal may be performed at a temperature of about 500°C or greater. After the thermal anneal, the material stress of the deposited material may be about 1.5 GPa or less. The silicon-containing precursor may be or may include silane. The boron-containing precursor may be or may include diborane. The dopant-containing precursor may be or may include nitrous oxide.
[0007] Some embodiments of the present technology may include a deposition method. The method may include delivering a deposition precursor comprising boron, silicon, or germanium to a processing region of a semiconductor processing chamber. The method may include providing a dopant comprising carbon, nitrogen, sulfur, or oxygen to the processing region. The method may include forming a plasma of the deposition precursor and the dopant within the processing region of the semiconductor processing chamber. The method may include depositing a material incorporating the dopant. The material may be characterized by an extinction coefficient at 633 nm of about 0.35 or less.
[0008] In some embodiments, the method can include annealing the deposited material to a temperature greater than about 500°C. After annealing, the material stress of the deposited material can be about 1.5 GPa or less. The extinction coefficient can be about 0.30 or less at 633 nm. The dopant can be incorporated into the film at about 2 atomic % or more. At least two dopants can be incorporated into the film. The deposited material can be or include silicon, boron, and germanium.
[0009] Some embodiments of the present technology may include a deposition method. The method may include delivering at least one of a silicon-containing precursor, a boron-containing precursor, or a germanium-containing precursor to a processing region of a semiconductor processing chamber. The method may include delivering a dopant-containing precursor to a processing region of the semiconductor processing chamber. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The method may include forming a plasma of all the precursors in the processing region of the semiconductor processing chamber. The method may include depositing a doped material on a substrate disposed in the processing region of the semiconductor processing chamber. The doped material may include about 1 atomic % or more of the dopant from the dopant-containing precursor.
[0010] In some embodiments, the method can include, after depositing, performing a thermal anneal of the silicon and boron material at a temperature of about 400° C. or greater. After performing the anneal, the material stress of the deposited material can be about 1.5 GPa or less. The extinction coefficient of the doped material can be about 0.30 or less at 633 nm.
[0011] Such technology may offer numerous advantages over conventional systems and techniques. For example, the process may produce films characterized by reduced surface roughness. Additionally, steps of embodiments of the technology may produce improved mask materials that may facilitate processing steps. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the description and accompanying drawings.
[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]
[0013] [Figure 1] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique; [Figure 2]
[0014] 1 illustrates exemplary steps in a processing method according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION
[0014]
[0015] Some drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.
[0015]
[0016] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used herein, the description is applicable to any one of the similar components having the same first reference numeral, regardless of the letter.
[0016]
[0017] During semiconductor manufacturing, several structures may be fabricated on a substrate using various deposition and etching processes. Mask materials may be used to partially etch materials or to etch to create features across the entire substrate. As device miniaturization progresses, improving selectivity between materials and facilitating structure formation, improved hard masks may facilitate fabrication. For example, compared to thermally generated amorphous silicon hard masks, silicon films incorporating boron are characterized by improved hardness and other material properties, which may facilitate their use as mask materials. However, many semiconductor manufacturing processes utilize thicker hard mask films to achieve larger vertical device structures. While hard masks may be characterized by sufficient transparency at certain thicknesses, film transparency may decrease as the thickness increases. When the film becomes sufficiently opaque, the process may require an additional step of opening areas near alignment markers to ensure proper orientation.
[0017]
[0018] Some prior art techniques improve transparency by increasing the hydrogen concentration in the resulting mask. This can lead to several problems. For example, increasing the hydrogen content reduces the absorption coefficient, but it can also reduce the selectivity of the resulting film during subsequent etching, potentially reducing the effectiveness of the mask and potentially rendering it unsuitable for the process being performed. Additionally, incorporating a large amount of hydrogen can affect the feasibility of subsequent thermal processing. For example, subsequent annealing can result in hydrogen outgassing, significantly increasing the tensile stress in the film. This stress can often lead to film cracking.
[0018]
[0019] The present technique can overcome these limitations by adjusting deposition parameters and materials to reduce the extinction coefficient of the deposited film without incorporating additional hydrogen. For example, the present technique can include additional dopants such as oxygen, carbon, nitrogen, and sulfur. These materials can form more transparent films while having limited impact on etch selectivity. Additionally, these materials may be capable of performing subsequent annealing with reduced stress changes to reduce cracking and film failure. It will be understood that the technique described is not intended to be limited to the specific films and processes described, as the described techniques can be used to improve numerous film formation processes and may be applicable to a variety of processing chambers and steps.
[0019]
[0020] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 in accordance with some embodiments of the present technique. This diagram may provide an overview of a system incorporating one or more aspects of the present technique and / or capable of performing one or more processes in accordance with embodiments of the present technique. Additional details of the chamber 100 or the method performed therein may be further described below. While the chamber 100 may be utilized to form a film layer in accordance with some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and enclosing the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126, which may conventionally be sealed for processing using a slit valve or door. The substrate 103 may be positioned on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 about which the shaft 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated for rotation as needed during the deposition process.
[0020]
[0021] A plasma profile modulator 111 may be disposed within the processing chamber 100 to control plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the processing chamber 100 surrounding the processing space 120, or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as a secondary gas distributor.
[0021]
[0022] The one or more isolators 110 a, 110 b may be a dielectric material such as a ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing process precursors into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that may be connected to a processing chamber. In some embodiments, the first power source 142 may be an RF power supply.
[0022]
[0023] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, but the face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be connected to ground in some embodiments.
[0023]
[0024] The first electrode 108 may be connected to a first tuned circuit 128 that may control the ground path of the processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuned circuit 128 may be or include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the processing space 120 during processing. In some illustrated embodiments, the first tuned circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node coupling both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be connected to the first electronic controller 134 to allow some degree of closed-loop control of the plasma conditions within the process space 120.
[0024]
[0025] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be integrated into the substrate support 104 or connected to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136, for example, by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms) disposed within a shaft 144 of the substrate support 104. The second tuning circuit 136 may include a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the process space 120.
[0025]
[0026] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to the substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.
[0026]
[0027] The lid assembly 106 and substrate support 104 of FIG. 1 can be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 100 can perform real-time control of plasma conditions within the processing space 120. The substrate 103 is placed on the substrate support 104, and process gases can flow through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases can be exhausted from the processing chamber 100 through the outlet 152. Power can be connected to the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate can be electrically biased using the third electrode 124.
[0027]
[0028] Upon exciting a plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134 and 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and the center-to-edge plasma density uniformity. In embodiments in which both electronic controllers may be variable capacitors, electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.
[0028]
[0029] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using the respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high. This results in a plasma shape with minimum aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to its maximum, thereby effectively covering the entire working area of the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract from the chamber walls, reducing the air coverage of the substrate support. The second electronic controller 140 may have a similar effect, increasing or decreasing the air coverage of the plasma above the substrate support as the capacitance of the second electronic controller 140 changes.
[0029]
[0030] Electronic sensors 130 and 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor. The sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the shape of the plasma may be selected and dynamically controlled during processing. While the above description is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component having an adjustable characteristic may be used to provide the tuning circuits 128 and 136 with an adjustable impedance.
[0030]
[0031] 2 illustrates exemplary steps in a deposition method 200 in accordance with some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps that may or may not be specifically associated with some embodiments of the method in accordance with the present technique. For example, many of the steps are described to provide a broader scope for structure formation, but may not be critical to the present technique or may be performed by alternative methodologies that will be readily understood.
[0031]
[0032] Method 200 may include additional steps prior to the commencement of the recited steps. For example, the additional processing steps may include forming structures on a semiconductor substrate, which may include both the formation and removal of materials. The prior processing steps may be performed in the chamber in which method 200 is performed, or processing may be performed in one or more other processing chambers before providing a substrate to a semiconductor processing chamber in which method 200 is performed. Nevertheless, method 200 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or to another chamber that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as substrate support 104, and which may be present in the processing region of a chamber, such as processing space 120 described above.
[0032]
[0033] The substrate can be any number of materials onto which a material can be deposited. The substrate can be or include silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any combination of these materials, and can be a substrate or a material formed on a substrate. In some embodiments, optional processing steps, such as pretreatment, can be performed to prepare the surface of the substrate for deposition. For example, pretreatment can be performed to provide specific ligand terminations on the surface of the substrate to promote nucleation of the deposited film. For example, by way of non-limiting example, other molecular terminations including hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals, such as amidogens or other functional groups, can be adsorbed, reacted, or formed on the surface of the substrate. Additionally, material removal, such as reduction of native oxides or etching of materials, can be performed, or any other process that can prepare one or more exposed surfaces of the substrate for deposition.
[0033]
[0034] In step 205, one or more precursors may be delivered to the processing region of the chamber. For example, the film to be deposited may be a mask film used in semiconductor processing. The deposition precursors may include any number of mask precursors, including silicon-containing precursors, germanium-containing precursors, and / or boron-containing precursors. The precursors may be flowed together or separately. For example, in an exemplary embodiment in which a boron-incorporated silicon film may be formed, a silicon-containing precursor and a boron-containing precursor may be delivered to the processing region of the processing chamber. In some embodiments of the present technique, plasma-enhanced deposition may be performed to promote reaction and deposition of materials. Additionally, a germanium-containing precursor may be flowed to produce a silicon-boron-germanium material on the substrate.
[0034]
[0035] As discussed above, masks containing silicon, boron, or germanium materials or alloys are relatively opaque, presenting processing challenges and requiring additional processing steps. To reduce the extinction coefficient and improve transparency, the hydrogen content in these materials can be increased; however, hydrogen can adversely affect etch selectivity and cause the material to crack during subsequent annealing due to hydrogen outgassing. Non-hydrogen-based dopants can be used in the present technique to improve transparency while still maintaining etch selectivity and integrity in subsequent annealing steps. Some embodiments of the present technique may include providing an additional dopant-containing precursor in step 210, along with other deposition precursors. The supplied precursors may all be used to form a plasma in the processing region of the semiconductor processing chamber in step 215. A material containing a dopant in the deposited material may be deposited on the substrate in step 220. In some embodiments, incorporating a dopant-containing precursor can control stress in the film while producing a film with improved transparency and a reduced extinction coefficient.
[0035]
[0036] Depending on the precursor used, the flow rate of the dopant precursor can be used to control the incorporation of the dopant. For example, while the flow rates of other deposition precursors, such as oxygen dopants, can be several hundred sccm or more, the dopant precursor can be flowed at a flow rate of about 250 sccm or less, and can be supplied at a flow rate of about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 40 sccm or less, about 30 sccm or less, about 25 sccm or less, about 20 sccm or less, about 15 sccm or less, about 10 sccm or less, about 5 sccm or less, or less. In addition, for other dopants, the flow rate can be higher. For example, for nitrogen dopants, the flow rate is about 500 sccm or greater, and can be about 750 sccm or greater, about 1000 sccm or greater, about 1250 sccm or greater, about 1500 sccm or greater, about 1750 sccm or greater, or greater, although only small amounts may be incorporated in exemplary film formations.
[0036]
[0037] Regarding silicon-containing precursors and boron-containing precursors, any number of precursors can be used in the present technology. For example, silicon-containing precursors can include any silicon-containing material, such as organosilanes, which can include silanes, disilanes, and other materials. Additional silicon-containing materials can include silicon, carbon, oxygen, or nitrogen, such as trisilylamine. Germanium-containing precursors can include germanes or any other germanium-containing precursors, such as those that additionally contain hydrogen, nitrogen, or carbon. Boron-containing materials can include boranes, such as borane, diborane, or other multi-center bonded boron materials, as well as any other boron-containing material that can be used to produce silicon and boron-containing materials. The incorporation of boron into silicon films can be based on any percentage incorporation. For example, the films produced may comprise about 5% or greater boron incorporation, and in some embodiments, about 10% or greater boron incorporation, about 15% or greater boron incorporation, about 20% or greater boron incorporation, about 25% or greater boron incorporation, about 30% or greater boron incorporation, about 35% or greater boron incorporation, about 40% or greater boron incorporation, about 45% or greater boron incorporation, about 50% or greater boron incorporation, about 55% or greater boron incorporation, about 60% or greater boron incorporation, about 65% or greater boron incorporation, about 70% or greater boron incorporation, about 75% or greater boron incorporation, about 80% or greater boron incorporation, about 85% or greater boron incorporation, about 90% or greater boron incorporation, about 95% or greater boron incorporation, or greater.
[0037]
[0038] Dopant precursors can include any precursor containing carbon, oxygen, nitrogen, sulfur, or any other dopant that can tailor the structure of the deposited film to improve transparency as well as thermal resistance. In embodiments of the present technology, any number of carbon-, nitrogen-, oxygen-, or sulfur-containing precursors can be used. In addition, combination precursors containing several of these elements can be used. For example, the oxygen-containing precursor used in some embodiments can be nitrous oxide, which can provide both oxygen and nitrogen for incorporation into the film. The dopant incorporation can be within any range, and this range can be related to the extinction coefficient. Here, the higher the dopant incorporation, the lower the extinction coefficient of the resulting film. Dopants can be selected for compatibility with other deposition precursors. For example, if silane is used as the silicon-containing precursor, the oxygen-containing dopant need not be diatomic oxygen; in some embodiments, nitrous oxide can be used. The resulting film can have one or more elements, including silicon, boron, germanium, oxygen, carbon, nitrogen, or sulfur. For example, the film may include a silicon-boron-germanium film doped with oxygen and nitrogen, or any other combination of materials.
[0038]
[0039] Dopants may be included in any amount or concentration, and may be included in the deposited film at about 1 atomic % or greater, and in some embodiments, at about 2 atomic % or greater, about 3 atomic % or greater, about 4 atomic % or greater, about 5 atomic % or greater, about 6 atomic % or greater, about 7 atomic % or greater, about 8 atomic % or greater, about 9 atomic % or greater, about 10 atomic % or greater, about 11 atomic % or greater, about 12 atomic % or greater, about 13 atomic % or greater, about 14 atomic % or greater, about 15 atomic % or greater, or greater. In some embodiments, hydrogen concentration may be minimized and limited to incorporation based on the hydrogen content in the deposition precursor. Additional hydrogen precursors, such as diatomic hydrogen, may not be included in the deposition precursor. For example, in some embodiments, the hydrogen concentration in the deposited film may be about 5 atomic % or less, and may be about 4 atomic % or less, about 3 atomic % or less, about 2 atomic % or less, about 1 atomic % or less, about 0.5 atomic % or less, or less.
[0039]
[0040] The temperature of the substrate can further affect the deposition. For example, in some embodiments, the substrate is maintained at a temperature of about 300°C or higher, and may be maintained at a temperature of about 325°C or higher, about 350°C or higher, about 375°C or higher, about 400°C or higher, about 425°C or higher, about 450°C or higher, about 475°C or higher, about 500°C or higher, about 525°C or higher, or higher. Performing deposition according to some embodiments of the present technology can reduce or limit hydrogen in the film. Increased hydrogen incorporation can increase compressive stress in the film. Thus, films according to embodiments of the present technology can be characterized by a greater tensile nature due to less hydrogen incorporation. For example, the as-deposited film can be characterized by a compressive stress of about -500 MPa or lower, which may be due in part to hydrogen incorporation. However, in some embodiments, method 200 can include steps that can further reduce hydrogen incorporation in the film. However, unlike some prior art techniques, incorporating dopants in accordance with embodiments of the present technique may reduce or limit damage from subsequent processing.
[0040]
[0041] For example, in some embodiments, the method 200 can include thermally annealing the formed material in an optional step 225 that can occur later during processing. While deposition can be performed at a first temperature, the thermal anneal can be performed at a second temperature that is higher than the first temperature. For example, the thermal anneal can be performed at a temperature of about 480°C or higher. The thermal anneal can also be performed at a temperature of about 500°C or higher, about 510°C or higher, about 520°C or higher, about 530°C or higher, about 540°C or higher, about 550°C or higher, about 560°C or higher, about 570°C or higher, about 580°C or higher, about 590°C or higher, about 600°C or higher, or higher.
[0041]
[0042] By performing a thermal anneal, the amount of hydrogen incorporated in the film can be removed through outgassing, and the compressive stress can be relieved. The film then becomes tensile in nature, and films with higher hydrogen content become more tensile during outgassing, so the film can exceed a threshold stress and crack. For example, when some conventional films with increased hydrogen content are exposed to a thermal anneal, hydrogen can be released from the film and the tensile stress can increase. The stress can increase to about 1.0 GPa or more, and can increase to about 1.1 GPa or more, about 1.2 GPa or more, about 1.3 GPa or more, about 1.4 GPa or more, about 1.5 GPa or more, about 1.6 GPa or more, or even higher, causing the film to crack. However, by utilizing dopants according to some embodiments of the present technology, the film stress following thermal annealing can be maintained at about 1.50 GPa or less, and can also be maintained at about 1.45 GPa or less, about 1.40 GPa or less, about 1.35 GPa or less, about 1.30 GPa or less, about 1.25 GPa or less, about 1.20 GPa or less, about 1.15 GPa or less, about 1.10 GPa or less, about 1.05 GPa or less, about 1.00 GPa or less, or even less.
[0042]
[0043] Additionally, as hydrogen incorporation within a film increases, this can affect film stress, as discussed above, and can further affect other film properties. For example, hard mask films are characterized by extinction coefficients for different wavelengths of light, which can affect lithography processes. Amorphous silicon materials are characterized by an extinction coefficient of approximately 0.2 for certain parameters, which can enable lithography at film thicknesses up to approximately 800 nm based on lower reflectivity. This can affect visibility through the mask. Silicon and boron films can be characterized by increased extinction coefficients for similar parameters. For example, increasing boron incorporation can increase the extinction coefficient to approximately 0.3 or greater, approximately 0.35 or greater, approximately 0.4 or greater, approximately 0.45 or greater, or even higher, while increasing hydrogen incorporation can at least partially decrease the extinction coefficient. However, increasing hydrogen incorporation can decrease selectivity and make the film more susceptible to damage during subsequent thermal processing.
[0043]
[0044] The effects of higher optical extinction coefficients include lithography challenges and the need for additional processing. For example, these increased extinction coefficients may limit lithographic field of view to film thicknesses of about 400 nm or less, about 300 nm or less, or less. However, by increasing dopant incorporation in accordance with embodiments of the present technology, the extinction coefficient at 633 nm may be reduced to about 0.35 or less, and may also be reduced to about 0.33 or less, about 0.30 or less, about 0.28 or less, about 0.25 or less, or less. This may enable lithography to be extended to thicknesses of about 400 nm or more, about 450 nm or more, about 500 nm or more, or even greater, without performing additional alignment key opening operations. Increasing the dopant concentration in accordance with the present technology may result in film structures that improve properties such as extinction coefficient and etch selectivity while maintaining or limiting hydrogen incorporation. Maintaining reduced hydrogen incorporation may result in improved thermal resistance and allow the film to maintain reduced film stress compared to conventional films.
[0044]
[0045] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.
[0045]
[0046] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. Furthermore, while a method or process may be described sequentially or in steps, it should be understood that steps may be performed simultaneously or in a different order than listed.
[0046]
[0047] Where a range of values is given, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit. Any smaller ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range in which either or both limits are included in the narrower range, or neither limit is included in the narrower range, is also encompassed within the technology and covers any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
[0047]
[0048] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes a reference to one or more layers and equivalents known to those skilled in the art, and so forth.
[0048]
[0049] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.
Claims
1. delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber; providing a dopant-containing precursor comprising one or more of carbon, nitrogen, oxygen, or sulfur along with the silicon-containing precursor and the boron-containing precursor; forming a plasma of all precursors in the processing region of the semiconductor processing chamber; depositing a silicon and boron material containing at least about 1 atomic % of dopant from the dopant-containing precursor onto a substrate disposed in the processing region of the semiconductor processing chamber; A deposition method comprising:
2. 10. The deposition method of claim 1, wherein the silicon and boron material is characterized by an extinction coefficient of about 0.3 or less at 633 nm.
3. 10. The deposition method of claim 1, wherein the hydrogen concentration in the film is maintained at about 3 atomic percent or less.
4. providing a germanium-containing precursor together with said silicon-containing precursor and said boron-containing precursor; The deposition method of claim 1 further comprising:
5. performing a thermal anneal of the silicon and boron material after said depositing. The deposition method of claim 1 further comprising:
6. The deposition method of claim 5 , wherein the thermal anneal is performed at a temperature of about 500° C. or greater.
7. 6. The deposition method of claim 5, wherein after said thermal anneal, said deposited material has a material stress of about 1.5 GPa or less.
8. The deposition method of claim 1 , wherein the silicon-containing precursor comprises silane and the boron-containing precursor comprises diborane.
9. The deposition method of claim 8 , wherein the dopant-containing precursor comprises nitrous oxide.
10. delivering a deposition precursor comprising boron, silicon, or germanium to a processing region of a semiconductor processing chamber; providing a dopant comprising carbon, nitrogen, sulfur, or oxygen to the processing region; forming a plasma of the deposition precursor and the dopant in the processing region of the semiconductor processing chamber; depositing a material incorporating the dopant, the material being characterized by an extinction coefficient at 633 nm of about 0.35 or less; A deposition method comprising:
11. annealing the deposited material to a temperature above about 500°C. The method of claim 10 further comprising:
12. 12. The deposition method of claim 11, wherein after said annealing, the material stress of the deposited material is about 1.5 GPa or less.
13. 11. The deposition method of claim 10, wherein the extinction coefficient is less than or equal to about 0.30 at 633 nm.
14. The deposition method of claim 13 , wherein the dopant is incorporated into the film at about 2 atomic % or greater.
15. The deposition method of claim 10 wherein at least two dopants are incorporated into the film.
16. The deposition method of claim 10 , wherein the deposited material comprises silicon, boron, and germanium.
17. delivering at least one of a silicon-containing precursor, a boron-containing precursor, and a germanium-containing precursor to a processing region of a semiconductor processing chamber; providing a dopant-containing precursor comprising one or more of carbon, nitrogen, oxygen, or sulfur to the processing region of the semiconductor processing chamber; forming a plasma of all precursors in the processing region of the semiconductor processing chamber; depositing a doped material containing at least about 1 atomic % of dopant from the dopant-containing precursor onto a substrate disposed in the processing region of the semiconductor processing chamber; A deposition method comprising:
18. performing a thermal anneal of the silicon and boron material at a temperature of about 400° C. or greater after the depositing. The deposition method of claim 17 further comprising:
19. 20. The deposition method of claim 18, wherein after performing the annealing, the material stress of the deposited material is about 1.5 GPa or less.
20. 20. The deposition method of claim 17, wherein the doped material has an extinction coefficient of about 0.30 or less at 633 nm.