Spatial and temporal control of ion bias voltage for plasma processing

Abstract

Systems, methods, and apparatus for modifying a plasma processing environment using a power supply SOLUTION: Systems and methods for plasma processing are disclosed. Exemplary systems may include a plasma processing chamber including a source for producing a plasma within the processing chamber and at least two bias electrodes arranged within the plasma processing chamber for controlling a plasma sheath proximate the bias electrodes. A chuck is disposed to support the substrate and a source generator is coupled to the plasma electrode. At least one bias supply is coupled to the at least two bias electrodes, and a controller is included for controlling the at least one bias supply to control a plasma sheath proximate the bias electrodes.SELECTED DRAWING: None

Description

[Technical Field]

[0001] (Claim of priority under 35 U.S.C. §119) This application for patent is entitled "SPATIAL AND TEMPORAL CONTROL This application claims priority to Provisional Application No. 62 / 588,224, entitled "A METHOD FOR USE IN A HIGH-TEMPERATURE ION BIAS VOLTAGE FOR PLASMA PROCESSING," filed November 17, 2017, which is assigned to the assignee of the present application and expressly incorporated herein by reference.

[0002] The present disclosure relates generally to plasma processing, and more particularly, but not by way of limitation, to systems, methods, and apparatus for modifying a plasma processing environment using a power supply. [Background technology]

[0003] A challenge for plasma processing chambers is controlling the uniformity of the plasma sheath above the substrate, particularly around the edge of the substrate. Discontinuities caused by the edge of the substrate, edges of buried electrical planes, insulating rings, and other chamber-related artifacts can affect the sheath uniformity, which can change the trajectories of ions relative to the substrate, and as a result, the processing of the substrate can be adversely affected.

[0004] Previous attempts have used physical changes to substrate holders, chamber shapes, and other physical geometries to try to mitigate these challenges, but these approaches are static, inflexible, and otherwise inadequate. Summary of the Invention [Means for solving the problem]

[0005] One aspect can be characterized as a system for plasma processing. The system includes a plasma processing chamber including a source for providing a plasma within the processing chamber, at least two bias electrodes arranged within the plasma processing chamber to control a plasma sheath adjacent to the bias electrodes, and a chuck positioned to support a substrate. The system also includes at least one bias source coupled to the at least two bias electrodes, and a controller for controlling the at least one bias source to apply an asymmetric periodic voltage waveform to each of the at least two bias electrodes and to control the plasma sheath adjacent to the bias electrodes.

[0006] Another aspect may be characterized as a method for processing a substrate in a plasma processing chamber, the method including generating a plasma in the plasma processing chamber, applying an asymmetric periodic voltage waveform to each of a plurality of zones in the plasma processing chamber using a corresponding plurality of bias sources, and adjusting one or more characteristics of the asymmetric periodic voltage waveform to modify a corresponding portion of the plasma sheath. The present invention provides, for example, the following items. (Item 1) 1. A system for plasma processing, the system comprising: 1. A plasma processing chamber comprising: a source for providing a plasma within the processing chamber; at least two bias electrodes, the at least two bias electrodes arranged within the plasma processing chamber to control a plasma sheath adjacent to the bias electrodes; a chuck positioned to support the substrate; a plasma processing chamber including: at least one bias source coupled to the at least two bias electrodes; a controller, the controller controlling the at least one bias supply to apply an asymmetric periodic voltage waveform to each of the at least two bias electrodes and to control the plasma sheath adjacent to the bias electrodes; A system comprising: (Item 2) Item 10. The system of item 1, wherein the source includes at least one of a remote plasma source or a source generator. (Item 3) 2. The system of claim 1, wherein the chuck is positioned between the plasma sheath and the at least two bias electrodes to enable the at least two bias electrodes to modify a portion of the sheath that affects at least one of ion trajectories or spatial distribution of ion energy relative to the substrate. (Item 4) Item 4. The system of item 3, wherein a portion of one of the at least two bias electrodes is positioned along the edge of the chuck to modify a portion of the sheath to affect at least one of ion trajectories or spatial distribution of ion energy relative to the edge of the substrate. (Item 5) The controller a monitoring circuit for measuring at least one characteristic of the power applied by the at least one bias supply; a chamber analysis component configured to determine a characteristic of an environment within the plasma processing chamber based on a measured characteristic of the power obtained from the monitoring circuit; and a control circuit that adjusts the power applied by the at least one bias supply and controls the plasma sheath adjacent to the bias electrode; Item 1. The system according to item 1, comprising: (Item 6) 6. The system of claim 5, wherein the chamber analysis component is configured to calculate a sheath capacitance of the plasma sheath proximate the bias electrode, and the control circuit is configured to adjust at least one characteristic of the applied power to adjust the sheath capacitance. (Item 7) Item 6. The system of item 5, wherein the controller includes at least one of an integrated controller integrated within the at least one bias supply source or a system controller that controls multiple components of the plasma processing system. (Item 8) Item 10. The system of item 1, including a source generator coupled to the plasma electrode. (Item 9) Item 3. The system of item 2, wherein the source generator is an RF generator. (Item 10) 1. A method for processing a substrate in a plasma processing chamber, the method comprising: generating a plasma in the plasma processing chamber; applying an asymmetric periodic voltage waveform to each of a plurality of zones within the plasma processing chamber using a corresponding plurality of bias sources; adjusting one or more characteristics of the asymmetric periodic voltage waveform to modify a corresponding portion of the plasma sheath; A method comprising: (Item 11) Item 11. The method of item 10, comprising applying the asymmetric periodic voltage waveform to each of a plurality of zones positioned proximate to a substrate within the plasma processing chamber. (Item 12) Item 11. The method of item 10, comprising applying at least one of the asymmetric periodic voltage waveforms to an area corresponding to an edge of the substrate. (Item 13) Item 13. The method of item 12, comprising applying the asymmetric periodic voltage waveform to an area corresponding to an edge of the substrate to suppress the density of the plasma adjacent to the edge of the substrate. (Item 14) Item 11. The method of item 10, comprising coupling the at least one source generator and one of the bias sources to a common electrode. (Item 15) Item 11. The method of item 10, comprising adjusting an asymmetric periodic voltage waveform to one or more upper sections to modify corresponding one or more portions of a plasma sheath proximate a top plate of the plasma processing chamber. (Item 16) measuring a characteristic of the asymmetric periodic voltage waveform applied to one or more of the areas by one or more of the bias sources; calculating a characteristic of an environment within the plasma processing chamber based on the measured characteristic of the power; adjusting the asymmetric periodic voltage waveform applied by the at least one bias source to control the plasma sheath adjacent the one or more regions; Item 11. The method according to item 10, comprising: (Item 17) 1. A non-transitory computer readable medium having instructions stored thereon, the instructions for execution by a processor or for configuring a field programmable gate array to perform a plasma process, the instructions comprising: controlling at least one of a remote plasma source or a source generator to generate a plasma in the plasma processing chamber; controlling a plurality of bias sources to apply an asymmetric periodic voltage waveform to each of a plurality of zones within the plasma processing chamber; controlling one or more of the plurality of bias sources to adjust one or more characteristics of the asymmetric periodic voltage waveform to modify a corresponding portion of the plasma sheath; A non-transitory computer-readable medium comprising instructions for performing [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a schematic diagram depicting a plasma processing system with multiple bias zones.

[0008] [Figure 2] FIG. 2 depicts another plasma processing system with multiple bias zones.

[0009] [Figure 3] FIG. 3 depicts yet another plasma processing system with multiple bias zones.

[0010] [Figure 4] FIG. 4 depicts another plasma processing system with multiple bias zones.

[0011] [Figure 5] FIG. 5 is a flowchart depicting a method that may be considered in connection with embodiments disclosed herein.

[0012] [Figure 6] FIG. 6 is a diagram depicting aspects of an exemplary control system.

[0013] [Figure 7] FIG. 7 is a schematic diagram depicting a side view of an exemplary bias supply.

[0014] [Figure 8] FIG. 8 includes a graph of the voltage waveform output from the bias supply, a graph of the corresponding sheath voltage, and a corresponding switch timing diagram.

[0015] [Figure 9] FIG. 9 is a graph depicting an example bias source waveform and example voltage values.

[0016] [Figure 10]Figure 10A depicts an implementation using two voltage sources to provide voltages to the bias supply depicted in Figure 7. Figure 10B depicts another implementation using two voltage sources to provide voltages to the bias supply depicted in Figure 7. Figure 10C depicts yet another implementation using two voltage sources to provide voltages to the bias supply depicted in Figure 7.

[0017] [Figure 11] Figure 11A depicts an implementation using three voltage sources to provide voltages to the bias supplies depicted in Figure 7. Figure 11B depicts another implementation using three voltage sources to provide voltages to the bias supplies depicted in Figure 7. Figure 11C depicts yet another implementation using three voltage sources to provide voltages to the bias supplies depicted in Figure 7.

[0018] [Figure 12] FIG. 12 is a diagram depicting aspects of an exemplary bias supply associated with a control system.

[0019] [Figure 13] FIG. 13 is a block diagram depicting an exemplary computing device. DETAILED DESCRIPTION OF THE INVENTION

[0020] The present disclosure generally describes systems, methods, and apparatus for controlling the uniformity and intensity of a capacitively (or inductively) coupled plasma, both spatially and temporally.

[0021] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, any reference herein to any prior publication (or information derived therefrom) or any matter that is publicly known is not an admission or acknowledgement, or in any way implied, that the prior publication (or information derived therefrom) or known matter is conventional, routine, or forms part of the common general knowledge in the field of endeavor to which this specification pertains.

[0022] By way of preamble, the flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, some blocks in these flowcharts or block diagrams may represent modules, segments, or portions of code, comprising one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may, in fact, be executed substantially in parallel, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system or a combination of dedicated hardware and computer instructions that performs the specified functions or acts.

[0023] While the use cases in the following disclosure involve wafer plasma processing, implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to effect surface modification, sub-surface modification, deposition, or removal by physical or chemical means.

[0024] The present disclosure may, but need not, utilize plasma processing and substrate bias techniques such as those disclosed in US9287092, US9287086, US9435029, US9309594, US9767988, US9362089, US9105447, US9685297, and US9210790, the entire contents of which are incorporated herein by reference.

[0025] For purposes of this disclosure, an "excitation source," "source generator," "RF source," or "RF power source" is one whose energy is primarily directed to generating and sustaining a plasma, while a "bias source" is one whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma. The frequencies of the source generator and bias source vary depending on various factors (e.g., application-specific factors), but in many embodiments, the source generator operates at frequencies of 13.56 MHz and above, and the bias source operates at frequencies below 2 MHz (e.g., without limitation, 2 MHz to 400 kHz). In other embodiments, it is contemplated that the source source frequency may be below 13.56 MHz and the bias source may operate at frequencies above 2 MHz. In many applications, the source source frequency exceeds the bias source frequency.

[0026] 1-4 each depict an exemplary plasma processing system including a generally cylindrically symmetric plasma processing chamber 100 with an upper electrode 285 (e.g., a cathode) and a lower (substrate) electrode 275 (e.g., an anode) of similar areas. This simplification of the geometry of the plasma processing chamber 100 is for ease of explanation but should not be a limitation on various implementations of the present disclosure. For example, the plasma processing chamber 100 may have a shape other than cylindrical (e.g., the processing chamber 100 may have a rectangular shape) and may not be symmetrical. In other embodiments, the upper and lower electrodes 285, 275 may not have the same shape and / or size.

[0027] 1-4 also depict the electrodes 275, 285 as insulators with the electrical surfaces 245, 249, 255 embedded therein. However, in other embodiments, the electrodes 275, 285 may comprise a conductive material or a metal with an insulating coating. More generally, the electrodes 275, 285 can be implemented as any structure capable of capacitively coupling energy to a plasma (upper electrode 285) or capacitively generating a bias voltage on the surface of the substrate 200 (lower electrode 275). While FIGS. 1-4 depict RF power from a source generator being capacitively coupled to the plasma in the plasma chamber 100, it should be appreciated that RF energy can also (or alternatively) be inductively coupled from the source generator 300 to the plasma processing chamber 100. Thus, the energy coupling component may be an inductive element (e.g., a coil) instead of the electrical surface 255. In some embodiments, instead of or in addition to utilizing a source generator (e.g., a source generator), the plasma is provided to the plasma chamber by a remote plasma source.

[0028] Substrate 200 is any object or item, and in some cases may be a surface, that is treated with a plasma to effect surface alteration, subsurface alteration, deposition, or removal by physical or chemical means.

[0029] FIG. 1 illustrates a plasma processing chamber 100 with an upper electrode 285 powered by a source generator 300 (also referred to as an "RF source") connected by a cable 475 or other conductor through a match 350 to an energy coupling component (e.g., a buried electrical plane 255). The upper electrode 285 is insulated from the body of the plasma processing chamber 100 by an insulating ring 105. The inner wall of the vacuum chamber is insulated from the plasma potential, in this example, by an insulating cylinder 107. RF excitation from the upper electrode 285 is used to generate, maintain, and control the plasma density. A substrate 200 is shown positioned on a lower electrode 275. This electrode 275 is insulated from the plasma chamber by an insulating ring 110. This embodiment includes two bias supplies 402, which may each include a DC power supply unit (PSU) 450 and an eV switch 400.

[0030] A challenge for plasma processing chambers is controlling the uniformity of the plasma sheath above the substrate 200, particularly around the edge of the substrate. Discontinuities caused by the substrate edge, the edge of buried electrical surfaces, the insulating ring 110, and other chamber-related artifacts can affect the sheath uniformity and, therefore, the processing uniformity of the substrate. Prior attempts have used physical variations in the substrate holder, chamber shape, and other physical geometries to attempt to mitigate these challenges. Additionally, many prior approaches operate with a symmetric (e.g., sinusoidal) output (e.g., the first half-cycle of the waveform has a corresponding symmetric component in the last half-cycle of the waveform). However, applying a sinusoidal waveform to the substrate induces a wide distribution of ion energy, which limits the ability of the plasma process to execute a desired etch profile. The present disclosure addresses these non-uniformities and deficiencies using a more dynamic and flexible approach.

[0031] Generally, FIG. 1 depicts multiple bias sources 402, each coupled to a corresponding electrical surface to form multiple zones (also referred to herein as bias zones) within the plasma processing chamber 100. While FIG. 1 depicts two zones, it should be appreciated that embodiments may include many more than two zones. As shown in FIG. 1, one of the bias sources 402 is coupled to the center electrical surface 249, and another bias source 402 is connected to the outer buried electrical surface 245. Each bias source 402 can be controlled independently from the other bias sources. The use of two buried surfaces 245, 249 and two bias sources 402 allows for non-uniform biasing across the electrode 275. For example, a higher bias can be applied to the outer buried surface 245 than to the center buried surface 249, or vice versa. Alternatively, different pulsing regimes can be applied to each buried surface 245, 249. Although a non-uniform bias may be applied, the result may be a uniform surface potential on the substrate 200. In other words, the present multiple buried surface method can be used to mitigate non-uniformities in the plasma, substrate, etc., thereby achieving a uniform plasma sheath above the substrate.

[0032] The duty cycles of the two bias sources may also be varied (while running the bias sources 402 at the same voltage) to compensate for different process rates due to non-uniformity effects in the plasma system. Alternatively, the bias sources 402 may be run at different voltages (between the bias sources) or a combination of both different duty cycles and different voltages to produce the desired process uniformity. Additional subdivision of the buried electrical planes and corresponding bias sources may also be utilized (e.g., two or more buried planes and corresponding bias sources 402 can be implemented). While separate bias sources 402 are shown, in practice these may be integrated into one unit with different outputs but a common DC voltage source (e.g., a single DC power supply unit feeding two or more eV switches). Furthermore, the output of the eV sources may be divided between the different buried electrical planes using a voltage divider.

[0033] 2 illustrates a further variation of the embodiment shown in FIG. 1. In this case, rather than being arranged below the outer edge of the substrate 200, the outer buried electrode 245 is arranged, at least in part, directly beneath the insulator ring 110. This allows for control of the bias and plasma sheath uniformity above the insulator ring 110. In some cases, the bias applied by the bias source 402 can be controlled to either eliminate RF plasma-induced bias above the insulator ring 110 and avoid treating the insulator ring 110 as a process consumable, or conversely, to enhance plasma treatment of the insulator ring 110.

[0034] Figure 3 illustrates yet another variation of the embodiment shown in Figure 2. In this case, an outer buried electrode 245 is inside the insulator ring 110 and controls the bias and sheath uniformity above the insulator ring 110. In some cases, the bias applied by the bias source can be controlled to either eliminate RF plasma-induced bias and avoid treating the insulator ring 110 as a process consumable, or conversely, enhance plasma treatment of the insulator ring 110.

[0035] FIG. 4 illustrates an embodiment in which one or more bias sources 402 are coupled to one or more top electrodes and one or more RF sources are coupled to the bottom electrode (through a matching network 350) along with another one or more bias sources 402. Filters that may be required to isolate the bias sources 402 and the source generator 300 are not shown but can be implemented by one skilled in the art. By varying the duty cycle and / or voltage level of the eV source, the plasma uniformity can be modified to affect the processing uniformity of the substrate. The material of the top electrode 285 may be used in the processing of the substrate, and therefore, by controlling the bias level of the bias source 402 in amplitude, time, uniformity, or a combination thereof, the processing uniformity and rate of the substrate 200 may be controlled. It may be desirable to suppress the RF-induced ion bias voltage above the surface of the top electrode 285, in which case the bias source 402 coupled to the electrical surfaces 257, 259 in the top electrode 285 can be used to null this bias voltage. If the RF induced voltage is non-uniform, multiple bias sources 402 (eg, two or more bias sources 402) can be used to counter these non-uniformities.

[0036] In another embodiment, one or more of the bias sources 402 may be pulsed and / or have their voltage modulated in synchronization with the pulsing and / or voltage changes of the source generator 300. For example, during the period in which one or more of the bias sources 402 reduces the bias voltage from a first bias voltage to a second bias voltage, the source generator 300 may pulse its output, reduce its voltage, or both pulse and reduce its voltage output.

[0037] These concepts should not be limited to the illustrated number of bias sources 402 and source generators 300. Rather, many sources (e.g., many bias sources 402 and many source generators 300) can be used, for example, if complex region-specific control of plasma density (e.g., to achieve plasma density uniformity) is desired. Also, it should be understood that the number of sources need not match the number of electrodes. For example, to give two non-limiting examples, four source generators 300 could drive three electrodes, or two source generators could drive five electrodes. Furthermore, each source may have a corresponding matching network, or a single matching network may be coupled to and impedance-matched to two or more sources. When two or more electrodes are coupled to one or more bias sources 402, the electrodes can be symmetric (e.g., concentric rings) or asymmetric (e.g., to account for asymmetries in the substrate and / or chamber).

[0038] Furthermore, if more than one bias source 402 is implemented, each bias source can be used to determine the localized ion current (and therefore ion energy and ion density) and the localized sheath capacitance.

[0039] The ion current I1 can be given as: [ka] where C1 represents the specific capacitance of components associated with the chamber, which may include the insulator, substrate, substrate support, and e-chuck.

[0040] Sheath capacitance C sheath may be given as: [ka]

[0041] The multiple bias sources 402 and their corresponding ability to measure ion current, and therefore ion density, at different locations within the chamber can be utilized as feedback for the bias sources 402 and / or the source generator 300. Also, sheath capacitance may be calculated and utilized as a parameter value to control the sheath capacitance and affect the plasma sheath. Alternatively, or in addition, this feedback can be used to control any electrical and / or mechanical feature of the processing chamber 100 or the source 300, 402. Alternatively, or in addition, this feedback can be used to control any one or more of the following: magnets of the plasma processing chamber 100 (e.g., magnets used to confine or shape the plasma or magnets used to direct ions generated via a microwave plasma source), pressure control (e.g., pressure valves), mass flow control, gas flow control, gas chemistry control, and the physical geometry of the chamber or components therein (e.g., vertical movement of a grounded silicon cap or lid). It should be further understood that a detailed description of various known RF sources (e.g., capacitive, inductive, microwave, etc.) is not appropriate here as these are well known in the art, however, the feedback and synchronization described herein is applicable to any known RF source.

[0042] Referring now to FIG. 5, shown is a flowchart depicting a method that may be considered in connection with some embodiments disclosed herein. The method includes providing a plasma processing chamber with a plurality of zones (block 500). As described with reference to FIGS. 1-4, each of the zones may be associated with a corresponding electrical surface. For example, each of electrical surfaces 245, 249, 250, 257, and 259 may establish a corresponding zone (when a periodic voltage waveform is applied from bias source 402) to affect a portion of a sheath of a plasma established in plasma processing chamber 100. Additionally, a substrate 200 is placed in plasma processing chamber 100 (block 502), and a plasma is generated in plasma processing chamber 100 using a source generator (block 504). As shown, a bias waveform (e.g., an asymmetric periodic voltage waveform) is applied to each of the plurality of zones (block 506), and one or more characteristics of the environment of plasma processing chamber 100 are monitored (block 508). Monitoring the one or more characteristics may be implemented by sensors or probes within the plasma processing chamber and / or by monitoring (outside the plasma processing chamber) one or more aspects of the power applied by the bias source 402 or the source generator 300. In response to the monitoring (block 508), the bias waveform (e.g., an asymmetric periodic voltage waveform) applied by one or more of the multiple zones is adjusted (block 510).

[0043] 6, shown are aspects of an exemplary control system that may be used in connection with embodiments herein. Also shown are representations of sheath capacitance (Csheath) and capacitance C1, which represents the inherent capacitance of components associated with plasma processing chamber 100, which may include the insulator, substrate, substrate support, and e-chuck.

[0044] As shown, the current and / or voltage may be measured (block 508) by the controller 660 to indirectly monitor one or more characteristics of the environment of the plasma processing chamber 100. An example characteristic of the environment of the plasma processing chamber 100 may be the sheath capacitance (Csheath), which may be calculated using Equation 2 using the measured output voltage Vout.

[0045] Monitoring (block 508) may be performed prior to processing a substrate to obtain stored data (e.g., about sheath capacitance and / or other characteristics of the plasma processing chamber environment), and the data is then utilized to adjust the bias waveform (block 510) (e.g., in a feedforward manner). The monitoring in block 508 may also be performed during plasma processing, and the adjustment in block 510 (e.g., by adjusting the voltage and / or duty cycle of the bias supply 602) may be made using real-time feedback using voltage and / or current measurements, for example, as shown in FIG.

[0046] Referring now to FIG. 7 , shown is a general representation of an exemplary bias supply 702 that can be used to implement bias supplies 402, 602. As shown, bias supply 702 utilizes three voltages, V1, V2, and V3. Because output Vout is capacitively coupled through the C-chuck, controlling the DC level of Vout is generally not necessary; the three voltages can be reduced to two by selecting one of V1, V2, or V3 to be ground (0 V). A separate chuck supply may be used, and therefore controlling the DC level of Vout is not necessary. If a separate chuck supply is not used, all three voltages can be controlled to control the DC level of Vout. Although not shown for clarity, two switches S1 and S2 may be controlled by a switch controller via electrical or optical connections to enable the switch controller to open and close switches S1 and S2, as disclosed below. The depicted switches S1, S2 may be realized by single-pole, single-throw switches, and as a non-limiting example, the switches S1, S2 may be realized by silicon carbide metal oxide field effect transistors (SiC MOSFETs).

[0047] In this implementation, voltages V1, V2, and V3 may be DC source voltages. As shown, a first switch S1 is arranged to switchably connect a first voltage V1 to the output Vout through an inductive element, and a second switch S2 is arranged to switchably couple a second voltage V2 to the output Vout through an inductive element. In this implementation, the two switches connect to a common node 670, and a common inductive element L1 is arranged between the common node and the output node Vout. Other arrangements of inductive elements are also possible. For example, there may be two separate inductive elements, one connecting S1 to Vout and another connecting S2 to Vout. In another embodiment, one inductive element may connect S1 to S2, and another inductive element may connect either S1 or S2 to Vout.

[0048] While referring to FIG. 7, reference is simultaneously made to FIG. 8, which depicts 1) cycles of the asymmetric periodic voltage waveform of bias source 702 output at Vout, 2) the corresponding sheath voltage, and 3) the corresponding switch positions of switches S1 and S2. As shown, the periodic voltage waveform output by bias source 702 is asymmetric, such that the first half-cycle of the voltage waveform does not have a corresponding symmetric component during the last half-cycle of the voltage waveform. In operation, the first switch S1 is momentarily closed along a first portion 860 of the voltage waveform (between voltages V0 and Va) to increase the level of the voltage at output node Vout to a first voltage level Va. Level Va is maintained along a second portion 862 of the waveform. The second switch S2 is then momentarily closed along a third portion 864 of the waveform to decrease the level of the voltage waveform at output node Vout to a second voltage level Vb. Note that S1 and S2 are open except for a brief period of time. As shown, the negative voltage swing along the third portion 864 affects the sheath voltage (Vsheath), and therefore the magnitude of Va-Vb can be controlled to affect the sheath voltage.

[0049] In this embodiment, while the first and second switches S1, S2 are open, a third voltage V3 is applied to the output node Vout through the second inductive element L2, further decreasing the level of the voltage at the output node Vout along a fourth portion 866 of the voltage waveform. As shown in FIG. 8, a negative voltage ramp along the fourth portion 866 can be established to maintain the sheath voltage by compensating for ions impacting the substrate.

[0050] Thus, S1 momentarily connects and then disconnects a first voltage V1 to the output Vout through the first inductive element L1, and after a period of time, S2 connects and then disconnects a second voltage (e.g., ground) to the output Vout through the first inductive element L1. A third voltage V3 is coupled to the output Vout through the second inductive element L2. In this implementation, the first voltage V1 may be higher than the third voltage V3, and the momentary connection and disconnection of the first voltage V1 to the output Vout increases the voltage of the output Vout to a first voltage level Va along the first portion 860 of the voltage waveform, which is sustained along the second portion of the waveform 862. The first voltage level Va may exceed the first voltage V1, and the second voltage V2 (e.g., ground) may be less than the first voltage level Va. The momentary connection and then disconnection of the second voltage V2 causes the voltage of the output to decrease in the third portion 864 to a second voltage level Vb that is below the second voltage V2 (eg, ground).

[0051] As an example, as shown in Figure 9, V1 may be -2,000 VDC, V2 may be ground, V3 may be -5,000 VDC, V0 may be -7,000 VDC, Vb may be -3,000 VDC, and Va may be 3,000 VDC. However, these voltages are merely exemplary to provide context for the relative magnitudes and polarities of the voltages described with reference to Figures 7 and 8.

[0052] 10A-10C, shown are possible arrangements of two DC voltage sources for providing the voltages V1, V2, and V3 depicted in FIGS. 7 and 9. In FIG. 10A, V2 is grounded and forms a common node between the two DC voltage sources. In FIG. 10B, V1 is grounded and V2 forms a common node between the DC voltage sources. Also, in FIG. 10C, V1 is grounded and forms a common node between each of the two DC voltage sources.

[0053] In some embodiments, as shown in Figures 11A, 11B, and 11C, three DC voltage sources may be utilized to apply three voltages V1, V2, and V3. As shown in Figure 11A, each of the three DC voltage sources may be coupled to ground, with each of the three DC voltage sources providing a corresponding one of V1, V2, and V3. In Figure 11B, one of the DC voltage sources is grounded, and the three DC voltage sources are arranged in series. In Figure 11C, one of the DC voltage sources is disposed between ground and V2, and each of the DC voltage sources is coupled to V2.

[0054] 12, shown is an exemplary bias supply 1202 that can be used to implement bias supplies 402, 602. As shown, bias supply 1202 includes a switch controller 1204 and two voltage sources to provide a first voltage V1, a second voltage V2, and a third voltage V3. While not shown for clarity, two switches S1 and S2 are coupled to switch controller 1204 (e.g., via electrical or optical connections) to enable switch controller 1204 to open and close switches S1, S2, as disclosed below. The depicted switches S1, S2 may be implemented by single-pole, single-throw, normally-open switches that are controllable by electrical or optical signals. As a non-limiting example, switches S1, S2 may be implemented by silicon carbide metal oxide field-effect transistors (SiC MOSFETs).

[0055] Also shown is an exemplary controller 1260, which may be implemented within the housing of each bias supply or may be implemented as part of a centralized tool controller. As shown, controller 1260 is coupled to receive information (e.g., voltage and / or current information) indicative of the power applied by bias supply 1202 at the bias supply output Vout. As shown, controller 1260 is also coupled to switch controller 1204 and two DC voltage sources to enable controller 1260 to control bias supply 1202 (e.g., control the plasma sheath adjacent to the bias electrode).

[0056] Additionally, the controller 1260 includes a monitoring circuit 1270 for measuring at least one characteristic of the power applied by the bias supply 1202 and a chamber analysis component 1272 configured to calculate a characteristic of the environment within the plasma processing chamber 100 based on the measured characteristic of the power obtained from the monitoring circuit 1270. Also shown within the controller 1260 is a control circuit 1274 for regulating the power applied by the bias supply 1202 and controlling the plasma sheath adjacent to the bias electrode. While the controller 1260 and the switch controller 1204 are depicted in FIG. 12 as separate structures, it should be appreciated that the controller 1260 and the switch controller 1204 may be integrated and / or share common underlying components. For example, the controller 1260 and the switch controller 1204 may be collocated on the same printed circuit board. As another example, the controller 1260 and the switch controller may be implemented by a system including an architecture similar to or identical to the computing device depicted in FIG. 13.

[0057] The monitoring circuit 1270 may include one or more sensors, such as a directional coupler, a VI sensor, a phase and gain sensor, a voltage sensor, and a current sensor. Those skilled in the art will understand that the measured characteristic of the power can include voltage, current, phase, and power. Additionally, the monitoring circuit 1270 may include an analog-to-digital conversion component to convert an analog signal from the sensor into a digital representation of the measured characteristic of the power. In other implementations, the sensor is separate from the controller 1260, and the monitoring circuit 1270 includes an analog-to-digital conversion component to convert an analog signal from the sensor into a digital representation of the measured characteristic of the power. In yet other implementations, the sensor may include a sensing element and an analog-to-digital conversion component, and the monitoring circuit 1270 may receive the digital representation of the characteristic of the power. Monitoring one or more characteristics of the environment of the plasma processing chamber may include measuring (using the monitoring circuit 1270) at least one characteristic of the power applied by at least one bias supply source.

[0058] The chamber analysis component 1272 is generally configured to determine characteristics of the environment within the plasma processing chamber based on measured characteristics of the power obtained from the monitoring circuitry 1270. Although the power may be measured (by the monitoring circuitry 1270) at a location external to the plasma processing chamber 100, the measured power characteristics may be used to calculate characteristics of the environment within the plasma processing chamber 100. For example, using Equation 1, the ion current in a region proximate to the bias zone may be calculated using a measurement of the voltage at Vout associated with C1. As another example, using Equation 2, the sheath capacitance in a region proximate to the bias zone may be calculated.

[0059] The control circuit 1274 generally operates to adjust the power applied by the bias source and to adjust aspects of the environment within the plasma processing chamber 100. For example, the plasma sheath adjacent to a zone (established by the bias source 1202) may be adjusted, and / or the ion current may also be adjusted. As shown, the controller 1260 may be coupled to the DC voltage source and switch controller 1204; thus, with reference to FIG. 8, the controller 1260 may be used to adjust the voltage V, the voltage V, t1, T, and the slope of the fourth portion 866. As discussed with reference to FIG. 8, the voltage of the plasma sheath adjacent to the bias zone associated with the bias source 1202 may be adjusted.

[0060] 12, in this implementation (incorporating the embodiment depicted in FIG. 10A), the second voltage V2 is provided at a node coupled to two DC voltage sources and coupled to ground, although in other implementations (e.g., as described above with reference to FIGS. 10B and 10C), the second voltage V2 need not be grounded. As shown, a first switch S1 is arranged to switchably connect the first voltage V1 to a common node 770 (common to S1 and S2), and a second switch S2 is arranged to switchably couple the second voltage V2 to the common node 770. In addition, a first inductive element L1 is arranged between the common node and the output node Vout.

[0061] In operation, the switch controller 1204 is configured to close the first switch S1 along a first portion 860 of the voltage waveform (between voltages V and V) to increase the level of the voltage at the output node V to a first voltage level V that is maintained along a second portion 862 of the waveform, and then the first switch S1 is opened. The switch controller 1204 then closes the second switch S2 along a third portion 864 of the waveform to decrease the level of the voltage waveform at the output node V to a second voltage level V, and then the switch controller 704 opens the second switch S2, so that S1 and S2 are open. As shown, the negative voltage swing along the third portion 864 affects the sheath voltage (V), and thus the magnitude of V can be controlled to affect the sheath voltage in close proximity to the electrode surface coupled to V. Those skilled in the art will appreciate that in this implementation, Vb is controllable by controlling V1, but Vb is not equal to V1 due to the effect of inductor L1.

[0062] In this embodiment, the second voltage source applies a third voltage V3 through the second inductive element L2 to the output node Vout while at least the first and second switches S1, S2 are open, functioning as an ion compensation component to further reduce the level of the voltage waveform at the output node Vout along a fourth portion 866 of the periodic asymmetric voltage waveform. As shown in FIG. 8 , a negative voltage ramp along the fourth portion 866 can be established to maintain the sheath voltage by compensating for ions impinging on the substrate.

[0063] Thus, S1 momentarily connects and then disconnects a first voltage V1 to the output Vout through the first inductive element L1, and after a period of time, S2 connects and then disconnects a second voltage (e.g., ground) to the output Vout through the first inductive element L1. A third voltage V3 is coupled to the output Vout through the second inductive element L2. In this implementation, the first voltage V1 may be higher than the third voltage V3, and the momentary connection and disconnection of the first voltage V1 to the output Vout increases the voltage of the output Vout to a first voltage level Va along the first portion 860 of the voltage waveform, which is sustained along the second portion of the waveform 862. The first voltage level Va may exceed the first voltage V1, and the second voltage V2 (e.g., ground) may be less than the first voltage level Va. The momentary connection and then disconnection of the second voltage V2 causes the voltage of the output to decrease in the third portion 864 to a second voltage level Vb that is below the second voltage V2 (eg, ground).

[0064] In some embodiments, one or more bias sources can be used to measure ion density, sheath capacitance, or other chamber parameters with or without a reference substrate in the chamber. One or more processing steps can be performed, and then the measurements can be repeated. In this way, changes in the chamber can be monitored.

[0065] When a silicon top lid is used, one or more bias sources 402, 602, 702, 1202 can be used to monitor local ion density and / or other chamber parameters. Silicon top lids (also referred to as silicon vacuum seals) are typically consumables, but may not consume in a uniform manner. Using multiple bias sources 402, 602, 702, 1202 to measure local plasma characteristics can provide a means for inferring non-uniform changes in the silicon vacuum seal. This feedback over time can be used to adjust the RF source 300 and / or bias sources 402, 602, 702, 1202 to account for time-varying non-uniformities in the silicon vacuum seal. Additionally, this feedback can be used to determine when the silicon vacuum seal should be replaced. In another embodiment, one or more bias sources 402, 602, 702, 1202 can be coupled to an electrode adjacent to the silicon vacuum seal (e.g., at the top of the chamber). Because the bias source 402, 702, 1202 can be used to modify or even eliminate the plasma sheath, the present top-mounted bias source 402, 602, 702, 1202 can be used to minimize or even eliminate the plasma sheath between the silicon vacuum seal and the plasma. In this way, erosion or consumption of the silicon vacuum seal can be reduced compared to current processes.

[0066] Along these lines, each bias supply 402, 602, 702, 1202 and corresponding electrode may be arranged at various locations in the processing chamber to locally control the plasma sheath, thereby reducing or eliminating ion bombardment on certain regions or components of the chamber. Ion density and sheath capacitance, and their local variations, may be used to monitor chamber cleanliness. For example, a change in local ion density over time may indicate that a local chamber surface is accumulating one or more films. In another embodiment, multiple spatially distributed electrostatic chuck voltages may be used to affect the local ion density.

[0067] The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor-executable code encoded in a non-transitory, tangible, processor-readable storage medium, or in a combination of the two. For example, referring to FIG. 13 , shown is a block diagram depicting physical components that may be utilized to implement the control aspects of the source generator 300 and bias supplies 402, 602, 702, 1202, according to an exemplary embodiment. As shown, in this embodiment, a display portion 1312 and non-volatile memory 1320 are coupled to a bus 1322, which is also coupled to a random access memory (“RAM”) 1324, a processing portion (including N processing components) 1326, a field programmable gate array (FPGA) 1327, and a transceiver component 1328 including N transceivers. While the components depicted in FIG. 13 represent physical components, FIG. 13 is not intended to be a detailed hardware diagram; thus, many of the components depicted in FIG. 13 may be realized by a common structure or distributed among additional physical components. Furthermore, it is contemplated that other existing and yet to be developed physical components and architectures may be utilized to implement the functional components described with reference to FIG.

[0068] The display portion 1312 generally operates to provide a user interface for a user, and in some implementations, the display is realized by a touchscreen display. Generally, the non-volatile memory 1320 is a non-transitory memory that functions to store (e.g., persistently store) data and processor-executable code (including executable code associated with effecting the methods described herein). For example, in some embodiments, the non-volatile memory 1320 includes boot loader code, operating system code, file system code, and non-transitory processor-executable code to facilitate execution of methods for biasing different localized regions of a substrate or plasma processing chamber 100 as described with reference to FIGS. 1-12 . One or more of the monitoring circuitry 1270, the chamber analysis component 1272, and the control circuitry 1272 may be realized, at least in part, by non-transitory processor-executable code.

[0069] In many implementations, non-volatile memory 1320 is realized by flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from non-volatile memory 1320, executable code in non-volatile memory is typically loaded into RAM 1324 and executed by one or more of the N processing components in processing portion 1326.

[0070] The N processing components associated with RAM 1324 generally operate to execute instructions stored in non-volatile memory 1320 to enable performance of the algorithms and functions disclosed herein. It should be appreciated that while several algorithms are disclosed herein, some of these algorithms are not represented in flowcharts. Processor-executable code for effecting methods for biasing different localized regions of a substrate or chamber as shown in and described with respect to FIGS. 1-12 may be persistently stored in non-volatile memory 1320 and executed by the N processing components in association with RAM 1324. As one skilled in the art would understand, processing portion 1326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing component or a combination of hardware and software processing components (e.g., an FPGA or an FPGA including a digital logic processing portion).

[0071] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1320 and accessed (e.g., during power-up) to configure the field programmable gate array (FPGA) to implement the algorithms disclosed herein and to effect one or more of the functions of controller 1260 or other aspects of RF source 300 and bias sources 402, 602, 702, 1202.

[0072] The input component 1330 operates to receive signals indicative of one or more aspects of synchronized control between the environment within the plasma processing chamber 100 and / or the source generator 300 and the bias sources 402, 602, 702, 1202 (e.g., current, voltage, and phase information, and / or synchronization signals between the bias sources and the source generators). Signals received at the input component may include, for example, synchronization signals, power control signals to various generators and power supply units, or control signals from a user interface. The output component generally operates to provide one or more analog or digital signals for effecting operational aspects of controlling the bias sources as disclosed herein (e.g., localized biasing of the substrate and / or other components within the plasma processing chamber 100) and / or signals for effecting synchronization between the RF source and the bias sources. For example, the output portion 1332 may provide a synchronization signal between the bias sources 402, 602, 702, 1202 and the source generator 300.

[0073] The depicted transceiver component 1328 includes N transceiver chains that can be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0074] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining all software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied thereon.

[0075] As used herein, the recitation of "at least one of A, B, or C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications of these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

[Claim 1] Systems, methods, and devices, etc.

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