On / off switching circuit

Abstract

To provide an on / off switching circuit capable of turning on / off the output of AC power by simple control.SOLUTION: The on / off switching circuit 100 includes a first circuit 110, a second circuit 120, and a control unit 140. The first circuit 110 has a pair of a first 1FET111 and a first 2FET112 whose source terminals are connected to each other, and is configured to be capable of outputting AC power input to one end 110in from the other end 110out. The second circuit 120 is configured to be able to apply a predetermined bias voltage to the first 1FET111 and the second 2FET112. The control unit 140 that controls the first 1FET111, the second 2FET112, and the second circuit 120 turns on and off the first 1FET111 and the second 2FET112 in synchronization with each other, controls the second circuit 120 such that a bias voltage is applied to the first LA and the second LA when the first LA and the second LA are turned off, and controls the second circuit 120 such that a bias voltage is not applied to the first LA and the second LA when the first LA and the second LA are turned on.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an on-off switching circuit. [Background technology]

[0002] BACKGROUND ART Conventionally, for example, in plasma processing apparatuses used for etching or the like in manufacturing semiconductor devices, RF pulses obtained by pulse-modulating the output of an RF power supply (RF: Radio Frequency) may be used.

[0003] Patent Document 1 listed below discloses a technology for controlling the level of an output signal in a switch circuit that includes diodes inserted in series in each signal line and a control circuit that applies a forward bias voltage or a reverse bias voltage to each diode to turn each diode on and off, by variably controlling the forward current that flows through the diode when the diode is on. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 06-085643 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional technology has a problem in that it is difficult to turn on and off the output of AC power with simple control.

[0006] The present invention provides an on / off switching circuit that enables the output of AC power to be turned on and off with simple control. [Means for solving the problem]

[0007] One aspect of the present invention is a first circuit including a pair of field effect transistors whose source terminals are connected to each other, and configured to be able to output AC power input to one end from the other end; a second circuit configured to be able to apply a predetermined bias voltage between the source terminal and the drain terminal of each of the pair of field effect transistors; a control unit that controls the pair of field-effect transistors and the second circuit; Equipped with The control unit The pair of field effect transistors are turned on and off synchronously, controlling the second circuit so that the bias voltage is applied to each of the pair of field effect transistors when the pair of field effect transistors is turned off; controlling the second circuit so that the bias voltage is not applied to each of the pair of field effect transistors when the pair of field effect transistors is turned on; It is an on / off switching circuit. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide an on / off switching circuit that can turn on and off the output of AC power with simple control. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an on / off switching circuit 100 according to this embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the effect achieved by the on / off switching circuit 100. In FIG. [Figure 3] FIG. 3 is a diagram showing an example of the first drain-source voltage Vds1 and the second drain-source voltage Vds2 when the filter circuit 130 shown in FIG. 1 is not provided. [Figure 4] FIG. 4 is a diagram showing an example of the first drain-source voltage Vds1 and the second drain-source voltage Vds2 when the filter circuit 130 shown in FIG. 1 is provided. [Figure 5]FIG. 5 is a diagram showing a modified example of the on / off switching circuit 100 of this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of an on / off switching circuit of the present invention will be described in detail below with reference to the drawings. The drawings should be viewed in the direction of the reference symbols. Note that not all elements described in the following embodiment are necessarily essential to the present invention. Furthermore, two or more of the elements described in the following embodiment may be arbitrarily combined. In the following, identical or similar elements will be assigned identical or similar reference symbols, and their description may be omitted or simplified.

[0011] (1. Configuration of the on / off switching circuit) First, a description will be given of an example of the configuration of an on / off switching circuit 100 according to one embodiment of the present invention. Fig. 1 is a diagram showing an example of the configuration of an on / off switching circuit 100 according to this embodiment.

[0012] The on / off switching circuit 100 shown in FIG. 1 is a circuit that is provided, for example, between an RF power source (RF: Radio Frequency) not shown and a load, and is capable of switching between "on" in which RF power output from the RF power source is output to the load, and "off" in which RF power is not output to the load.

[0013] Here, RF power is an example of AC power. The load may be a capacitive load such as plasma generated between a cathode electrode and a counter electrode that are disposed opposite each other at a predetermined distance in a chamber of a plasma processing apparatus. A matching box for impedance matching may be provided between the RF power supply and the on-off switching circuit 100, or between the on-off switching circuit 100 and the load.

[0014] As shown in FIG. 1, the on / off switching circuit 100 includes a first circuit 110, a second circuit 120, a filter circuit 130, and a control unit 140, for example.

[0015] The first circuit 110 is a circuit that has a first FET 111 and a second FET 112 (FET: Field Effect Transistor) as an example of a pair of switches connected in series, and is configured to be able to output RF power input to one end 110in from the other end 110out. The one end 110in is electrically connected (hereinafter also simply referred to as "connected") to, for example, the RF power source or matching box described above. The other end 110out is connected to, for example, the load or matching box described above.

[0016] The first FET 111 is a switch provided on the one end 110in side of the first FET 111 and the second FET 112. As an example, in this embodiment, the first FET 111 is an NMOS transistor (NMOS: n-Channel Metal-Oxide-Semiconductor), and the drain terminal of the first FET 111 is connected to the one end 110in which is the input side of the first circuit 110.

[0017] The second FET 112 is a switch provided on the other end 110out side of the first FET 111 and the second FET 112. As an example, in this embodiment, the second FET 112 is an NMOS transistor, and the drain terminal of the second FET 112 is connected to the other end 110out, which is the output side of the first circuit 110. For example, the same type of NMOS transistor is used as the first FET 111 and the second FET 112.

[0018] The source terminals of the first FET 111 and the second FET 112 are connected to each other. A connection point P1 between the source terminals of the first FET 111 and the second FET 112 is connected to a reference potential line Lref of the second circuit 120 via a fifth inductor 135 (described later). The reference potential line Lref is a floating power line that is insulated from the ground and has a reference potential Vref. Therefore, the reference potential Vref is applied to the connection point P1. In other words, the potentials of the source terminals of the first FET 111 and the second FET 112 can be set to the reference potential Vref.

[0019] The gate terminals of the first FET 111 and the second FET 112 are connected to the control unit 140, which will be described later. This allows the control unit 140 to control the gate voltages applied to the gate terminals of the first FET 111 and the second FET 112, thereby turning the first FET 111 and the second FET 112 on (i.e., conductive state) or off (i.e., non-conductive state).

[0020] The second circuit 120 is a circuit configured to be able to apply a predetermined bias voltage between the source terminal and drain terminal of each of the first FET 111 and the second FET 112. Specifically, the second circuit 120 has a first bias voltage circuit unit 121 that applies a bias voltage between the source terminal and drain terminal of the first FET 111, and a second bias voltage circuit unit 122 that applies a bias voltage between the source terminal and drain terminal of the second FET 112.

[0021] The bias voltage applied by the first bias voltage circuit unit 121 to the first FET 111 and the bias voltage applied by the second bias voltage circuit unit 122 to the second FET 112 are greater than 0 [V] and have the same voltage value. An example of these bias voltages is 800 [V].

[0022] The first bias voltage circuit section 121 has a first high-side switch 121a and a first low-side switch 121b, an input terminal 121c to which a DC voltage having the above-mentioned bias voltage is input from a DC power supply (not shown), a reference terminal 121d connected to a reference potential line Lref, and a capacitor 121e.

[0023] The first high-side switch 121a and the first low-side switch 121b are connected in series between the input terminal 121c and the reference terminal 121d of the first bias voltage circuit section 121, with the first high-side switch 121a on the input terminal 121c side and the first low-side switch 121b on the reference terminal 121d side.

[0024] Furthermore, the first high-side switch 121a and the first low-side switch 121b are each connected to the control unit 140 and operate under the control of the control unit 140. In other words, the first bias voltage circuit unit 121 (i.e., the second circuit 120) applies a bias voltage to the first FET 111 under the control of the control unit 140.

[0025] The first high-side switch 121a and the first low-side switch 121b are each realized by, for example, an NMOS transistor. In this case, the control unit 140 is connected to the gate terminals of the first high-side switch 121a and the first low-side switch 121b. As a result, the control unit 140 can turn on and off the first high-side switch 121a and the first low-side switch 121b by controlling the gate voltages applied to the gate terminals of the first high-side switch 121a and the first low-side switch 121b.

[0026] The first high-side switch 121a and the first low-side switch 121b may each be configured by a plurality of switching elements (for example, NMOS transistors) connected in series. The capacitor 121e is provided in parallel with the first high-side switch 121a and the first low-side switch 121b, and functions as a bypass capacitor that stabilizes the DC voltage (i.e., bias voltage) input to the first bias voltage circuit unit 121 and removes high-frequency noise.

[0027] The second bias voltage circuit section 122 has a second high-side switch 122a and a second low-side switch 122b, an input terminal 122c to which a DC voltage having the above-mentioned bias voltage is input from a DC power supply (not shown), a reference terminal 122d connected to a reference potential line Lref, and a capacitor 122e.

[0028] The second high-side switch 122a and the second low-side switch 122b are connected in series between the input terminal 122c and the reference terminal 122d of the second bias voltage circuit section 122, with the second high-side switch 122a on the input terminal 122c side and the second low-side switch 122b on the reference terminal 122d side.

[0029] Furthermore, the second high-side switch 122a and the second low-side switch 122b are each connected to the control unit 140 and operate under the control of the control unit 140. In other words, the second bias voltage circuit unit 122 (i.e., the second circuit 120) applies a bias voltage to the second FET 112 under the control of the control unit 140.

[0030] The second high-side switch 122a and the second low-side switch 122b are each realized by, for example, an NMOS transistor. In this case, the control unit 140 is connected to the gate terminals of the second high-side switch 122a and the second low-side switch 122b. This allows the control unit 140 to turn on and off the second high-side switch 122a and the second low-side switch 122b by controlling the gate voltages applied to the gate terminals of the second high-side switch 122a and the second low-side switch 122b.

[0031] The second high-side switch 122a and the second low-side switch 122b may each be configured by a plurality of switching elements (e.g., NMOS transistors) connected in series. The capacitor 122e is provided in parallel with the second high-side switch 122a and the second low-side switch 122b, and functions as a bypass capacitor that stabilizes the DC voltage (i.e., bias voltage) input to the second bias voltage circuit unit 122 and removes high-frequency noise.

[0032] The filter circuit 130 is provided between the first circuit 110 and the second circuit 120, and is a circuit that suppresses RF power input to the first circuit 110 from flowing into the second circuit 120. The second circuit 120 may have stray capacitance, and in order to suppress the flow of RF power into the stray capacitance of the second circuit 120, the filter circuit 130 is preferably configured as described below.

[0033] The filter circuit 130 includes a first filter section 131 having a first inductor 131a and a first capacitor 131b connected in series, and a second filter section 132 having a second inductor 132a and a second capacitor 132b connected in series. For example, the impedances of the first inductor 131a and the second inductor 132a are set equal to each other in order to balance the voltages applied to the first FET 111 and the second FET 112.

[0034] It is preferable that the impedance of each of the first inductor 131a and the second inductor 132a be relatively large in order to prevent RF power from leaking to the other end 110out (i.e., the output side) through the inductors. On the other hand, it is preferable that the impedance of each of the first inductor 131a and the second inductor 132a be smaller than the impedance of each of the third inductor 133, the fourth inductor 134, and the fifth inductor 135.

[0035] The filter circuit 130 also includes a third inductor 133, a fourth inductor 134, and a fifth inductor 135, each of which has a higher impedance than the first inductor 131a and the second inductor 132a. For example, the impedances of the third inductor 133, the fourth inductor 134, and the fifth inductor 135 are assumed to be equal to each other.

[0036] 1, one end of the first filter section 131 on the first inductor 131a side is connected between one end 110in of the first circuit 110 and the first FET 111. More specifically, in this embodiment, one end of the first filter section 131 on the first inductor 131a side is connected to the drain terminal of the first FET 111 connected to one end 110in.

[0037] 1, the other end of the first filter section 131 on the first capacitor 131b side is connected to the reference potential line Lref via a fifth inductor 135. More specifically, in this embodiment, the other end of the first filter section 131 on the first capacitor 131b side is connected between the fifth inductor 135 and a connection point P1 between the source terminals of the first FET 111 and the second FET 112.

[0038] A connection point P4 between the first inductor 131a and the first capacitor 131b in the first filter section 131 is connected to the first bias voltage circuit section 121 via the third inductor 133. More specifically, in this embodiment, the connection point P4 is connected to a connection point P5 between the first high-side switch 121a and the first low-side switch 121b in the first bias voltage circuit section 121 via the third inductor 133.

[0039] 1, one end of the second filter section 132 on the second inductor 132a side is connected between the other end 110out of the first circuit 110 and the second FET 112. More specifically, in this embodiment, one end of the second filter section 132 on the second inductor 132a side is connected to the drain terminal of the second FET 112 connected to the other end 110out.

[0040] 1, the other end of the second filter section 132 on the second capacitor 132b side is connected to the reference potential line Lref via a fifth inductor 135. More specifically, in this embodiment, the other end of the second filter section 132 on the second capacitor 132b side is connected between the fifth inductor 135 and a connection point P1 between the source terminals of the first FET 111 and the second FET 112, similar to the other end of the first filter section 131 on the first capacitor 131b side.

[0041] A connection point P7 between the second inductor 132a and the second capacitor 132b in the second filter section 132 is connected to the second bias voltage circuit section 122 via the fourth inductor 134. More specifically, in this embodiment, the connection point P7 is connected to a connection point P8 between the second high-side switch 122a and the second low-side switch 122b in the second bias voltage circuit section 122 via the fourth inductor 134.

[0042] 1 includes the third inductor 133, the fourth inductor 134, and the fifth inductor 135, so that at least one inductor exists on each path through which current can flow from the first circuit 110 to the second circuit 120. Therefore, each path can be maintained at a high impedance compared to when no inductor exists on each path. This makes it possible to prevent RF power from the first circuit 110 from flowing into the second circuit 120.

[0043] However, the configuration of the filter circuit 130 is not limited to the example described here. For example, if the wiring between the connection point P4 and the connection point P5 shown in FIG. 1 has sufficient impedance (more specifically, impedance greater than that of the first inductor 131a), it is not necessary to separately provide the third inductor 133 as a component.

[0044] Similarly, if the wiring between connection point P7 and connection point P8 has sufficient impedance, there is no need to provide a separate fourth inductor 134 as a component, and if the wiring between connection point P3 and the reference potential line Lref has sufficient impedance, there is no need to provide a separate fifth inductor 135 as a component.

[0045] In other words, only the first filter section 131 and the second filter section 132 may be provided as the filter circuit 130. In this way, the configuration of the filter circuit 130 can be simplified, and the first filter section 131 and the second filter section 132, which are LC filters that can be easily and simply configured, can suppress the RF power input to the first circuit 110 from flowing into the second circuit 120.

[0046] Furthermore, if the wiring between the connection points P2 and P4 has sufficient impedance, the first inductor 131a does not need to be provided separately as a component, and if the wiring between the connection points P6 and P7 has sufficient impedance, the second inductor 132a does not need to be provided separately as a component. Furthermore, the filter circuit 130 itself may be omitted as appropriate.

[0047] The control unit 140 controls the first FET 111 and the second FET 112, which are an example of a pair of switches included in the first circuit 110, and the second circuit 120. For example, the control unit 140 is realized by a microcomputer or the like configured to include a CPU (Central Processing Unit), a memory, an I / F (Interface), and the like.

[0048] (2. Operation of the on / off switching circuit) Next, an example of the operation of the on / off switching circuit 100 of this embodiment will be described. In the on / off switching circuit 100, the control unit 140 synchronously turns on and off the first FET 111 and the second FET 112. In other words, when the control unit 140 turns on the first FET 111 and the second FET 112, it turns them on simultaneously, and when the control unit 140 turns off the first FET 111 and the second FET 112, it turns them off simultaneously.

[0049] The control unit 140 may turn on and off the first FET 111 and the second FET 112 at a predetermined cycle, or may turn on and off the first FET 111 and the second FET 112 based on a control signal received from an external device (not shown) or the like. In other words, the timing at which the control unit 140 turns on and off the first FET 111 and the second FET 112 is not particularly limited.

[0050] Then, when the control unit 140 turns off the first FET 111 and the second FET 112, the control unit 140 controls the second circuit 120 so that a bias voltage is applied to each of the first FET 111 and the second FET 112. Specifically, at this time, the control unit 140 turns on the first high-side switch 121a of the first bias voltage circuit unit 121 and turns off the first low-side switch 121b, so that a bias voltage is applied between the source terminal and the drain terminal of the first FET 111. At this time, the control unit 140 also turns on the second high-side switch 122a of the second bias voltage circuit unit 122 and turns off the second low-side switch 122b, so that a bias voltage is applied between the source terminal and the drain terminal of the second FET 112.

[0051] On the other hand, when the control unit 140 turns on the first FET 111 and the second FET 112, it controls the second circuit 120 so that a bias voltage is not applied to each of the first FET 111 and the second FET 112. Specifically, at this time, the control unit 140 turns off the first high-side switch 121a of the first bias voltage circuit unit 121 and turns on the first low-side switch 121b, thereby preventing a bias voltage from being applied between the source terminal and the drain terminal of the first FET 111. At this time, the control unit 140 also turns off the second high-side switch 122a of the second bias voltage circuit unit 122 and turns on the second low-side switch 122b, thereby preventing a bias voltage from being applied between the source terminal and the drain terminal of the second FET 112.

[0052] (3. Effect of the on / off switching circuit) Next, an example of the effect achieved by the on / off switching circuit 100 of this embodiment will be described. FIG. 2 is a diagram showing an example of the effect achieved by the on / off switching circuit 100. In (a) of FIG. 2, the vertical axis represents the output voltage from the other end 110out of the first circuit 110, and the horizontal axis represents time. In (b) of FIG. 2, the vertical axis represents the first drain-source voltage Vds1, which is the voltage between the source terminal and drain terminal of the first FET 111, and the horizontal axis represents time. In (c) of FIG. 2, the vertical axis represents the second drain-source voltage Vds2, which is the voltage between the source terminal and drain terminal of the second FET 112, and the horizontal axis represents time.

[0053] A period T11 from time t10 to time t11 shown in FIG. 2 is a period during which the first FET 111 and the second FET 112 are both turned off and a bias voltage is applied to each of the first FET 111 and the second FET 112.

[0054] During the period T11, a bias voltage is applied to each of the first FET 111 and the second FET 112, thereby reducing the output capacitance (so-called "Coss") of the first FET 111 and the second FET 112. This increases the impedance of the first circuit 110, more specifically, between one end 110in and the other end 110out.

[0055] The output voltage from the other end 110out is, for example, a voltage divided by the first circuit 110 and the load connected to the other end 110out. Therefore, by increasing the impedance of the first circuit 110, the output voltage from the other end 110out can be made approximately 0 [V], as shown in (a) of Fig. 2. Therefore, it is possible to prevent RF power from being output from the other end 110out.

[0056] On the other hand, a period T12 from time t11 to time t12 shown in FIG. 2 is a period during which the first FET 111 and the second FET 112 are both turned on and no bias voltage is applied to the first FET 111 or the second FET 112.

[0057] During period T12, the first FET 111 and the second FET 112 are turned on, and therefore the first FET 111 and the second FET 112 are in a low resistance state (in other words, a low impedance state). This reduces the impedance of the first circuit 110, more specifically, the impedance between one end 110in and the other end 110out. By reducing the impedance of the first circuit 110, an output voltage corresponding to the input voltage to the one end 110in can be output from the other end 110out, as shown in (a) of FIG. 2. Therefore, RF power can be output from the other end 110out.

[0058] As described above, according to the on / off switching circuit 100 of the present embodiment, when the first FET 111 and the second FET 112 are turned off, a bias voltage is applied to each of the first FET 111 and the second FET 112, thereby reducing the output capacitance of the first FET 111 and the second FET 112 and increasing the impedance of the first circuit 110. Therefore, in this case, it is possible to prevent RF power from being output from the other end 110out, which is the output side of the first circuit 110. On the other hand, according to the on / off switching circuit 100, when the first FET 111 and the second FET 112 are turned on, a bias voltage is not applied to each of the first FET 111 and the second FET 112, thereby allowing RF power to be output from the other end 110out, which is the output side of the first circuit 110.

[0059] As described above, according to the on / off switching circuit 100 of this embodiment, it is possible to switch on / off the output of RF power by simple control such as turning on / off the first FET 111 and the second FET 112 as a pair of switches of the first circuit 110 and applying a bias voltage to the first FET 111 and the second FET 112.

[0060] In response to this, for example, a configuration is conceivable in which an amplifier circuit is provided in the first circuit 110 and the RF power output from the first circuit 110 is switched on and off by this amplifier circuit. However, since the control of the amplifier circuit tends to be complicated, with such a configuration, it becomes difficult to switch on and off the RF power output from the first circuit 110 with simple control.

[0061] Furthermore, according to the on / off switching circuit 100 of this embodiment, the switch of the first circuit 110 is configured by the first FET 111 and the second FET 112, so that the output of RF power from the first circuit 110 can be turned on and off more quickly than when this switch is configured by a PIN diode.

[0062] Furthermore, if the switch of the first circuit 110 were configured using only the first FET 111, when the first FET 111 was turned off, a half wave on the negative potential side of the RF power would flow through the body diode of the first FET 111, which could make it impossible to turn on and off the output from the other end 110out of the first circuit 110 in a pulsed manner. In contrast, according to the on / off switching circuit 100 of the present embodiment, the switch of the first circuit 110 is configured using the first FET 111 and the second FET 112, so it is possible to turn on and off the output from the other end 110out of the first circuit 110 in a pulsed manner.

[0063] Furthermore, according to the on / off switching circuit 100 of this embodiment, the first circuit 110 and the second circuit 120 are connected via the filter circuit 130, so it is possible to prevent RF power input to the first circuit 110 from flowing into the second circuit 120. An example of the effect achieved when the filter circuit 130 shown in FIG. 1 is provided will now be described in detail.

[0064] First, in order to make it easier to understand the effect of providing the filter circuit 130 shown in FIG. 1, an example of the first drain-source voltage Vds1 and the second drain-source voltage Vds2 when this filter circuit 130 is not provided (for example, when the first circuit 110 and the second circuit 120 are directly connected) will be described.

[0065] 3 is a diagram showing an example of the first drain-source voltage Vds1 and the second drain-source voltage Vds2 when the filter circuit 130 shown in FIG. 1 is not provided. In FIG. 3, the vertical axis represents the voltage, which is the magnitude of the first drain-source voltage Vds1 and the second drain-source voltage Vds2, and the horizontal axis represents the time. Note that FIG. 3 also shows the first drain-source voltage Vds1 and the second drain-source voltage Vds2 during a period when the first FET 111 and the second FET 112 are turned off (for example, the period T11 shown in FIG. 2).

[0066] Even during a period in which the first FET 111 and the second FET 112 are turned off, an RF voltage corresponding to the RF power input to the first circuit 110 can be applied to the drain terminal and source terminal of the first FET 111 and the drain terminal and source terminal of the second FET 112. Therefore, the potential of these terminals, such as the connection point P1, can become higher than the reference potential Vref of the second circuit 120.

[0067] If the first circuit 110 and the second circuit 120 were directly connected, it would be difficult to maintain high impedance along each path through which current can flow from the first circuit 110 to the second circuit 120, and therefore the RF power of the first circuit 110 would flow into the second circuit 120 via a path with low impedance (for example, a path from the connection point P1 to the reference potential line Lref).

[0068] In this way, when RF power flows from the first circuit 110 to the second circuit 120, that is, when a leakage current occurs from the first circuit 110 to the second circuit 120, there is a risk that the first drain-source voltage Vds1 and the second drain-source voltage Vds2 will become unbalanced, as shown in Fig. 3. As a result, even though the first circuit 110 is configured with two switches, the first FET 111 and the second FET 112, a large voltage will be applied unevenly to one of the switches (the first FET 111 in the example shown in Fig. 3), which will put a strain on the withstand voltage requirements of this switch. Furthermore, the power loss (in other words, heat generation) will also be shared unevenly by one of the switches.

[0069] 4 is a diagram showing an example of the first drain-source voltage Vds1 and the second drain-source voltage Vds2 when the filter circuit 130 shown in FIG. 4 is provided. In FIG. 4 as well, the vertical axis represents the voltage, which is the magnitude of the first drain-source voltage Vds1 and the second drain-source voltage Vds2, and the horizontal axis represents the time. As in FIG. 3, FIG. 4 also plots the first drain-source voltage Vds1 and the second drain-source voltage Vds2 during the period when the first FET 111 and the second FET 112 are off.

[0070] As described above, the filter circuit 130 shown in FIG. 1 includes at least one inductor on each path through which current can flow from the first circuit 110 to the second circuit 120. This maintains high impedance on each path, thereby preventing RF power from the first circuit 110 from flowing into the second circuit 120. This allows the first drain-source voltage Vds1 and the second drain-source voltage Vds2 to be balanced, as shown in FIG. 4 . In other words, unlike the case shown in FIG. 3 , it is possible to prevent a large voltage from being applied unevenly to one of the switches of the first FET 111 and the second FET 112. Therefore, it is possible to accommodate RF power with a larger RF voltage without improving the voltage resistance or heat resistance of the first FET 111 and the second FET 112.

[0071] (4. Modified Example of On / Off Switching Circuit) Next, a modified example of the on / off switching circuit 100 of this embodiment will be described. Fig. 5 is a diagram showing a modified example of the on / off switching circuit 100 of this embodiment. Note that the following description will focus on differences from the previously described embodiment (the configuration shown in Fig. 1, etc.), and descriptions of similarities to the previously described embodiment will be omitted or simplified as appropriate.

[0072] 5, filter circuit 130 is illustrated simply as a dashed rectangle for ease of viewing, but filter circuit 130 may be configured to include, for example, the components shown in FIG. 1. In this modification, filter circuit 130 may be configured to further include other components in addition to the components shown in FIG. 1. As an example, in this case, filter circuit 130 may have filter sections (i.e., LC filters) having a configuration similar to that of first filter section 131 and second filter section 132 between third FET 113 and third bias voltage circuit section 123, and between fourth FET 114 and fourth bias voltage circuit section 124, both of which will be described later.

[0073] 5, the first circuit 110 may have a third FET 113 and a fourth FET 114 in addition to the first FET 111 and the second FET 112 as a pair of switches. In this case, the source terminal of the third FET 113 is connected to the drain terminal of the first FET 111, and the drain terminal is connected to one end 110in of the first circuit 110. Furthermore, the source terminal of the fourth FET 114 is connected to the drain terminal of the second FET 112, and the drain terminal is connected to the other end 110out of the first circuit 110.

[0074] In this case, the second circuit 120 is also configured to be able to apply a bias voltage between the source terminal and drain terminal of each of the third FET 113 and the fourth FET 114. Specifically, in this case, the second circuit 120 further includes a third bias voltage circuit unit 123 that applies a bias voltage between the source terminal and drain terminal of the third FET 113, and a fourth bias voltage circuit unit 124 that applies a bias voltage between the source terminal and drain terminal of the fourth FET 114.

[0075] The third bias voltage circuit section 123 and the fourth bias voltage circuit section 124 are configured similarly to the first bias voltage circuit section 121 and the second bias voltage circuit section 122, respectively. However, in this case, it should be noted that the reference potential Vref in the first bias voltage circuit section 121 and the second bias voltage circuit section 122, the reference potential in the third bias voltage circuit section 123, and the reference potential in the fourth bias voltage circuit section 124 must be independent of each other.

[0076] In this case, the control unit 140 synchronously turns on and off the first FET 111, the second FET 112, the third FET 113, and the fourth FET 114. When the control unit 140 turns off the first FET 111, the second FET 112, the third FET 113, and the fourth FET 114, the control unit 140 controls the second circuit 120 so that a bias voltage is applied to each of the first FET 111, the second FET 112, the third FET 113, and the fourth FET 114.

[0077] On the other hand, when the control unit 140 turns on the first FET 111, the second FET 112, the third FET 113, and the fourth FET 114, it controls the second circuit 120 so that no bias voltage is applied to each of the first FET 111, the second FET 112, the third FET 113, and the fourth FET 114.

[0078] According to the on / off switching circuit 100 of this modified example, the RF voltage applied to each FET of the first circuit 110 can be reduced compared to the configuration shown in FIG. 1, and therefore it is possible to accommodate RF power with a larger RF voltage without improving the voltage resistance of each FET of the first circuit 110.

[0079] Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to these examples. It is clear that a person skilled in the art can conceive of various modifications or alterations within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention. Furthermore, the components of the above embodiments may be combined in any manner without departing from the spirit of the invention.

[0080] For example, in the above-described embodiment, the switch of the first circuit 110 is configured with the first FET 111 and the second FET 112, but this is not limiting. Instead of the first FET 111 and the second FET 112, the switch of the first circuit 110 may be configured with a pair of diodes (e.g., PIN diodes) whose anode terminals or cathode terminals are connected to each other. In this case, the second circuit 120, under the control of the control unit 140, applies a positive bias voltage to each of the pair of diodes when the pair of diodes is off, and applies a negative bias voltage to each of the pair of diodes when the pair of diodes is on. This also makes it possible to switch the RF power output from the first circuit 110 on and off with simple control.

[0081] This specification etc. describes at least the following matters. Note that the components etc. corresponding to those in the above-mentioned embodiment are shown in parentheses, but are not limited to these.

[0082] (1) A first circuit (first circuit 110) having a pair of field effect transistors (first FET 111, second FET 112) whose source terminals are connected to each other, and configured to be able to output AC power input to one end (one end 110in) from the other end (the other end 110out); a second circuit (a second circuit 120, a first bias voltage circuit unit 121, a second bias voltage circuit unit 122) configured to be able to apply a predetermined bias voltage between the source terminal and the drain terminal of each of the pair of field effect transistors; a control unit (control unit 140) that controls the pair of field effect transistors and the second circuit; Equipped with The control unit The pair of field effect transistors are turned on and off synchronously, controlling the second circuit so that the bias voltage is applied to each of the pair of field effect transistors when the pair of field effect transistors is turned off; controlling the second circuit so that the bias voltage is not applied to each of the pair of field effect transistors when the pair of field effect transistors is turned on; On / off switching circuit.

[0083] According to (1), when the pair of field-effect transistors of the first circuit are turned off, a bias voltage is applied to each of the pair of field-effect transistors, thereby reducing the output capacitance (so-called "Coss") of the pair of field-effect transistors and increasing the impedance of the first circuit, and AC power is not output from the other end, which is the output side of the first circuit. On the other hand, according to (1), when the pair of field-effect transistors of the first circuit are turned on, a bias voltage is not applied to each of the pair of field-effect transistors, thereby AC power is output from the other end, which is the output side of the first circuit. This makes it possible to turn on and off the AC current output from the first circuit through simple control of turning on and off the pair of field-effect transistors of the first circuit and applying a bias voltage to them.

[0084] (2) The on / off switching circuit according to (1), the pair of field effect transistors is composed of a first field effect transistor (first FET 111) on one end side of the first circuit and a second field effect transistor (second FET 112) on the other end side of the first circuit, the first circuit further includes a third field effect transistor (third FET 113) and a fourth field effect transistor (fourth FET 114) different from the first field effect transistor and the second field effect transistor, respectively; the second circuit is configured to be able to further apply the bias voltage between a source terminal and a drain terminal of each of the third field effect transistor and the fourth field effect transistor; the third field effect transistor has a source terminal connected to a drain terminal of the first field effect transistor and a drain terminal connected to one end of the first circuit; the fourth field effect transistor has a source terminal connected to a drain terminal of the second field effect transistor and a drain terminal connected to the other end of the first circuit; The control unit turning on and off the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor in synchronization with each other; controlling the second circuit so that the bias voltage is applied to each of the field-effect transistors when each of the field-effect transistors is turned off; controlling the second circuit so that the bias voltage is not applied to each of the field effect transistors when each of the field effect transistors is turned on; On / off switching circuit.

[0085] According to (2), the AC voltage applied to each field effect transistor of the first circuit can be reduced compared to when the first circuit has only a pair of field effect transistors, namely, the first field effect transistor and the second field effect transistor. Therefore, it becomes possible to adapt to AC power having a larger AC voltage without improving the voltage resistance of each field effect transistor.

[0086] (3) The on / off switching circuit according to (1) or (2), The first circuit and the second circuit are connected via a filter circuit (filter circuit 130) that prevents the AC power input to the first circuit from flowing into the second circuit. On / off switching circuit.

[0087] According to (3), it is possible to prevent AC power input to the first circuit from flowing into the second circuit. [Explanation of symbols]

[0088] 100 On / off switching circuit 110 1st circuit 110in one end 110out other end 111 First FET (switch, first field effect transistor) 112 Second FET (switch, second field effect transistor) 113 Third FET (third field effect transistor) 114 4th FET (4th field effect transistor) 120 2nd circuit 121 First bias voltage circuit section (second circuit) 122 Second bias voltage circuit section (second circuit) 130 Filter Circuit 140 Control Unit P1 connection point

Claims

1. a first circuit including a pair of field effect transistors whose source terminals are connected to each other, and configured to be able to output AC power input to one end from the other end; a second circuit configured to be able to apply a predetermined bias voltage between the source terminal and the drain terminal of each of the pair of field effect transistors; a control unit that controls the pair of field-effect transistors and the second circuit; Equipped with The control unit The pair of field effect transistors are turned on and off synchronously, controlling the second circuit so that the bias voltage is applied to each of the pair of field effect transistors when the pair of field effect transistors is turned off; controlling the second circuit so that the bias voltage is not applied to each of the pair of field effect transistors when the pair of field effect transistors is turned on; On / off switching circuit.

2. 2. The on / off switching circuit according to claim 1, the pair of field effect transistors includes a first field effect transistor on one end side of the first circuit and a second field effect transistor on the other end side of the first circuit, the first circuit further includes a third field effect transistor and a fourth field effect transistor different from the first field effect transistor and the second field effect transistor, respectively; the second circuit is configured to be able to further apply the bias voltage between a source terminal and a drain terminal of each of the third field effect transistor and the fourth field effect transistor; the third field effect transistor has a source terminal connected to a drain terminal of the first field effect transistor and a drain terminal connected to one end of the first circuit; the fourth field effect transistor has a source terminal connected to the drain terminal of the second field effect transistor and a drain terminal connected to the other end of the first circuit; The control unit turning on and off the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor in synchronization with each other; controlling the second circuit so that the bias voltage is applied to each of the field effect transistors when each of the field effect transistors is turned off; controlling the second circuit so that the bias voltage is not applied to each of the field effect transistors when each of the field effect transistors is turned on; On / off switching circuit.

3. 3. The on / off switching circuit according to claim 1, the first circuit and the second circuit are connected via a filter circuit that prevents the AC power input to the first circuit from flowing into the second circuit; On / off switching circuit.

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