Sic-based electronic device with improved electrical performance and method of manufacture

Abstract

To provide an electronic device based on SiC having improved electrical performance, and to provide a method of manufacturing the electronic device.SOLUTION: It comprises a silicon-carbide semiconducting body 53 having a front side 53a and a first conductivity type and accommodating an active region 54 and an edge region 55 lateral to the active region along a first direction. A first termination doped region 62 extends from the front surface into the semiconductor body at least partially into the edge region, the first termination doped region having the second conductivity type. A first metal region 65 extends on the front surface above the active region and the first termination doped region, wherein the first metal region has a first thickness and is interrupted above the first termination doped region along the first direction. A second metal region 72 extends transversely to the first metal region along the first direction at a distance from the front surface above the edge region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Italian Patent Application No. 102024000014086, filed June 19, 2024, and entitled "ELECTRONIC DEVICE BASED ON SiC HAVING IMPROVED ELECTRICAL PERFORMANCES AND MANUFACTURING METHOD," which is incorporated herein by reference to the fullest extent permitted by law.

[0002] The present disclosure relates to SiC-based electronic devices with improved electrical performance and methods for manufacturing the electronic devices. [Background technology]

[0003] Silicon carbide (SiC) is of great interest in the semiconductor industry, especially for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0004] Electronic devices fabricated on silicon carbide substrates of different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC) have many advantages, including low output resistance when conducting, low leakage current, high temperature operation tolerance, and high frequency operation tolerance.

[0005] FIG. 1 shows a cross-sectional view of a portion of an electronic device 1 of known type (here exemplarily a JBS “Junction Barrier Schottky” diode) in an orthogonal (three-axis) reference system of axes X, Y and Z.

[0006] The JBS device 1 comprises a semiconductor body 3 of N-type SiC having an upper surface 3a and a lower surface 3b. The semiconductor body 3 may include, for example, a substrate and one or more regions epitaxially grown on the substrate, the regions being N-type and having respective doping concentration values.

[0007] The JBS device 1 also comprises a plurality of junction barrier elements 9 (hereinafter also referred to as JB, junction barrier, elements 9) in the semiconductor body 3, the JB elements 9 facing the top surface 3a and each comprising a respective implanted region of P type in the semiconductor body 3 and an ohmic contact on the implanted region at the level of the top surface 3a of the semiconductor body 3.

[0008] The JBS device 1 further comprises a first metallization 8 extending over the top surface 3a and in electrical contact with the JB elements 9 via respective ohmic contacts (not shown).

[0009] The JBS device 1 further comprises an edge termination region 10 (or guard ring) that completely surrounds the JB element 9, specifically the P-type implant region.

[0010] The edge termination region 10 is 15 ~10 18 atoms / cm 3 The doping level is included in

[0011] Schottky diode 12 is formed at the interface between first metallization 8 and semiconductor body 3, where a semiconductor-metal Schottky junction is formed. The region of JBS device 1 that includes JB element 9 and Schottky diode 12 (i.e., the region contained within guard ring 10) is the active region 4 of JBS device 1.

[0012] The JBS device 1 further comprises a second metallization 6 extending onto the lower surface 3b. The first and second metallizations 8, 6 form anode and cathode electrical terminals, respectively, that can be biased during use of the JBS device 1.

[0013] Electrically passive region 16 extends outside edge termination region 10 .

[0014] An insulating layer 18, particularly of silicon oxide (SiO 2 ), extends partially over the edge termination region 10.

[0015] First metallization 8 is in electrical contact with the portion of edge termination region 10 not covered by insulating layer 18 and extends partially above insulating layer 18 .

[0016] The first metallization 8 has the same thickness both over the active region 4 (where the first metallization 8 functions as the anode metallization) and over the insulating layer 18 (where the first metallization 8 functions as the field plate region).

[0017] Here, an interfacial layer 20 of silicon nitride (SiN) extends above the first metallization 8 and the insulating layer 18 .

[0018] Furthermore, the JBS device 1 comprises a passivation layer 22, in particular made of polyimide, which layer extends above the interfacial layer 20. In other words, the interfacial layer 20 serves as an interface between the passivation layer 22 and the underlying layers, here the first metallization 8 and the insulating layer 18.

[0019] Here, a protective layer 24 of resin, for example Bakelite, extends above the passivation layer 22 to protect the JBS device 1 and form a package.

[0020] The interface layer 20 ensures a better adhesion of the passivation layer 22 than would be the case if the passivation layer 22 extended directly onto the top surface 3 a of the semiconductor body 3 , for example.

[0021] However, Applicant has determined that certain critical conditions of use or thermal or thermo-mechanical testing of JBS Device 1 can cause delamination or partial delamination of passivation layer 22 from interface layer 20 due to the stresses generated. This occurs particularly in the presence of high operating temperatures (e.g., above 150°C). This effect not only structurally weakens JBS Device 1, but can also promote the occurrence of undesirable electrical discharges that can cause JBS Device 1 to malfunction or completely impair its functionality.

[0022] In fact, the applicant has found that, depending on the processing conditions of thermomechanical or mechanical stress after the assembly process, the interface layer 20 may have one or more local cracks throughout its thickness, which may cause such discharges to occur in the first metallization 8. This problem occurs especially when the JBS device 1 is subjected to high temperature thermal fluctuations and high voltage differences under reverse bias conditions.

[0023] Therefore, a need is felt to overcome the aforementioned problems. Summary of the Invention

[0024] In accordance with the present disclosure, there are provided SiC-based electronic devices and methods for their manufacture, as defined in the accompanying claims. [Brief explanation of the drawings]

[0025] In order that the present disclosure may be better understood, embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which:

[0026] [Figure 1] 1 shows a cross-sectional view of an electronic device of a known type; [Figure 2] 1 illustrates a cross-sectional view of an electronic device, according to one embodiment. [Figure 3A] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3B] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3C] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3D] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3E] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3F] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0027] 2 shows an electronic device 50. The electronic device 50 is in particular a Schottky diode of the JBS type. However, the present description is not limited to this device and also finds application to other types of electronic devices, in particular Schottky diodes of different types (for example of the MPS type), or other electronic devices of the vertical conduction type, in particular for power applications, such as MOSFETs, IGBTs, PN diodes, PiN diodes, etc.

[0028] In particular, FIG. 2 shows the edge of electronic device 50, in a cartesian reference system XYZ having orthogonal axes X, Y, and Z, arranged around the periphery of a die of semiconductor material on which electronic device 50 is integrated.

[0029] The device 50 comprises a semiconductor body 53 having a front surface 53a and a back surface 53b spaced apart from each other along the Z axis.

[0030] The semiconductor body 53 also comprises side surfaces 53c transverse, in particular substantially perpendicular, to the front surface 53a.

[0031] In particular, the side surface 53c laterally defines the semiconductor body 53 at one end along the X-axis.

[0032] Side surface 53c may be formed, for example, following a step of dicing a wafer of semiconductor material during the manufacturing process of electronic device 50.

[0033] Semiconductor body 53 is N-type or P-type silicon carbide (SiC) (hereinafter, non-limiting reference will be made to N-type only). In particular, semiconductor body 53 is 4H-SiC type, although other polytypes such as 2H-SiC, 3C-SiC, and 6H-SiC can also be used.

[0034] In the embodiment of FIG. 2, semiconductor body 53 includes a substrate 53' and a drift region 53'' extending over substrate 53' and formed, for example, by one or more epitaxial layers grown on substrate 53'.

[0035] For example, the substrate 53' is 1·10 18 atoms / cm 3 ~1·10 22 atoms / cm 3 and may have a thickness measured along the Z axis comprised, for example, between 100 μm and 450 μm, in particular equal to about 360 μm. Drift region 53″ may have a dopant concentration lower than the dopant concentration of substrate 53′ and a thickness along the Z axis comprised, for example, between 5 and 20 μm.

[0036] The semiconductor body 53 includes an active region 54 and an edge region 55 extending laterally relative to the active region 54 along the X-axis and specifically monolithic with the active region 54 .

[0037] In FIG. 2, for clarity of illustration, a dashed line parallel to the Z axis separates the active area 54 from the edge area 55, purely by way of example and not limitation.

[0038] The edge region 55 may extend around and surround the active region 54 .

[0039] In particular, in the embodiment of FIG. 2, the edge region 55 may extend along the X-axis to the side surface 53c of the semiconductor body 53.

[0040] Metallization 57, which in this example forms a cathode metallization of, for example, Ti / NiV / Ag or Ti / NiV / Au, extends onto back surface 53b. Metallization 57 may also include an ohmic contact layer (e.g., nickel silicide or titanium) extending into contact with back surface 53b.

[0041] A plurality of barrier-doped regions 59′ of opposite conductivity type to that of the semiconductor body 53, i.e., P-type here, extend from the front surface 53a into the semiconductor body 53 (particularly into the drift region 53″) at a distance from one another along the X-axis.

[0042] The barrier doped region 59' may have a width along the X-axis that is comprised between 0.5 μm and 10 μm, for example.

[0043] In this embodiment, the electronic device 50 also optionally comprises, for each barrier-doped region 59', a respective ohmic contact region 59'' received in the barrier-doped region 59' at the front surface 53a.

[0044] Each doped region 59' and respective ohmic contact region 59'' form a junction barrier element 59, also referred to hereinafter as a JB (junction barrier) element 59.

[0045] In embodiments in which electronic device 50 is a JBS or MPS type Schottky diode, active region 54 may be defined as the portion of semiconductor body 53 in which JB element 59 is housed.

[0046] Electronic device 50 further comprises an anode termination region 62 of opposite conductivity type (i.e., here P-type) to that of semiconductor body 53, which extends within semiconductor body 53, particularly within drift region 53″, into edge region 55.

[0047] The anode termination region 62 is preferably formed of a material such as a silicon dioxide film, e.g., 10 17 ~10 21 atoms / cm3 In fact, anode termination region 62 may have metallic or semi-metallic behavior from an electrical standpoint.

[0048] Anode termination region 62 begins at front surface 53 a and extends into epitaxial region 53 ″ at a distance along the X-axis from barrier-doped region 59 ′. In particular, anode termination region 62 extends along a direction parallel to the X-axis between barrier-doped region 59 ′ and side surface 53 c of semiconductor body 53.

[0049] 2, anode termination region 62 extends completely into edge region 55. In effect, anode termination region 62 laterally bounds active area 54.

[0050] However, the anode termination region 62 may extend partially into the active region 54 depending on the particular structure of the electronic device 50 .

[0051] The anode termination region 62 may have a width along the X-axis that is larger than the barrier doped region 59', for example, comprised between 10 μm and 100 μm.

[0052] The electronic device 50 further comprises an edge termination region, or guard ring 63 .

[0053] An edge termination region 63 is formed at the front surface 53a by a further doped region, here P-type, that extends into the edge region 55 in the drift region 53''.

[0054] The edge termination region 63 has a lower concentration of doping species than the anode termination region 62, e.g., 10 15 ~10 18 atoms / cm 3 The concentration of the doping species may be included in the

[0055] In the XY plane, the edge termination region 63 extends around the active region 54 in plan view.

[0056] Edge termination region 63 may partially overlap anode termination region 62 .

[0057] However, edge termination region 63 is not essential and may be omitted.

[0058] The electronic device 50 further includes metal contact regions 65 and (metal) field plate regions 72 .

[0059] Metal contact region 65 is on and in contact with front surface 53 a , extending both over active region 54 and partially over anode termination region 62 , terminating above anode termination region 62 .

[0060] In fact, metal contact region 65 also extends partially above edge region 55 .

[0061] In particular, the metal contact region 65 includes an interface portion 66 formed by a metal layer 67, for example of titanium, nickel, Mo, TiN, MoN, V, Ta, W, WC, extending directly onto the front surface 53a, and an upper portion 70, for example of AlSiCu, AlCu, Al, or more generally an Al-based alloy, extending onto the interface portion 66.

[0062] The interface portion 66 has a thickness that is less than the thickness of the upper portion 70 .

[0063] The interface portion 66 may have a thickness (measured along the Z axis) comprised for example between 10 nm and 200 nm.

[0064] The upper part 70 has a thickness greater than the interface part 66, for example comprised between 2 μm and 10 μm, which can ensure a reliable and robust electrical connection of the metal contact region 65.

[0065] Overall, the metal contact region 65 may have a thickness, measured along the Z axis, of 2 μm or more.

[0066] The upper portion 70 extends from the active region 54 toward the outside of the electronic device 50, i.e., toward the side surface 53c, in a direction parallel to the X-axis, and terminates facing the anode termination region 62 along the Z-axis.

[0067] 2, interface region 66 extends beyond top portion 70 in a direction parallel to the X-axis, away from active region 54. This feature is optional and can simplify achieving physical and electrical continuity between metal contact region 65 and metal field plate region 72 during fabrication.

[0068] A plurality of Schottky diodes 71 are formed laterally at the interface between the semiconductor body 53 and the metal contact regions 65 and between the barrier doped regions 59'. In particular, the Schottky diodes are formed by semiconductor-metal junctions formed by portions of the semiconductor body 53 that are in direct contact with the metal contact regions 65.

[0069] In effect, metal contact region 65 forms the anode metallization of electronic device 50 .

[0070] Additionally, metal contact regions 65 are also in direct electrical contact with JB elements 59, and in particular in ohmic contact with respective ohmic contact regions 59''.

[0071] Field plate region 72 is made of a metallic material and extends above edge region 55 at a distance from front surface 53a along the Z axis.

[0072] In the illustrated embodiment, field plate regions 72 are formed by raised portions of metal layer 67 adjacent interface 66. The fact that field plate regions 72 are formed by the same layer as metal contact regions 65 may simplify fabrication of electronic device 50.

[0073] Field plate region 72 has a thickness that is less than metal contact region 65. In particular, in this embodiment, field plate region 72 has the same thickness as interface region 66. This thickness allows region 72 to effectively act as a field plate.

[0074] Field plate region 72 is adjacent to metal layer interface 66 and therefore in direct electrical contact with metal contact region 65 .

[0075] Field plate region 72 extends beyond anode termination region 62 in a direction parallel to the X-axis. In particular, in the embodiment of Figure 2, field plate region 72 terminates above edge termination region 63 and faces edge termination region 63 at a distance along the Z-axis.

[0076] Field plate region 72 may extend in a direction parallel to the X-axis toward side surface 53c with a width that is adjustable during the design step depending on the particular application.

[0077] For example, field plate region 72 may terminate above (parallel to the Z-axis) edge termination region 63, and edge termination region 63 may extend beyond field plate region 72 toward side 53c (parallel to the X-axis). In particular, edge termination region 63 may extend beyond field plate region 72 by a width measured along the X-axis in the direction of side 53c that is comprised between 0 μm (i.e., the outer boundary of field plate region 72 may be aligned with the outer boundary of edge termination region 63) and 50 μm, depending on the voltage class of electronic device 50.

[0078] The electronic device 50 further comprises a number of insulating layers 80, 81, 82, 83.

[0079] An insulating layer 80 of an electrically insulating or dielectric material (eg, silicon oxide or TEOS - tetraethyl orthosilicate) extends directly onto the front surface 53 a of the semiconductor body 53 above the edge region 55 .

[0080] The insulating layer 80 may have a thickness along the Z axis comprised for example between 0.1 μm and 5 μm.

[0081] In particular, insulating layer 80 includes a portion 80A that extends below field plate region 72, separating field plate region 72 from front surface 53a, and a portion 80B that extends laterally in a direction parallel to the X-axis and adjacent portion 80A onto edge region 55.

[0082] An insulating layer 81 of electrically insulating or dielectric material (eg, silicon oxide or TEOS - tetraethyl orthosilicate) extends over the front surface 53 a of the semiconductor body 53 .

[0083] The insulating layer 81 may have a thickness along the Z axis comprised for example between 0.01 μm and 5 μm.

[0084] In particular, insulating layer 81 includes a portion 81A that extends over field plate region 72 and over at least a portion of metal contact region 65 above active region 54, and a portion 81B that extends laterally in a direction parallel to the X-axis and adjacent portion 81A onto portion 80B of insulating layer 80.

[0085] Insulating layer 81 may be of the same material as insulating layer 80 and may therefore be indistinguishable from insulating layer 80 in the overlying zone, and therefore the boundary between insulating layers 80 and 81 is shown by a dashed line in Figure 2.

[0086] The insulating layer 82, also called interface layer, consists of an electrically insulating or dielectric material different from the insulating layer 81, such as a nitride or oxynitride, in particular silicon nitride, or aluminum oxide, hafnium oxide, or the like.

[0087] The insulating layer 82 may have a thickness comprised between 0.01 μm and 5 μm, for example.

[0088] The insulating layer 82 extends conformally over the insulating layer 81 , and in particular to the insulating layer 81 .

[0089] In this embodiment, insulating layer 82 also extends partially directly onto the top 70 of metal contact region 65 and partially onto front surface 53a along the outer periphery of insulating layers 80, 81.

[0090] In particular, insulating layer 82 includes a portion 82A facing metal regions 65, 72 at a distance along the Z axis and extending above metal regions 65, 72, and a portion 82B extending laterally and adjacent to portion 82A onto portion 81B of insulating layer 81.

[0091] The insulating layer 83, also called passivation layer, consists of an electrically insulating or dielectric material, in particular an organic material, more particularly a polymeric material, such as for example polyimide (for example PIX).

[0092] The insulating layer 83 may have a planarized upper surface.

[0093] The insulating layer 83 may have a thickness comprised between 1 μm and 20 μm, for example.

[0094] Insulating layer 83 includes portions 83A, 83B that completely cover insulating layer 82, and in particular overlie respective portions 82A, 82B.

[0095] The insulating layer 83 may extend partially over the active region 54, directly onto the tops 70 of the metal contact regions 65, and partially over the edge regions 55 directly onto the front surface 53a.

[0096] In fact, the insulating layer 82 extends between the passivation layer 83 and the underlying insulating layers (80, 81) and favors adhesion of the overlying passivation layer 83.

[0097] One or more further protective insulating layers, not shown here, of a resin such as Bakelite, may extend above passivation layer 83 to package electronic device 50 .

[0098] In electronic device 50, the presence of metal field plate region 72, which is thinner than metal contact region 65, makes it possible to reduce the risk of cracks in insulating layers 80-83, and in particular insulating layer .

[0099] In fact, the thickness of field plate region 72 forms a step inside the insulating region formed by insulating layers 80-83, particularly at the boundary between each portion 81A, 82A facing metal field plate region 72 and each adjacent portion 81B, 82B. The fact that the thickness of field plate region 72 is smaller than the thickness of metal contact region 65 reduces the height of the step and, therefore, the risk of cracking.

[0100] This risk may be particularly reduced if the overlying insulating region includes a nitride layer (eg, insulating layer 82) that is thin and conforms to the profile of the underlying layer.

[0101] The risk of cracking can remain low even after numerous thermal cycles and / or harsh environmental conditions.

[0102] The absence of cracks ensures high electrical robustness of the electronic device 50 during use. Indeed, even when high voltages are present in the peripheral parts of the insulating layers 80-83, which may cause delamination, the metal areas 65, 72 can remain protected from electrical discharges that may cause malfunction or damage to the electronic device 50.

[0103] Additionally, anode termination region 62 can at least partially shield overlying metal contact region 65 from high electric fields that may develop within semiconductor body 53 during use, particularly under reverse bias, which contributes to increasing the electrical robustness of electronic device 50 during use.

[0104] This effect occurs when the anode termination region 62 has a high doping level (e.g., 10 17 ~10 21 atoms / cm 3It may be even more advantageous if the compound has a structure such that

[0105] The presence of the triple insulating layer (insulating layers 80-83) further protects the electronic device 50 from the external environment, and in particular prevents moisture from reaching the high voltage structures and metallization (65, 72).

[0106] This protection can be enhanced when insulating layer 81 surrounds and seals the periphery of metallization 65, when insulating layer 82 surrounds and seals insulating layer 81 at both the top and its side edges, and especially when insulating layer 83 surrounds and seals insulating layer 82 at both the top and its side edges.

[0107] 3A-3F, the steps for fabricating electronic device 50 will now be described, focusing on those steps useful for understanding the present disclosure.

[0108] Referring to FIG. 3A, wafer 100 is first processed to form JB elements 59, anode termination regions 62, and edge termination regions 63 in a semiconductor body 53 of SiC in a manner known per se.

[0109] Next, in FIG. 3B, an insulating layer 80 is formed on the front surface 53a.

[0110] Insulating layer 80 may be formed by blanket deposition of an insulating or dielectric material, for example by CVD (chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition), followed by patterning (eg, lithography and etching).

[0111] Referring to FIG. 3C, a metal layer 67, for example of titanium or nickel, is deposited on wafer 100 over front surface 53a and insulating layer 80, and a top metal layer 105 (forming top portion 70 of metal contact region 65 in FIG. 1) is deposited on metal layer 67.

[0112] In particular, the metal layers 67, 105 are blanket deposited by evaporation or sputtering.

[0113] Next, in FIG. 3D, top metal layer 105 is patterned by lithography and etching steps in such a way as to form upper portions 70 of metal contact regions 65 that extend above active region 54 and partially onto anode termination region 62.

[0114] Partial removal of the top metal layer 105 exposes the underlying metal layer 67 above the edge region 55 .

[0115] In FIG. 3E, metal layer 67 is patterned by lithography and etching steps in such a way as to form field plate regions 72.

[0116] Thereafter, in FIG. 3F, insulating layers 81, 82, 83 are formed, for example by deposition and subsequent patterning.

[0117] The manufacturing process then continues with subsequent steps to form further elements of the electronic device 50 (e.g., to form the ohmic contact layer 56 and the cathode metallization 57) that are not described in detail here, as well as dicing the wafer 100 to form the electronic device 50.

[0118] The present manufacturing process allows the electronic device 50 to be obtained in a simple and cost-effective manner.

[0119] In particular, the fact of forming field plate region 72 starting from the same metal layer 67 used for metal contact region 65 makes it possible to easily obtain a metal field plate region that is thinner than metal contact region 65.

[0120] In fact, maintaining a thickness greater than that of the metal contact region 65 can facilitate electrical connection operations (eg, by wire bonding) of the electronic device 50 .

[0121] Finally, it will be apparent that modifications and variations can be made to the electronic devices and manufacturing processes described and illustrated herein without departing from the scope of the present disclosure, as defined in the appended claims.

[0122] For example, the insulating region above front surface 53a may include a different number of insulating layers made from different materials, in particular two insulating layers (e.g., only layers 82 and 83) above metal regions 65, 82. For example, layer 81 may not be present, in which case layer 82 (e.g., nitride or oxynitride) may extend directly over metal regions 65, 72 and over portion 80B of metal layer 80.

Claims

1. 1. An electronic device comprising: a semiconductor body of silicon carbide having a front surface and a first conductivity type, the semiconductor body containing an active region and an edge region lateral to the active region along a first direction; a first termination doped region extending from the front side into the semiconductor body and at least partially into the edge region, the first termination doped region having a second conductivity type different from the first conductivity type; a first metal region extending on the front surface of the semiconductor body above the active region and the first termination doped region, the first metal region having a first thickness and being terminated above the first termination doped region along the first direction; a second metal region extending transversely to the first metal region along the first direction above the edge region and at a distance from the front surface; Equipped with the second metal region has a second thickness that is less than the first thickness; Electronic devices.

2. 10. The electronic device of claim 1, further comprising an insulating region having a first portion extending over the first metal region and the second metal region, and a second portion extending on the front surface transversely to the first portion along the first direction and above the edge region.

3. The electronic device of claim 1 , wherein the first metal region has a thickness of 2 μm or greater.

4. The electronic device according to claim 1, wherein said second metal region has a thickness comprised between 10 nm and 200 nm.

5. The electronic device of claim 1 , wherein the second metal region is in electrical contact with the first metal region.

6. 2. The electronic device of claim 1, wherein the first metal region comprises a first metal layer and a second metal layer on the first metal layer, and the second metal region comprises a third metal layer adjacent to the first metal layer and made of the same material as the first metal layer.

7. The first termination doped region is 10 １７ atoms / cm ３ 10. The electronic device of claim 1, having a doping level greater than

8. 2. The electronic device according to claim 1, wherein the electronic device is a JBS or MPS type Schottky diode.

9. 2. The electronic device of claim 1, wherein the first metal region makes Schottky contact with the semiconductor body in the active region.

10. 2. The electronic device of claim 1, further comprising a plurality of barrier-doped regions extending from said front surface into said active region of said semiconductor body at a distance from one another along said first direction, said barrier-doped regions having said second conductivity type.

11. 1. A method of manufacturing an electronic device, comprising: starting with a semiconductor body of silicon carbide having a front surface and a first conductivity type, the semiconductor body containing an active region and an edge region lateral to the active region along a first direction; forming a first termination doped region in the semiconductor body from the front side and extending at least partially into the edge region, the first termination doped region having a second conductivity type different from the first conductivity type; forming a first metal region extending on the front surface of the semiconductor body above the active region and the first termination doped region, the first metal region having a first thickness and terminating above the first termination doped region along the first direction; forming a second metal region above the edge region at a distance from the front surface, the second metal region extending transversely to the first metal region along the first direction; Including, the second metal region has a second thickness that is less than the first thickness; Manufacturing method.

12. forming a first metal region; depositing a first metal layer on the front side of the semiconductor body; depositing a second metal layer on the first metal layer, the second metal layer having a thickness greater than that of the first metal layer; The method of claim 11 , comprising:

13. The method of claim 12 , wherein the second metal region is formed by a portion of the first metal layer by patterning the first metal layer.

14. forming a second metal region; forming a first insulating layer on the front side prior to depositing the first metal layer; depositing the first metal layer over a portion of the first insulating layer; The method of claim 12, comprising:

15. forming the first metal region and the second metal region; performing a blanket deposition of the first metal layer; performing a blanket deposition of the second metal layer on the first metal layer; Etching the second metal layer; etching the first metal layer after etching the second metal layer so that the first metal region includes a first portion of the first metal layer extending on the front surface and a portion of the second metal layer extending over the first portion of the first metal layer, and so that the second metal region includes a second portion of the first metal layer extending at a distance from the front surface; The method of claim 12, comprising:

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