Semiconductor device

Abstract

To achieve both reduction in on-resistance and suppression of reduction in breakdown voltage.SOLUTION: The semiconductor device 10 includes a semiconductor layer including a cell region 21, a plurality of first trenches 60 provided in the cell region 21 and spaced apart from each other in a plan view, a second trench provided in the cell region 21 and connecting adjacent first trenches 60 of the plurality of first trenches 60, a first insulating layer provided in the first trench 60, a second insulating layer provided in the second trench, a field plate electrode 110 embedded in the first insulating layer in the first trench 60, and a gate electrode including a first gate portion 121 embedded in the first insulating layer in the first trench 60 and a second gate portion 122 embedded in the second insulating layer in the second trench and connected to the first gate portion 121.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having multiple trench gate structures formed in a stripe pattern, each of which includes a gate trench and two electrodes embedded in the gate trench and separated in the depth direction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-125649

[0004] [overview] In semiconductor devices, there is room for improvement in achieving both a reduction in on-resistance and suppression of a decrease in breakdown voltage.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer including a cell region, a plurality of first trenches provided in the cell region and spaced apart from each other in a planar view, a second trench provided in the cell region and connecting adjacent first trenches among the plurality of first trenches, a first insulating layer provided in the first trench, a second insulating layer provided in the second trench, a field plate electrode embedded in the first insulating layer within the first trench, a first gate portion embedded in the first insulating layer within the first trench, and a second gate portion embedded in the second insulating layer within the second trench and connected to the first gate portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2]FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic plan view showing an enlarged view of a part of the cell region and the outer periphery region of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic plan view showing an enlarged electrode structure in the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic perspective view showing the positional relationship between a part of the gate electrode and the field plate electrode. [Figure 8] FIG. 8 is a schematic cross-sectional view of the semiconductor device taken along line F8-F8 in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view illustrating a manufacturing process of an exemplary method for manufacturing a semiconductor device according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16] FIG. 16 is a schematic plan view of a semiconductor device of a comparative example. [Figure 17] FIG. 17 is a schematic cross-sectional view of the semiconductor device of the comparative example taken along line F17-F17 in FIG. [Figure 18]FIG. 18 is a schematic cross-sectional view showing an enlarged view of a first trench and its periphery in a semiconductor device according to a modified example. [Figure 19] FIG. 19 is a schematic plan view showing an enlarged view of a part of the cell region and the outer periphery region in a semiconductor device according to a modified example. [Figure 20] FIG. 20 is a schematic cross-sectional view of the semiconductor device taken along line F20-F20 in FIG. [Figure 21] FIG. 21 is a schematic plan view showing an enlarged view of a part of the cell region and the outer periphery region in a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, depth, length) of A are equal to the dimensions (width, depth, length) of B" or "the dimensions (width, depth, length) of A and the dimensions (width, depth, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, depth, length) of A and the dimensions (width, depth, length) of B is, for example, within 10% of the dimensions (width, depth, length) of A.

[0011] <Embodiment> [Overall planar structure of semiconductor device] The planar structure of an exemplary semiconductor device 10 according to one embodiment will be described with reference to Fig. 1. Fig. 1 schematically illustrates the planar structure of the semiconductor device 10. In Fig. 1, a portion of the internal structure of the semiconductor device 10 is indicated by dashed lines. As will be described below, the semiconductor device 10 may be configured as a trench-gate MISFET.

[0012] As shown in FIG. 1, the semiconductor device 10 includes a semiconductor layer 20. The semiconductor layer 20 may be made of a material containing, for example, silicon (Si). The semiconductor layer 20 is flat, with the Z direction in FIG. 1 as its thickness direction. Hereinafter, two mutually orthogonal directions perpendicular to the Z direction will be referred to as the "X direction" and the "Y direction." Furthermore, the term "planar view" used in this specification refers to viewing the semiconductor device 10 from the Z direction, unless explicitly stated otherwise.

[0013] The semiconductor layer 20 has, for example, a rectangular shape in a plan view. The semiconductor layer 20 includes a first surface 20S, a second surface 20R (see FIG. 2) facing the opposite side from the first surface 20S, and first to fourth side surfaces 20A to 20D connecting the first surface 20S and the second surface 20R. The first side surface 20A and the second side surface 20B constitute both end surfaces of the semiconductor layer 20 in the X direction. The third side surface 20C and the fourth side surface 20D constitute both end surfaces of the semiconductor layer 20 in the Y direction.

[0014] The semiconductor layer 20 includes a cell region 21 indicated by a dashed line in FIG. 1 and a peripheral region 22 surrounding the cell region 21 in a planar view. The cell region 21 is a region having transistor cells. In one example, the cell region 21 has a polygonal shape having four sides parallel to the first to fourth side surfaces 20A to 20D in a planar view. In the example shown in FIG. 1, the cell region 21 has a quadrangular shape in a planar view. The peripheral region 22 has an annular shape extending along the first to fourth side surfaces 20A to 20D so as to surround the cell region 21 in a planar view. In the example shown in FIG. 1, the peripheral region 22 has a quadrangular annular shape in a planar view.

[0015] The semiconductor device 10 includes an insulating layer 30 located on the first surface 20S of the semiconductor layer 20. In one example, the insulating layer 30 may include at least one of a silicon oxide (SiO) layer, a silicon nitride (SiN) layer, and a silicon oxynitride (SiON) layer.

[0016] The semiconductor device 10 may include a gate wiring 40 located on the insulating layer 30. The gate wiring 40 can be said to be provided on the semiconductor layer 20. The gate wiring 40 is disposed in the peripheral region 22. The gate wiring 40 may include a gate pad portion 44 and first to third gate wiring portions 41 to 43. In one example, the first to third gate wiring portions 41 to 43 and the gate pad portion 44 are integrated.

[0017] The gate pad portion 44 is arranged near a corner portion of the semiconductor device 10 in a plan view. In one example, the gate pad portion 44 is arranged near a corner portion defined by the first side surface 20A and the fourth side surface 20D of the semiconductor layer 20 in a plan view. The first gate wiring portion 41 is arranged near the first side surface 20A of the semiconductor layer 20. The first gate wiring portion 41 extends along the Y direction in a plan view. The first gate wiring portion 41 is connected to the gate pad portion 44. The first gate wiring portion 41 extends throughout the entire cell region 21 in the Y direction. The second gate wiring portion 42 is arranged near the second side surface 20B of the semiconductor layer 20. The second gate wiring portion 42 extends along the Y direction in a plan view. The second gate wiring portion 42 extends throughout the entire cell region 21 in the Y direction. The third gate wiring portion 43 is arranged near the fourth side surface 20D of the semiconductor layer 20. The third gate wiring portion 43 extends along the X direction in a plan view. The third gate wiring portion 43 connects the gate pad portion 44 and the second gate wiring portion 42. As described above, in the example shown in Fig. 1, the gate wiring 40 has a concave shape that surrounds the cell region 21 from the first side surface 20A, the fourth side surface 20D, and the second side surface 20B in a planar view. Note that the shape of the gate wiring 40 in a planar view is not limited to the example shown in Fig. 1 and can be changed as desired.

[0018] The semiconductor device 10 may include a source wiring 50 located on the insulating layer 30. In other words, the source wiring 50 can be said to be provided on the semiconductor layer 20. The source wiring 50 is located apart from the gate wiring 40. The source wiring 50 may include an inner source wiring portion 51 and a peripheral source wiring portion 52. In one example, the inner source wiring portion 51 and the peripheral source wiring portion 52 are integrated. The inner source wiring portion 51 may be at least partially surrounded by the gate wiring 40 in a planar view. The inner source wiring portion 51 is provided so as to cover the entire cell region 21 in a planar view. A portion of the inner source wiring portion 51 is provided at a position overlapping the peripheral region 22 in a planar view. The inner source wiring portion 51 provided at a position overlapping the peripheral region 22 in a planar view is connected to the peripheral source wiring portion 52. The peripheral source wiring portion 52 may surround the gate wiring 40 in a planar view. The peripheral source wiring portion 52 is provided in the peripheral region 22. 1, the peripheral source wiring portion 52 has a rectangular ring shape in plan view that surrounds the gate wiring 40. The shape of the source wiring 50 in plan view is not limited to the example shown in FIG. 1 and can be changed as desired.

[0019] The semiconductor device 10 includes a first trench 60 and a second trench 70 provided in the semiconductor layer 20. The first trenches 60 and the second trenches 70 are indicated by dashed lines in Fig. 1. As shown in Fig. 1, a plurality of the first trenches 60 and a plurality of the second trenches 70 are provided.

[0020] Each of the multiple first trenches 60 and the multiple second trenches 70 is provided in the cell region 21. The multiple first trenches 60 are arranged spaced apart from one another in the X and Y directions in a plan view. In the example shown in FIG. 1, the multiple first trenches 60 are arranged in a matrix. Each first trench 60 has a polygonal shape in a plan view. In the example shown in FIG. 1, each first trench 60 has a rectangular shape in a plan view. The multiple second trenches 70 connect adjacent first trenches 60 among the multiple first trenches 60.

[0021] The semiconductor device 10 may include a third trench 80 and a peripheral trench 90 provided in the semiconductor layer 20. In FIG. 1, the third trench 80 and the peripheral trench 90 are indicated by dashed lines. As shown in FIG. 1, a plurality of third trenches 80 are provided. The plurality of third trenches 80 are arranged spaced apart from each other in the Y direction. The plurality of third trenches 80 are provided corresponding to the first trenches 60 arranged in the Y direction.

[0022] Each of the multiple third trenches 80 extends from the cell region 21 to the periphery region 22. That is, each third trench 80 extends so as to straddle the boundary between the cell region 21 and the periphery region 22 in plan view.

[0023] The peripheral trench 90 is provided in the peripheral region 22. In plan view, the peripheral trench 90 has an annular shape surrounding the cell region 21. Details of the trench structure including the first trench 60, the second trench 70, the third trench 80, and the peripheral trench 90 will be described later with reference to FIGS.

[0024] The semiconductor device 10 includes a mesa region 23. The mesa region 23 is provided in the semiconductor layer 20 between the multiple first trenches 60 in a plan view and at a position different from the second trenches 70. The mesa region 23 is a region including the first surface 20S of the semiconductor layer 20. The mesa region 23 includes a region of the semiconductor layer 20 defined by the multiple first trenches 60 and the multiple second trenches 70. A plurality of mesa regions 23 are provided and spaced apart from each other in the X direction and the Y direction. In the example shown in FIG. 1, the multiple mesa regions 23 are arranged in a matrix.

[0025] In one example, the multiple mesa regions 23 include multiple inner mesa regions 23A, multiple outer mesa regions 23B, and multiple corner mesa regions 23C. The multiple inner mesa regions 23A are mesa regions arranged inside the cell region 21. Each inner mesa region 23A is cross-shaped in plan view. The multiple outer mesa regions 23B are arranged on the outer periphery of the cell region 21. Each outer mesa region 23B includes a convex portion in plan view. The multiple corner mesa regions 23C are mesa regions provided at the four corners of the cell region 21. Each corner mesa region 23C is L-shaped in plan view.

[0026] [Cross-sectional structure of semiconductor device] The schematic cross-sectional structure of the semiconductor device 10 will be described with reference to Fig. 2. Fig. 2 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F2-F2 in Fig. 1. Fig. 2 schematically shows an enlarged cross-sectional structure of one first trench 60 and its surroundings.

[0027] 2, the semiconductor layer 20 includes an n-type drain region 24. The drain region 24 may include at least a portion of the second surface 20R of the semiconductor layer 20. The n-type impurity concentration of the drain region 24 is 1×10 18 cm -3 More than 1×10 20 cm -3 The drain region 24 may have a thickness of 40 μm or more and 450 μm or less.

[0028] The semiconductor layer 20 includes an n-type drift region 25. The drift region 25 is provided on the drain region 24. The drift region 25 may contain n-type impurities at a concentration lower than that of the drain region 24. The n-type impurity concentration of the drift region 25 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 25 may have a thickness of 1 μm or more and 25 μm or less.

[0029] The semiconductor layer 20 includes a p-type body region 26. The body region 26 is provided on the drift region 25. The body region 26 is provided in a surface portion of the semiconductor layer 20 closer to the first surface 20S. The body region 26 is provided in the mesa region 23. The p-type impurity concentration of the body region 26 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 26 may have a thickness of at least 0.5 μm and at most 1.5 μm.

[0030] The semiconductor layer 20 includes an n-type source region 27. The source region 27 is provided in a surface portion of the body region 26. The source region 27 is provided over the entire surface portion of the body region 26. Therefore, it can be said that the source region 27 is provided on the body region 26. The source region 27 may include at least a part of the first surface 20S of the semiconductor layer 20. The source region 27, like the body region 26, is provided in the mesa region 23. In other words, it can be said that the mesa region 23 includes the body region 26 and the source region 27. The source region 27 may contain n-type impurities at a higher concentration than the drift region 25. The n-type impurity concentration of the source region 27 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 27 may have a thickness of 0.1 μm or more and 1 μm or less.

[0031] In one example, the drain region 24 may be formed of a semiconductor substrate. The drain region 24 may be formed of a Si substrate as the semiconductor substrate. The drift region 25, the body region 26, and the source region 27 may be formed of epitaxial layers. The drift region 25, the body region 26, and the source region 27 may be formed of Si epitaxial layers.

[0032] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0033] The semiconductor device 10 may include a drain electrode 28 provided on the second surface 20R of the semiconductor layer 20. The drain electrode 28 is in contact with the second surface 20R. This electrically connects the drain electrode 28 to the drain region 24. The drain electrode 28 may be made of at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0034] [Trench structure] The trench structure provided in the semiconductor layer 20 will be described with reference to FIGS. FIG. 3 schematically shows the planar structure of trenches and contacts in the cell region 21 and a portion of the peripheral region 22. FIG. 4 schematically shows the planar structure of electrodes in the trench structure in the cell region 21 and a portion of the peripheral region 22. FIG. 5 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F5-F5 in FIG. 3. FIG. 6 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F6-F6 in FIG. 3. FIG. 7 schematically shows a perspective view of a portion of the gate electrode 120 and the field plate electrode 110. FIG. 8 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F8-F8 in FIG. 3. FIG. 9 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F9-F9 in FIG. 3.

[0035] (Trench structure of trenches 1 to 3) As shown in FIG. 3, each first trench 60 has a quadrangular shape in plan view. Each first trench 60 includes a pair of sides extending along the X direction and a pair of sides extending along the Y direction. In the example shown in FIG. 3, each first trench 60 has a square shape in plan view. Note that each first trench 60 may have a rectangular shape in plan view. In this case, each first trench 60 may have a rectangular shape with its longer side extending in the X direction in plan view, or may have a rectangular shape with its longer side extending in the Y direction in plan view.

[0036] 1, the multiple first trenches 60 include multiple first outer end trenches 60A located on the outermost periphery of the cell region 21 and multiple first inner trenches 60B located inward from the first outer end trenches 60A. The first outer end trenches 60A and the first inner trenches 60B have the same structure. Therefore, in the following description, when a description is common to both the first outer end trenches 60A and the first inner trenches 60B, the first trenches 60 will be used.

[0037] 3, adjacent first inner trenches 60B among the multiple first inner trenches 60B are connected in the X and Y directions by multiple second trenches 70. That is, one first inner trench 60B is connected to four second trenches 70. In other words, four second trenches 70 communicate with one first inner trench 60B.

[0038] As shown in FIG. 1, among the multiple first outer end trenches 60A, first outer end trenches 60A adjacent to each other in the X direction are connected in the X direction by second trenches 70. As shown in FIGS. 1 and 3, among the multiple first outer end trenches 60A, first outer end trenches 60A adjacent to each other in the Y direction are connected in the Y direction by second trenches 70. Two or three second trenches 70 are connected to each first outer end trench 60A. In other words, two or three second trenches 70 are connected to one first outer end trench 60A. Specifically, two second trenches 70 are connected to the first outer end trenches 60A arranged at both ends in the Y direction among the first outer end trenches 60A. Three second trenches 70 are connected to the remaining first outer end trenches 60A. Furthermore, third trenches 80 are connected to the first outer end trenches 60A arranged at both ends in the X direction of the cell region 21. Since there is no first trench 60 on the side where the third trench 80 extends relative to the first outer end trench 60A, the two or three second trenches 70 are connected to a side of one first outer end trench 60A in plan view that is different from the side to which the third trench 80 is connected.

[0039] As shown in FIG. 1, an end trench 100 is connected to a first outer end trench 60A arranged at an end of the cell region 21 closer to the third side surface 20C in the Y direction. The end trench 100 extends in the Y direction from the cell region 21 toward the outer periphery region 22. The end trench 100 is provided within the cell region 21. In other words, the tip of the end trench 100 is located closer to the cell region 21 than the boundary between the cell region 21 and the outer periphery region 22. The end trench 100 is connected to a side of the first outer end trench 60A that is different from the side to which the two second trenches 70 and the third trench 80 are connected (the side closer to the third side surface 20C in the example shown in FIG. 1).

[0040] As shown in FIG. 3 , the distance between adjacent first trenches 60 (hereinafter, “first trench distance DT”) is smaller than the width W1 of the first trenches 60. Here, the first trench distance DT can be defined by the distance between adjacent first trenches 60 in the X-axis direction or the distance between adjacent first trenches 60 in the Y-axis direction. The first trench distance DT can be said to be equal to the length L2 of the second trench 70. Also, in one example, the first trench distance DT is larger than the width W2 of the second trench 70. Also, in one example, the first trench distance DT is larger than the distance DC between the field plate electrode 110 and the sidewall 61 of the first trench 60. In other words, the first trench distance DT is larger than the thickness of the field insulating portion 31B. Here, the length L2 of the second trench 70 can be defined by the dimension in the arrangement direction of the adjacent first trenches 60 connected by the second trench 70. The width W2 of the second trench 70 can be defined as the dimension in a direction perpendicular to the length L2 of the second trench 70 in a plan view.

[0041] 2, the first trench 60 extends in the Z direction from the first surface 20S toward the second surface 20R of the semiconductor layer 20. The first trench 60 penetrates the source region 27 and the body region 26 in the Z direction and reaches the drift region 25.

[0042] The first trench 60 includes four side walls 61 and a bottom wall 62. In the example shown in FIG. 2, each side wall 61 extends along the Z direction. The bottom wall 62 is configured with a flat surface perpendicular to the Z direction. The shape of the first trench 60 is not limited to the shape shown in FIG. 2 and can be arbitrarily changed. In one example, the four side walls 61 may be inclined so that the opening area of ​​the first trench 60 gradually decreases from the first surface 20S toward the bottom wall 62. In one example, the bottom wall 62 may be curved so as to convex downward. In one example, the corner portions between each side wall 61 and the bottom wall 62 may be curved so as to convex outward.

[0043] As shown in FIG. 5, the second trench 70 extends in the Z direction from the first surface 20S toward the second surface 20R of the semiconductor layer 20. The second trench 70 penetrates the source region 27 and the body region 26 in the Z direction to reach the drift region 25. The depth H2 of the second trench 70 is shallower than the depth H1 of the first trench 60 (see FIG. 2). The width W2 of the second trench 70 is smaller than the width W1 of the first trench 60 (see FIG. 2). As shown in FIG. 3, the width W2 of the second trench 70 is smaller than the length L2 of the second trench 70.

[0044] 3, in one example, the second trench 70 extending in the Y direction is connected to the center in the X direction of the first trench 60. In one example, the second trench 70 extending in the X direction is connected to the center in the Y direction of the first trench 60.

[0045] As shown in FIG. 5, the second trench 70 includes two side walls 71 and a bottom wall 72. The two side walls 71 are provided to face each other in a direction perpendicular to the direction in which the second trench 70 extends (the length direction) in a plan view. In the example shown in FIG. 5, each side wall 71 extends along the Z direction. The bottom wall 72 is configured by a flat surface perpendicular to the Z direction. The shape of the second trench 70 is not limited to the shape shown in FIG. 5 and can be arbitrarily changed. In one example, the two side walls 71 may be inclined so that the opening area of ​​the second trench 70 gradually decreases from the first surface 20S toward the bottom wall 72. In one example, the bottom wall 72 may be curved so as to be convex downward. In one example, the corner portions between each side wall 71 and the bottom wall 72 may be curved so as to be convex outward.

[0046] As shown in FIGS. 3 and 6, the third trench 80, like the second trench 70, extends in the Z direction from the first surface 20S of the semiconductor layer 20 toward the second surface 20R. The portion of the third trench 80 disposed in the cell region 21 penetrates the source region 27 and the body region 26 (both see FIG. 5) in the Z direction and reaches the drift region 25. The depth H3 of the third trench 80 is shallower than the depth H1 of the first trench 60 (see FIG. 2). In one example, the depth H3 of the third trench 80 is equal to the depth H2 of the second trench 70 (see FIG. 5). The width W3 of the third trench 80 shown in FIG. 3 is equal to the width W2 of the second trench 70.

[0047] 6, the third trench 80 extends from the cell region 21 to a position where it overlaps with the second gate wiring portion 42 of the gate wiring 40 in a plan view. On the other hand, the third trench 80 is disposed inward from the peripheral source wiring portion 52 of the source wiring 50. As shown in FIG. 3, the length L3 of the third trench 80 is longer than the length L2 of the second trench 70.

[0048] The third trench 80 includes three side walls 81 and a bottom wall 82. Two of the three side walls 81 facing each other are provided to face each other in a direction perpendicular to the extension direction of the third trench 80 in a plan view. In the example shown in FIG. 6, each side wall 81 extends along the Z direction. The bottom wall 82 is configured by a flat surface perpendicular to the Z direction. The shape of the third trench 80 is not limited to the shape shown in FIG. 6 and can be arbitrarily changed. In one example, the two facing side walls 81 may be inclined so that the opening area of ​​the third trench 80 gradually decreases from the first surface 20S toward the bottom wall 82. In one example, the bottom wall 82 may be curved so as to convex downward. In one example, a corner portion between each side wall 81 and the bottom wall 82 may be curved so as to convex outward.

[0049] 2 and 5, the semiconductor device 10 includes a first insulating layer 31 provided in the first trench 60 and a second insulating layer 32 provided in the second trench 70. Furthermore, as shown in FIG. 6, the semiconductor device 10 may include a third insulating layer 33 provided in the third trench 80. It can also be said that the insulating layer 30 includes the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33. Therefore, the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may include at least one of an SiO layer, a SiN layer, and an SiON layer. In one example, the first to third insulating layers 31 to 33 are made of the same material.

[0050] 2 and 6, the semiconductor device 10 includes a field plate electrode 110 embedded in a first insulating layer 31 and a gate electrode 120 embedded in an insulating layer 30. The field plate electrode 110 is provided in a first trench 60. The gate electrode 120 is provided across the first trench 60, the second trench 70, and the third trench 80. The gate electrode 120 can also be said to be embedded in the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33. The field plate electrode 110 and the gate electrode 120 are made of, for example, the same material. The field plate electrode 110 and the gate electrode 120 are made of, for example, conductive polysilicon.

[0051] 2, the field plate electrode 110 has a needle shape extending in the Z direction. In the example shown in Figures 2 and 7, the field plate electrode 110 has a quadrangular prism shape extending in the Z direction.

[0052] 2, the field plate electrode 110 includes an upper surface 111 and a lower surface 112. The upper surface 111 of the field plate electrode 110 is located, for example, below the first surface 20S of the semiconductor layer 20 in the Z direction. The upper surface 111 of the field plate electrode 110 is located, for example, above the boundary BD between the source region 27 and the body region 26. The lower surface 112 of the field plate electrode 110 is located away from the bottom wall 62 of the first trench 60 in the Z direction.

[0053] The shape of the field plate electrode 110 is not limited to a quadrangular prism and can be changed as desired. For example, the field plate electrode 110 may have a truncated quadrangular pyramid shape that tapers from the upper surface 111 to the lower surface 112.

[0054] 6, the gate electrode 120 includes a first gate portion 121 and a second gate portion 122. The second gate portion 122 is connected to the first gate portion 121. In one example, the first gate portion 121 and the second gate portion 122 are integrated.

[0055] The first gate portion 121 is provided in the first trench 60. The first gate portion 121 is buried in the first insulating layer 31. A plurality of first gate portions 121 are provided corresponding to the plurality of first trenches 60. As shown in FIG. 8, the plurality of first gate portions 121 are arranged at the same positions as each other in the Z direction.

[0056] 4 and 7, the first gate portion 121 has an annular shape surrounding the field plate electrode 110 in a plan view. In one example, the first gate portion 121 has a rectangular annular shape in a plan view. More specifically, the first gate portion 121 has a rectangular annular shape extending along the four sidewalls 61 of the first trench 60 in a plan view. The first gate portion 121 is disposed at a distance from the field plate electrode 110 in a plan view.

[0057] 2, the first gate portion 121 includes an upper surface 121S and a lower surface 121R opposite to the upper surface 121S. The upper surface 121S of the first gate portion 121 is located lower than the first surface 20S of the semiconductor layer 20 in the Z direction, for example. The upper surface 121S of the first gate portion 121 can also be said to be located at the same position as the upper surface 111 of the field plate electrode 110 in the Z direction. The lower surface 121R of the first gate portion 121 is located lower than the boundary BD between the drift region 25 and the body region 26. The lower surface 121R of the first gate portion 121 is located higher than the lower surface 112 of the field plate electrode 110. Therefore, the thickness TG1 of the first gate portion 121 can be said to be thinner than the thickness TF of the field plate electrode 110.

[0058] 2, the width WG1 of the first gate portion 121 is smaller than the width WF of the field plate electrode 110. The relationship between the width WG1 of the first gate portion 121 and the width WF of the field plate electrode 110 can be changed as desired. In one example, the width WG1 of the first gate portion 121 may be equal to the width WF of the field plate electrode 110. In another example, the width WG1 may be larger than the width WF. The width WG1 of the first gate portion 121 and the width WF of the field plate electrode 110 may each be changed depending on, for example, the electrical characteristics required of the gate electrode 120 and the electrical characteristics required of the field plate electrode 110.

[0059] The first gate portion 121 is disposed opposite the field plate electrode 110 in a direction perpendicular to the Z direction. The first gate portion 121 is also disposed opposite the sidewall 61 of the first trench 60 in a direction perpendicular to the Z direction. A distance DA between the first gate portion 121 and the field plate electrode 110 in a plan view is greater than a distance DB that is the shortest distance between the first gate portion 121 and the sidewall 61 of the first trench 60.

[0060] As shown in FIG. 5, the second gate portion 122 is provided in the second trench 70. The second gate portion 122 is buried in the second insulating layer 32. As shown in FIG. 3, a plurality of second gate portions 122 are provided corresponding to the plurality of second trenches 70. The second gate portions 122 connect adjacent first gate portions 121 to each other. A width WG2 of the second gate portion 122 is smaller than a width W2 of the second trench 70. In the example shown in FIG. 3, the second gate portion 122 is disposed in the center of the second trench 70 in a plan view.

[0061] The second gate portion 122 includes an upper surface 122S and a lower surface 122R opposite to the upper surface 122S. The upper surface 122S of the second gate portion 122 is located lower than the first surface 20S of the semiconductor layer 20, for example, in the Z direction. The upper surface 122S of the second gate portion 122 can also be said to be located at the same position as the upper surface 111 of the field plate electrode 110 in the Z direction. The lower surface 122R of the second gate portion 122 can also be said to be located at the same position as the boundary BD between the drift region 25 and the body region 26 in the Z direction. The lower surface 122R of the second gate portion 122 can also be said to be located higher than the lower surface 121R of the first gate portion 121 (see FIG. 2 for both). Therefore, the thickness TG2 of the second gate portion 122 is thinner than the thickness TG1 of the first gate portion 121 (see FIG. 2).

[0062] 6, the gate electrode 120 includes a third gate portion 123. The third gate portion 123 is connected to the first gate portion 121. In one example, the third gate portion 123 is integrated with the first gate portion 121. The third gate portion 123 is connected to a portion of the first gate portion 121 that is different from the second gate portion 122. In other words, the third gate portion 123 is disposed apart from the second gate portion 122.

[0063] The third gate portion 123 is disposed at the same position as the second gate portion 122 in the Z direction. The third gate portion 123 includes an upper surface 123S and a lower surface 123R opposite to the upper surface 123S. The third gate portion 123 is buried in the third insulating layer 33. The upper surface 123S of the third gate portion 123 is disposed, for example, lower than the first surface 20S of the semiconductor layer 20 in the Z direction. It can also be said that the upper surface 123S of the third gate portion 123 is disposed at the same position as the upper surface 111 of the field plate electrode 110 in the Z direction. In this way, it can be said that the upper surfaces 121S, 122S, 123S of the first to third gate portions 121 to 123 are disposed at the same position as one another in the Z direction. The lower surface 123R of the third gate portion 123 is disposed at the same position as the boundary BD (see FIG. 5) between the drift region 25 and the body region 26 in the Z direction. It can be said that the lower surface 123R of the third gate portion 123 is located at the same position in the Z direction as the lower surface 122R of the second gate portion 122. Therefore, the thickness TG3 of the third gate portion 123 is equal to the thickness TG2 of the second gate portion 122. In other words, the thickness TG3 of the third gate portion 123 is thinner than the thickness TG1 of the first gate portion 121.

[0064] 4, a plurality of third gate portions 123 are provided corresponding to the plurality of third trenches 80. A width WG3 of the third gate portion 123 is smaller than a width W3 of the third trench 80. In the example shown in FIG. 4, the third gate portion 123 is disposed in the center of the third trench 80 in the width direction of the third trench 80 (the Y direction in FIG. 4) in a plan view.

[0065] 2, the first insulating layer 31 is provided on the sidewall 61 and bottom wall 62 of the first trench 60. The first insulating layer 31 is provided to insulate between the mesa region 23 and the first gate portion 121 and field plate electrode 110, and between the first gate portion 121 and the field plate electrode 110. Specifically, the first insulating layer 31 includes a gate insulating portion 31A, a field insulating portion 31B, and an electrode insulating portion 31C.

[0066] The gate insulating portion 31A is provided between the sidewall 61 of the first trench 60 and the first gate portion 121. In other words, the gate insulating portion 31A insulates the first gate portion 121 from the mesa region 23. The gate insulating portion 31A is in contact with both the sidewall 61 and the first gate portion 121. Here, a step portion 63 is provided at the upper end of the sidewall 61 of the first trench 60. The step portion 63 makes the opening area of ​​the first trench 60 larger above the step portion 63.

[0067] The field insulator 31B is provided between the sidewall 61 of the first trench 60 and the field plate electrode 110. That is, the field insulator 31B insulates the field plate electrode 110 from the mesa region 23. The field insulator 31B is in contact with both the sidewall 61 and the field plate electrode 110. The field insulator 31B is integrated with the gate insulator 31A. The thickness of the field insulator 31B (the dimension of the field insulator 31B in the X direction in FIG. 2) is greater than the thickness of the gate insulator 31A (the dimension of the gate insulator 31A in the X direction in FIG. 2). Furthermore, because the first trench 60 has a square (rectangular) shape in a plan view, the thickness of the field insulator 31B shown in FIG. 8, which cuts the first trench 60 diagonally, is greater than the thickness of the field insulator 31B shown in FIG. 2.

[0068] The electrode insulating portion 31C is provided between the field plate electrode 110 and the first gate portion 121. That is, the electrode insulating portion 31C insulates the field plate electrode 110 from the first gate portion 121. The electrode insulating portion 31C is in contact with both the field plate electrode 110 and the first gate portion 121. The electrode insulating portion 31C is integrated with the field insulating portion 31B. Because the distance DA between the first gate portion 121 and the field plate electrode 110 is greater than the distance DB between the first gate portion 121 and the sidewall 61, the thickness of the electrode insulating portion 31C (the dimension of the electrode insulating portion 31C in the X direction in FIG. 2) is greater than the thickness of the gate insulating portion 31A (the dimension of the gate insulating portion 31A in the X direction in FIG. 2).

[0069] 6 and 9, the second insulating layer 32 is provided to insulate the mesa region 23 from the second gate portion 122. As shown in Fig. 5, the second insulating layer 32 is provided between the sidewall 71 and bottom wall 72 of the second trench 70 and the second gate portion 122. The second insulating layer 32 is in contact with both the sidewall 71 and bottom wall 72 and the second gate portion 122.

[0070] 6, the third insulating layer 33 is provided to insulate the mesa region 23 from the third gate portion 123. The third insulating layer 33 is provided between the sidewall 81 and the bottom wall 82 of the third trench 80 and the third gate portion 123. The third insulating layer 33 is in contact with both the sidewall 81 and the bottom wall 82 and the third gate portion 123.

[0071] 3, the semiconductor device 10 includes a first source contact 131, a second source contact 132, and a gate contact 133. Each of the first source contact 131, the second source contact 132, and the gate contact 133 may be made of at least one of Ti, Al, Cu, tungsten (W), an Al alloy, and a Cu alloy. Here, the second source contact 132 is an example of a "source contact."

[0072] As shown in FIG. 6, the first source contact 131 connects the field plate electrode 110 and the source wiring 50. More specifically, the first source contact 131 connects the field plate electrode 110 and the inner source wiring portion 51. This electrically connects the field plate electrode 110 and the source wiring 50. The first source contact 131 penetrates the insulating layer 30 in the Z direction. A plurality of first source contacts 131 are provided corresponding to the plurality of field plate electrodes 110. As shown in FIG. 1, the plurality of first source contacts 131 are arranged in a matrix in a plan view.

[0073] As shown in FIG. 8 , the second source contact 132 connects the mesa region 23 and the source wiring 50. More specifically, the second source contact 132 is connected to the inner source wiring portion 51. The second source contact 132 penetrates the source region 27 in the mesa region 23 and reaches the body region 26. Meanwhile, the second source contact 132 is located above the drift region 25. Therefore, the second source contact 132 electrically connects the body region 26 and the source region 27 to the source wiring 50. The second source contact 132 penetrates the insulating layer 30. A plurality of second source contacts 132 are provided corresponding to the plurality of mesa regions 23. As shown in FIG. 1 , the plurality of second source contacts 132 are arranged in a matrix in a plan view.

[0074] 1, the shape of the second source contact 132 in a plan view varies depending on the position of the mesa region 23. More specifically, the second source contact 132 has a shape that follows the shape of the mesa region 23 in a plan view. That is, the second source contact 132 connected to the inner mesa region 23A, which is cross-shaped in a plan view, is cross-shaped in a plan view. The second source contact 132 connected to the outer mesa region 23B, which is convex in a plan view, is convex in a plan view. The second source contact 132 connected to the corner mesa region 23C, which is L-shaped in a plan view, is L-shaped in a plan view.

[0075] 8, the body region 26 includes a body contact region 29 in contact with the second source contact 132. The body contact region 29 has a higher p-type impurity concentration than the body region 26. The p-type impurity concentration of the body contact region 29 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 It can be as follows:

[0076] As shown in FIG. 6, the gate contact 133 connects the third gate portion 123 and the gate wiring 40. More specifically, the gate contact 133 is connected to a portion of the third gate portion 123 that is provided in the outer periphery region 22. The gate contact 133 is also connected to one of the first to third gate wiring portions 41 to 43 (see FIG. 1) of the gate wiring 40. In the example shown in FIG. 6, the gate contact 133 is connected to the second gate wiring portion 42. This electrically connects the third gate portion 123 and the gate wiring 40. In other words, the gate electrode 120 and the gate wiring 40 are electrically connected. The gate contact 133 penetrates the insulating layer 30 in the Z direction. A plurality of gate contacts 133 are provided, corresponding to the number of third gate portions 123.

[0077] As shown in FIG. 1, the end trench 100 extends from the first outer end trench 60A closer to the third side surface 20C of the semiconductor layer 20 toward the third side surface 20C in a plan view. A plurality of end trenches 100 are provided at the end closer to the third side surface 20C, corresponding to the plurality of first outer end trenches 60A spaced apart in the X direction. The end trench 100 includes sidewalls and a bottom wall. The shapes of the sidewalls and bottom wall of the end trench 100 are the same as, for example, the three sidewalls 81 and bottom wall 82 of the third trench 80 (see FIG. 6).

[0078] Although not shown, the semiconductor device 10 includes an edge insulating layer provided in the edge trench 100 and an edge gate electrode embedded in the edge insulating layer. The insulating layer 30 can also be said to include the edge insulating layer. The edge insulating layer may include at least one of an SiO2 layer, a SiN layer, and an SiON layer, for example. The edge insulating layer is provided to insulate the semiconductor layer 20 (mesa region 23) from the edge gate electrode. The edge gate electrode is connected to the first gate portion 121. The edge gate electrode is, for example, integrated with the first gate portion 121. The edge gate electrode extends from the first gate portion 121 toward the third side surface 20C.

[0079] (perimeter trench) 1 and 3 , the annular peripheral trench 90 includes recesses 93 that are recessed so as to avoid each of the multiple third trenches 80 in plan view. In other words, the peripheral trench 90 is provided so as to surround the third trench 80 with the recesses 93 in plan view. A plurality of recesses 93 are provided corresponding to the multiple third trenches 80.

[0080] 3, the peripheral trench 90 has a first width WA1 in a portion corresponding to the recessed portions 93 and a second width WA2 in a portion between adjacent recessed portions 93. The first width WA1 is smaller than the second width WA2.

[0081] As shown in FIGS. 6 and 9 , the peripheral trench 90 includes sidewalls 91 and a bottom wall 92. In the example shown in FIGS. 6 and 9 , each sidewall 91 extends along the Z direction. The bottom wall 92 is formed of a flat surface perpendicular to the Z direction. The bottom wall 92 is provided at the same position in the Z direction as the bottom wall 62 of the first trench 60. That is, the depth H4 of the peripheral trench 90 is the same as the depth H1 of the first trench 60 (see FIG. 2 ). The depth H4 of the peripheral trench 90 is deeper than both the depth H2 of the second trench 70 (see FIG. 5 ) and the depth H3 of the third trench 80. Note that the shape of the peripheral trench 90 is not limited to the shape shown in FIGS. 6 and 9 and can be arbitrarily modified. In one example, the two sidewalls 91 may be inclined so that the opening area of ​​the peripheral trench 90 gradually decreases from the first surface 20S toward the bottom wall 92. In one example, the bottom wall 92 may be curved to be convex downward. In one example, the corners between each side wall 91 and the bottom wall 92 may be curved to be convex outward.

[0082] The semiconductor device 10 includes a periphery insulating layer 140 provided in the periphery trench 90 and a periphery field plate electrode 150 embedded in the periphery insulating layer 140 within the periphery trench 90. It can be said that the insulating layer 30 includes the periphery insulating layer 140. The periphery insulating layer 140 may include, for example, at least one of an SiO layer, a SiN layer, and a SiON layer. The periphery insulating layer 140 is provided to insulate the periphery field plate electrode 150 from the semiconductor layer 20.

[0083] 1, the peripheral field plate electrode 150 has an annular shape surrounding the cell region 21 in plan view. As shown in FIG. 4, the peripheral field plate electrode 150 includes a plurality of electrode recesses 153 provided in a plurality of recesses 93 of the peripheral trench 90. Therefore, the peripheral field plate electrode 150 is provided so as to surround the third gate portion 123 in plan view. In one example, the electrode recesses 153 are formed along the recesses 93 of the peripheral trench 90 in plan view.

[0084] 4, the peripheral field plate electrode 150 has a first width WB1 in a portion corresponding to the electrode recesses 153 and a second width WB2 in a portion between adjacent electrode recesses 153. The first width WB1 is smaller than the second width WB2. In one example, the second width WB2 is larger than the width WF of the field plate electrode 110 (see FIG. 2). In one example, the first width WB1 is larger than the width WF of the field plate electrode 110.

[0085] The peripheral field plate electrode 150 includes an upper surface 151 and a lower surface 152 opposite to the upper surface 151. The upper surface 151 of the peripheral field plate electrode 150 is located, for example, below the first surface 20S of the semiconductor layer 20. The upper surface 151 of the peripheral field plate electrode 150 can also be said to be located at the same position in the Z direction as the upper surface 111 of the field plate electrode 110. The lower surface 152 of the peripheral field plate electrode 150 is located at the same position in the Z direction as the lower surface 112 of the field plate electrode 110. Therefore, the thickness TA of the peripheral field plate electrode 150 is equal to the thickness TF of the field plate electrode 110. By providing the peripheral field plate electrode 150 to surround the cell region 21 in this way, it is possible to suppress the influence of an external electric field on the cell region 21.

[0086] The semiconductor device 10 includes peripheral contacts 134. The peripheral contacts 134 are provided in the peripheral region 22. As shown in FIG. 1, a plurality of (four) peripheral contacts 134 are provided corresponding to the first to fourth side surfaces 20A to 20D of the semiconductor layer 20. The peripheral contacts 134 extend along the corresponding first to fourth side surfaces 20A to 20D. Each peripheral contact 134 may be made of at least one of Ti, Al, Cu, W, an Al alloy, and a Cu alloy.

[0087] 9, peripheral contact 134 connects peripheral field plate electrode 150 and peripheral source wiring portion 52 of source wiring 50. This electrically connects peripheral field plate electrode 150 and source wiring 50. Peripheral contact 134 penetrates insulating layer 30 in the Z direction.

[0088] [Method of manufacturing semiconductor device] An example of a method for manufacturing the semiconductor device 10 will be described with reference to Figures 10 to 15. Figures 10 to 15 schematically show cross-sectional structures for illustrating an example of a manufacturing process for a trench structure of one first trench 60 and two second trenches 70.

[0089] Although not shown, the manufacturing method of the semiconductor device 10 includes forming a semiconductor layer 820. Forming the semiconductor layer 820 includes forming a drain region. Forming the drain region includes, for example, preparing a semiconductor substrate. The semiconductor substrate may be, for example, a Si substrate. An n-type impurity is introduced into the semiconductor substrate.

[0090] Subsequently, forming the semiconductor layer 820 includes forming an epitaxial layer 821. The epitaxial layer 821 is formed by epitaxial growth on the semiconductor substrate. In one example, the epitaxial layer 821 is formed on the semiconductor substrate by chemical vapor deposition (CVD). In this case, n-type impurities in the semiconductor substrate are diffused into the epitaxial layer 821 by thermal diffusion. This forms an n-type drift region 825. Through the above steps, the semiconductor layer 820 is formed.

[0091] 10 , the method for manufacturing semiconductor device 10 includes forming first trench 60, forming first insulating layer 831, and forming field plate electrode 110. In one example, the method for manufacturing semiconductor device 10 is performed in the following order: forming first trench 60, forming first insulating layer 831, and forming field plate electrode 110.

[0092] To form the first trench 60, the epitaxial layer 821 is selectively removed by etching using a mask (not shown) of a predetermined pattern formed on the epitaxial layer 821 (first surface 820S of the semiconductor layer 820). In this way, the first trench 60 is formed.

[0093] Next, the first insulating layer 831 is formed so as to conform to the first surface 820S of the semiconductor layer 820 and the sidewall 61 and bottom wall 62 of the first trench 60. The first insulating layer 831 is SiO formed by, for example, thermal oxidation. In another example, the first insulating layer 831 may be formed by CVD.

[0094] Next, to form the field plate electrode 110, a conductive layer is first formed on the first insulating layer 831. Therefore, the conductive layer is filled into the recess space formed by the first insulating layer 831 in the first trench 60. The conductive layer is made of, for example, conductive polysilicon. Next, a portion of the conductive layer is removed by etching, thereby forming the field plate electrode 110.

[0095] Next, the manufacturing method of semiconductor device 10 includes partially removing first insulating layer 831. This exposes first surface 820S of semiconductor layer 820. Furthermore, a part of the opening side of sidewall 61 of first trench 60 is exposed. Furthermore, an upper portion of field plate electrode 110 is exposed.

[0096] 11, the method for manufacturing semiconductor device 10 includes forming an insulating layer 840. Insulating layer 840 is formed on first surface 820S of semiconductor layer 820 and to cover exposed sidewalls 61 in first trench 60 and upper portions of field plate electrodes 110. Insulating layer 840 is SiO formed by, for example, thermal oxidation. In another example, insulating layer 840 may be formed by CVD.

[0097] 11 and 12, the manufacturing method of the semiconductor device 10 includes partially removing the insulating layer 840. In this step, as shown in FIG. 11, first, a hard mask 900 is formed on a portion of the insulating layer 840. The hard mask 900 is formed, for example, in a portion that overlaps the entire first trench 60 in a plan view. Next, as shown in FIG. 12, the portion of the insulating layer 840 that is exposed from the hard mask 900 is removed. This exposes the first surface 820S of the semiconductor layer 820 and a portion of the opening side of the sidewall 61 of the first trench 60. Meanwhile, the upper portion of the field plate electrode 110 is covered with the insulating layer 840.

[0098] 13, the manufacturing method for the semiconductor device 10 includes forming a second trench 70. In this step, the epitaxial layer 821 is selectively removed by etching using a mask (not shown) of a predetermined pattern formed on the epitaxial layer 821 (the first surface 820S of the semiconductor layer 820 shown in FIG. 12). As a result, the second trench 70 is formed.

[0099] As shown in FIG. 14, the method for manufacturing the semiconductor device 10 includes forming a second insulating layer 832 and forming a gate electrode 120. By forming the second insulating layer 832, for example, the second insulating layer 832 is formed in the second trench 70. The second insulating layer 832 is SiO formed by, for example, a thermal oxidation method. In another example, the second insulating layer 832 may be formed by a CVD method. In this process, a step portion 63 is formed in the first trench 60.

[0100] Next, forming the gate electrode 120 involves first forming a recess in the second insulating layer 832 corresponding to the first gate portion 121. The recess is formed by partially removing the second insulating layer 832. Then, the gate electrode 120 is formed on the second insulating layer 832. As a result, the first gate portion 121 is formed in the first trench 60, and the second gate portion 122 is formed in the second trench 70. That is, the gate electrode 120 is formed across the first trench 60 and the second trench 70. The gate electrode 120 is made of, for example, conductive polysilicon. In this way, forming the gate electrode 120 includes forming the first gate portion 121 in the first trench 60 and forming the second gate portion 122 connected to the first gate portion 121 in the second trench 70.

[0101] 15, the method for manufacturing the semiconductor device 10 includes forming an insulating layer 850. The insulating layer 850 is formed so as to cover the gate electrode 120. The insulating layer 850 is integrated with the insulating layer 840, for example. The insulating layer 850 is formed by, for example, a CVD method. Through the above steps, the semiconductor device 10 is manufactured.

[0102] [Operation of the embodiment] The operation of the semiconductor device 10 of this embodiment will now be described. Fig. 16 is a schematic plan view of a portion of the semiconductor device 10X of the comparative example. Fig. 17 is a schematic cross-sectional view of the semiconductor device 10X of the comparative example taken along line F17-F17 in Fig. 16.

[0103] 16, the semiconductor device 10X of the comparative example has a configuration in which first trenches 60X arranged in a matrix and gate trenches 200 extending in the X direction and the Y direction between adjacent first trenches 60X are provided in a semiconductor layer 20X. In the example of Fig. 16, the gate trenches 200 extending in the X direction and the gate trenches 200 extending in the Y direction intersect with each other.

[0104] 17, a first insulating layer 31X is provided in the first trench 60X. A needle-shaped field plate electrode 110X is provided in the first insulating layer 31X. Furthermore, a gate insulating layer 201 is provided in the gate trench 200. A gate electrode 120X is provided in the gate insulating layer 201.

[0105] 16 and 17, a mesa region 23X is provided between the first trench 60X and the gate trench 200. The mesa region 23X has, for example, a ring shape surrounding the first trench 60X in a plan view. The mesa region 23X has a source contact portion 210 electrically connected to the source region 27 and the body region 26 in the mesa region 23X. The source contact portion 210 has a ring shape surrounding the first trench 60X in a plan view.

[0106] In the semiconductor device 10X of this comparative example, because the gate trench 200 is disposed between adjacent first trenches 60X, it is difficult to shorten the distance DX between the first trenches 60X. Therefore, for example, if the n-type impurity concentration of the drift region 25 of the semiconductor layer 20X is increased to reduce the on-resistance, the depletion layer extending to the mesa region 23X between the first trenches 60X becomes less likely to expand. Furthermore, if the distance DX between the first trenches 60X is large, the depletion layers extending from adjacent first trenches 60X to the mesa region 23X become less likely to connect to each other. As a result, the breakdown voltage of the semiconductor device 10X may decrease.

[0107] In addition, the gate trench 200 is exposed to the drain region 24 through the drift region 25 of the semiconductor layer 20X. As a result, the gate electrode 120X is exposed to the drain electrode 28 through the gate insulating layer 201, which increases the feedback capacitance Crss. As a result, the switching loss of the semiconductor device 10X increases.

[0108] In this regard, in the semiconductor device 10 of this embodiment, the first gate portion 121, which is a part of the gate electrode 120, and the field plate electrode 110 are provided in the first trench 60. In other words, a part of the gate trench is provided in the first trench 60. This makes it possible to reduce the distance between adjacent first trenches 60. Therefore, a depletion layer is more likely to be formed so as to connect adjacent first trenches 60, and therefore, even if the n-type impurity concentration in the drift region 25 is increased to reduce the on-resistance, a decrease in the breakdown voltage of the semiconductor device 10 can be suppressed.

[0109] In addition, since the first gate portion 121 is provided in the first trench 60, the first gate portion 121 is prevented from being exposed to the drain electrode 28. Therefore, an increase in the feedback capacitance Crss is suppressed, and an increase in the switching loss of the semiconductor device 10 can be suppressed.

[0110] [Effects of the embodiment] According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a semiconductor layer 20 including a cell region 21, a plurality of first trenches 60 provided in the cell region 21 and spaced apart from one another in a planar view, a second trench 70 provided in the cell region 21 and connecting adjacent first trenches 60 among the plurality of first trenches 60, a first insulating layer 31 provided in the first trench 60, a second insulating layer 32 provided in the second trench 70, a field plate electrode 110 embedded in the first insulating layer 31 in the first trench 60, and a gate electrode 120 including a first gate portion 121 embedded in the first insulating layer 31 in the first trench 60 and a second gate portion 122 embedded in the second insulating layer 32 in the second trench 70 and connected to the first gate portion 121.

[0111] According to this configuration, adjacent first trenches 60 can be brought closer to each other, and therefore, when a voltage is applied to the field plate electrode 110, a depletion layer is likely to spread across the region between adjacent first trenches 60 in the semiconductor layer 20. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 10 even if the impurity concentration in the region between adjacent first trenches 60 in the semiconductor layer 20 is increased. Therefore, it is possible to achieve both a reduction in the on-resistance of the semiconductor device 10 and suppression of a decrease in the breakdown voltage.

[0112] In addition, since adjacent first gate portions 121 are connected to each other by the second gate portion 122, the configuration for connecting adjacent first gate portions 121 to each other can be simplified and the connection distance between adjacent first gate portions 121 can be shortened compared to a configuration in which the first gate portions 121 are connected to each other at a position different from the first gate portions 121 in the Z direction, for example.

[0113] (2) The field plate electrode 110 has a needle shape extending in the thickness direction (Z direction) of the semiconductor layer 20. The first gate portion 121 of the gate electrode 120 has a ring shape surrounding the field plate electrode 110 in a plan view.

[0114] According to this configuration, the opposing area between the first gate portion 121 and the semiconductor layer 20 increases, thereby increasing the number of current paths within the semiconductor layer 20. Therefore, the on-resistance of the semiconductor device 10 can be reduced.

[0115] (3) The first trench 60 has a rectangular shape in a plan view. The first trenches 60 are arranged in a matrix in a plan view. According to this configuration, adjacent first trenches 60 can be disposed close to each other, thereby shortening the distance between adjacent first trenches 60. This allows the impurity concentration in the region of the semiconductor layer 20 between adjacent first trenches 60 to be further increased while maintaining the breakdown voltage of the semiconductor device 10. Therefore, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 10 and further reduce the on-resistance.

[0116] (4) The depth H2 of the second trench 70 is shallower than the depth H1 of the first trench 60. According to this configuration, a decrease in the breakdown voltage of the semiconductor device 10 can be suppressed compared to when the depth H2 of the second trench 70 is equal to or greater than the depth H1 of the first trench 60.

[0117] (5) The width W2 of the second trench 70 is smaller than the length L2 of the second trench 70. This configuration can prevent the opposing area between the first gate portion 121 and the semiconductor layer 20 from becoming smaller, thereby preventing the current path in the semiconductor layer 20 from becoming smaller. Therefore, an increase in the on-resistance of the semiconductor device 10 can be prevented.

[0118] (6) The thickness TF of the field plate electrode 110 is greater than the thickness TG1 of the first gate portion 121. According to this configuration, the field plate electrode 110 faces the mesa region 23 via the first insulating layer 31, thereby enabling depletion of the mesa region 23. Therefore, the breakdown voltage of the semiconductor device 10 can be improved.

[0119] (7) The semiconductor layer 20 includes a first surface 20S and a second surface 20R opposite to the first surface 20S. The semiconductor device 10 includes a mesa region 23 provided in the semiconductor layer 20 between the multiple first trenches 60 in a plan view and at a position different from the second trenches 70, a source wiring 50 provided on the semiconductor layer 20 and electrically connected to the field plate electrode 110, and a drain electrode 28 provided on the second surface 20R. The mesa region 23 includes a body region 26 provided in a surface portion closer to the first surface 20S and a source region 27 provided in a surface portion of the body region 26. The lower surface 122R of the second gate portion 122 is located at the same position as the lower surface of the body region 26 in the thickness direction (Z direction) of the semiconductor layer 20. The lower surface 121R of the first gate portion 121 is located lower than the lower surface of the body region 26 in the Z direction.

[0120] According to this configuration, both the first gate portion 121 and the second gate portion 122 face the entire body region 26 in the Z direction, and therefore a channel is easily formed throughout the entire body region 26 in the Z direction. Therefore, a current easily flows from the drain electrode 28 to the source wiring 50.

[0121] (8) In a plan view, the distance DA between the first gate portion 121 and the field plate electrode 110 is greater than the distance DB, which is the shortest distance between the first gate portion 121 and the sidewall 61 of the first trench 60. This configuration makes it easier to ensure insulation between the first gate portion 121 and the field plate electrode 110.

[0122] (9) The first inter-trench distance DT is smaller than the width W1 of the first trenches 60 in the arrangement direction of the first trenches 60. According to this configuration, adjacent first trenches 60 can be disposed close to each other, thereby shortening the distance between adjacent first trenches 60. This allows the impurity concentration in the region of the semiconductor layer 20 between adjacent first trenches 60 to be further increased while maintaining the breakdown voltage of the semiconductor device 10. Therefore, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 10 and further reduce the on-resistance.

[0123] (10) The semiconductor device 10 includes a second source contact 132 that is connected to the source wiring 50 and penetrates the source region 27 to reach the body region 26. A body contact region 29 that is in contact with the second source contact 132 is provided in the body region 26. The p-type impurity concentration of the body contact region 29 is higher than the p-type impurity concentration of the body region 26. This configuration reduces the electrical resistance in the current path through which current flows from the drain electrode 28 to the second source contact 132.

[0124] (11) The semiconductor layer 20 includes a peripheral region 22 surrounding the cell region 21. The multiple first trenches 60 include a first outer end trench 60A provided at the outermost periphery of the cell region 21. The semiconductor device 10 includes a third trench 80 connected to the first outer end trench 60A and extending toward the peripheral region 22, a gate wiring 40 provided on the semiconductor layer 20, and a third insulating layer 33 provided in the third trench 80. The gate electrode 120 includes a third gate portion 123 embedded in the third insulating layer 33 in the third trench 80. The semiconductor device 10 includes a gate contact 133 connecting the third gate portion 123 and the gate wiring 40. The third gate portion 123 is disposed apart from the second gate portion 122 and is connected to the first gate portion 121.

[0125] According to this configuration, the gate electrode 120 is electrically connected to the gate wiring 40 by the gate contact 133 connected to the third gate portion 123. Because the third gate portion 123 extends into the peripheral region 22, the gate contact 133 is disposed in the peripheral region 22. That is, the gate electrode 120 is electrically connected to the gate wiring 40 in the peripheral region 22. This allows the area of ​​the source wiring 50 to be larger than in a configuration in which the gate electrode 120 is electrically connected to the gate wiring 40 in, for example, the cell region 21. Therefore, for example, it is possible to suppress a reduction in the number of second source contacts 132, thereby suppressing an increase in on-resistance.

[0126] (12) Semiconductor device 10 includes a perimeter trench 90 provided in perimeter region 22, a perimeter insulating layer 140 provided in perimeter trench 90, and a perimeter field plate electrode 150 embedded in perimeter insulating layer 140 within perimeter trench 90. Perimeter trench 90 includes a recess 93 that is recessed to avoid third trench 80 in plan view. Perimeter field plate electrode 150 includes an electrode recess 153 provided in recess 93. With this configuration, perimeter field plate electrode 150 surrounds third gate portion 123 in plan view. This makes it possible to alleviate electric field concentration in third gate portion 123.

[0127] (13) The second gate portion 122 is disposed at the center of the second trench 70 in the width direction. This configuration can suppress variations in the formation of channels on both sides of the second trench 70 in the width direction, compared to when the second gate portion 122 is positioned offset relative to the second trench 70 in the width direction of the second trench 70.

[0128] (14) A method for manufacturing a semiconductor device 10 includes forming a semiconductor layer 820 including a cell region 21, forming a plurality of first trenches 60 in the cell region 21 so as to be spaced apart from one another in a planar view, forming a second trench 70 in the cell region 21 so as to connect adjacent first trenches 60 among the plurality of first trenches 60, forming a first insulating layer 31 in the first trench 60, forming a second insulating layer 32 in the second trench 70, embedding a field plate electrode 110 in the first insulating layer 31 in the first trench 60, and forming a gate electrode 120 across the first trench 60 and the second trench 70. Forming the gate electrode 120 includes forming a first gate portion 121 in the first trench 60 and forming a second gate portion 122 in the second trench 70 so as to be connected to the first gate portion 121.

[0129] According to this configuration, adjacent first trenches 60 can be brought closer to each other, and therefore, when a voltage is applied to the field plate electrode 110, a depletion layer is likely to spread across the region between adjacent first trenches 60 in the semiconductor layer 20. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 10 even if the impurity concentration in the region between adjacent first trenches 60 in the semiconductor layer 20 is increased. Therefore, it is possible to achieve both a reduction in the on-resistance of the semiconductor device 10 and suppression of a decrease in the breakdown voltage.

[0130] In addition, since adjacent first gate portions 121 are connected to each other by the second gate portion 122, the configuration for connecting adjacent first gate portions 121 to each other can be simplified and the connection distance between adjacent first gate portions 121 can be shortened compared to a configuration in which the first gate portions 121 are connected to each other at a position different from the first gate portions 121 in the Z direction, for example.

[0131] (15) The first gate portion 121 and the second gate portion 122 are integrally formed. According to this process, the gate electrode 120 can be manufactured more easily than when the first gate portion 121 and the second gate portion 122 are formed separately.

[0132] (16) The first gate portion 121, the second gate portion 122, and the third gate portion 123 are integrally formed. According to this configuration, gate electrode 120 can be manufactured more easily than when first gate portion 121, second gate portion 122, and third gate portion 123 are formed separately.

[0133] <Example of change> The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0134] (Example of modification of the configuration of the semiconductor device) The p-type impurity concentration of the body contact region 29 can be changed arbitrarily. The body contact region 29 may be omitted.

[0135] The first trench-to-trench distance DT (see FIG. 3), which is the distance between adjacent first trenches 60, can be changed arbitrarily. In one example, the first trench-to-trench distance DT may be equal to the width W1 of the first trench 60. In another example, the first trench-to-trench distance DT may be greater than the width W1 of the first trench 60. In yet another example, the first trench-to-trench distance DT may be equal to the width W2 of the second trench 70. In yet another example, the first trench-to-trench distance DT may be smaller than the width W2 of the second trench 70.

[0136] The relationship between the width W2 and the length L2 of the second trench 70 can be changed as desired. In one example, the width W2 and the length L2 of the second trench 70 may be equal to each other. In another example, the width W2 of the second trench 70 may be longer than the length L2 of the second trench 70.

[0137] The width W2 of the second trench 70 can be changed as desired. In one example, the width W2 of the second trench 70 may be equal to the width W1 of the first trench 60. In another example, the width W2 of the second trench 70 may be greater than the width W1 of the first trench 60.

[0138] The depth H2 of the second trench 70 can be changed as desired. In one example, the depth H2 of the second trench 70 may be equal to the depth H1 of the first trench 60. In another example, the depth H2 of the second trench 70 may be deeper than the depth H1 of the first trench 60.

[0139] The depth H3 of the third trench 80 may be different from the depth H2 of the second trench 70. In one example, the depth H3 of the third trench 80 may be shallower than the depth H2 of the second trench 70. In another example, the depth H3 of the third trench 80 may be deeper than the depth H2 of the second trench 70.

[0140] The third trenches 80 arranged in the Y-axis direction may be connected to the first trenches 60 at positions offset from the center in the Y-axis direction. The third trenches 80 arranged in the X-axis direction may be connected to the first trenches 60 at positions offset from the center in the X-axis direction.

[0141] The depth H4 of the peripheral trench 90 can be changed as desired. In one example, the depth H4 of the peripheral trench 90 may be shallower than the depth H1 of the first trench 60. In one example, the depth H4 of the peripheral trench 90 may be equal to the depth H2 of the second trench 70. In one example, the depth H4 of the peripheral trench 90 may be equal to the depth H3 of the third trench 80. In one example, the depth H4 of the peripheral trench 90 may be shallower than the depth H2 of the second trench 70. In one example, the depth H4 of the peripheral trench 90 may be shallower than the depth H3 of the third trench 80.

[0142] The first width WA1 and the second width WA2 of the peripheral trench 90 can each be changed as desired. In one example, the first width WA1 or the second width WA2 of the peripheral trench 90 may be equal to the width W1 of the first trench 60. In another example, at least one of the first width WA1 and the second width WA2 may be smaller than the width W1.

[0143] The configuration of periphery trench 90 can be changed as desired. For example, recess 93 may be omitted from periphery trench 90. In this case, periphery trench 90 may be, for example, annular in shape having a first width WA1 in plan view. In conjunction with this change in the configuration of periphery trench 90, electrode recess 153 may be omitted from periphery field plate electrode 150.

[0144] The peripheral trench 90 may be omitted, and accordingly the peripheral insulating layer 140 and the peripheral field plate electrode 150 may also be omitted. The end trench 100 may be omitted, and accordingly the end insulating layer and end electrode may also be omitted.

[0145] The configuration of the first gate portion 121 can be changed as desired. In one example, the thickness TG1 of the first gate portion 121 may be equal to the thickness TG2 of the second gate portion 122. FIG. 18 shows a modified example of the first gate portion 121. FIG. 18 schematically shows the cross-sectional structure of the first trench 60, the second trench 70, and the surrounding areas.

[0146] 18, the first gate portion 121 and the second gate portion 122 may be disposed at the same position in the Z direction. Therefore, although not shown, both the lower surface 121R of the first gate portion 121 and the lower surface 122R of the second gate portion 122 may be at the same position in the Z direction as the lower surface of the body region 26 (the boundary BD between the body region 26 and the drift region 25).

[0147] The position of the first gate portion 121 within the first trench 60 can be changed as desired. In one example, the first gate portion 121 may be arranged so that the distance DA between the first gate portion 121 and the field plate electrode 110 in a plan view is equal to the distance DB, which is the shortest distance between the first gate portion 121 and the sidewall 61 of the first trench 60. In another example, the first gate portion 121 may be arranged so that the distance DA is smaller than the distance DB.

[0148] The second gate portion 122 may be disposed offset from the center of the second trench 70 in the width direction of the second trench 70 . The third gate portion 123 may be disposed offset from the center of the third trench 80 in the width direction of the third trench 80 .

[0149] The connection structure between the gate electrode 120 and the gate wiring 40 is not limited to the connection structure using the third gate portion 123 and the gate contact 133, and can be changed as desired. In one example, the third gate portion 123 may be omitted. In this case, the connection structure between the gate electrode 120 and the gate wiring 40 may include, for example, an inner gate contact connected to the first gate portion 121, a gate connection wiring portion connected to the inner gate contact, and the gate contact 133. The gate connection wiring portion may be embedded in, for example, the insulating layer 30. The gate connection wiring portion is connected to the gate contact 133.

[0150] The configuration of the peripheral field plate electrode 150 can be changed as desired. In one example, the first width WB1 or the second width WB2 of the peripheral field plate electrode 150 may be equal to the width WF of the field plate electrode 110. In another example, at least one of the first width WB1 and the second width WB2 may be smaller than the width WF.

[0151] The electrode structure within the peripheral trench 90 can be modified as desired. FIGS. 19 and 20 show modified examples of the electrode structure within the peripheral trench 90. FIG. 19 schematically shows the planar structure of part of the cell region 21 and the peripheral region 22. FIG. 20 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F20-F20 in FIG. 19.

[0152] 19 and 20, the outer periphery trench 90 is different from the embodiment in that it is connected to the third trench 80. In other words, the outer periphery trench 90 communicates with the third trench 80.

[0153] The gate electrode 120 includes a peripheral gate portion 124. The peripheral gate portion 124 is annular in plan view. In one example, the peripheral gate portion 124 is rectangular in plan view. The peripheral gate portion 124 is provided in the peripheral region 22. More specifically, the peripheral gate portion 124 is provided in the peripheral trench 90. The peripheral gate portion 124 is embedded in the peripheral insulating layer 140 within the peripheral trench 90. The third gate portion 123 of the gate electrode 120 is connected to the peripheral gate portion 124. In one example, the first gate portion 121, the second gate portion 122, the third gate portion 123, and the peripheral gate portion 124 may be integrated.

[0154] 20, the depth H4 of the peripheral trench 90 is deeper than the depth H3 of the third trench 80 (see FIG. 6). The depth H4 of the peripheral trench 90 is deeper than the depth H1 of the first trench 60 (see FIG. 2). The width WA of the peripheral trench 90 is greater than the width WF of the field plate electrode 110. The width WA of the peripheral trench 90 is greater than the width W1 of the first trench 60.

[0155] 20, the thickness TG4 of the peripheral gate portion 124 is thicker than the thickness TG3 of the third gate portion 123. The thickness TG4 of the peripheral gate portion 124 is thicker than the thickness TG1 of the first gate portion 121. The thickness TG4 of the peripheral gate portion 124 is thicker than the thickness TF of the field plate electrode 110.

[0156] The width WG4 of the peripheral gate portion 124 is larger than the width WG3 of the third gate portion 123. The width WG4 of the peripheral gate portion 124 is larger than the width WF of the field plate electrode 110. The width WG4 of the peripheral gate portion 124 is larger than the width WG1 of the first gate portion 121. Note that the depth H4 and width WA of the peripheral trench 90 can each be changed as desired. Furthermore, the thickness TG4 and width WG4 of the peripheral gate portion 124 can each be changed as desired.

[0157] The shape of the first trench 60 in plan view can be changed arbitrarily. For example, the first trench 60 may have a polygonal shape with five or more sides in plan view. FIG. 21 shows a modified example of the first trench 60. FIG. 21 schematically shows the planar structure of a portion of the cell region 21 and the peripheral region 22.

[0158] As shown in FIG. 21 , each first trench 60 may be hexagonal in plan view. The multiple first trenches 60 are arranged in a honeycomb pattern in plan view. The multiple first trenches 60 can also be said to be arranged in a staggered pattern in plan view. In each first outer end trench 60A, second trenches 70 are connected to four sides in plan view. Therefore, the multiple second trenches 70 extend in directions perpendicular to each of the four sides. In each first outer end trench 60A, third trenches 80 are connected to the remaining two sides in plan view. In the example shown in FIG. 21 , the third trenches 80 extend in the X-axis direction.

[0159] The field plate electrode 110 is disposed in the center of each first trench 60 in plan view. The field plate electrode 110 has a hexagonal shape in plan view. Although not shown, the first gate portion 121 of the gate electrode 120 is annular in shape surrounding the field plate electrode 110 in a plan view. The first gate portion 121 is hexagonal in shape in a plan view. The second gate portion 122 extends along the second trench 70 in a plan view. The second gate portion 122 connects adjacent first gate portions 121. The third gate portion 123 has the same configuration as the third gate portion 123 in the embodiment. The connection structure between the gate electrode 120 and the gate wiring 40 (see FIG. 1) is the same as in the embodiment.

[0160] The multiple mesa regions 23 are arranged around the first trench 60 in plan view. Each inner mesa region 23A is a region surrounded by the first trench 60 and the second trench 70 in plan view. Each outer mesa region 23B is a region surrounded by the first outer end trench 60A, the second trench 70, the third trench 80, and the peripheral trench 90 in plan view. A second source contact 132 is provided in each mesa region 23. The configuration shown in FIG. 21 also provides the same effects as those of the embodiment.

[0161] In each embodiment, an n-type semiconductor region may be replaced with a p-type semiconductor region, and a p-type semiconductor region may be replaced with an n-type semiconductor region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0162] (Modification of the manufacturing method of the semiconductor device) Although the first gate portion 121, the second gate portion 122, and the third gate portion 123 are integrally formed, this is not limitative. The first gate portion 121, the second gate portion 122, and the third gate portion 123 may be formed separately. In one example, the first gate portion 121, the second gate portion 122, and the third gate portion 123 may be formed in this order.

[0163] Although the second trench 70 and the third trench 80 are formed integrally in the above embodiment, this is not limiting. The second trench 70 and the third trench 80 may be formed separately. In one example, the second trench 70 and the third trench 80 may be formed in this order.

[0164] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0165] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0166] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0167] [Appendix 1] a semiconductor layer (20) including a cell region (21); a plurality of first trenches (60) provided in the cell region (21) and arranged spaced apart from one another in a plan view; a second trench (70) provided in the cell region (21) and connecting adjacent first trenches (60) among the plurality of first trenches (60); a first insulating layer (31) provided in the first trench (60); a second insulating layer (32) provided in the second trench (70); a field plate electrode (110) embedded in the first insulating layer (31) within the first trench (60); a gate electrode (120) including a first gate portion (121) embedded in the first insulating layer (31) in the first trench (60) and a second gate portion (122) embedded in the second insulating layer (32) in the second trench (70) and connected to the first gate portion (121); A semiconductor device (10) comprising:

[0168] [Appendix 2] The field plate electrode (110) has a needle shape extending in the thickness direction (Z) of the semiconductor layer (20), The first gate portion (121) has a frame shape surrounding the field plate electrode (110) in a plan view. 2. The semiconductor device according to claim 1.

[0169] [Appendix 3] The first trench (60) has a rectangular shape in a plan view, The plurality of first trenches (60) are arranged in a matrix in plan view. 3. The semiconductor device according to claim 1 or 2.

[0170] [Appendix 4] The depth (H2) of the second trench (70) is shallower than the depth (H1) of the first trench (60). 4. The semiconductor device according to any one of claims 1 to 3.

[0171] [Appendix 5] The width (W2) of the second trench (70) is smaller than the width (W1) of the first trench (60). 5. The semiconductor device according to any one of claims 1 to 4.

[0172] [Appendix 6] The width (W2) of the second trench (70) is smaller than the length (L2) of the second trench (70). 6. The semiconductor device according to any one of claims 1 to 5.

[0173] [Appendix 7] The thickness (TF) of the field plate electrode (110) is greater than the thickness (TG1) of the first gate portion (121). 7. The semiconductor device according to any one of claims 1 to 6.

[0174] [Appendix 8] The thickness (TG1) of the first gate portion (121) includes a portion that is thicker than the thickness (TG2) of the second gate portion (122). 8. The semiconductor device according to any one of claims 1 to 7.

[0175] [Appendix 9] The semiconductor layer (20) includes a first surface (20S) and a second surface (20R) opposite to the first surface (20S), a mesa region (23) provided in the semiconductor layer (20) between the plurality of first trenches (60) in a plan view and at a position different from the second trenches (70); a source wiring (50) provided on the semiconductor layer (20) and electrically connected to the field plate electrode (110); a drain electrode (28) provided on the second surface (20R); Including, The mesa region (23) is a body region (26) provided in a surface layer portion closer to the first surface (20S); a source region (27) provided in a surface layer portion of the body region (26); Including, a lower surface (122R) of the second gate portion (122) is at the same position as a lower surface (BD) of the body region (26) in a thickness direction (Z) of the semiconductor layer (20); A lower surface (121R) of the first gate portion (121) is located lower than a lower surface (BD) of the body region (26) in a thickness direction (Z) of the semiconductor layer (20). 9. The semiconductor device according to any one of appendices 1 to 8.

[0176] [Appendix 10] the first gate portion (121) and the second gate portion (122) are disposed at the same position in the thickness direction (Z) of the semiconductor layer (20); The thickness (TG1) of the first gate portion (121) is equal to the thickness (TG2) of the second gate portion (122). 8. The semiconductor device according to any one of claims 1 to 7.

[0177] [Appendix 11] The semiconductor layer (20) includes a first surface (20S) and a second surface (20R) opposite to the first surface (20S), a mesa region (23) provided in the semiconductor layer (20) between the plurality of first trenches (60) in a plan view and at a position different from the second trenches (70); a source wiring (50) provided on the semiconductor layer (20) and electrically connected to the field plate electrode (110); a drain electrode (28) provided on the second surface (20R); Including, The mesa region (23) is a body region (26) provided in a surface layer portion closer to the first surface (20S); a source region (27) provided in a surface layer portion of the body region (26); Including, The lower surface (121R) of the first gate portion (121) and the lower surface (122R) of the second gate portion (122) are both at the same position as the lower surface (BD) of the body region (26) in the thickness direction (Z) of the semiconductor layer (20). 11. The semiconductor device according to claim 10.

[0178] [Appendix 12] The distance (DA) between the first gate portion (121) and the field plate electrode (110) in a plan view is greater than the shortest distance (DB) between the first gate portion (121) and the sidewall (61) of the first trench (60). 12. The semiconductor device according to any one of claims 1 to 11.

[0179] [Appendix 13] A first trench distance (DT), which is the distance between adjacent first trenches (60) in the arrangement direction of the first trenches (60), is greater than a distance (DC) between the field plate electrode (110) and a sidewall (61) of the first trench (60) in a plan view. 13. The semiconductor device according to any one of claims 1 to 12.

[0180] [Appendix 14] The first trench distance (DT) is smaller than the width (W1) of the first trenches (60) in the arrangement direction of the first trenches (60). 14. The semiconductor device according to claim 13.

[0181] [Appendix 15] The first trench distance (DT) is greater than the width (W2) of the second trench (70). 15. The semiconductor device according to claim 13 or 14.

[0182] [Appendix 16] a source contact (132) connected to the source wiring (50) and passing through the source region (27) to reach the body region (26); The body region (26) is provided with a body contact region (29) that contacts the source contact (132), The impurity concentration of the body contact region (29) is higher than the impurity concentration of the body region (26). 12. The semiconductor device according to claim 9 or 11.

[0183] [Appendix 17] The semiconductor layer (20) includes an outer peripheral region (22) surrounding the cell region (21), The plurality of first trenches (60) include a first outer end trench (60A) provided at the outermost periphery of the cell region (21), a third trench (80) connected to the first outer end trench (60A) and extending toward the outer periphery region (22); a gate wiring (40) provided on the semiconductor layer (20); a third insulating layer (33) provided in the third trench (80); Including, the gate electrode (120) includes a third gate portion (123) embedded in the third insulating layer (33) in the third trench (80); a gate contact (133) connecting the third gate portion (123) and the gate wiring (40); The third gate portion 123 is disposed apart from the second gate portion 122 and is connected to the first gate portion 121. 17. The semiconductor device according to any one of claims 1 to 16.

[0184] [Appendix 18] a peripheral trench (90) provided in the peripheral region (22); a peripheral insulating layer (140) provided in the peripheral trench (90); a peripheral field plate electrode (150) embedded in the peripheral insulating layer (140) within the peripheral trench (90); Including, the outer circumferential trench (90) includes a recess (93) recessed so as to avoid the third trench (80) in a plan view, The peripheral field plate electrode (150) includes an electrode recess (153) provided in the recess (93). 18. The semiconductor device according to claim 17.

[0185] [Appendix 19] The widths (WB1, WB2) of the peripheral field plate electrode (150) are greater than the width (WF) of the field plate electrode (110). 19. The semiconductor device according to claim 18.

[0186] [Appendix 20] a peripheral trench (90) provided in the peripheral region (22) and connected to the third trench (80); a peripheral insulating layer (140) provided in the peripheral trench (90); Including, the gate electrode (120) includes a peripheral gate portion (124) embedded in the peripheral insulating layer (140) within the peripheral trench (90); The third gate portion (123) is connected to the outer peripheral gate portion (124). 18. The semiconductor device according to claim 17.

[0187] [Appendix 21] The width (WG4) of the peripheral gate portion (124) is greater than the width (WF) of the field plate electrode (110). 21. The semiconductor device according to claim 20.

[0188] [Appendix 22] The width (WA) of the peripheral trench (90) is greater than the width (W1) of the first trench (60). 22. The semiconductor device according to any one of claims 18 to 21.

[0189] [Appendix 23] The depth (H4) of the peripheral trench (90) is deeper than the depth (H3) of the third trench (80), The thickness (TG4) of the outer gate portion (124) is greater than the thickness (TG3) of the third gate portion (123). 21. The semiconductor device according to claim 20.

[0190] [Appendix 24] The depth (H4) of the peripheral trench (90) is deeper than the depth (H1) of the first trench (60). 24. The semiconductor device according to any one of claims 18 to 23.

[0191] [Appendix 25] The depth (H3) of the third trench (80) is equal to the depth (H2) of the second trench (70). 25. The semiconductor device according to any one of claims 18 to 24.

[0192] [Appendix 26] The width (WG1) of the first gate portion (121) is smaller than the width (WF) of the field plate electrode (110). Attachment 1 to 25: The semiconductor device according to any one of attachments 1 to 25.

[0193] [Appendix 27] The plurality of first trenches (60) are arranged in a honeycomb pattern in a plan view. 3. The semiconductor device according to claim 1 or 2.

[0194] [Appendix 28] The second gate portion (122) is disposed at the center of the second trench (70) in the width direction. 28. The semiconductor device according to any one of claims 1 to 27.

[0195] [Appendix 29] forming a semiconductor layer (820) including a cell region (21); forming a plurality of first trenches (60) in the cell region (21) that are spaced apart from one another in a plan view; forming second trenches (70) in the cell region (21) so as to connect adjacent first trenches (60) among the plurality of first trenches (60); forming a first insulating layer (831) in the first trench (60); forming a second insulating layer (832) in the second trench (70); burying a field plate electrode (110) in the first insulating layer (831) in the first trench (60); forming a gate electrode (120) across the first trench (60) and the second trench (70); Including, forming the gate electrode (120) forming a first gate portion (121) in the first trench (60); forming a second gate portion (122) connected to the first gate portion (121) in the second trench (70); Contains A method for manufacturing a semiconductor device.

[0196] [Appendix 30] The first gate portion (121) and the second gate portion (122) are integrally formed. 30. A method for manufacturing a semiconductor device according to claim 29.

[0197] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0198] 10...Semiconductor device 20...Semiconductor layer 20S…Side 1 20R...2nd stage 20A~20D…1st~4th side 21...Cell area 22...Outer area 23...Mesa area 23A...Inner mesa region 23B...Outer mesa region 23C…Corner Mesa area 24...Drain region 25...Drift area 26...Body area 27...Source region 28...Drain electrode 29...Body contact area 30...insulating layer 31...First insulating layer 31A...Gate insulation part 31B...Field insulation section 31C...Electrode insulation part 32...Second insulating layer 33...Third insulating layer 40...Gate wiring 41...First gate wiring section 42...Second gate wiring section 43...Third gate wiring section 44...Gate pad section 50...Source wiring 51...Inner source wiring section 52...Peripheral source wiring section 60...First trench 60A...First outer trench 60B...First inner trench 61...Side wall 62...Bottom wall 63...Step 70...Second trench 71...Side wall 72...Bottom wall 80...Third trench 81...Side wall 82...Bottom wall 90...Periphery trench 91...Side wall 92...Bottom wall 93...recess 100...End trench 110...Field plate electrode 111…Top surface 112…Bottom surface 120...Gate electrode 121...First Gate 121S…Top surface 121R…Bottom surface 122...Second Gate 122S…Top surface 122R…Bottom surface 123...Third Gate 123S…Top surface 123R…Bottom surface 124...Outer gate section 131...First Source Contact 132...Second Source Contact 133...Gate contact 134...Peripheral contact 140...Outer insulating layer 150...Peripheral field plate electrode 151…Top surface 152…Bottom surface 153...electrode recess 200...Gate trench 201...Gate insulating layer 210...Source contact part 820...Semiconductor layer 820S...Page 1 821...Epitaxial layer 825...Drift area 831...First insulating layer 832...Second insulating layer 840, 850...insulating layer 900...Hard mask BD: Boundary between the drift region and the body region DA: distance between the first gate and the field plate electrode DB: the shortest distance between the first gate portion and the sidewall of the first trench 60 DC: Distance between the field plate electrode and the sidewall of the first trench DT: First trench distance H1: Depth of the first trench H2: Depth of the second trench H3: Depth of the third trench H4: Depth of outer trench L2: Length of the second trench L3: Length of the third trench TA: Thickness of the outer field plate electrode TF: Field plate electrode thickness TG1: Thickness of the first gate TG2: Thickness of the second gate TG3: Thickness of the third gate TG4: Thickness of outer gate W1: Width of the first trench W2: Width of second trench W3: Width of the third trench WA: Width of outer trench WA1: First width of outer trench WA2: Second width of outer trench WB1: First width of peripheral field plate electrode WB2: Second width of the peripheral field plate electrode WF: Width of field plate electrode WG1: Width of first gate WG2: Width of second gate WG3: Width of the third gate WG4: Width of outer gate

Claims

1. a semiconductor layer including a cell region; a plurality of first trenches provided in the cell region and spaced apart from each other in a plan view; a second trench provided in the cell region and connecting adjacent first trenches among the plurality of first trenches; a first insulating layer disposed in the first trench; a second insulating layer disposed in the second trench; a field plate electrode embedded in the first insulating layer within the first trench; a gate electrode including a first gate portion embedded in the first insulating layer within the first trench, and a second gate portion embedded in the second insulating layer within the second trench and connected to the first gate portion; 10. A semiconductor device comprising:

2. the field plate electrode has a needle shape extending in a thickness direction of the semiconductor layer, The first gate portion has an annular shape surrounding the field plate electrode in a plan view. The semiconductor device according to claim 1 .

3. the first trench has a rectangular shape in a plan view, The plurality of first trenches are arranged in a matrix in plan view. The semiconductor device according to claim 1 .

4. The depth of the second trench is shallower than the depth of the first trench. The semiconductor device according to claim 1 .

5. The width of the second trench is smaller than the width of the first trench. The semiconductor device according to claim 1 .

6. The width of the second trench is smaller than the length of the second trench. The semiconductor device according to claim 1 .

7. The thickness of the field plate electrode is greater than the thickness of the first gate portion. The semiconductor device according to claim 1 .

8. The width of the first gate portion is greater than the width of the field plate electrode. The semiconductor device according to claim 1 .

9. The thickness of the first gate portion includes a portion that is thicker than the thickness of the second gate portion. The semiconductor device according to claim 1 .

10. the semiconductor layer includes a first surface and a second surface opposite to the first surface, a mesa region provided in the semiconductor layer between the plurality of first trenches and at a position different from the second trenches in a plan view; a source wiring provided on the semiconductor layer and electrically connected to the field plate electrode; a drain electrode provided on the second surface; Including, The mesa region is a body region provided in a surface layer portion closer to the first surface; a source region provided in a surface layer portion of the body region; Including, a lower surface of the second gate portion is at the same position as a lower surface of the body region in a thickness direction of the semiconductor layer, The lower surface of the first gate portion is located lower than the lower surface of the body region in the thickness direction of the semiconductor layer. The semiconductor device according to claim 1 .

11. the first gate portion and the second gate portion are disposed at the same position in a thickness direction of the semiconductor layer, The thickness of the first gate portion is equal to the thickness of the second gate portion. The semiconductor device according to claim 1 .

12. the semiconductor layer includes a first surface and a second surface opposite to the first surface, a mesa region provided in the semiconductor layer between the plurality of first trenches and at a position different from the second trenches in a plan view; a source wiring provided on the semiconductor layer and electrically connected to the field plate electrode; a drain electrode provided on the second surface; Including, The mesa region is a body region provided in a surface layer portion closer to the first surface; a source region provided in a surface layer portion of the body region; Including, The lower surface of the first gate portion and the lower surface of the second gate portion are both at the same position as the lower surface of the body region in the thickness direction of the semiconductor layer. The semiconductor device according to claim 11.

13. The distance between the first gate portion and the field plate electrode in a plan view is greater than the shortest distance between the first gate portion and a sidewall of the first trench. The semiconductor device according to claim 1 .

14. A first trench distance, which is a distance between adjacent first trenches in an arrangement direction of the first trenches, is greater than a distance between the field plate electrode and a sidewall of the first trench in a plan view. The semiconductor device according to claim 1 .

15. The distance between the first trenches is smaller than the width of the first trenches in the arrangement direction of the first trenches. The semiconductor device according to claim 14.

16. The distance between the first trenches is greater than the width of the second trenches. The semiconductor device according to claim 14.

17. a source contact connected to the source wiring and passing through the source region to reach the body region; The body region includes a body contact region in contact with the source contact. The semiconductor device according to claim 10.

18. the semiconductor layer includes a peripheral region surrounding the cell region, the plurality of first trenches include a first outer trench provided at the outermost periphery of the cell region; a third trench connected to the first outer end trench and extending toward the outer periphery region; a gate wiring provided on the semiconductor layer; a third insulating layer provided in the third trench; Including, the gate electrode includes a third gate portion embedded in the third insulating layer in the third trench; a gate contact that connects the third gate portion and the gate wiring; The third gate portion is disposed apart from the second gate portion and is connected to the first gate portion. The semiconductor device according to any one of claims 1 to 17.

19. a peripheral trench provided in the peripheral region; a peripheral insulating layer provided in the peripheral trench; a peripheral field plate electrode embedded in the peripheral insulating layer within the peripheral trench; Including, the outer periphery trench includes a recess that is recessed so as to avoid the third trench in a plan view, The peripheral field plate electrode includes an electrode recess provided in the recess.

19. The semiconductor device according to claim 18.

20. a peripheral trench provided in the peripheral region and connected to the third trench; a peripheral insulating layer provided in the peripheral trench; Including, the gate electrode includes a peripheral gate portion embedded in the peripheral insulating layer within the peripheral trench; The third gate portion is connected to the outer circumferential gate portion.

19. The semiconductor device according to claim 18.

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