Semiconductor integrated circuit device, analog front end, and sensor

Abstract

To provide a semiconductor integrated circuit device capable of improving the gain accuracy of a resistance feedback type amplifier circuit and suppressing the increase of the layout area of a resistor.SOLUTION: The semiconductor IC device (13) includes a resistance feedback amplifier circuit including first to sixth resistors and an amplifier (A2). A part of the first resistance (R3), a part of the second resistance (R51), a part of the fourth resistance (R4), and a part of the fifth resistance (R61) are arranged in a first W11 (well) configured to have the same potential as a first voltage (AM). The remaining part of the first resistor, the remaining part of the second resistor, the remaining part of the fourth resistor, and the remaining part of the fifth resistor are disposed in a second W12 configured to have the same potential as a second voltage. The third resistors (R52, R53) and the sixth resistors (R62, R63) are arranged in a third well (W13) configured to be at the same potential as the third voltage (VREF).SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device, an analog front end, and a sensor. [Background technology]

[0002] BACKGROUND ART Resistance feedback amplifier circuits have been known in the past (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-40843

[0004] [overview] In a resistance feedback amplifier circuit, the resistance value of the resistor fluctuates due to the potential difference between the resistor and the substrate on which the amplifier circuit is provided, which may result in a decrease in gain accuracy.

[0005] A semiconductor integrated circuit device according to a first aspect disclosed in the present specification includes a first voltage node configured to receive a first voltage, a second voltage node configured to receive a second voltage, a third voltage node configured to receive a third voltage, a fourth voltage node configured to receive a fourth voltage, a first well configured to have the same potential as the first voltage node, a second well configured to have the same potential as the second voltage node, a third well configured to have the same potential as the third voltage node, an amplifier, and first to sixth resistors, wherein a first end of the first resistor is connected to the first voltage node, a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor, and a third well is connected to a second input terminal of the amplifier and a first end of the second resistor. a first end of the fourth resistor is connected to a first end of the third resistor, a second end of the third resistor is connected to an output terminal of the amplifier and the third voltage node, a first end of the fourth resistor is connected to the second voltage node, a second end of the fourth resistor is connected to a second input terminal of the amplifier and a first end of the fifth resistor, a second end of the fifth resistor is connected to a first end of the sixth resistor, and a second end of the sixth resistor is connected to the fourth voltage node; a portion of the first resistor, a portion of the second resistor, a portion of the fourth resistor, and a portion of the fifth resistor are disposed in the first well; a remainder of the first resistor, a remainder of the second resistor, a remainder of the fourth resistor, and a remainder of the fifth resistor are disposed in the second well; and the third resistor and the sixth resistor are disposed in the third well.

[0006] A semiconductor integrated circuit device according to a second aspect disclosed in this specification includes a first voltage node configured to receive a first voltage, a second voltage node configured to receive a second voltage, a third voltage node configured to receive a third voltage, a fourth voltage node configured to receive a fourth voltage, a first well configured to have the same potential as the third voltage node, a second well (W14) configured to have the same potential as an intermediate voltage between the first voltage and the second voltage, an amplifier, and first to sixth resistors, wherein a first terminal of the first resistor is connected to the first voltage node and a second terminal of the first resistor is connected to a first input terminal of the amplifier and a second input terminal of the amplifier. and a first end of the second resistor, a second end of the second resistor is connected to a first end of the third resistor, a second end of the third resistor is connected to an output terminal of the amplifier and the third voltage node, a first end of the fourth resistor is connected to the second voltage node, a second end of the fourth resistor is connected to a second input terminal of the amplifier and a first end of the fifth resistor, a second end of the fifth resistor is connected to a first end of the sixth resistor, and a second end of the sixth resistor is connected to the fourth voltage node, the third resistor and the sixth resistor are disposed in the first well, and the first resistor, the second resistor, the fourth resistor, and the fifth resistor are disposed in the second well.

[0007] A semiconductor integrated circuit device according to a third aspect disclosed in this specification includes a first voltage node configured to receive a first voltage, a second voltage node configured to receive a second voltage, a third voltage node configured to receive a third voltage, and a fourth voltage node configured to receive a fourth voltage; the first well configured to have the same potential as the first voltage node, a second well configured to have the same potential as the second voltage node, a third well configured to have the same potential as the third voltage node, an amplifier, and first to sixth resistors, wherein a first end of the first resistor is connected to the first voltage node, a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor, a second end of the second resistor is connected to a first end of the third resistor, a second end of the third resistor is connected to an output terminal of the amplifier and the third voltage node, a first end of the fourth resistor is connected to the second voltage node, a second end of the fourth resistor is connected to a second input terminal of the amplifier and a first end of the fifth resistor, a second end of the fifth resistor is connected to a first end of the sixth resistor, and a second end of the sixth resistor is connected to the fourth voltage node; the first and second resistors are disposed in the first well, the third and sixth resistors are disposed in the third well, and the fourth and fifth resistors are disposed in the second well.

[0008] A semiconductor integrated circuit device according to a fourth aspect disclosed in this specification includes a first voltage node configured to receive a first voltage, a second voltage node configured to receive a second voltage, a third voltage node configured to receive a third voltage, a fourth voltage node configured to receive a fourth voltage, a first well configured to have the same potential as the first voltage node, a second well configured to have the same potential as the second voltage node, a third well configured to have the same potential as the third voltage node, a fourth well configured to have the same potential as the fourth voltage node, an amplifier, and first to sixth resistors, wherein a first end of the first resistor is connected to the first voltage node and a second end of the first resistor is connected to the amplifier. a first input terminal of the amplifier and a first terminal of the second resistor, a second terminal of the second resistor connected to a first terminal of the third resistor, a second terminal of the third resistor connected to an output terminal of the amplifier and the third voltage node, a first terminal of the fourth resistor connected to the second voltage node, a second terminal of the fourth resistor connected to a second input terminal of the amplifier and a first terminal of the fifth resistor, a second terminal of the fifth resistor connected to a first terminal of the sixth resistor, and a second terminal of the sixth resistor connected to the fourth voltage node, the first resistor and the second resistor being disposed in the first well, the third resistor being disposed in the third well, the fourth resistor and the fifth resistor being disposed in the second well, and the sixth resistor being disposed in the fourth well.

[0009] The analog front end disclosed in this specification includes a semiconductor integrated circuit device having any of the above configurations and an AD converter configured to perform AD conversion of the output of the amplifier.

[0010] The sensor disclosed herein comprises a sensor element and an analog front end of the above configuration configured to process the output of the sensor element. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a configuration of a current sensor according to a first comparative example. [Figure 2] FIG. 2 is a diagram showing the gain characteristics of the rear-stage amplifier circuit in the first comparative example. [Figure 3] FIG. 3 is a diagram showing a current sensor according to a first comparative example in which the resistor of the post-stage amplifier circuit is subdivided. [Figure 4] FIG. 4 is a diagram showing the potential difference between the resistance of the post-amplifier circuit with respect to the input of the post-amplifier circuit and the substrate. [Figure 5] FIG. 5 is a diagram showing a configuration of a current sensor according to a second comparative example. [Figure 6] FIG. 6 is a diagram schematically showing examples of resistor arrangements in the first and second comparative examples. [Figure 7] FIG. 7 is a diagram showing the configuration of the current sensor according to the first embodiment. [Figure 8] FIG. 8 is a diagram schematically illustrating an example of resistor placement in the first embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of a current sensor according to the second embodiment. [Figure 10] FIG. 10 is a diagram schematically illustrating an example of resistor placement in the second embodiment. [Figure 11] FIG. 11 is a diagram showing the configuration of a current sensor according to the third embodiment. [Figure 12] FIG. 12 is a diagram schematically illustrating an example of resistor arrangement in the third embodiment. [Figure 13] FIG. 13 is a diagram showing the configuration of a current sensor according to the fourth embodiment. [Figure 14] FIG. 14 is a diagram schematically illustrating an example of resistor placement in the fourth embodiment. [Figure 15] FIG. 15 is a diagram showing a modified example of the well in the first embodiment. [Figure 16] FIG. 16 is a diagram showing a modified example of the well in the second embodiment. [Figure 17] FIG. 17 is a diagram showing a modified example of the well in the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] [Detailed explanation] <Current sensor (first comparative example)> 1 is a diagram showing the configuration of a current sensor according to a first comparative example (= a general configuration to be compared with the embodiments described later). A current sensor 101 shown in FIG. 1 is a sensor that outputs a voltage corresponding to a current flowing through a load LD.

[0013] The current sensor 101 includes a shunt resistor RS and an analog front end that processes the output of the shunt resistor RS. The analog front end of the current sensor 101 includes a semiconductor integrated circuit device 11, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0014] The shunt resistor RS is an example of a sensor element. A first end of the shunt resistor RS is externally connected to the terminal INP of the semiconductor integrated circuit device 11. A constant voltage Vcc is applied to the first end of the shunt resistor RS and the terminal INP of the semiconductor integrated circuit device 11. A second end of the shunt resistor RS and a first end of the load LD are externally connected to the terminal INM of the semiconductor integrated circuit device 11. A ground voltage VG is applied to the second end of the load LD. The voltage across the shunt resistor RS is proportional to the current flowing through the load LD.

[0015] The semiconductor integrated circuit device 11 generates an output voltage VOUT corresponding to the voltage across the shunt resistor RS, and outputs the output voltage VOUT from a terminal OUT to the outside of the semiconductor integrated circuit device 11. The semiconductor integrated circuit device 11 is a current detection amplifier having a circuit configuration that performs two-stage amplification. In other words, the semiconductor integrated circuit device 11 is a current detection amplifier having a circuit configuration that includes a front-stage amplifier circuit and a rear-stage amplifier circuit.

[0016] The front-stage amplifier circuit of the semiconductor integrated circuit device 11 includes capacitors C1 to C4, an amplifier A1, and resistors R1 and R2. The amplifier A1 is a differential input and differential output type amplifier. The rear-stage amplifier circuit of the semiconductor integrated circuit device 11 includes resistors R3 to R6 and an amplifier A2. The amplifier A2 is a differential input and non-differential output type amplifier. The semiconductor integrated circuit device 11 also includes terminals INP, INM, GND, OUT, REF, and VDD.

[0017] A first end of capacitor C1 is connected to terminal INP. A first end of capacitor C2 is connected to terminal INM. A second end of capacitor C1 and a first end of capacitor C3 are connected to the non-inverting input terminal of amplifier A1. A second end of capacitor C2 and a first end of capacitor C4 are connected to the inverting input terminal of amplifier A1.

[0018] The second terminal of capacitor C3, the first terminal of resistor R1, and the first terminal of resistor R3 are connected to the inverting output terminal of amplifier A1. A voltage AM is output from the inverting output terminal of amplifier A1. The second terminal of capacitor C4, the first terminal of resistor R2, and the first terminal of resistor R4 are connected to the non-inverting output terminal of amplifier A1. A voltage AP is output from the non-inverting output terminal of amplifier A1.

[0019] The second end of the resistor R1 and the second end of the resistor R2 are connected to each other. A constant voltage is applied to the connection node between the resistors R1 and R2, and a common-mode voltage VCM is generated at the connection node between the resistors R1 and R2.

[0020] The second end of resistor R3 and the first end of resistor R5 are connected to the inverting input terminal of amplifier A2. The second end of resistor R4 and the first end of resistor R6 are connected to the non-inverting input terminal of amplifier A2. The second end of resistor R5 is connected to the output terminal of amplifier A2 and terminal OUT. The second end of resistor R6 is connected to terminal REF.

[0021] A power supply voltage Vdd is applied to the terminal VDD. A first end of the external capacitor CO and a first end of the external resistor RO1 are externally connected to the terminal VDD. A ground voltage VG is applied to the terminal GND. A second end of the external capacitor CO and a first end of the external resistor RO2 are externally connected to the terminal GND.

[0022] The second terminal of the external resistor RO1 and the second terminal of the external resistor RO2 are connected to each other. A reference voltage VREF generated at the connection node between the external resistors RO1 and RO2 is applied to the terminal REF. The external resistors RO1 and RO2 divide the power supply voltage Vdd to generate the reference voltage VREF.

[0023] The input terminal of the AD converter 20 is externally connected to a terminal OUT. The output of the AD converter 20, which is the output of the current sensor 101, is supplied to the microcomputer 30.

[0024] For example, if each of the resistors R3 to R6 is a polycrystalline silicon element, the polycrystalline silicon element contains majority carriers. Therefore, if each of the resistors R3 to R6 is a polycrystalline silicon element, the resistance values ​​of the resistors R3 to R6 will fluctuate due to the potential difference between the substrate on which the resistors R3 to R6 are provided and the resistors R3 to R6, reducing the gain accuracy of the post-stage amplifier circuit.

[0025] For example, if resistors R3 to R6 are each P-type polycrystalline silicon elements, when the potential of resistors R3 to R6 is higher than the potential of the substrate, the majority carriers increase and the resistance values ​​of resistors R3 to R6 decrease, and when the potential of resistors R3 to R6 is lower than the potential of the substrate, the majority carriers decrease and the resistance values ​​of resistors R3 to R6 increase. Therefore, when resistors R3 to R6 are each P-type polycrystalline silicon elements, when the potential of resistors R3 to R6 is higher than the potential of the substrate, the gain G1 is lower than the gain G2 when the potential of resistors R3 to R6 is assumed to be the same as the potential of the substrate (see Figure 2).

[0026] On the other hand, if each of the resistors R3 to R6 is an N-type polycrystalline silicon element, for example, if the potential of the resistors R3 to R6 is higher than the potential of the substrate, the majority carriers decrease and the resistance values ​​of the resistors R3 to R6 increase, and if the potential of the resistors R3 to R6 is lower than the potential of the substrate, the majority carriers increase and the resistance values ​​of the resistors R3 to R6 decrease.

[0027] Fig. 3 is a diagram showing the current sensor 101 when the resistors R5 and R6 of the post-stage amplifier circuit are subdivided. In Fig. 3, the resistor R5 is subdivided into resistors R51 to R53, and the resistor R6 is subdivided into resistors R61 to R63.

[0028] A first terminal of the resistor R51 is connected to the second terminal of the resistor R3 and the inverting input terminal of the amplifier A2. A second terminal of the resistor R51 is connected to the first terminal of the resistor R52. A second terminal of the resistor R52 is connected to the first terminal of the resistor R53. A second terminal of the resistor R53 is connected to the output terminal of the amplifier A2 and the terminal OUT.

[0029] A first terminal of resistor R61 is connected to a second terminal of resistor R4 and the non-inverting input terminal of amplifier A2. A second terminal of resistor R61 is connected to a first terminal of resistor R62. A second terminal of resistor R62 is connected to a first terminal of resistor R63. A second terminal of resistor R63 is connected to terminal REF.

[0030] FIG. 4 is a diagram showing the potential difference (VR-VSUB) between each resistor and the substrate on which each resistor is provided, with respect to the input (AP-AM) of the post-amplifier circuit in each of resistors R3, R4, R51 to R55, and R61 to R63.

[0031] As can be seen from Figure 4, when the input (AP-AM) to the post-amplifier circuit increases, the output voltage VOUT increases, and the potential difference (VR-VSUB) at resistor R63, which is close to terminal OUT, increases. As a result, if resistors R3, R4, R51-R55, and R61-R63 are each P-type polycrystalline silicon elements, the resistance value of resistor R63 fluctuates in a direction that decreases the gain of the post-amplifier circuit, and the gain accuracy of the post-amplifier circuit decreases. The gain accuracy of the post-amplifier circuit can also be expressed in other words as the linearity of the input / output characteristics of the post-amplifier circuit.

[0032] <Current sensor (second comparative example)> Fig. 5 is a diagram showing the configuration of a current sensor according to a second comparative example (= a general configuration to be compared with the embodiments described later). Current sensor 102 shown in Fig. 5 differs from current sensor 101 shown in Fig. 3 in that it includes semiconductor integrated circuit device 12 instead of semiconductor integrated circuit device 11, but is otherwise basically similar to current sensor 101 shown in Fig. 3.

[0033] The semiconductor integrated circuit device 12 differs from the semiconductor integrated circuit device 11 shown in FIG. 3 in that resistors R3, R4, R51 to R53, and R61 to R63 are each placed in wells W1 to W8, and in order to suppress fluctuations in resistance value, resistor R3 and well W1 are at the same potential, resistor R4 and well W2 are at the same potential, resistors R51 to R53 and wells W3 to W5 are each at the same potential, and resistors R61 to R63 and wells W6 to W7 are each at the same potential; otherwise, the semiconductor integrated circuit device 12 is basically the same as the semiconductor integrated circuit device 11 shown in FIG. 3.

[0034] Generally, the distance between wells needs to be longer than the distance between polycrystalline silicon elements. Therefore, as shown in Fig. 6, the layout area required for arranging resistors R3, R4, R51 to R53, and R61 to R63 is larger in the semiconductor integrated circuit device 12 shown in Fig. 5 than in the semiconductor integrated circuit device 11 shown in Fig. 3. Furthermore, in the semiconductor integrated circuit device 12 shown in Fig. 5, the resistors R3, R4, R51 to R53, and R61 to R63 are arranged in different wells, which increases the distance between resistors and makes it difficult to match the resistance values ​​of the resistors R3, R4, R51 to R53, and R61 to R63.

[0035] <Current Sensor (First Embodiment)> Fig. 7 is a diagram showing the configuration of a current sensor according to the first embodiment. Current sensor 103 shown in Fig. 7 differs from current sensor 101 shown in Fig. 3 in that it includes semiconductor integrated circuit device 13 instead of semiconductor integrated circuit device 11, but is otherwise basically similar to current sensor 101 shown in Fig. 3.

[0036] The semiconductor integrated circuit device 13 differs from the semiconductor integrated circuit device 11 shown in FIG. 3 in that it includes wells W11 to W13, but is otherwise basically similar to the semiconductor integrated circuit device 11 shown in FIG.

[0037] Well W11 is at the same potential as the inverting output terminal of amplifier A1 to which voltage AM is applied, well W12 is at the same potential as the non-inverting output terminal of amplifier A1 to which voltage AP is applied, and well W13 is at the same potential as terminal OUT to which output voltage VOUT is applied.

[0038] A portion of resistor R3, a portion of resistor R51, a portion of resistor R4, and a portion of resistor R61 are disposed in well W11.

[0039] The remainder of resistor R3, the remainder of resistor R51, the remainder of resistor R4, and the remainder of resistor R61 are arranged in well W12. A first combined resistor, which is a series circuit of resistors R52 and R53, and a second combined resistor, which is a series circuit of resistors R62 and R63, are arranged in well W13.

[0040] In the semiconductor integrated circuit device 13, since the amplifier A2 processes differential signals, no major problem occurs even if the potentials of the wells W11 and W12 in which the resistors R3, R4, R51, and R61 are arranged are a pair of voltages AM and AP.

[0041] In the semiconductor integrated circuit device 13, the potential of the well W13 in which the resistors R52, R53, R62, and R63 are arranged is the same potential as the output voltage VOUT.

[0042] With this configuration, when the absolute value of the output voltage VOUT increases, the potential difference between the well W13 in which the resistor R53 is provided and the resistor R53 is reduced, but the potential difference between the well W13 and the resistor R52 increases. However, the potential difference between the well W13 and the resistor R62 and the potential difference between the well W13 and the resistor R63 tend to have the same tendency as the potential difference between the well W13 and the resistor R52, so that the potential difference between the well W13 and the resistor R52 tends to cancel out the potential difference between the well W13 and the resistor R62 and the potential difference between the well W13 and the resistor R63 due to differentiation, thereby improving the gain accuracy of the subsequent-stage amplifier circuit.

[0043] FIG. 8 is a diagram schematically showing an example of the arrangement of the resistors R3, R4, R51 to R53, and R61 to R63 in the first embodiment.

[0044] The first combined resistor and the second combined resistor are each composed of a plurality of elements, and the elements of the first combined resistor and the elements of the second combined resistor are alternately arranged along a predetermined direction D1. Furthermore, the elements of the first combined resistor and the elements of the second combined resistor are also alternately arranged along a direction D2 perpendicular to the predetermined direction D1. This makes it possible to reduce mismatches in resistance values.

[0045] <Current Sensor (Second Embodiment)> Fig. 9 is a diagram showing the configuration of a current sensor according to the second embodiment. Current sensor 104 shown in Fig. 9 differs from current sensor 103 shown in Fig. 7 in that it includes a semiconductor integrated circuit device 14 instead of semiconductor integrated circuit device 13, but is otherwise basically similar to current sensor 103 shown in Fig. 7.

[0046] The semiconductor integrated circuit device 14 differs from the semiconductor integrated circuit device 13 shown in FIG. 7 in that resistors R3, R51, R4, and R61 are arranged in well W14, but is otherwise basically similar to the semiconductor integrated circuit device 13 shown in FIG. 7.

[0047] Well W13 is at the same potential as voltage VCM. Voltage VCM is an intermediate voltage between voltages AM and AP. The value of voltage VCM is determined by the values ​​of voltages AM and AP and the resistance values ​​of resistors R1 and R2.

[0048] FIG. 10 is a diagram schematically showing an example of the arrangement of resistors R3, R4, R51 to R53, and R61 to R63 in the second embodiment.

[0049] <Current Sensor (Third Embodiment)> Fig. 11 is a diagram showing the configuration of a current sensor according to the third embodiment. Current sensor 105 shown in Fig. 11 differs from current sensor 103 shown in Fig. 7 in that it includes semiconductor integrated circuit device 15 instead of semiconductor integrated circuit device 13, but is otherwise basically similar to current sensor 103 shown in Fig. 7.

[0050] The semiconductor integrated circuit device 15 differs from the semiconductor integrated circuit device 13 shown in FIG. 7 in that the resistors R3 and R51 are all arranged in the well W11, and the resistors R4 and R61 are all arranged in the well W12, but is otherwise basically similar to the semiconductor integrated circuit device 13 shown in FIG. 7.

[0051] 12 is a diagram schematically illustrating an example of the arrangement of resistors R3, R4, R51 to R53, and R61 to R63 in the third embodiment. In the third embodiment, unlike the first and second embodiments, the resistors R3, R4, R51, and R61 are arranged together.

[0052] <Current Sensor (Fourth Embodiment)> Fig. 13 is a diagram showing the configuration of a current sensor according to the fourth embodiment. Current sensor 106 shown in Fig. 13 differs from current sensor 105 shown in Fig. 11 in that it includes semiconductor integrated circuit device 16 instead of semiconductor integrated circuit device 15, but is otherwise basically similar to current sensor 105 shown in Fig. 11.

[0053] The semiconductor integrated circuit device 16 differs from the semiconductor integrated circuit device 15 shown in FIG. 11 in that it includes a well W15, but is otherwise basically the same as the semiconductor integrated circuit device 15 shown in FIG.

[0054] Well W15 is at the same potential as reference voltage VREF. In this embodiment, resistors R62 and R63 are placed in well W15 instead of in well W13.

[0055] 14 is a diagram schematically illustrating an example of the arrangement of resistors R3, R4, R51 to R53, and R61 to R63 in the fourth embodiment. In the fourth embodiment, unlike the third embodiment, the resistors R52, R53, R62, and R63 are arranged together.

[0056] <Other> In addition to the above-described embodiments, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiments are illustrative in all respects and should be considered not to be limiting. The technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0057] For example, in the above-described embodiments, the semiconductor integrated circuit device is configured to include a pre-amplifier circuit and a post-amplifier circuit, but the semiconductor integrated circuit device may be configured not to include a pre-amplifier circuit.

[0058] For example, in the above-described embodiment, the semiconductor integrated circuit device is applied to a current sensor, but the semiconductor integrated circuit device may be applied to sensors other than current sensors. Examples of sensors other than current sensors include magnetic sensors and pressure sensors. Furthermore, the semiconductor integrated circuit device may be applied to devices, equipment, systems, etc. other than sensors.

[0059] The well to which a predetermined voltage is applied may be a single well or multiple wells electrically connected to each other. For example, in FIG. 8, the well W13 having the same potential as the output voltage VOUT is configured as a single well. However, as shown in FIG. 15, the well W13 having the same potential as the output voltage VOUT may be configured as multiple wells W13A and W13B. For example, in FIG. 10, the well W13 having the same potential as the output voltage VOUT is configured as a single well. However, as shown in FIG. 16, the well W13 having the same potential as the output voltage VOUT may be configured as multiple wells W13A and W13B. For example, in FIG. 10, the well W14 having the same potential as the common-mode voltage VCM is configured as a single well. However, as shown in FIG. 16, the well W14 having the same potential as the common-mode voltage VCM may be configured as multiple wells W14A and W14B. For example, in FIG. 12, the well W13 having the same potential as the output voltage VOUT is configured as a single well. However, as shown in FIG. 17, the well W13 having the same potential as the output voltage VOUT may be configured as multiple wells W13A and W13B. In the above modification, the number of wells electrically connected to each other is two, but the number of wells electrically connected to each other may be three or more.

[0060] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0061] A semiconductor integrated circuit device (13) according to a first aspect of the present disclosure includes a first voltage node configured to receive a first voltage (AM), a second voltage node configured to receive a second voltage (AP), a third voltage node configured to receive a third voltage (VOUT), a fourth voltage node configured to receive a fourth voltage (VREF), a first well (W11) configured to have the same potential as the first voltage node, a second well (W12) configured to have the same potential as the second voltage node, a third well (W13) configured to have the same potential as the third voltage node, an amplifier (A2), and first to sixth resistors, wherein a first terminal of the first resistor (R3) is connected to the first voltage node, a second terminal of the first resistor is connected to a first input terminal of the amplifier and a first terminal of the second resistor (R51), and a third terminal of the second resistor (R52) is connected to a first input terminal of the amplifier and a first terminal of the second resistor (R51). a second end of the fourth resistor (R4) is connected to a first end of the third resistor (R52, R53), a second end of the third resistor is connected to an output terminal of the amplifier and the third voltage node, a first end of the fourth resistor (R4) is connected to the second voltage node, a second end of the fourth resistor is connected to a second input terminal of the amplifier and a first end of the fifth resistor (R61), a second end of the fifth resistor is connected to a first end of the sixth resistor (R62, R63), and a second end of the sixth resistor is connected to the fourth voltage node; a portion of the first resistor, a portion of the second resistor, a portion of the fourth resistor, and a portion of the fifth resistor are disposed in the first well; a remainder of the first resistor, a remainder of the second resistor, a remainder of the fourth resistor, and a remainder of the fifth resistor are disposed in the second well; and the third resistor and the sixth resistor are disposed in the third well (first configuration).

[0062] A semiconductor integrated circuit device (14) according to a second aspect of the present disclosure includes a first voltage node configured to receive a first voltage (AM), a second voltage node configured to receive a second voltage (AP), a third voltage node configured to receive a third voltage (VOUT), a fourth voltage node configured to receive a fourth voltage (VREF), a first well (W13) configured to have the same potential as the third voltage node, a second well (W14) configured to have the same potential as an intermediate voltage (VCM) between the first voltage and the second voltage, an amplifier (A2), and first to sixth resistors, wherein a first terminal of the first resistor (R3) is connected to the first voltage node, and a second terminal of the first resistor (R4) is connected to a first input terminal and a second input terminal of the amplifier. a first terminal of the fourth resistor (R4) connected to the second voltage node; a second terminal of the fourth resistor (R51) connected to the first terminal of the third resistor (R52, R53); a second terminal of the third resistor connected to the output terminal of the amplifier and the third voltage node; a first terminal of the fourth resistor (R4) connected to the second voltage node; a second terminal of the fourth resistor connected to the second input terminal of the amplifier and the first terminal of the fifth resistor (R61); a second terminal of the fifth resistor connected to the first terminal of the sixth resistor (R62, 63); a second terminal of the sixth resistor connected to the fourth voltage node; the third and sixth resistors disposed in the first well; and the first, second, fourth, and fifth resistors disposed in the second well (second configuration).

[0063] A semiconductor integrated circuit device according to a third aspect of the present disclosure includes a first voltage node configured to receive a first voltage (AM), a second voltage node configured to receive a second voltage (AP), a third voltage node configured to receive a third voltage (VOUT), a fourth voltage node configured to receive a fourth voltage (VREF), a first well (W11) configured to have the same potential as the first voltage node, a second well (W12) configured to have the same potential as the second voltage node, a third well (W13) configured to have the same potential as the third voltage node, an amplifier (A2), and first to sixth resistors, wherein a first terminal of the first resistor (R3) is connected to the first voltage node, and a second terminal of the first resistor (R4) is connected to a first input terminal of the amplifier and a second input terminal of the amplifier. a first terminal of the fourth resistor (R4) connected to the second voltage node; a second terminal of the fourth resistor (R51) connected to the first terminal of the third resistor (R52, R53); a second terminal of the third resistor connected to the output terminal of the amplifier and the third voltage node; a first terminal of the fourth resistor (R4) connected to the second voltage node; a second terminal of the fourth resistor connected to the second input terminal of the amplifier and the first terminal of the fifth resistor (R61); a second terminal of the fifth resistor connected to the first terminal of the sixth resistor (R62, R63); a second terminal of the sixth resistor connected to the fourth voltage node; the first and second resistors disposed in the first well; the third and sixth resistors disposed in the third well; and the fourth and fifth resistors disposed in the second well (third configuration).

[0064] A semiconductor integrated circuit device according to a fourth aspect of the present disclosure includes a first voltage node configured to receive a first voltage (AM), a second voltage node configured to receive a second voltage (AP), a third voltage node configured to receive a third voltage (VOUT), a fourth voltage node configured to receive a fourth voltage (VREF), a first well (W11) configured to have the same potential as the first voltage node, a second well (W12) configured to have the same potential as the second voltage node, a third well (W13) configured to have the same potential as the third voltage node, a fourth well (W15) configured to have the same potential as the fourth voltage node, an amplifier (A2), and first to sixth resistors, wherein a first end of the first resistor (R3) is connected to the first voltage node, and a second end of the first resistor (R4) is connected to the amplifier (A2). a first input terminal of the amplifier and a first terminal of the second resistor (R51), a second terminal of the second resistor is connected to a first terminal of the third resistor (R52, R53), a second terminal of the third resistor is connected to an output terminal of the amplifier and the third voltage node, a first terminal of the fourth resistor (R4) is connected to the second voltage node, a second terminal of the fourth resistor is connected to a second input terminal of the amplifier and a first terminal of the fifth resistor (R61), a second terminal of the fifth resistor is connected to a first terminal of the sixth resistor (R62, R63), and a second terminal of the sixth resistor is connected to the fourth voltage node, the first resistor and the second resistor are disposed in the first well, the third resistor is disposed in the third well, the fourth resistor and the fifth resistor are disposed in the second well, and the sixth resistor is disposed in the fourth well (fourth configuration).

[0065] According to the semiconductor integrated circuit device having any one of the first to fourth configurations, it is possible to improve the gain accuracy of the resistance feedback amplifier circuit and to suppress an increase in the layout area of ​​the resistors.

[0066] In the semiconductor integrated circuit device of any of the first to third configurations, the third resistor and the sixth resistor may each be configured with a plurality of elements, and the elements of the third resistor and the resistive elements of the sixth resistor may be arranged alternately along a predetermined direction (fifth configuration).

[0067] In the semiconductor integrated circuit device of the fifth configuration, the elements of the third resistor and the resistive elements of the sixth resistor may be arranged alternately also along a direction perpendicular to the predetermined direction (sixth configuration).

[0068] In the semiconductor integrated circuit device of any of the first to sixth configurations, each of the first to sixth resistors may be a polycrystalline silicon element (seventh configuration).

[0069] The semiconductor integrated circuit device of any of the first to seventh configurations may have a configuration (eighth configuration) including a pre-stage amplifier circuit (C1 to C4, R1, R2, A2) configured to receive an input signal and amplify the input signal, and a post-stage amplifier circuit including the amplifier and the first to sixth resistors configured to receive an output signal from the pre-stage amplifier circuit and amplify the output signal from the pre-stage amplifier circuit.

[0070] The analog front end of the present disclosure has a configuration (ninth configuration) including a semiconductor integrated circuit device of any one of the first to seventh configurations and an AD converter (20) configured to AD convert the output of the post-stage amplifier circuit.

[0071] The sensors (103 to 106) of the present disclosure have a configuration (tenth configuration) including a sensor element (Rs) and an analog front end of the ninth configuration configured to process the output of the sensor element. [Explanation of symbols]

[0072] 11-16 Semiconductor integrated circuit devices 20 AD converter 30 Microcomputer 101~106 Current sensors A1, A2 amplifiers C1~C4 capacitors CO External Capacitor INM, INP, GND, OUT, REF, VDD terminal LD load R1~R6, R51~R53, R61~R63 resistance RO1, RO2 external resistors RS Shunt resistor Wells W1-W8, W11-W15

Claims

1. a first voltage node configured to have a first voltage applied thereto; a second voltage node configured to have a second voltage applied thereto; a third voltage node configured to have a third voltage applied thereto; a fourth voltage node configured to have a fourth voltage applied thereto; a first well configured to be at the same potential as the first voltage node; a second well configured to be at the same potential as the second voltage node; a third well configured to have the same potential as the third voltage node; An amplifier and First to sixth resistors; Equipped with a first end of the first resistor connected to the first voltage node; a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor; a second end of the second resistor is connected to a first end of the third resistor; a second end of the third resistor is connected to the output end of the amplifier and the third voltage node; a first end of the fourth resistor connected to the second voltage node; a second terminal of the fourth resistor is connected to a second input terminal of the amplifier and a first terminal of the fifth resistor; a second end of the fifth resistor is connected to a first end of the sixth resistor; a second end of the sixth resistor connected to the fourth voltage node; a portion of the first resistor, a portion of the second resistor, a portion of the fourth resistor, and a portion of the fifth resistor are disposed in the first well; a remainder of the first resistor, a remainder of the second resistor, a remainder of the fourth resistor, and a remainder of the fifth resistor are disposed in the second well; the third resistor and the sixth resistor are disposed in the third well. Semiconductor integrated circuit device.

2. a first voltage node configured to have a first voltage applied thereto; a second voltage node configured to have a second voltage applied thereto; a third voltage node configured to have a third voltage applied thereto; a fourth voltage node configured to have a fourth voltage applied thereto; a first well configured to have the same potential as the third voltage node; a second well configured to have the same potential as an intermediate voltage between the first voltage and the second voltage; An amplifier and First to sixth resistors; Equipped with a first end of the first resistor connected to the first voltage node; a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor; a second end of the second resistor is connected to a first end of the third resistor; a second end of the third resistor is connected to the output end of the amplifier and the third voltage node; a first end of the fourth resistor connected to the second voltage node; a second terminal of the fourth resistor is connected to a second input terminal of the amplifier and a first terminal of the fifth resistor; a second end of the fifth resistor is connected to a first end of the sixth resistor; a second end of the sixth resistor connected to the fourth voltage node; the third resistor and the sixth resistor are disposed in the first well; the first resistor, the second resistor, the fourth resistor, and the fifth resistor are disposed in the second well. Semiconductor integrated circuit device.

3. a first voltage node configured to have a first voltage applied thereto; a second voltage node configured to have a second voltage applied thereto; a third voltage node configured to have a third voltage applied thereto; a fourth voltage node configured to have a fourth voltage applied thereto; a first well configured to be at the same potential as the first voltage node; a second well configured to be at the same potential as the second voltage node; a third well configured to have the same potential as the third voltage node; An amplifier and First to sixth resistors; Equipped with a first end of the first resistor connected to the first voltage node; a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor; a second end of the second resistor is connected to a first end of the third resistor; a second end of the third resistor is connected to the output end of the amplifier and the third voltage node; a first end of the fourth resistor connected to the second voltage node; a second terminal of the fourth resistor is connected to a second input terminal of the amplifier and a first terminal of the fifth resistor; a second end of the fifth resistor is connected to a first end of the sixth resistor; a second end of the sixth resistor connected to the fourth voltage node; the first resistor and the second resistor are disposed in the first well; the third resistor and the sixth resistor are disposed in the third well; the fourth resistor and the fifth resistor are disposed in the second well. Semiconductor integrated circuit device.

4. a first voltage node configured to have a first voltage applied thereto; a second voltage node configured to have a second voltage applied thereto; a third voltage node configured to have a third voltage applied thereto; a third voltage node configured to have a fourth voltage applied thereto; a first well configured to be at the same potential as the first voltage node; a second well configured to be at the same potential as the second voltage node; a third well configured to have the same potential as the third voltage node; a fourth well configured to have the same potential as the fourth voltage node; An amplifier and First to sixth resistors; Equipped with a first end of the first resistor connected to the first voltage node; a second end of the first resistor is connected to a first input terminal of the amplifier and a first end of the second resistor; a second end of the second resistor is connected to a first end of the third resistor; a second end of the third resistor is connected to the output end of the amplifier and the third voltage node; a first end of the fourth resistor connected to the second voltage node; a second terminal of the fourth resistor is connected to a second input terminal of the amplifier and a first terminal of the fifth resistor; a second end of the fifth resistor is connected to a first end of the sixth resistor; a second end of the sixth resistor connected to the fourth voltage node; the first resistor and the second resistor are disposed in the first well; the third resistor is disposed in the third well; the fourth resistor and the fifth resistor are disposed in the second well; the sixth resistor is disposed in the fourth well. Semiconductor integrated circuit device.

5. 4. The semiconductor integrated circuit device according to claim 1, wherein the third resistor and the sixth resistor are each composed of a plurality of elements, and the elements of the third resistor and the resistive elements of the sixth resistor are alternately arranged along a predetermined direction.

6. 6. The semiconductor integrated circuit device according to claim 5, wherein the elements of said third resistor and the resistive elements of said sixth resistor are also arranged alternately in a direction perpendicular to said predetermined direction.

7. 5. The semiconductor integrated circuit device according to claim 1, wherein each of said first to sixth resistors is a polycrystalline silicon element.

8. a preamplifier circuit configured to receive an input signal and amplify the input signal; 5. The semiconductor integrated circuit device according to claim 1, wherein a subsequent-stage amplifier circuit including the amplifier and the first to sixth resistors is configured to receive an output signal from the previous-stage amplifier circuit and amplify the output signal from the previous-stage amplifier circuit.

9. a semiconductor integrated circuit device according to claim 8; an AD converter configured to AD convert the output of the post-stage amplifier circuit; An analog front end comprising:

10. A sensor element; 10. An analog front end according to claim 9 configured to process the output of the sensor element; A sensor comprising:

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