Method for manufacturing nitride semiconductor device

Abstract

To provide a method of manufacturing a nitride semiconductor device capable of obtaining a high breakdown voltage.SOLUTION: The method for manufacturing the nitride-based FET 100 includes a step of preparing the first nitride-based FET layer 120 including the channel layer 124 and the barrier layer 126, a step of forming, in the first nitride-based FET layer, the first recess side 140S and the second recess side 140D between which the channel layer and the barrier layer are interposed, and a step of forming the second nitride-based FET layer 142S containing gallium and an impurity in the first recess and the third nitride-based FET layer 142D containing gallium and an impurity in the second recess in a chamber by sputtering. The process of forming the second nitride semiconductor layer and the third nitride semiconductor layer includes repeating a process of supplying gallium, an impurity, and nitrogen radicals into the chamber while maintaining the pressure inside the chamber at a first pressure and a process of stopping the supply of gallium and the impurity and supplying nitrogen radicals into the chamber while maintaining the pressure inside the chamber at a second pressure lower than the first pressure.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In order to reduce contact resistance and the like in nitride semiconductor devices, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2008 / 0176366 [Patent Document 2] U.S. Patent No. 9,515,161 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for further improvement in pressure resistance.

[0005] An object of the present disclosure is to provide a method for manufacturing a nitride semiconductor device that can obtain a high breakdown voltage. [Means for solving the problem]

[0006] A method for manufacturing a nitride semiconductor device according to the present disclosure includes the steps of: preparing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a first recess and a second recess in the first nitride semiconductor layer along a second axis perpendicular to the first axis, the first recess sandwiching the channel layer and the barrier layer therebetween; and forming a second nitride semiconductor layer containing gallium and an impurity in the first recess by sputtering in a chamber, the second nitride semiconductor layer containing gallium and an impurity, and a third nitride semiconductor layer containing gallium and the impurity in the second recess. The steps of forming the second nitride semiconductor layer and the third nitride semiconductor layer include repeated steps of supplying gallium, the impurity, and nitrogen radicals into the chamber while maintaining a pressure in the chamber at a first pressure; and stopping the supply of gallium and the impurity and supplying nitrogen radicals into the chamber while maintaining the pressure in the chamber at a second pressure lower than the first pressure. [Effects of the Invention]

[0007] According to the present disclosure, a high breakdown voltage can be obtained. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) illustrating a method for manufacturing a nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 3) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 4) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 5) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 6) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 7]FIG. 7 is a cross-sectional view (part 7) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 8) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a timing chart showing a method for forming the second nitride semiconductor layer and the third nitride semiconductor layer. [Figure 10] FIG. 10 is a cross-sectional view (part 1) showing a method for forming the second nitride semiconductor layer and the third nitride semiconductor layer. [Figure 11] FIG. 11 is a cross-sectional view (part 2) showing a method for forming the second nitride semiconductor layer and the third nitride semiconductor layer. [Figure 12] FIG. 12 is a cross-sectional view (part 3) showing a method for forming the second nitride semiconductor layer and the third nitride semiconductor layer. [Figure 13] FIG. 13 is a cross-sectional view (part 4) showing a method for forming a second nitride semiconductor layer and a third nitride semiconductor layer. [Figure 14] FIG. 14 is a cross-sectional view (part 5) showing a method for forming a second nitride semiconductor layer and a third nitride semiconductor layer. [Figure 15] FIG. 15 is a cross-sectional view showing a phenomenon occurring in a method for manufacturing a nitride semiconductor device according to a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A method for manufacturing a nitride semiconductor device according to one embodiment of the present disclosure includes the steps of: preparing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a first recess and a second recess in the first nitride semiconductor layer along a second axis perpendicular to the first axis, the first recess sandwiching the channel layer and the barrier layer therebetween; and forming a second nitride semiconductor layer containing gallium and an impurity in the first recess by a sputtering method in a chamber, the second nitride semiconductor layer containing gallium and an impurity, and a third nitride semiconductor layer containing gallium and the impurity in the second recess. The steps of forming the second nitride semiconductor layer and the third nitride semiconductor layer include repeated steps of: supplying gallium, the impurity, and nitrogen radicals into the chamber while maintaining a pressure in the chamber at a first pressure; and stopping the supply of gallium and the impurity and supplying nitrogen radicals into the chamber while maintaining the pressure in the chamber at a second pressure lower than the first pressure.

[0011] In the step of supplying gallium, impurities, and nitrogen radicals into the chamber while maintaining the pressure in the chamber at a first pressure, the mean free paths of the gallium, impurities, and nitrogen radicals are shortened, and droplets containing gallium, impurities, and nitrogen are formed with high uniformity. Furthermore, in the step of stopping the supply of gallium and impurities and supplying nitrogen radicals into the chamber while maintaining the pressure in the chamber at a second pressure lower than the first pressure, a nitride semiconductor layer is formed from the droplets. Therefore, high flatness can be achieved on the upper surfaces of the second nitride semiconductor layer and the third nitride semiconductor layer.

[0012] Generally, when the second nitride semiconductor layer and the third nitride semiconductor layer are formed by sputtering, polycrystalline layers may be formed in unnecessary locations. Therefore, if depressions are formed unevenly on the top surfaces of the second nitride semiconductor layer and the third nitride semiconductor layer, the portions of the second nitride semiconductor layer and the third nitride semiconductor layer with low crystallinity near the depressions may be etched when the polycrystalline layers are removed, and the barrier layer and the channel layer may also be etched, resulting in a decrease in breakdown voltage.

[0013] On the other hand, if the upper surfaces of the second nitride semiconductor layer and the third nitride semiconductor layer are highly flat, the barrier layer and the channel layer are not etched, and the nitride semiconductor device can have a high breakdown voltage.

[0014] [2] In [1], the difference between the first pressure and the second pressure may be 0.3 Pa or more and 1 Pa or less. By making this difference 0.3 Pa or more, the gallium and impurities ejected from the target collide with each other before entering the second nitride semiconductor layer and the third nitride semiconductor layer, resulting in a wide angular distribution of their respective motion directions, and the effect of shielding by the polycrystalline layer can be suppressed. For example, it is possible to allow the gallium and impurities to reach parts of the polycrystalline layer that are shaded from the target. This reduces depressions. By making this difference 1 Pa or less, it is possible to suppress the gallium and impurities from excessively colliding with each other and reacting and deactivating before adhering to the second nitride semiconductor layer and the third nitride semiconductor layer.

[0015] [3] In [1] or [2], the mean free path of the nitrogen radicals in the chamber maintained at the first pressure may be 0.5 cm or more and 2 cm or less. By making this mean free path 0.5 cm or more, the gallium and impurities emitted from the target collide with each other before entering the second nitride semiconductor layer and the third nitride semiconductor layer, resulting in a wide angular distribution of their respective motion directions, thereby suppressing the effect of shielding by the polycrystalline layer. For example, this allows the gallium and impurities to reach parts of the polycrystalline layer that are shaded from the target. This reduces depressions. By making this mean free path 2 cm or less, the gallium and impurities emitted from the target collide with each other excessively, suppressing deactivation before adhering to the second nitride semiconductor layer and the third nitride semiconductor layer.

[0016] [4] In any of [1] to [3], the mean free path of the nitrogen radicals in the chamber maintained at the second pressure may be 2 cm or more and 8 cm or less. A mean free path of 2 cm or more prevents the nitrogen radicals from being deactivated before reaching the second nitride semiconductor layer and the third nitride semiconductor layer, allowing the deposition of second nitride semiconductor layer and third nitride semiconductor layer with better crystallinity. A mean free path of 8 cm or less allows the generation of a large number of radicals, allowing the nitrogen radicals to be effectively supplied to the second nitride semiconductor layer and the third nitride semiconductor layer.

[0017] [5] In any one of [1] to [4], the time for supplying gallium, the impurities, and nitrogen radicals into the chamber may be shorter than the time for stopping the supply of gallium and the impurities and supplying nitrogen radicals into the chamber, in which case the droplets are more likely to disappear when the nitride semiconductor layer is formed from the droplets.

[0018] [6] In any of [1] to [5], the method may further include a step of forming an insulating layer on the first surface, the insulating layer having a first opening connected to the first recess and a second opening connected to the second recess, between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess, and after the steps of forming the second nitride semiconductor layer and the third nitride semiconductor layer, a step of removing a polycrystalline layer formed on the insulating layer when forming the second nitride semiconductor layer and the third nitride semiconductor layer. This avoids etching the barrier layer and the channel layer when removing the unnecessary polycrystalline layer formed on the insulating layer.

[0019] [7] In any one of [1] to [6], in each of the second nitride semiconductor layer and the third nitride semiconductor layer, the concentration of the impurity is 1×10 20 cm -3 In this case, it is easy to obtain particularly low electrical resistance in the second nitride semiconductor layer and the third nitride semiconductor layer.

[0020] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the nitride semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the −Z direction may be referred to as downward, lower side, or bottom.

[0021] 1 to 8 are cross-sectional views illustrating a method for manufacturing a nitride semiconductor device according to an embodiment.

[0022] First, as shown in FIG. 1, a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128 are formed on a substrate 110. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method. Next, an insulating layer 130 is formed on the cap layer 128. The insulating layer 130 can be formed by, for example, a CVD method. In this manner, a first nitride semiconductor layer 120 is obtained.

[0023] The substrate 110 is, for example, a substrate for growing a gallium nitride (GaN)-based semiconductor layer, such as a semi-insulating silicon carbide (SiC) substrate. When the substrate 110 is a SiC substrate, the upper surface of the substrate 110 is a silicon (Si) polar plane. When the surface of the substrate 110 is a Si polar plane, the first nitride semiconductor layer 120 undergoes crystal growth with the gallium (Ga) polar plane as the growth plane.

[0024] The first nitride semiconductor layer 120 has a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 are stacked in this order along the Z axis. The first nitride semiconductor layer 120 has a top surface 161 perpendicular to the Z axis. The top surface 161 is located on the cap layer 128. The Z axis is an example of a first axis. The top surface 161 is an example of a first surface. When the first nitride semiconductor layer 120 is grown as a crystal with a Ga polarity plane as the growth plane, the top surface 161 is a Ga polarity plane. When the top surface 161 is a Ga polarity plane, it is also said that the top surface 161 has Ga polarity.

[0025] A buffer layer 122 is formed on the substrate 110. The buffer layer 122 is, for example, an aluminum nitride (AlN) layer. The buffer layer 122 may include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer. A channel layer 124 is formed on the buffer layer 122. The channel layer 124 is, for example, an undoped gallium nitride (GaN) layer. A barrier layer 126 is formed on the channel layer 124. The barrier layer 126 is, for example, an n-type AlGaN layer. A channel region 155 including a two-dimensional electron gas (2DEG) exists near the upper surface of the channel layer 124. A cap layer 128 is formed on the barrier layer 126. The cap layer 128 is, for example, an n-type GaN layer.

[0026] Next, as shown in FIG. 2, a mask 200 is formed on the insulating layer 130. The mask 200 has an opening 201 for a source and an opening 202 for a drain. For example, the mask 200 is formed from photoresist. The openings 201 and 202 are formed by patterning. The opening 202 is on the +X side of the opening 201. The X axis is an example of the second axis.

[0027] 3, the insulating layer 130 is etched through the openings 201 and 202 to form an opening 130S that connects to the opening 201 and an opening 130D that connects to the opening 202 in the insulating layer 130. The openings 130S and 130D can be formed by reactive ion etching (RIE) using a reactive gas containing fluorine (F), for example. The opening 130S is an example of a first opening, and the opening 130D is an example of a second opening.

[0028] Next, as shown in FIG. 4 , the first nitride semiconductor layer 120 is etched through the openings 201 and 202 to form a first recess 140S connected to the opening 130S and a second recess 140D connected to the opening 130D in the first nitride semiconductor layer 120. The first recess 140S and the second recess 140D sandwich the channel layer 124 and the barrier layer 126 along the X-axis. The first recess 140S and the second recess 140D can be formed by RIE using a reactive gas containing chlorine (Cl), for example. For example, the angle formed between the sidewall surface of the first recess 140S and the top surface 161 of the first nitride semiconductor layer 120 is greater than, but preferably close to, 90 degrees. For example, the angle formed between the sidewall surface of the second recess 140D and the top surface 161 of the first nitride semiconductor layer 120 is greater than, but preferably close to, 90 degrees. The first recess 140S and the second recess 140D may not expose the buffer layer 122. For example, the first recess 140S and the second recess 140D may sandwich the unetched portion of the channel layer 124 between themselves and the buffer layer 122.

[0029] Next, as shown in FIG. 5 , the mask 200 is removed. Next, a second nitride semiconductor layer 142S is formed in the first recess 140S and the opening 130S, and a third nitride semiconductor layer 142D is formed in the second recess 140D and the opening 130D. The second nitride semiconductor layer 142S is formed on the channel layer 124 in the first recess 140S and the opening 130S. The third nitride semiconductor layer 142D is formed on the channel layer 124 in the second recess 140D and the opening 130D. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can be formed by, for example, a sputtering method. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are, for example, n-type GaN layers. The electrical resistance of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D is lower than the electrical resistance of the channel region 155. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are epitaxially grown as single crystals. Meanwhile, a polycrystalline layer 142X is also formed on the insulating layer 130. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are single crystals because they are formed on the channel layer 124, but the polycrystalline layer 142X is polycrystalline because it is formed on the insulating layer 130. Details of the method for forming the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D will be described later.

[0030] Next, as shown in Fig. 6, the polycrystalline layer 142X is removed. Fig. 6 shows the state after the polycrystalline layer 142X has been removed. The polycrystalline layer 142X can be removed using an alkaline etchant such as tetramethylammonium hydroxide (TMAH). At this time, the single-crystal second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are hardly removed.

[0031] 7, a source electrode 44S is formed on the second nitride semiconductor layer 142S, and a drain electrode 44D is formed on the third nitride semiconductor layer 142D. The source electrode 44S and the drain electrode 44D can be formed by, for example, evaporation and lift-off. The source electrode 44S is in ohmic contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in ohmic contact with the third nitride semiconductor layer 142D.

[0032] 8, opening 130G is formed in insulating layer 130. Opening 130G can be formed by RIE using a reactive gas containing fluorine (F), for example. To form opening 130G, a mask is formed and patterned in the same manner as in the formation of openings 201 and 202, but details are omitted here. Next, gate electrode 50 is formed on insulating layer 130, making Schottky contact with first nitride semiconductor layer 120 through opening 130G.

[0033] In this manner, the nitride semiconductor device 100 can be manufactured.

[0034] Next, a method for forming the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D will be described. Here, germanium (Ge) is used as the n-type impurity. FIG. 9 is a timing chart showing a method for forming the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. FIG. 9 shows whether or not Ga, Ge, and N radicals are supplied to the first nitride semiconductor layer 120 during the formation of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. "ON" in FIG. 9 indicates that there is supply, and "OFF" indicates that there is no supply. FIGS. 10 to 14 are cross-sectional views showing a method for forming the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D.

[0035] After the substrate 110 on which the first nitride semiconductor layer 120 and the like are formed is placed in a chamber, the temperature and pressure in the chamber are set to a predetermined temperature and a predetermined pressure, respectively. The predetermined temperature and pressure are selected so that the saturated vapor pressure of Ga at the predetermined temperature is lower than the predetermined pressure. For example, the predetermined temperature is 600°C, and the predetermined pressure is higher than the saturated vapor pressure of Ga at 600°C. Note that the saturated vapor pressure of Ge is lower than the saturated vapor pressure of Ga.

[0036] When the temperature and pressure in the chamber are stabilized at predetermined temperatures and pressures, respectively, the supply of N radicals 12 to the first nitride semiconductor layer 120 starts at time t11, and the supply of N radicals 12 is stopped at time t12. The supply of N radicals 12 from time t11 to time t12 cleans the surface of the first nitride semiconductor layer 120. For example, the N radicals 12 are generated by inductively coupled plasma (ICP).

[0037] At a subsequent time t1, the supply of Ga, Ge, and N radicals 12 to the first nitride semiconductor layer 120 is started, and at a subsequent time t2, the supply of Ga and Ge is stopped while the supply of N radicals 12 continues. From time t1 to time t2, the pressure in the chamber is maintained at a first pressure. The first pressure is, for example, 0.25 Pa or more and 1.05 Pa or less. By supplying Ga, Ge, and N radicals 12 from time t1 to time t2, an n-type GaN layer 10 is formed as shown in FIG. 10. Furthermore, along with the formation of the n-type GaN layer 10, droplets 11 of an alloy of Ga and Ge are formed on the surface of the n-type GaN layer 10. For example, Ga is supplied by RF (radio frequency) sputtering, and Ge is supplied by direct current (DC) pulse sputtering. The time from time t1 to time t2 is, for example, 10 seconds or more and 30 seconds or less, and may be 20 seconds or more and 30 seconds or less.

[0038] For example, the number density of droplets 11 is 6.1 × 10 4 cm -2 The droplets 11 have an average diameter of about 300 nm and a height of about 57 nm.

[0039] At time t3, the supply of Ga and Ge is started while the supply of N radicals 12 continues, as at time t1. From time t2 to time t3, the pressure in the chamber is maintained at a second pressure lower than the first pressure. The second pressure is, for example, 0.05 Pa or more and 0.1 Pa or less.

[0040] During the period from time t2 to time t3, the supply of Ga is stopped, and therefore, as shown in FIG. 11, a portion of Ga evaporates from the droplet 11 as gaseous Ga 13. Meanwhile, although the supply of Ge is also stopped, Ge remains in the droplet 11 because the saturated vapor pressure of Ge is lower than that of Ga. Furthermore, because the supply of N radicals 12 continues, Ga in the droplet 11 is nitrided while incorporating Ge. As a result, an n-type GaN layer 20 is formed, as shown in FIG. 12. During the formation of the n-type GaN layer 20, Ge remains in the droplet 11, while a portion of Ga evaporates as gaseous Ga 13. Therefore, the ratio of Ge to the total amount of Ga and Ge in the droplet 11 becomes higher than the ratio of Ge to the total amount of Ga and Ge in the n-type GaN layer 10. Therefore, the n-type GaN layer 20 formed from the droplet 11 from which Ga has evaporated contains a higher Ge concentration than the n-type GaN layer 10. The time from time t2 to time t3 is, for example, 15 seconds or more and 120 seconds or less. For example, the time from time t1 to time t2 is shorter than the time from time t2 to time t3.

[0041] Furthermore, even if the proportion of Ge in droplets 11 increases with the evaporation of Ga, the Ge does not aggregate to the extent that a critical nucleus is formed. Even if minute elemental Ge atoms are temporarily generated, the supply of Ge is stopped between time t2 and time t3, so the elemental Ge atoms decompose before growing to a critical nucleus. Therefore, no Ge precipitates are formed during the formation of n-type GaN layer 20.

[0042] At a subsequent time t2, the supply of Ga and Ge is stopped while continuing the supply of N radicals 12. By supplying Ga, Ge, and N radicals 12 from time t3 (t1) to time t2, an n-type GaN layer 10 is newly formed, and droplets 11 of an alloy of Ga and Ge are formed on the surface of the n-type GaN layer 10, as shown in FIG.

[0043] Thereafter, the process from time t1 to time t3 is repeated. As a result, a second nitride semiconductor layer 142S and a third nitride semiconductor layer 142D are formed in which n-type GaN layers 10 and 20 are alternately stacked, as shown in Fig. 14. Each of the n-type GaN layers 10 and 20 may be in direct contact with the first nitride semiconductor layer 120, for example.

[0044] In general, the lower the pressure in the chamber, the higher the crystallinity of the semiconductor layer formed by sputtering. However, when the pressure in the chamber is maintained at the second pressure during the supply of Ga and Ge in a nitride semiconductor device manufacturing method according to a reference example employing hypothetical conditions, depressions 165 may be formed near the insulating layer 130 on the upper surfaces of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, as shown in FIG. 15 . This is because droplets 11 are unlikely to be formed uniformly on the surface of the n-type GaN layer 10, resulting in dense and sparse areas of droplets 11 on the surface of the n-type GaN layer 10. Furthermore, the shape and size of the depressions 165 in the ZX cross section are nonuniform along the Y-axis.

[0045] When removing the polycrystalline layer 142X, the single-crystal portions of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are hardly etched, but the low-crystallinity portions near the recesses 165 may be etched. If the low-crystallinity portions of the second nitride semiconductor layer 142S are slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recesses 165 in the ZX cross section. Similarly, if the low-crystallinity portions of the third nitride semiconductor layer 142D are slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recesses 165 in the ZX cross section. Furthermore, the degree of etching of the barrier layer 126 becomes non-uniform along the Y-axis. This causes the 2DEG concentration to become non-uniform along the Y-axis, and current tends to concentrate in areas with high 2DEG concentration and low electrical resistance. This can result in a decrease in breakdown voltage.

[0046] On the other hand, in this embodiment, the pressure in the chamber is maintained at the second pressure when the supply of Ga and Ge is stopped and N radicals 12 are supplied into the chamber, while the pressure in the chamber is maintained at the first pressure when Ga, Ge, and N radicals 12 are supplied into the chamber. As a result, the mean free paths of the Ga, Ge, and N radicals 12 are shortened when the droplets 11 are formed, and the droplets 11 are formed with high uniformity on the surface of the n-type GaN layer 10. Therefore, the depressions 165 are unlikely to be formed, and the cap layer 128, the barrier layer 126, and the channel layer 124 are not etched when the polycrystalline layer 142X is removed. Therefore, a high breakdown voltage is obtained for the nitride semiconductor device 100.

[0047] For example, the difference between the first pressure and the second pressure is, for example, 0.3 Pa or more and 1 Pa or less. When this pressure difference is 0.3 Pa or more, the gallium and impurities ejected from the target collide with each other before entering the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, resulting in a wide angular distribution of their respective motion directions, thereby suppressing the effect of shielding by the polycrystalline layer 142X. For example, the gallium and impurities can reach portions of the polycrystalline layer 142X that are shaded from the target. This reduces the formation of depressions 165. When this pressure difference is 1 Pa or less, it is possible to suppress excessive collisions, reactions, and deactivation of the gallium and impurities before they adhere to the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. This pressure difference may be 0.4 Pa or more and 0.9 Pa or less, or 0.5 Pa or more and 0.7 Pa or less.

[0048] The mean free path of the N radicals in the chamber maintained at the first pressure is, for example, 0.5 cm or more and 2 cm or less. When this mean free path is 0.5 cm or more, the gallium and impurities emitted from the target collide with each other before entering the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, resulting in a wide angular distribution of their respective motion directions, thereby suppressing the effect of shielding by the polycrystalline layer 142X. For example, the gallium and impurities can reach portions of the polycrystalline layer 142X that are shaded from the target. This reduces the formation of depressions 165. When this mean free path is 2 cm or less, the gallium and impurities emitted from the target collide with each other excessively, suppressing deactivation before adhering to the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The mean free path may be 0.7 cm or more and 1.8 cm or less, or 1 cm or more and 1.5 cm or less.

[0049] The mean free path of the N radicals in the chamber maintained at the second pressure is, for example, 2 cm or more and 8 cm or less. A mean free path of 2 cm or more prevents the nitrogen radicals from being deactivated before reaching the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, making it possible to form the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D with better crystallinity. A mean free path of 8 cm or less allows a large number of radicals to be generated, and the nitrogen radicals can be efficiently supplied to the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The mean free path may be 3 cm or more and 7 cm or less, or 4 cm or more and 6 cm or less.

[0050] If the time from time t1 to time t2 is shorter than the time from time t2 to time t3, the droplets 11 tend to disappear when the n-type GaN layer 20 is formed from the droplets 11.

[0051] By including n-type impurities in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, it is easy to obtain low electrical resistance in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The n-type impurity is not limited to Ge, but may be silicon (Si). The first and second pressures described above can be set for Si as well as for Ge. The concentration of the n-type impurity is, for example, 1×10 20 cm -3 The concentration of n-type impurities is 1×10 20 cm -3 When the concentration of n-type impurities is 5×10 or more, it is easy to obtain a particularly low electrical resistance in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. 20 cm -3 May be greater than 1 x 10 21 cm -3 The concentration of the n-type impurity can be measured by, for example, secondary ion mass spectrometry (SIMS).

[0052] As described above, by alternately stacking n-type GaN layers 10 and 20 formed at different pressures, it is possible to reduce recesses 165 without impairing crystallinity, thereby improving the breakdown voltage of nitride semiconductor device 100.

[0053] The multiple sets of n-type GaN layers 10 and 20 may be divided into two sets, and the first and second pressures used to form the first set may be different from the first and second pressures used to form the second set. For example, the first and second pressures used to form the second set may be higher than the first and second pressures used to form the first set. This improves the crystallinity of the first set compared to the second set, while preventing the formation of recesses 165 in the second set.

[0054] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0055] 10:n-type GaN layer 11:Droplet 12:N radical 20:n-type GaN layer 44D: Drain electrode 44S: Source electrode 50: Gate electrode 100: Nitride semiconductor device 110: Substrate 120: First nitride semiconductor layer 122: Buffer layer 124: Channel layer 126: Barrier layer 128: Cap layer 130: Insulating layer 130D, 130G, 130S, 201, 202: Aperture 140D: Second recess 140S: First recess 142D: Third nitride semiconductor layer 142S: Second nitride semiconductor layer 142X: Polycrystalline layer 155: Channel region 161:Top surface 165: Depression 200: Mask t1, t2, t3, t11, t12: Time

Claims

1. providing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a first recess and a second recess in the first nitride semiconductor layer along a second axis perpendicular to the first axis, the first recess and the second recess sandwiching the channel layer and the barrier layer therebetween; forming a second nitride semiconductor layer containing gallium and an impurity in the first recess by a sputtering method in a chamber, and forming a third nitride semiconductor layer containing gallium and an impurity in the second recess; and The steps of forming the second nitride semiconductor layer and the third nitride semiconductor layer include: supplying gallium, the impurities, and nitrogen radicals into the chamber while maintaining a pressure in the chamber at a first pressure; stopping the supply of gallium and the impurity and supplying nitrogen radicals into the chamber while maintaining the pressure in the chamber at a second pressure lower than the first pressure; a nitride semiconductor device manufacturing method comprising the steps of:

2. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein a difference between the first pressure and the second pressure is 0.3 Pa or more and 1 Pa or less.

3. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a mean free path of nitrogen radicals in said chamber maintained at said first pressure is not less than 0.5 cm and not more than 2 cm.

4. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a mean free path of nitrogen radicals in said chamber maintained at said second pressure is not less than 2 cm and not more than 8 cm.

5. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a time period for the step of supplying gallium, the impurity, and nitrogen radicals into the chamber is shorter than a time period for the step of stopping the supply of gallium and the impurity and supplying nitrogen radicals into the chamber.

6. a step of forming an insulating layer on the first surface, the insulating layer having a first opening connected to the first recess and a second opening connected to the second recess, between the step of forming the first nitride semiconductor layer and the step of forming the first recess and the second recess; 3. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising, after the steps of forming the second nitride semiconductor layer and the third nitride semiconductor layer, a step of removing a polycrystalline layer formed on the insulating layer when forming the second nitride semiconductor layer and the third nitride semiconductor layer.

7. In each of the second nitride semiconductor layer and the third nitride semiconductor layer, the concentration of the impurity is 1×10 ２０ cm －３ The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein:

Images