Memory system

Abstract

To provide a memory system capable of preventing failure of initialization due to fluctuation of supply voltage.SOLUTION: According to an embodiment, a memory system includes a memory, a controller, and a power supply control circuit. The controller controls the memory. The power supply control circuit includes a DC / DC converter that controls power supplied to the memory and the controller and generates an internal power supply voltage of the memory system. The DC / DC converter can generate an internal power supply voltage in one of a first mode in which the DC / DC converter is automatically switched to one of a pulse width modulation mode and a pulse frequency modulation mode and a second mode in which the DC / DC converter is fixed to the pulse width modulation mode, and starts an operation in the second mode after the memory system transitions from a low power consumption mode to a normal operation mode.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a memory system including a nonvolatile memory and a power supply control circuit for the memory system. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memory have become widespread. One such memory system is the solid-state drive (SSD) equipped with NAND flash memory. SSDs are used as the main storage of various computing devices.

[0003] The memory system includes a power supply control circuit that controls the power supplied to each component in the memory system.

[0004] The memory system may also be set to a low power consumption mode, which consumes less power than the normal operating mode.

[0005] When the memory system returns from the low power consumption mode to the normal operation mode, at least a part of the memory system is initialized. Furthermore, the power supplied from the power supply control circuit to each component in the memory system immediately after the return may have large voltage fluctuations. Such fluctuations in the supply voltage may cause the initialization of the memory system to fail. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 9,030,182 [Patent Document 2] U.S. Patent No. 9,748,838 [Patent Document 3] U.S. Patent No. 8,953,341 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a memory system and a power supply control circuit that can prevent initialization failures due to fluctuations in the supply voltage. [Means for solving the problem]

[0008] According to an embodiment, a memory system includes a memory, a controller, and a power supply control circuit. The controller controls the memory. The power supply control circuit controls power supplied to the memory and the controller and includes a DC / DC converter that generates an internal power supply voltage for the memory system. The DC / DC converter can generate the internal power supply voltage in either a first mode that is automatically switched between a pulse width modulation mode and a pulse frequency modulation mode, or a second mode that is fixed to the pulse width modulation mode, and starts operating in the second mode after the memory system transitions from a low power consumption mode to a normal operation mode. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a power supply control circuit in a memory system according to the embodiment. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a DC / DC mode setting register used in the memory system according to the embodiment. [Figure 4] 10 is a time chart showing the operation and voltage transition when a memory system according to a comparative example returns from a low power consumption mode to a normal operation mode. [Figure 5] FIG. 10 is a diagram showing an example of the configuration of a sleep mode control register used in a memory system according to a comparative example. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a sleep mode control register used in the memory system according to the embodiment. [Figure 7]FIG. 10 is a sequence diagram showing an example of an operation when the memory system according to the embodiment returns from a low power consumption mode to a normal operation mode. [Figure 8] 6 is a time chart showing an example of transitions in operation, voltage, and current when the memory system according to the embodiment returns from a low power consumption mode to a normal operation mode. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] First, an example of the configuration of an information processing system 1 including a memory system according to an embodiment will be described with reference to Fig. 1. The information processing system 1 includes a host device 2 and a memory system 3.

[0012] The host device 2 is, for example, a storage server or a personal computer, and is capable of saving data to the memory system 3 and reading data from the memory system 3. Hereinafter, the host device 2 will also be referred to as the host 2.

[0013] The memory system 3 is a storage device configured to write data to a nonvolatile memory such as a NAND flash memory 5 and read data from the nonvolatile memory. Note that the nonvolatile memory is not limited to a NAND flash memory. The memory system 3 is also called a storage device. The memory system 3 is realized as, for example, a solid state drive (SSD).

[0014] The memory system 3 can be used as storage for the host 2. The memory system 3 is connected to the host 2 via, for example, a cable.

[0015] The interface for connecting the host 2 and the memory system 3 complies with standards such as PCI Express (PCIe) (registered trademark) and NVM Express (NVMe) (registered trademark).

[0016] The memory system 3 operates, for example, in either a normal operation mode or a low power consumption mode. The low power consumption mode is an operation mode in which power consumption is lower than that in the normal operation mode. Examples of low power consumption modes include an off mode in which power supply to at least a portion of the configuration within the memory system 3 is stopped, and a low power mode (LPM) in which operation and performance are limited to lower power consumption than in normal operation. Low power modes also include a mode called a sleep mode. Providing multiple low power consumption modes such as the off mode and sleep mode makes it possible to more effectively control the reduction of power consumption in the memory system 3. The low power consumption mode may include two or more modes. As described above, the low power consumption mode of the memory system 3 of this embodiment may be provided with multiple power states with different power consumptions.

[0017] The memory system 3 includes, for example, a dynamic random access memory (DRAM) 4, a NAND flash memory 5, a power supply control circuit 6, and a controller 7.

[0018] The DRAM 4 is a volatile RAM, and is provided with a storage area for firmware (FW) 51, for example.

[0019] The FW 51 is a program for controlling the operation of the controller 7. The FW 51 is loaded from the NAND flash memory 5 to the DRAM 4 when the memory system 3 is started up, for example.

[0020] The NAND flash memory 5 includes multiple blocks (not shown). Each of the multiple blocks includes multiple pages. A block functions as the smallest unit of a data erase operation. A block may also be referred to as an "erase block" or a "physical block." Each of the multiple pages includes multiple memory cells connected to a single word line. A page functions as a unit of a data write operation and a data read operation. Note that a word line may also function as a unit of a data write operation and a data read operation.

[0021] The power supply control circuit 6 is a circuit that controls the power supplied to each component of the memory system 3 (e.g., the DRAM 4, the NAND flash memory 5, and the controller 7). The power supply control circuit 6 is realized, for example, as a power management IC (PMIC). The power supply control circuit 6 transitions to sleep mode in response to the memory system 3 transitioning from normal operation mode to low power consumption mode. The power supply control circuit 6 returns from sleep mode in response to the memory system 3 transitioning from low power consumption mode to normal operation mode. The sleep mode is a mode in which at least some of the circuit blocks in the power supply control circuit 6 are turned off to reduce power consumption.

[0022] The power supply control circuit 6 can communicate with the controller 7. The communication between the power supply control circuit 6 and the controller 7 complies with a serial communication standard such as Inter-Integrated Circuit (I2C) (not shown). The power supply control circuit 6 receives, for example, a command from the controller 7 through communication. This command is, for example, a command for controlling the operation of the power supply control circuit 6. A specific configuration of the power supply control circuit 6 will be described later with reference to FIG. 2.

[0023] The controller 7 is configured to control the DRAM 4, the NAND flash memory 5, and the power supply control circuit 6. The controller 7 is realized by a circuit such as a system-on-a-chip (SoC). The controller 7 may include a static random access memory (SRAM) or a DRAM. In this case, the DRAM 4 external to the controller 7 may not be provided.

[0024] The controller 7 includes, for example, a host interface (host I / F) 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, and a CPU 14. The host I / F 11, the NAND I / F 12, the DRAM I / F 13, and the CPU 14 are connected via, for example, a bus 10.

[0025] The host I / F 11 functions as a circuit that receives various commands, such as I / O commands, various control commands, and data, from the host 2. The host I / F 11 also functions as a circuit that transmits responses to commands and data to the host 2. The host I / F 11 includes a PCIe PHY 15.

[0026] The PCIe PHY 15 is a circuit that connects to the host 2 via a serial interface. This serial interface includes a link that can interconnect the host 2 and the memory system 3. The PCIe PHY 15 corresponds to the physical layer defined by the PCIe standard. The PCIe PHY 15 has, for example, a physical connection format that complies with the PCIe standard. The PCIe PHY 15 performs interface operations to physically send and receive data via the link.

[0027] The NAND I / F 12 electrically connects the controller 7 and the NAND flash memory 5. The NAND I / F 12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0028] The NAND I / F 12 functions as a NAND control circuit configured to control access to the NAND flash memory 5. The NAND I / F 12 may be connected to multiple memory chips in the NAND flash memory 5 via multiple channels (Ch). By driving multiple memory chips in parallel, it is possible to widen the bandwidth of access to the entire NAND flash memory 5.

[0029] The DRAM I / F 13 functions as a DRAM control circuit configured to control access to the DRAM 4 .

[0030] The CPU 14 is a processor configured to control the host I / F 11, the NAND I / F 12, and the DRAM I / F 13. The CPU 14 performs various processes by executing the FW 51 loaded from the NAND flash memory 5 to the DRAM 4. The FW 51 is a control program including a group of instructions for causing the CPU 14 to perform various processes. The CPU 14 can execute command processing and the like for processing various commands from the host 2. The operation of the CPU 14 is controlled by the FW 51 executed by the CPU 14.

[0031] The functions of the various units in the controller 7 may be realized by dedicated hardware in the controller 7, or may be realized by the CPU 14 executing the FW 51.

[0032] Next, a description will be given of the configuration of the power supply control circuit 6. FIG.

[0033] The power supply control circuit 6 includes, for example, a control logic 61, a load switch 62, a low dropout (LDO) regulator 63, and one or more DC / DC converters 64 (64-1, 64-2, 64-3, 64-4, . . . ).

[0034] The control logic 61 is a circuit that controls each unit in the power supply control circuit 6. The control logic 61 controls the operation of each unit in the power supply control circuit 6, for example, by sending a control signal. The control logic 61 can also monitor a value related to a current flowing through a circuit block to which power is supplied from the power supply control circuit 6. The monitored current value may be the current value itself, or an index or signal representing the current value. The circuit block is included in, for example, either the controller 7 or the NAND flash memory 5. More specifically, the circuit block is, for example, the SoC core part that is the controller 7, the core part and input / output (I / O) part of the NAND flash memory 5, and the PCIe PHY 15. From the perspective of the power supply control circuit 6, the circuit block to which power is supplied is also referred to as a load. The current flowing through the load is also referred to as a load current.

[0035] The load switch 62 is a switch circuit that switches between supplying (ON) and stopping (OFF) power to each component in the power supply control circuit 6. A power supply voltage VIN is supplied to the load switch 62 from an external power supply. The load switch 62 switches the power supply ON and OFF in response to a control signal from the control logic 61. While the load switch 62 is set to ON, it outputs a power supply voltage VOUT.

[0036] The power supply voltage VOUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The power supply voltage VOUT is taken into the power supply control circuit 6 via another pin of the power supply control circuit 6. More specifically, the power supply voltage VOUT is input as an input power supply voltage LDO_IN of an LDO regulator 63. The power supply voltage VOUT is also input as an input power supply voltage PVIN of one or more DC / DC converters 64.

[0037] The LDO regulator 63 is a linear regulator that can operate with a low input / output potential difference. The LDO regulator 63 adjusts the input power supply voltage LDO_IN by voltage control and outputs the internal power supply voltage LDO_OUT. The input power supply voltage LDO_IN may be a voltage other than the output voltage VOUT of the load switch 62. The operation of the LDO regulator 63 is set to operate (ON) or stop (OFF) according to a control signal from the control logic 61. While the LDO regulator 63 is set to ON, it outputs the internal power supply voltage LDO_OUT.

[0038] The internal power supply voltage LDO_OUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The internal power supply voltage LDO_OUT is, for example, 1.8 volts (V). The internal power supply voltage LDO_OUT is used, for example, as an analog power supply for the SoC that is the controller 7.

[0039] Each of the one or more DC / DC converters 64 is a converter that converts voltage with direct current. Each of the one or more DC / DC converters 64 generates an internal power supply voltage to be supplied to a circuit block included in either the controller 7 or the NAND flash memory 5. The number of DC / DC converters 64 provided in the power supply control circuit 6 is based on the number of components (e.g., circuit blocks) in the memory system 3 to which power is supplied from the power supply control circuit 6. In the following description, any one of the one or more DC / DC converters 64 may be simply referred to as a DC / DC converter 64. Here, a case will be described in which the one or more DC / DC converters 64 include four DC / DC converters 64-1, 64-2, 64-3, and 64-4 as shown in the figure.

[0040] The first DC / DC converter 64-1 receives the power supply voltage VOUT from the load switch 62 as the input power supply voltage PVIN1. The first DC / DC converter 64-1 adjusts the input power supply voltage PVIN1 by voltage control and outputs an internal power supply voltage DC / DC1_OUT. A voltage other than the output voltage VOUT of the load switch 62 may be used as the input power supply voltage PVIN1. The operation of the first DC / DC converter 64-1 is set to operate (ON) or stop (OFF) in accordance with a control signal from the control logic 61. While the first DC / DC converter 64-1 is set to ON, it outputs the internal power supply voltage DC / DC1_OUT.

[0041] The internal power supply voltage DC / DC1_OUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The internal power supply voltage DC / DC1_OUT is, for example, 2.5 V. The internal power supply voltage DC / DC1_OUT is used, for example, as a power supply for a core portion of the NAND flash memory 5. In other words, the internal power supply voltage DC / DC1_OUT is supplied to a circuit block of the core portion of the NAND flash memory 5. The power supply path through which the internal power supply voltage DC / DC1_OUT is supplied from the first DC / DC converter 64-1 to the core portion of the NAND flash memory 5 is referred to as a DC / DC channel CH1. Information (for example, a number) that can uniquely identify the corresponding DC / DC converter 64 is assigned to the DC / DC channel that is the power supply path.

[0042] The second DC / DC converter 64-2 receives the power supply voltage VOUT from the load switch 62 as the input power supply voltage PVIN2. The second DC / DC converter 64-2 adjusts the input power supply voltage PVIN2 by voltage control and outputs an internal power supply voltage DC / DC2_OUT. A voltage other than the output voltage VOUT of the load switch 62 may be used as the input power supply voltage PVIN2. The operation of the second DC / DC converter 64-2 is set to operate (ON) or stop (OFF) in accordance with a control signal from the control logic 61. While the second DC / DC converter 64-2 is set to ON, it outputs the internal power supply voltage DC / DC2_OUT.

[0043] The internal power supply voltage DC / DC2_OUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The internal power supply voltage DC / DC2_OUT is, for example, 1.2 V. The internal power supply voltage DC / DC2_OUT is used, for example, as a power supply for the I / O portion of the NAND flash memory 5. In other words, the internal power supply voltage DC / DC2_OUT is supplied to the circuit block of the I / O portion of the NAND flash memory 5. The power supply path from the second DC / DC converter 64-2 to the I / O portion of the NAND flash memory 5 via the internal power supply voltage DC / DC2_OUT is referred to as DC / DC channel CH2.

[0044] The third DC / DC converter 64-3 receives the power supply voltage VOUT from the load switch 62 as the input power supply voltage PVIN3. The third DC / DC converter 64-3 adjusts the input power supply voltage PVIN3 by voltage control and outputs the internal power supply voltage DC / DC3_OUT. A voltage other than the output voltage VOUT of the load switch 62 may be used as the input power supply voltage PVIN3. The operation of the third DC / DC converter 64-3 is set to operate (ON) or stop (OFF) in accordance with a control signal from the control logic 61. While the third DC / DC converter 64-3 is set to ON, it outputs the internal power supply voltage DC / DC3_OUT.

[0045] The internal power supply voltage DC / DC3_OUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The internal power supply voltage DC / DC3_OUT is, for example, 1.2 V. The internal power supply voltage DC / DC3_OUT is used, for example, to power the PCIe PHY 15 included in the SoC that is the controller 7. In other words, the internal power supply voltage DC / DC3_OUT is supplied to a circuit block of the PCIe PHY 15. The power supply path from the third DC / DC converter 64-3 to the PCIe PHY 15 via the internal power supply voltage DC / DC3_OUT is referred to as a DC / DC channel CH3.

[0046] The fourth DC / DC converter 64-4 receives the power supply voltage VOUT from the load switch 62 as an input power supply voltage PVIN4. The fourth DC / DC converter 64-4 adjusts the input power supply voltage PVIN4 by voltage control and outputs an internal power supply voltage DC / DC4_OUT. A voltage other than the output voltage VOUT of the load switch 62 may be used as the input power supply voltage PVIN4. The operation of the fourth DC / DC converter 64-4 is set to operate (ON) or stop (OFF) in accordance with a control signal from the control logic 61. While the fourth DC / DC converter 64-4 is set to ON, it outputs the internal power supply voltage DC / DC4_OUT.

[0047] The internal power supply voltage DC / DC4_OUT is output to the outside of the power supply control circuit 6 via a pin of the power supply control circuit 6. The internal power supply voltage DC / DC4_OUT is, for example, 0.8 V. The internal power supply voltage DC / DC4_OUT is used as a power supply for the core part of the SoC, which is, for example, the controller 7. In other words, the internal power supply voltage DC / DC4_OUT is supplied to the circuit blocks of the core part of the SoC.

[0048] Note that, as the DC / DC converter 64 of the power supply control circuit 6, another DC / DC converter that outputs a power supply voltage to the DRAM 4 shown in FIG. 1 may be provided.

[0049] The control logic 61 also includes, for example, one or more registers 65 .

[0050] Each of the registers 65 is a storage element. Each of the storage elements may store, for example, a value that defines the operation of at least a part of the configuration of the power supply control circuit 6. The values ​​stored in the storage elements are set or updated, for example, in response to a request from the controller 7. The request from the controller 7 is realized, for example, as a command issued by the CPU 14 executing the firmware 51. The registers 65 include, for example, a DC / DC mode setting register 65-1 and a sleep mode control register 65-2.

[0051] The DC / DC mode setting register 65-1 is a register for setting the operation mode of each of one or more DC / DC converters 64 (64-1, 64-2, 64-3, 64-4, ...). A specific configuration example of the DC / DC mode setting register 65-1 will be described later with reference to FIG.

[0052] For example, while the memory system 3 is set to the normal operation mode, each of the DC / DC converters 64 can operate in an operation mode based on the value set in the DC / DC mode setting register 65-1. Each of the DC / DC converters 64 includes a circuit such as a switch that operates based on the value set in the DC / DC mode setting register 65-1.

[0053] The sleep mode control register 65-2 is a register for (1) settings related to the transition of the power supply control circuit 6 to sleep mode and recovery from sleep mode, and (2) settings related to the operation modes of the LDO regulator 63 and the DC / DC converter 64 while the power supply control circuit 6 is in sleep mode. A specific configuration example of the sleep mode control register 65-2 will be described later with reference to FIG. 6.

[0054] The power supply control circuit 6 (more specifically, the LDO regulator 63 and the DC / DC converter 64) can operate based on the value set in the sleep mode control register 65-2, for example, when the memory system 3 transitions from the normal operation mode to the low power consumption mode, and when the memory system 3 transitions from the low power consumption mode to the normal operation mode. Each of the LDO regulator 63 and the DC / DC converter 64 includes a circuit such as a switch that operates based on the value set in the sleep mode control register 65-2.

[0055] Here, the operation mode of the DC / DC converter 64 will be described.

[0056] The operating mode of the DC / DC converter 64 is, for example, any of a pulse frequency modulation (PFM) mode, a pulse width modulation (PWM) mode, an auto mode, and an off mode. Each of PFM and PWM is a voltage control method used by the DC / DC converter 64 to generate an output voltage.

[0057] Pulse frequency modulation mode (PFM mode) is a voltage control mode with a variable frequency and a constant pulse width. In PFM mode, power consumption is low, but output voltage fluctuations are large.

[0058] Pulse width modulation mode (hereinafter referred to as PWM mode) is a mode that uses a voltage control method in which the frequency is constant and the pulse width is variable. In PWM mode, power consumption is high, but the fluctuation of the output voltage is small.

[0059] Auto mode is a mode that automatically switches between PFM mode and PWM mode depending on the load current. In auto mode, if the load current exceeds a boundary while operating in PFM mode, the mode switches to PWM mode. Also, if the load current falls below the boundary while operating in PWM mode, the mode switches to PFM mode. The boundary value has hysteresis to prevent frequent switching between PFM mode and PWM mode near the boundary value. Due to hysteresis, for example, the boundary value can be set higher when switching from PFM mode to PWM mode than when switching from PWM mode to PFM mode.

[0060] 3 is a diagram showing an example of the configuration of a DC / DC mode setting register 65-1 used in the memory system 3. The DC / DC mode setting register 65-1 includes, for example, an 8-bit storage area. Hereinafter, the 8-bit storage areas of the register will be referred to, starting from the least significant bit, as the 0th bit storage area, the 1st bit storage area, ..., and the 7th bit storage area.

[0061] The seventh bit storage area stores a value indicating the operation mode of the first DC / DC converter 64-1 (i.e., DC / DC channel CH1) while the memory system 3 is in normal operation mode. If the stored value is 0, the first DC / DC converter 64-1 operates in auto mode. If the stored value is 1, the first DC / DC converter 64-1 operates in forced PWM mode. Forced PWM mode is a PWM mode in which automatic switching does not occur, as in auto mode. When set to forced PWM mode, the operation mode of the DC / DC converter 64 is fixed to PWM mode.

[0062] The sixth bit of the storage area stores a value indicating the operation mode of the second DC / DC converter 64-2 (i.e., DC / DC channel CH2) while the memory system 3 is in the normal operation mode. If the stored value is 0, the second DC / DC converter 64-2 operates in the auto mode. If the stored value is 1, the second DC / DC converter 64-2 operates in the forced PWM mode.

[0063] The fifth bit of the storage area stores a value indicating the operation mode of the third DC / DC converter 64-3 (i.e., DC / DC channel CH3) while the memory system 3 is in the normal operation mode. If the stored value is 0, the third DC / DC converter 64-3 operates in the auto mode. If the stored value is 1, the third DC / DC converter 64-3 operates in the forced PWM mode.

[0064] The storage area for the 4th bit to the 0th bit is an unused (reserved) area.

[0065] The DC / DC mode setting register 65-1 may further store values ​​indicating the operation modes of other DC / DC converters 64.

[0066] Each of the DC / DC converters 64 can operate based on the value set in the DC / DC mode setting register 65-1 while the memory system 3 is in the normal operation mode, for example. Therefore, by setting a value in the DC / DC mode setting register 65-1, the operation mode of each of the DC / DC converters 64 while the memory system 3 is in the normal operation mode can be set to either the auto mode or the forced PWM mode. Note that the value set in the DC / DC mode setting register 65-1 is performed based on a command issued to the power supply control circuit 6 from the CPU 14 that executes the firmware 51, for example.

[0067] Here, we will explain the operation of the memory system according to the comparative example when it returns from the low power consumption mode to the normal operation mode. The memory system according to the comparative example has the same configuration as the memory system 3 according to this embodiment, except for the configuration related to the control of the operation mode of the DC / DC converter.

[0068] 4 is a time chart 8 showing operation and voltage transitions when a memory system according to a comparative example returns from a low power consumption mode to a normal operation mode. That is, the time chart 8 shows transitions over time of an internal power supply voltage 81 supplied to the NAND flash memory, an operation mode 82 of a DC / DC converter, an internal power supply voltage 83 supplied to a PCIe PHY, and an operation 84 of the PCIe PHY. The horizontal axis of the time chart 8 represents time.

[0069] Time t11 is the time when the memory system is requested to return from low power consumption mode to normal operation mode. At time t11, the memory system is in low power consumption mode, and the power supply control circuit is in sleep mode. Therefore, the operation mode 82 of the DC / DC converters in the power supply control circuit is either off or in PFM mode, which consumes less power for each DC / DC converter. The internal power supply voltage 81 supplied to the NAND flash memory is off and low, and the DC / DC converters that are on are in PFM mode. In addition, operation 84 of the PCIe PHY is disabled.

[0070] The period from time t11 to time t12 is the period during which the memory system transitions from the low power consumption mode to the normal operation mode. During this period, the internal power supply voltage 81 supplied to the NAND flash memory gradually increases.

[0071] At time t12, the memory system returns from the low power consumption mode to the normal operation mode. At time t12, the operation mode 82 of the DC / DC converter transitions to the auto mode. At this time, the load current is small, so the PFM mode is set based on the automatic switching in the auto mode.

[0072] Next, during the period from time t12 to time t14, the operation 84 of the PCIe PHY transitions from disabled to activated, and then transitions to initialization. The initialization includes, for example, calibration. The calibration is, for example, an operation of passing a current through a resistor provided in the PCIe PHY to adjust for variations between chips (ICs). The load current of the PCIe PHY during the activation and initialization is small. Therefore, the operation mode 82 of the DC / DC converter is maintained in PFM mode. While the operation mode 82 of the DC / DC converter is in PFM mode, fluctuations in the internal power supply voltage 83 supplied to the PCIe PHY become large.

[0073] Within the period from time t12 to time t14, the period from time t13 to time t14 is a period during which the internal power supply voltage 83 supplied to the PCIe PHY fluctuates significantly. During this period, the PCIe PHY starts initialization. For example, calibration involves passing a current through a resistor provided in the PCIe PHY to adjust for variations between chips, so it is necessary to minimize voltage fluctuations. In other words, calibration is an operation that is sensitive to voltage fluctuations. However, because the internal power supply voltage 83 fluctuates significantly, the PCIe PHY may not perform appropriate calibration. Therefore, under such voltage fluctuations in the internal power supply voltage 83, initialization of the PCIe PHY may fail.

[0074] At time t14, the initialization of the PCIe PHY operation 84 is completed and the operation shifts to normal operation. At this timing, the operation mode 82 of the DC / DC converter is maintained in the PFM mode.

[0075] Thereafter, at time t15, the operation mode 82 of the DC / DC converters transitions to the PWM mode based on automatic switching in the auto mode. The timing at which the automatic switching is triggered is set, for example, when the load current corresponding to any of the DC / DC converters exceeds a preset boundary value.

[0076] As in the comparative example described above, there is a possibility that initialization of the PCIe PHY will fail depending on the operation when the memory system returns from the low power consumption mode.

[0077] For example, at time t12, after the memory system returns from the low-power consumption mode to the normal operating mode, the DC / DC converter's operating mode can be transitioned to the forced PWM mode by setting the DC / DC mode setting register. This method also allows the PCIe PHY to be initialized while the DC / DC converter operates in the forced PWM mode, which has a small voltage fluctuation. In this case, however, it is desirable to transition the DC / DC converter to the forced PWM mode immediately after the memory system returns from the low-power consumption mode to the normal operating mode. This is because power consumption increases during the transition from the low-power consumption mode to the forced PWM mode. On the other hand, transitioning to the forced PWM mode immediately after returning from the low-power consumption mode to the normal operating mode requires issuing a command to set the forced PWM mode after returning to the normal operating mode, which delays the timing of starting access to the NAND flash memory by the time required for this operation. Furthermore, if the DC / DC converter continues to be maintained in the forced PWM mode, power consumption may increase compared to when the DC / DC converter is set to the auto mode.

[0078] 5 is a diagram showing an example of the configuration of a sleep mode control register used in a memory system according to a comparative example, which includes, for example, an 8-bit storage area.

[0079] The seventh bit storage area stores a value indicating the operation of the DC / DC channel CH1 while the power supply control circuit is in sleep mode.

[0080] If the stored value is 0, the DC / DC channel CH1 is turned off, i.e., the first DC / DC converter is in the off mode.

[0081] If the stored value is 1, DC / DC channel CH1 is open and transitions to low power mode (LPM). While DC / DC channel CH1 is in LPM, the first DC / DC converter is fixed in PFM mode. In the first DC / DC converter fixed in PFM mode, circuit blocks that are only used in PWM mode are turned off. In other words, power is not supplied to circuit blocks that are only used in PWM mode. This allows the DC / DC channel set to LPM to reduce power consumption.

[0082] The sixth bit of the storage area stores a value indicating the operation of the DC / DC channel CH2 while the power supply control circuit is in the sleep mode.

[0083] If the stored value is 0, the DC / DC channel CH2 is turned off, i.e., the second DC / DC converter is in the off mode.

[0084] If the stored value is 1, the DC / DC channel CH2 is open and transitions to LPM, in which case the second DC / DC converter is fixed in PFM mode.

[0085] The fifth bit of the storage area stores a value indicating the operation of the DC / DC channel CH3 while the power supply control circuit is in the sleep mode.

[0086] If the stored value is 0, the DC / DC channel CH3 is turned off, that is, the third DC / DC converter is in the off mode.

[0087] If the stored value is 1, the DC / DC channel CH3 is open and transitions to LPM, in which case the third DC / DC converter is fixed in PFM mode.

[0088] The fourth bit of the storage area stores a value indicating the operation of the LDO regulator while the power supply control circuit 6 is in the sleep mode.

[0089] If the stored value is 0, the power path provided by the LDO regulator is turned off, i.e., the LDO regulator is in off mode.

[0090] If the stored value is 1, the power supply path of the LDO regulator is open, and the LDO regulator transitions to LPM. In this case, the LDO regulator reduces the control current.

[0091] The storage area from the third bit to the first bit is an unused area.

[0092] The 0th bit of the memory area stores a value related to the transition and return of the power supply control circuit to and from sleep mode. If the stored value is 0, the power supply control circuit returns from sleep mode. If the stored value is 1, the power supply control circuit transitions to sleep mode.

[0093] In this way, in the memory system according to the comparative example, the first to third DC / DC converters and the LDO regulator are each set to off mode or LPM while the power supply control circuit is in sleep mode by setting the sleep mode control register. This reduces power consumption in the power supply control circuit. Whether the first to third DC / DC converters and the LDO regulator are set to off mode or LPM is determined based on the power state of the low power consumption mode to which the memory system is set.

[0094] Furthermore, the sleep mode control register of the memory system according to the comparative example does not specify the operating mode of the DC / DC converter when the memory system returns from the low power consumption mode to the normal operating mode (i.e., when the power supply control circuit returns from the sleep mode). Therefore, in this case, the operating mode of the DC / DC converter typically transitions to, for example, auto mode, but because the load current is small, it is set to PFM mode based on automatic switching in auto mode. In this PFM mode, the voltage fluctuations are large, which may result in initialization failure in the PCIe PHY, for example.

[0095] In contrast, in the memory system 3 of this embodiment, when the memory system 3 returns from the low power consumption mode to the normal operation mode, the operation mode of the DC / DC converter 64 is transitioned to the forced PWM mode. The forced PWM mode is a PWM mode in which automatic switching, such as in the auto mode, does not occur. In the forced PWM mode, voltage fluctuations are small. Therefore, initialization failures in the memory system 3 (e.g., PCIe PHY 15) can be prevented.

[0096] More specifically, in the memory system 3, when the memory system 3 returns from the low power consumption mode to the normal operation mode, the sleep mode control register 65-2 is used to transition the operation mode of the DC / DC converter 64 to the forced PWM mode.

[0097] 6 is a diagram showing an example of the configuration of a sleep mode control register 65-2 used in the memory system 3. The sleep mode control register 65-2 differs from the sleep mode control register of the comparative example described above with reference to FIG. 5 in the contents of the storage area for the 0th bit. The value stored in the storage areas for the 7th to 1st bits may be the same as the value stored in the storage areas for the 7th to 1st bits of the sleep mode control register of the comparative example.

[0098] The storage area of ​​bit 0 of the sleep mode control register 65-2 stores a value related to the transition to and return from sleep mode of the power supply control circuit 6. When the stored value is 0, the power supply control circuit 6 returns from sleep mode and transitions all DC / DC channels CH1 to CH4 (i.e., DC / DC converters 64-1 to 64-4) to forced PWM mode. When the stored value is 1, the power supply control circuit 6 transitions to sleep mode.

[0099] By using such a sleep mode control register 65-2, when the power supply control circuit 6 returns from the sleep mode in response to the memory system 3 returning from the low power consumption mode to the normal operation mode, the DC / DC converters 64-1 to 64-4 transition to the forced PWM mode. As a result, for example, the PCIe PHY 15 can be initialized while the third DC / DC converter 64-3 is operating in the forced PWM mode. In other words, the PCIe PHY 15 can be initialized while voltage fluctuations are small. Therefore, initialization failure can be prevented in the memory system 3. Note that in the memory system 3, the circuit block (load) targeted for preventing initialization failure is not limited to the PCIe PHY 15, and may be another circuit block that is sensitive to voltage fluctuations.

[0100] An example of the operation when the memory system 3 returns from the low power consumption mode will be specifically described.

[0101] 7 is a sequence diagram showing an example of operation when the memory system 3 returns from the low power consumption mode to the normal operation mode. Here, the operations of the control logic 61, the third DC / DC converter 64-3, and the PCIe PHY 15 are illustrated. The other DC / DC converters 64-1, 64-2, and 64-4 can operate in the same manner as the third DC / DC converter 64-3. It is also assumed that the third DC / DC converter 64-3 is set to the PFM mode while the memory system 3 is set to the low power consumption mode.

[0102] First, in response to the memory system 3 returning from the low power consumption mode to the normal operation mode, the control logic 61 sends the value stored in the sleep mode control register 65-2 to all DC / DC converters 64, including the third DC / DC converter 64-3 (A11). A value (i.e., 0) indicating that the system is returning from sleep mode and that all DC / DC channels are set to forced PWM mode is set in the 0th bit of the sleep mode control register 65-2.

[0103] The third DC / DC converter 64-3 transitions from PFM mode to forced PWM mode based on the value stored in the sleep mode control register 65-2 (A12). Note that while the memory system 3 is set to the low power consumption mode, the third DC / DC converter 64-3 may be set to the off mode. In that case, the third DC / DC converter 64-3 transitions from the off mode to the forced PWM mode based on the value stored in the sleep mode control register 65-2. As a result, the third DC / DC converter 64-3 supplies the internal power supply voltage DC / DC3_OUT to the PCIe PHY 15 in the forced PWM mode (A13).

[0104] While the power supply voltage DC / DC3_OUT is being supplied from the third DC / DC converter 64-3 in forced PWM mode, the PCIe PHY 15 performs initialization (A14). The initialization of the PCIe PHY 15 includes, for example, calibration and link training processing. The calibration is an operation that applies a current to a resistor provided in the PCIe PHY 15 to adjust for variations between chips (ICs). The link training processing is a process for making the link available, such as synchronizing the clock signals between the host 2 and the memory system 3.

[0105] Furthermore, the control logic 61 detects that the load current of any of the one or more circuit blocks corresponding to each of the one or more DC / DC converters 64 has exceeded a boundary value (A15).Then, the control logic 61 instructs all of the DC / DC converters 64, including the third DC / DC converter 64-3, to transition to the auto mode (A16).

[0106] The control logic 61 may detect that the load current of the PCIe PHY 15 corresponding to the third DC / DC converter 64-3 has exceeded a boundary value. In this case, the control logic 61 instructs the third DC / DC converter 64-3 to transition to the auto mode, for example.

[0107] Next, the third DC / DC converter 64-3 transitions from the forced PWM mode to the auto mode (A17) in response to an instruction from the control logic 61. The third DC / DC converter 64-3 supplies the internal power supply voltage DC / DC3_OUT to the PCIe PHY 15 in the auto mode (A18).

[0108] In the auto mode, the operation mode of the third DC / DC converter 64-3 is automatically switched to either the PFM mode or the PWM mode depending on the load current. Therefore, the third DC / DC converter 64-3 can supply the internal power supply voltage DC / DC3_OUT to the PCIe PHY 15 in either the PFM mode or the PWM mode switched depending on the load current.

[0109] In this way, the PCIe PHY 15 performs initialization while the internal power supply voltage DC / DC3_OUT is supplied from the third DC / DC converter 64-3 in forced PWM mode. In other words, the PCIe PHY 15 performs initialization while voltage fluctuations are small. This prevents initialization failure in the memory system 3.

[0110] Furthermore, when the load current exceeds a boundary value, the DC / DC converter 64 transitions from the forced PWM mode to the auto mode, which prevents the DC / DC converter 64 from being fixed in a state where power consumption is high (i.e., being maintained in the forced PWM mode).

[0111] The register 65 provided in the control logic 61 may further include a channel designation register 65-3. The channel designation register 65-3 is a register for designating a DC / DC channel (i.e., a DC / DC converter 64) to be transitioned to the forced PWM mode in response to the power supply control circuit 6 returning from the sleep mode. Specifically, the channel designation register 65-3 includes, for example, a plurality of storage areas. Each of the plurality of storage areas stores information indicating a DC / DC channel to be transitioned to the forced PWM mode in response to the power supply control circuit 6 returning from the sleep mode.

[0112] In this case, in A11, in response to the memory system 3 returning from the low power consumption mode to the normal operation mode, the control logic 61 may send the value stored in the sleep mode control register 65-2 and the information stored in the channel designation register 65-3 to the DC / DC converter 64. For example, the 0th bit of the sleep mode control register 65-2 stores a value (i.e., 0) indicating that the memory system 3 is to return from the sleep mode and transition the designated DC / DC channel to the forced PWM mode. Also, the channel designation register 65-3 stores information designating the DC / DC channel to transition to the forced PWM mode.

[0113] In this case, in A12, the DC / DC converter 64 corresponding to the specified DC / DC channel transitions from PFM mode (or off mode) to forced PWM mode based on the value stored in the channel designation register 65-3. Note that the DC / DC converter 64 corresponding to the undesignated DC / DC channel transitions from PFM mode (or off mode) to auto mode based on, for example, the value stored in the DC / DC mode setting register 65-1. Furthermore, the DC / DC converter 64 that transitioned to forced PWM mode transitions to auto mode in A17 in response to the load current exceeding the boundary value.

[0114] In this way, by using the configuration further including the channel specification register 65-3, when the memory system 3 returns from the low power consumption mode to the normal operation mode, only a specific DC / DC converter 64 can be transitioned to the forced PWM mode. Furthermore, the specific DC / DC converter 64 that has been transitioned to the forced PWM mode can be transitioned to the auto mode when the load current exceeds a boundary value.

[0115] 8 is a time chart 9 showing an example of transitions in operation, voltage, and current when the memory system 3 returns from the low power consumption mode to the normal operation mode. That is, the time chart 9 shows transitions over time in an internal power supply voltage 91 (i.e., DC / DC1_OUT) supplied to the NAND flash memory 5, an operation mode 92 of the DC / DC converter 64, an internal power supply voltage 93 (i.e., DC / DC3_OUT) supplied to the PCIe PHY 15, an operation 94 of the PCIe PHY 15, and a load current 95 of the PCIe PHY 15. The horizontal axis of the time chart 9 indicates time.

[0116] The boundary value 95A is a current value used to determine whether to switch between PFM mode and PWM mode when DC / DC converter 64 is in auto mode. More specifically, when load current 95 exceeds boundary value 95A, DC / DC converter 64 in auto mode is switched from PFM mode to PWM mode. When load current 95 becomes equal to or less than boundary value 95A, DC / DC converter 64 in auto mode is switched from PWM mode to PFM mode. The boundary value 95A is also used to determine whether to switch to auto mode when DC / DC converter 64 is in forced PWM mode.

[0117] Time t21 is the time when the memory system 3 is requested to return from the low power consumption mode to the normal operation mode. At time t21, the memory system 3 is in the low power consumption mode, and the power supply control circuit 6 is in the sleep mode. Therefore, the operation mode 92 of the DC / DC converters 64 in the power supply control circuit 6 is either off or in the PFM mode, which consumes less power, for each DC / DC converter. The internal power supply voltage 81 supplied to the NAND flash memory 5 is off and low, and the DC / DC converters 64 that are on are in the PFM mode. The operation 94 of the PCIe PHY is disabled. In addition, the load current 95 is low.

[0118] The period from time t21 to time t22 is a period during which the memory system 3 transitions from the low power consumption mode to the normal operation mode. During this period, the internal power supply voltage 91 supplied to the NAND flash memory 5 gradually increases and becomes higher.

[0119] Time t22 is the time when the memory system 3 returns from the low power consumption mode to the normal operation mode. At time t22, the operation mode 92 of the DC / DC converter 64 transitions to the forced PWM mode.

[0120] During the period from time t22 to time t23, the PCIe PHY operation 94 transitions from disabled to activated. While the load current 95 of the PCIe PHY 15 during activation is smaller than the boundary value 95 A, the DC / DC converter 64 is in the forced PWM mode, so fluctuations in the internal power supply voltage 93 supplied to the PCIe PHY 15 are small.

[0121] Time t23 is the time when the PCIe PHY operation 94 transitions from startup to initialization (eg, calibration).

[0122] During the period from time t23 to time t24, the PCIe PHY 15 starts initialization. While the load current 95 of the PCIe PHY 15 is smaller than the boundary value 95 A during initialization, the fluctuation of the internal power supply voltage 93 supplied to the PCIe PHY 15 is small while the DC / DC converter 64 is in the forced PWM mode. The small fluctuation of the internal power supply voltage 93 prevents the PCIe PHY from failing to initialize. For example, the risk of improper calibration of the PCIe PHY 15 is reduced.

[0123] At time t24, the initialization of the PCIe PHY 94 is completed and the operation mode 92 of the DC / DC converter 64 is changed to the normal operation. At this timing, the operation mode 92 of the DC / DC converter 64 is maintained in the forced PWM mode. After the operation mode 94 of the PCIe PHY 15 changes to the normal operation, the load current 95 of the PCIe PHY 15 may increase.

[0124] Thereafter, at time t25, the operation mode 92 of the DC / DC converter 64 transitions from the forced PWM mode to the auto mode based on an instruction from the control logic 61 in response to, for example, the load current 95 of the PCIe PHY 15 exceeding a boundary value 95 A. The timing of the transition to the auto mode is instructed by the control logic 61 based on the load current 95. Therefore, a configuration external to the power supply control circuit 6, such as the CPU 14 that executes the firmware 51, does not need to control the operation mode 92 of the DC / DC converter 64. Note that a configuration external to the power supply control circuit 6 may also control the operation mode 92 of the DC / DC converter 64 to transition from the forced PWM mode to the auto mode at any timing.

[0125] Although the example shown here shows the operation mode 92 of the DC / DC converter 64 transitioning to the auto mode in response to the load current 95 of the PCIe PHY 15 exceeding the boundary value 95A, the operation mode 92 of the DC / DC converter 64 may transition to the auto mode in response to the load current corresponding to any of the DC / DC converters 64 exceeding the boundary value. Alternatively, the operation mode 92 of the DC / DC converter 64 may transition to the auto mode in response to the load current corresponding to any of the DC / DC converters 64 set to the forced PWM mode exceeding the boundary value.

[0126] Thereafter, the operating mode 92 of the DC / DC converter 64 is set to either the PFM mode or the PWM mode based on automatic switching in the auto mode, thereby preventing the DC / DC converter 64 from being fixed in a state where power consumption is high (i.e., being maintained in the PWM mode).

[0127] As described above, according to this embodiment, it is possible to prevent initialization failure due to fluctuations in the supply voltage. The DC / DC converter 64 transitions to the forced PWM mode in response to the memory system 3 transitioning from the low power consumption mode to the normal operation mode.

[0128] For example, the third DC / DC converter 64-3 supplies the internal power supply voltage DC / DC3_OUT to the PCIe PHY 15. The PCIe PHY 15 performs initialization while the third DC / DC converter 64-3 is in the forced PWM mode. In the forced PWM mode, voltage fluctuations are small. Therefore, the possibility of initialization failure in the PCIe PHY 15 can be reduced compared to when initialization is performed while the third DC / DC converter 64-3 is in the PFM mode (i.e., a mode in which voltage fluctuations are large).

[0129] Each of the various functions described in this embodiment may be realized by a circuit (processing circuit). An example of a processing circuit includes a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing a computer program (a set of instructions) stored in a memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Each of the components other than the CPU described in this embodiment may also be realized by a processing circuit.

[0130] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0131] 1...information processing system, 2...host, 3...memory system, 4...DRAM, 5...NAND flash memory, 6...power supply control circuit, 7...controller, 11...host I / F, 12...NAND I / F, 13...DRAM I / F, 14...CPU, 15...PCIe PHY, 51...FW, 61...control logic, 62...load switch, 63...LDO regulator, 64...DC / DC converter, 64-1...first DC / DC converter, 64-2...second DC / DC converter, 64-3...third DC / DC converter, 64-4...fourth DC / DC converter, 65...register, 65-1...DC / DC mode setting register, 65-2...sleep mode control register, 65-3...channel specification register.

Claims

1. 1. A memory system comprising: Memory and a controller for controlling the memory; a power supply control circuit including a DC / DC converter that controls power supplied to the memory and the controller and generates an internal power supply voltage for the memory system; the DC / DC converter is capable of generating the internal power supply voltage in either a first mode that is automatically switched between a pulse width modulation mode and a pulse frequency modulation mode, or a second mode that is fixed to the pulse width modulation mode, and starts operating in the second mode after the memory system transitions from a low power consumption mode to a normal operation mode. Memory system.

2. When a load current of the controller or the memory exceeds a boundary value while the DC / DC converter is operating in the second mode, the DC / DC converter transitions from the second mode to the first mode, in which the mode is switched between the pulse width modulation mode and the pulse frequency modulation mode based on the load current.

10. The memory system of claim 1.

3. the controller includes a circuit block; When a load current of the circuit block exceeds a boundary value while the DC / DC converter is operating in the second mode, the DC / DC converter transitions from the second mode to the first mode, which is switched between the pulse width modulation mode and the pulse frequency modulation mode based on the load current.

10. The memory system of claim 1.

4. the circuit block performs an initialization operation while the DC / DC converter is operating in the second mode; 4. The memory system of claim 3.

5. the power supply control circuit includes a register that stores a first value indicating that the memory system starts operating in the second mode after transitioning from the low power consumption mode to the normal operation mode; the DC / DC converter starts operating in the second mode after the memory system has transitioned from the low power consumption mode to the normal operation mode based on the first value of the register.

10. The memory system of claim 1.

6. the power supply control circuit further includes a plurality of DC / DC converters including the DC / DC converter, and a register that stores information specifying at least one DC / DC converter among the plurality of DC / DC converters; when the information in the register specifies the DC / DC converter, the DC / DC converter starts operating in the second mode after the memory system transitions from the low power consumption mode to the normal operation mode.

10. The memory system of claim 1.

7. the power supply control circuit further includes another DC / DC converter different from the DC / DC converter; the other DC / DC converter starts operating in the second mode after the memory system has transitioned from the low power consumption mode to the normal operation mode.

10. The memory system of claim 1.

8. 1. A memory system comprising: Memory and a controller for controlling the memory; a power supply control circuit including a DC / DC converter that generates a power supply voltage to be supplied to a load included in the memory or the controller, the DC / DC converter operates in a pulse width modulation mode regardless of the amount of load current of the load while the memory system is operating in a normal operation mode; Memory system.

9. the controller includes a circuit block; When a load current of the circuit block exceeds a boundary value while the DC / DC converter is operating in the pulse width modulation mode, the DC / DC converter transitions from the pulse width modulation mode to a mode in which switching is performed between the pulse width modulation mode and a pulse frequency modulation mode based on the load current.

9. The memory system of claim 8.

10. the circuit block performs an initialization operation while the DC / DC converter is operating in the pulse width modulation mode; 10. The memory system of claim 9.

11. the power supply control circuit includes a register that stores a first value indicating that the memory system starts operating in the pulse width modulation mode after transitioning from the low power consumption mode to the normal operation mode; the DC / DC converter starts operating in the pulse width modulation mode after the memory system transitions from the low power consumption mode to the normal operation mode based on the first value of the register.

9. The memory system of claim 8.

12. the power supply control circuit further includes a plurality of DC / DC converters including the DC / DC converter, and a register that stores information specifying at least one DC / DC converter among the plurality of DC / DC converters; the DC / DC converter operates in the pulse width modulation mode while the memory system operates in the normal operating mode if the information in the register specifies the DC / DC converter.

9. The memory system of claim 8.

13. the power supply control circuit further includes another DC / DC converter different from the DC / DC converter; the other DC / DC converter operates in the pulse width modulation mode while the memory system operates in the normal operation mode.

9. The memory system of claim 8.

14. the circuit block includes a circuit for connecting to a host connected to the memory system via a serial interface; 10. The memory system according to claim 3 or claim 9.

15. The serial interface complies with the PCI Express standard.

15. The memory system of claim 14.

16. The memory includes a NAND flash memory.

9. The memory system according to claim 1 or 8.

17. 1. A method for controlling a power supply voltage supplied to a memory or a controller in a memory system including a memory and a controller that controls the memory, comprising: a power supply voltage to be supplied to the memory or the controller is generated by a DC / DC converter included in a power supply control circuit, the DC / DC converter being capable of generating the power supply voltage in either a first mode that is automatically switched between a pulse width modulation mode and a pulse frequency modulation mode, or a second mode that is fixed to the pulse width modulation mode; After the memory system has transitioned from the low power consumption mode to the normal operation mode, the DC / DC converter starts operating in the second mode. Control method.

18. If a load current of the controller or the memory exceeds a boundary value while the DC / DC converter is operating in the second mode, the DC / DC converter is transitioned from the second mode to the first mode, which is switched between the pulse width modulation mode and the pulse frequency modulation mode based on the load current.

18. The control method of claim 17.

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