Semiconductor memory device and method of manufacturing the same

Abstract

To provide a semiconductor storage device capable of improving electric characteristics, and to provide a method of manufacturing the semiconductor storage device.SOLUTION: In one embodiment, a semiconductor memory device includes a stacked body and a dividing portion. The stacked body includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The dividing portion penetrates the stacked body and extends in the first direction and a second direction crossing the first direction. When a direction crossing the first direction and the second direction is defined as a third direction, the dividing portion includes a first film and a second film. The first film extends in the first direction and the second direction and has an insulating property. The second film is located between the conductive layer and the first film in the third direction, extends in the first direction and the second direction, has a smaller thickness in the third direction than the first film, and includes a material different from the first film.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-41054 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor memory device and a method for manufacturing the semiconductor memory device that can improve electrical characteristics. [Means for solving the problem]

[0005] In one embodiment, a semiconductor memory device includes a stacked body and a dividing portion. The stacked body includes a plurality of conductive layers and a plurality of insulating layers, the plurality of conductive layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction. The dividing portion penetrates the stacked body and extends in the first direction and a second direction intersecting the first direction. When a direction intersecting the first direction and the second direction is defined as a third direction, the dividing portion includes a first film and a second film. The first film extends in the first direction and the second direction and has insulating properties. The second film is located between the conductive layer and the first film in the third direction, extends in the first direction and the second direction, has a smaller thickness in the third direction than the first film, and includes a different material from the first film. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing a part of a semiconductor memory device according to a first embodiment. [Figure 4] 4 is an enlarged cross-sectional view showing a region surrounded by line F4 of the semiconductor memory device shown in FIG. 3. [Figure 5] FIG. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device shown in FIG. 4. [Figure 6] FIG. 4 is a cross-sectional view taken along line F6-F6 of the semiconductor memory device shown in FIG. 3. [Figure 7] 7 is an enlarged cross-sectional view showing a region surrounded by line F7 of the semiconductor memory device shown in FIG. 6; [Figure 8] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 9] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 10A and 10B are cross-sectional views illustrating a first modification of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 18]10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 19] FIG. 10 is a cross-sectional view showing a third modification of the semiconductor memory device of the first embodiment. [Figure 20] 20 is a cross-sectional view for explaining a method of manufacturing the semiconductor memory device shown in FIG. 19. [Figure 21] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 22] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 23] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 24] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 25] 10 is a cross-sectional view illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. FIG. [Figure 26] 10A and 10B are cross-sectional views illustrating a third modification of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 27] FIG. 10 is a cross-sectional view showing a first modification of the semiconductor memory device of the first embodiment. [Figure 28] FIG. 10 is a plan view showing a second modified example of the semiconductor memory device of the first embodiment. [Figure 29] FIG. 10 is a cross-sectional view showing a third modification of the semiconductor memory device of the first embodiment. [Figure 30] 30 is a cross-sectional view for explaining a method of manufacturing the semiconductor memory device shown in FIG. 29. [Figure 31] FIG. 10 is a cross-sectional view showing a fourth modification of the semiconductor memory device of the first embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing a fifth modification of the semiconductor memory device of the first embodiment. [Figure 33] FIG. 10 is a cross-sectional view showing a sixth modification of the semiconductor memory device of the first embodiment. [Figure 34] FIG. 13 is a cross-sectional view showing a seventh modification of the semiconductor memory device of the first embodiment. [Figure 35]FIG. 13 is a cross-sectional view for explaining an advantage of the seventh modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A semiconductor memory device and a method for manufacturing the semiconductor memory device according to the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions will be assigned the same reference numerals. Further, duplicate descriptions of those components may be omitted. In the following description, reference numerals ending with a distinguishing number or letter may have the number or letter omitted if they do not need to be distinguished from each other.

[0008] In this application, terms are defined as follows: "Parallel," "orthogonal," or "same" may include the cases of "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. That is, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected via another element interposed therebetween. "Overlapping" is not limited to the case where multiple elements are in contact with each other, but may also include the case where multiple elements are separated (the case where the projected images of multiple elements overlap when viewed from a certain direction).

[0009] The +X direction, −X direction, +Y direction, −Y direction, +Z direction, and −Z direction are defined as follows: The +X direction is the direction in which the word lines WL, which will be described later, extend (see FIG. 3). The −X direction is the opposite direction of the +X direction. When the +X direction and the −X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction that intersects (e.g., is perpendicular to) the X direction. The +Y direction is a direction in which the bit lines BL extend (see FIG. 6). The −Y direction is the opposite direction of the +Y direction. When the +Y direction and the −Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (e.g., is perpendicular to) the X direction and the Y direction. The +Z direction is the direction from the bit lines BL, which will be described later, toward the stack 40 (see FIG. 3). The −Z direction is the opposite direction of the +Z direction. When the +Z direction and the −Z direction are not distinguished, they are simply referred to as the Z direction.

[0010] In this application, the +Z direction side may be referred to as "upper" and the -Z direction side as "lower." Also, in this application, the position in the Z direction may be referred to as "height." However, these expressions are used for convenience of explanation and do not define the direction of gravity. The Z direction is an example of a "first direction." The X direction is an example of a "second direction." The Y direction is an example of a "third direction." Also, in the drawings described below, illustrations of configurations that are not relevant to the explanation may be omitted.

[0011] (First embodiment) <1. Configuration of Semiconductor Memory Device> FIG. 1 is a block diagram showing a portion of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 1). A block BLK is a collection of memory cell transistors. A block BLK is used as a unit for erasing data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0013] The command register 12 holds the command CMD that the semiconductor memory device 1 receives from the host device. The address register 13 holds address information ADD that the semiconductor memory device 1 receives from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0014] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line and transfers the determination result to the host device as read data DAT.

[0015] 2. Electrical Configuration of Memory Cell Array Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. Fig. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, five strings STR0 to STR4).

[0016] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0017] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to one of word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, thereby retaining data in a non-volatile manner.

[0018] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. The drain-side select transistor STD connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain-side select gate line SGD.

[0019] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to a source line SL. The control gate of the source-side select transistor STS is connected to a source-side select gate line SGS. The source-side select transistor STS connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side select gate line SGS.

[0020] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn. In the same string STR, the control gates of the drain-side select transistors STD are commonly connected to the corresponding drain-side select gate line SGD. The control gates of the source-side select transistors STS are commonly connected to the source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS to which the same column address is assigned in multiple strings STR.

[0021] <3. Structure of semiconductor memory device> Next, the structure of the semiconductor memory device 1 will be described. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0022] <3.1 First Chip> The first chip 2 is a circuit chip including a peripheral circuit, and includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0023] The semiconductor substrate 21 is, for example, a substrate that serves as the base of the first chip 2. At least a portion of the semiconductor substrate 21 is plate-shaped and extends along the X and Y directions. The semiconductor substrate 21 is made of, for example, a semiconductor material such as silicon.

[0024] The peripheral circuit 22 is a circuit for causing the memory cell array 11 to function. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. An insulating section 23 covers the peripheral circuit 22. A plurality of pads 24 are provided on the surface of the insulating section 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0025] <3.2 Second Chip> The second chip 3 is an array chip including a memory cell array 11. The second chip 3 has, for example, the memory cell array 11, an insulating section 31, and a plurality of pads 32. Here, the insulating section 31 and the plurality of pads 32 will be described, and the memory cell array 11 will be described later.

[0026] The insulating section 31 covers the memory cell array 11 from the -Z direction side. A plurality of pads 32 are provided on the surface of the insulating section 31. Each pad 32 is electrically connected to a wiring (e.g., wiring 71 or wiring 72) included in a wiring section 70 of the memory cell array 11, which will be described later. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3 face to face with each other.

[0027] 4. Physical Configuration of Memory Cell Array Next, the physical configuration of the memory cell array 11 will be described. As shown in FIG. 3, the memory cell array 11 includes, for example, a stack 40, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars MH, a plurality of contacts VY for the memory pillars MH, a contact CC for the conductive layer, a wiring portion 70, and a plurality of separation portions DV (see FIG. 6).

[0028] 4.1 Laminate First, the laminate 40 will be described. 4 is an enlarged cross-sectional view of the region surrounded by line F4 of the memory cell array 11 shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line F6-F6 of the semiconductor memory device 1 shown in FIG. 3. FIG. 7 is an enlarged cross-sectional view of the region surrounded by line F7 of the semiconductor memory device shown in FIG. 6. The stacked body 40 includes, for example, a plurality of conductive layers 41 and a plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction.

[0029] 4.2 Conductive layer 3, 4, 6, and 7, each conductive layer 41 is provided along the X direction and the Y direction. As shown in Fig. 7, each conductive layer 41 includes a conductive portion 45, a barrier metal film 46, and an insulating film 47.

[0030] The conductive portions 45 are provided along the X and Y directions. The conductive portions 45 include a conductive material. For example, the conductive portions 45 are made of tungsten, molybdenum, or silicon doped with impurities.

[0031] The barrier metal film 46 is provided along the Z-direction surface and X-direction surface of the conductive portion 45 and the Y-direction surface on the memory pillar MH side. The insulating film 47 is provided along the Z-direction surface and X-direction surface of the barrier metal film 46 and the Y-direction surface on the memory pillar MH side. As a result, the barrier metal film 46 is located between the conductive portion 45 and the insulating film 47. Furthermore, the insulating film 47 is provided along the Y-direction surface on the separating portion ST side of the insulating layer 42. That is, the insulating film 47 penetrates the stacked body 40 and extends in the Z and X directions (see FIG. 7).

[0032] The barrier metal film 46 is a film for suppressing diffusion of the conductive material contained in the conductive portion 45. The barrier metal film 46 includes, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The insulating film 47 improves the voltage resistance of the conductive layer 41. The insulating film 47 is formed of, for example, a film containing aluminum and oxygen (for example, an aluminum oxide film).

[0033] 3, 4, and 6, one or more (for example, a plurality of) lower conductive layers 41 among the plurality of conductive layers 41 function as drain-side select gate lines SGD. The drain-side select gate lines SGD are provided in common to a plurality of memory pillars MH aligned in the X direction or Y direction. The intersections of the drain-side select gate lines SGD and channel layers 52 (described later) of each memory pillar MH function as the above-mentioned drain-side select transistors STD.

[0034] Of the multiple conductive layers 41, one or more (for example, multiple) conductive layers 41 located at the top function as a source-side select gate line SGS. The source-side select gate line SGS is provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersection of the source-side select gate line SGS and the channel layer 52 of each memory pillar MH functions as the source-side select transistor STS described above.

[0035] Of the multiple conductive layers 41, at least some of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain-side select gate lines SGD and the source-side select gate lines SGS function as word lines WL. The word lines WL are provided in common to the multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersections of the word lines WL and the channel layers 52 of each memory pillar MH function as memory cell transistors MT.

[0036] 4.2 Insulating layer The insulating layer 42 is an interlayer insulating film provided between two conductive layers 41 adjacent to each other in the Z direction, and insulates the two conductive layers 41. The insulating layer 42 extends in the X direction and the Y direction. The insulating layer 42 is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film).

[0037] <4.4 Source line> The source line SL is disposed above the stacked body 40. The source line SL is formed of, for example, a conductive layer or a semiconductor layer extending in the X and Y directions. The source line SL is formed of a conductive material such as tungsten or molybdenum, or a semiconductor material containing silicon.

[0038] <4.5 Memory Pillar> The memory pillars MH are aligned in the X and Y directions (see FIG. 3). Each memory pillar MH extends in the Z direction within the stack 40 and penetrates the stack 40. The upper end of each memory pillar MH contacts a source line SL. Meanwhile, the lower end of each memory pillar MH contacts a contact CH, which will be described later. The memory pillar MH is an example of a "columnar body."

[0039] Fig. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device 1 shown in Fig. 4. The memory pillar MH includes, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap portion 54 (see Fig. 4).

[0040] The memory film 51 is provided on the outer periphery of the channel layer 52. The memory film 51 is located between the plurality of conductive layers 41 and the channel layer 52. The memory film 51 includes, for example, a block insulating film 61, a charge trapping film 62, and a tunnel insulating film 63.

[0041] The block insulating film 61 is provided between the plurality of conductive layers 41 and the charge trap film 62. The block insulating film 61 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 62. The block insulating film 61 is formed in a ring shape and extends in the Z direction. For example, the block insulating film 61 extends over the entire length of the memory pillar MH in the Z direction. The block insulating film 61 is a laminated structure film in which a plurality of insulating films, such as a film containing silicon and oxygen or a film containing metal and oxygen, are stacked. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 61 may include a high-dielectric-constant material (high-k material) such as silicon nitride or hafnium oxide.

[0042] The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in a ring shape and extends in the Z direction. For example, the charge trap film 62 extends over the entire length of the memory pillar MH in the Z direction. The charge trap film 62 is a functional film that has a large number of crystal defects (trap levels) and can trap charges in the crystal defects. The charge trap film 62 is formed of, for example, a film containing silicon and nitrogen. The portions of the charge trap film 62 adjacent to each word line WL are an example of a "charge storage section" that can store information by accumulating charges.

[0043] The tunnel insulating film 63 is provided between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is, for example, annular along the outer peripheral surface of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 63 extends, for example, over the entire length of the memory pillar MH in the Z direction. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0044] The channel layer 52 is provided inside the memory film 51. The channel layer 52 is formed in a ring shape. The channel layer 52 extends in the Z direction. For example, the channel layer 52 covers the entire length of the memory pillar MH in the Z direction. The channel layer 52 is formed of a semiconductor material such as polysilicon. The channel layer 52 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 forms a channel to electrically connect the bit line BL and the source line SL.

[0045] As a result, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Note that the memory film 51 may have a floating gate type charge storage portion (floating gate electrode) as the charge storage portion instead of the charge trap film 62. The floating gate electrode is formed of, for example, polysilicon containing impurities.

[0046] The insulating core 53 is provided inside the channel layer 52. The insulating core 53 fills at least a portion of the inside of the channel layer 52. The insulating core 53 is formed of a film containing silicon and oxygen. A portion of the insulating core 53 is formed in an annular shape along the inner circumferential surface of the channel layer 52 and may have a hollow portion (air gap) inside. The insulating core 53 extends in the Z direction. For example, the insulating core 53 spans most of the memory pillar MH in the Z direction except for the upper end portion of the memory pillar MH (see FIG. 4).

[0047] Returning to FIG. 4 , the cap portion 54 will now be described. The cap portion 54 is provided below the insulating core 53. The cap portion 54 is a semiconductor portion made of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 54 may be doped with impurities. The cap portion 54 is disposed on the inner periphery of the lower end of the memory film 51 and is formed integrally with the channel layer 52. The cap portion 54, together with the lower end of the channel layer 52, forms the lower end of the memory pillar MH. The contact CH contacts the cap portion 54 from the -Z direction.

[0048] 4.6 Bit Lines Next, returning to FIG. 3, the bit lines BL will be described. The bit line BL is a wiring for selecting one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below (on the -Z direction side of) the stacked body 40. The multiple bit lines BL are spaced apart in the X direction and lined up in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass below the corresponding multiple memory pillars MH.

[0049] Each bit line BL is connected to the channel layer 52 of the memory pillar MH via a contact VY and a contact CH. This allows any memory cell transistor MT to be selected from multiple memory cell transistors MT arranged three-dimensionally by combining word lines WL and bit lines BL.

[0050] <4.7 Memory pillar contact channel> The contacts CH are arranged between the memory pillars MH and the bit lines BL. Each contact CH is an electrical connection portion that electrically connects the contact VY and the memory pillar MH. The contact CH has, for example, a cylindrical or truncated cone shape. When viewed from the Z direction, the outer shape of the contact CH is, for example, the same as or slightly smaller than the outer shape of the memory pillar MH.

[0051] The contacts CH are disposed below the corresponding memory pillars MH and are in contact with the lower ends of the memory pillars MH. The contacts CH are in contact with, for example, the cap portions 54 of the memory pillars MH (see FIG. 4). The contacts CH are formed of, for example, a metal material such as tungsten or molybdenum.

[0052] <4.8 VY contact for memory pillar> The contacts VY are arranged between the contacts CH and the bit lines BL. Each contact VY is an electrical connection portion that electrically connects the bit line BL to the contact CH. The width of the contact VY in the X direction is smaller than the width of the contact CH in the X direction.

[0053] The contact VY is disposed above the corresponding bit line BL and is in contact with the lower end of the contact CH and the bit line BL. The contact VY is disposed at a position offset from the center of the contact CH and the center of the memory pillar MH in the X direction. The contact VY is formed of a metal material such as tungsten or molybdenum. The material forming the contact VY is, for example, the same as the material forming the contact CH.

[0054] 4.9 Contacts for Conductive Layers 3, the contacts CC are electrical connection parts that electrically connect the conductive layer 41 and the wiring 72 (described later) included in the wiring section 70. The contacts CC are arranged, for example, in a staircase region in the laminate 40 where the ends of the conductive layers 41 are arranged in a staircase pattern. The contacts CC extend in the Z direction and, for example, have different lengths in the Z direction. The upper end of each contact CC is in contact with the corresponding conductive layer 41. The upper end of each contact CC is electrically connected to the corresponding conductive layer 41.

[0055] <4.10 Wiring section> Next, a description will be given of the wiring section 70. The wiring section 70 is disposed, for example, between the stacked body 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, and a plurality of wirings 72.

[0056] The wiring 71 is an electrical connection portion that electrically connects the bit line BL and the pad 32. The multiple wirings 71 are arranged, for example, below the multiple bit lines BL. Each wiring 71 extends, for example, in the X direction or the Y direction. A via V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0057] The wiring 72 is an electrical connection portion that electrically connects the conductive layer contact CC and the pad 32. The wiring 72 is electrically connected to the conductive layer 41 via the conductive layer contact CC. A voltage is applied to the wiring 72 to select the conductive layer 41 (word line WL, drain side select gate line SGD, or source side select gate line SGS).

[0058] <5. Separation of laminate> Next, the dividing portion DV will be described. 6 is a cross-sectional view of the semiconductor memory device 1 shown in FIG. 3 taken along line F6-F6. In this embodiment, a plurality of dividing portions DV are provided in the stacked body 40. The plurality of dividing portions DV are arranged separately in the Y direction. Each of the plurality of dividing portions DV extends in the Z direction within the stacked body 40, and divides one or more conductive layers 41, including the lowest layer among the plurality of conductive layers 41, in the Y direction. The plurality of dividing portions DV include, for example, a plurality of dividing portions ST and a plurality of dividing portions SHE.

[0059] <5.1 Separation ST> Next, the dividing portion ST will be described. 7 is an enlarged cross-sectional view of the region surrounded by line F7 of the semiconductor memory device shown in FIG. 6. In this embodiment, the dividing portion ST is a wall portion that divides the stacked body 40 in the Y direction. The dividing portions ST are arranged separately in the Y direction. The dividing portions ST extend in the Z direction, penetrate the stacked body 40, and extend in the X direction. In other words, the dividing portions ST are walls that extend along the Z direction and the X direction. The dividing portions ST divide each of all of the conductive layers 41 included in the stacked body 40 in the Y direction.

[0060] As shown in FIG. 7, the dividing portion ST includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc (not shown in FIG. 6). The buried insulating film STb is an example of a "first film." The diffusion barrier layer STa is an example of a "second film." The sidewall insulating film STc is an example of a "third film."

[0061] 7, the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc that form the dividing portion ST are embedded in a region between the insulating layers 42 and in which the conductive layer 41 is not present. As a result, at the position of the dividing portion ST that contacts the conductive layer 41, the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc protrude toward the conductive layer 41.

[0062] The buried insulating film STb extends in the Z direction and the X direction. The buried insulating film STb has insulating properties and penetrates the stacked body 40. The buried insulating film STb is formed of, for example, a film containing silicon and oxygen. In this embodiment, as shown in FIG. 7, a diffusion barrier layer STa and a sidewall insulating film STc are arranged between the buried insulating film STb and the source line SL, and the diffusion barrier layer STa and the sidewall insulating film STc are provided continuously so as to surround the buried insulating film STb.

[0063] 7, the diffusion barrier layer STa is located between the conductive layer 41 and the buried insulating film STb in the Y direction. The diffusion barrier layer STa is also located between the source line SL and the buried insulating film STb in the Z direction. The diffusion barrier layer STa located between the conductive layer 41 and the buried insulating film STb extends in the Z direction and the X direction, and penetrates the stacked body 40. The thickness ta of the diffusion barrier layer STa in the Y direction is smaller than the thickness tb of the buried insulating film STb in the Y direction.

[0064] In this specification, the Y-direction thickness tb of the embedded insulating film STb is defined as the average thickness of the Y-direction thickness tb1 (the distance between both ends in the Y direction) on one side in the Z direction of the stacked body 40 (the lower side in Figure 7) and the Y-direction thickness tb2 (the distance between both ends in the Y direction) on the opposite side in the Z direction to the one side of the stacked body 40 (the upper side in Figure 7). When a cavity is formed in the buried insulating film STb, the thickness tb of the buried insulating film STb in the Y direction also includes the cavity in the buried insulating film STb.

[0065] In addition, in this specification, the Y-direction thickness ta of the diffusion barrier layer STa is defined as the average thickness of the Y-direction thickness ta1 on one side in the Z direction of the laminate 40 (the lower side in Figure 7) and the Y-direction thickness ta2 on the opposite side in the Z direction of the laminate 40 (the upper side in Figure 7). The thickness tc of the sidewall insulating film STc in the Y direction is defined as the average thickness of the thickness tc1 in the Y direction on one side of the stacked body 40 in the X direction (the lower side in FIG. 7) and the thickness tc2 in the Y direction on the opposite side of the stacked body 40 in the X direction (the upper side in FIG. 7).

[0066] The diffusion barrier layer STa is a film for suppressing diffusion of impurities such as hydrogen contained in the buried insulating film STb, improving the reliability of the memory cell array 11, and improving the electrical characteristics of the semiconductor memory device 1. The material of the diffusion barrier layer STa may be a material different from that of the buried insulating film STb, as long as it can suppress the diffusion of the impurities contained in the buried insulating film STb. Therefore, the diffusion barrier layer STa may be conductive or insulating.

[0067] The material of the diffusion barrier layer STa may contain silicon and nitrogen, or may contain aluminum, hafnium, zirconium, or titanium. The diffusion barrier layer STa includes, for example, a material containing nitrogen and one or more elements selected from aluminum, hafnium, zirconium, and titanium, or a material containing oxygen and one or more elements selected from aluminum, hafnium, zirconium, and titanium.

[0068] The sidewall insulating film STc extends in the Z direction and the X direction, penetrating the stacked body 40. The sidewall insulating film STc is located between the conductive layer 41 and the diffusion barrier layer STa in the Y direction. The sidewall insulating film STc is located between the source line SL and the diffusion barrier layer STa in the Z direction. The sidewall insulating film STc has insulating properties and contains a material different from that of the diffusion barrier layer STa.

[0069] The sidewall insulating film STc is provided as necessary. The sidewall insulating film STc may not be provided when the diffusion barrier layer STa is insulating and also functions as the sidewall insulating film STc. The sidewall insulating film STc is preferably provided when the diffusion barrier layer STa is conductive. The sidewall insulating film STc is formed of, for example, a film containing silicon and oxygen. Furthermore, the thickness tc of the sidewall insulating film STc in the Y direction is smaller than the thickness tb of the buried insulating film STb in the Y direction.

[0070] The thickness of the sidewall insulating film STc in the Y direction is preferably 5 nm to 10 nm. When the thickness of the sidewall insulating film STc in the Y direction is 5 nm or more, better insulating properties can be obtained. Furthermore, when the thickness of the sidewall insulating film STc in the Y direction is 10 nm or less, diffusion of hydrogen from the sidewall insulating film STc to the conductive layer 41 can be suppressed, and the reliability of the memory cell array 11 is further improved.

[0071] Between the buried insulating film STb forming the separating portion ST and the source line SL, only the diffusion barrier layer STa or the sidewall insulating film STc may be disposed, or the buried insulating film STb may be in contact with the source line SL in the Z direction. Therefore, the diffusion barrier layer STa may be a pair separated in the Y direction by the buried insulating film STb. Also, the sidewall insulating film STc may be a pair separated in the Y direction by the buried insulating film STb.

[0072] <5.2 Divided part SHE> The dividing portion SHE is a dividing portion that is shallower in the Z direction than the dividing portion ST, and is a wall portion that divides the lower end portion of the stack 40 in the Y direction. The dividing portions SHE are arranged separately in the Y direction. In this embodiment, a plurality of (for example, three) dividing portions SHE are present between two dividing portions ST adjacent to each other in the Y direction. The dividing portion SHE is provided at the lower end portion of the stack 40, and extends in the Z direction partway through the stack 40, and also extends in the X direction. In other words, the dividing portion SHE is a wall portion that extends along the Z direction and the X direction.

[0073] The dividing portion SHE penetrates some of the conductive layers 41, including the lowest layer, of the plurality of conductive layers 41, and divides the some of the conductive layers 41 in the Y direction. For example, the dividing portion SHE penetrates each of all of the conductive layers 41 that function as drain-side select gate lines SGD. On the other hand, the dividing portion SHE does not reach the conductive layers 41 that function as word lines WL. The dividing portion SHE divides only the conductive layers 41 that function as drain-side select gate lines SGD in the Y direction. The dividing portion SHE is formed, for example, from a film containing silicon and oxygen.

[0074] 6. Manufacturing Method of Semiconductor Memory Device Next, a method for manufacturing the semiconductor memory device 1 will be described. The steps related to the formation of the dividing portion ST will be described in detail below. Details of other manufacturing steps are described in, for example, Japanese Patent Application Laid-Open No. 2022-41054, the entirety of which is incorporated herein by reference.

[0075] 8 to 26 are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 1 of the first embodiment. For ease of explanation, the configurations illustrated in Fig. 8 to 26 show the cross section of the region surrounded by line F7 of the semiconductor memory device shown in Fig. 6.

[0076] First, the source line SL is formed on a semiconductor substrate (not shown in FIG. 8) using, for example, a semiconductor material containing silicon. Next, an insulating layer 42 is stacked on the source line SL, and then insulating layers 202 and 42 are stacked alternately one by one on top of that, and finally, insulating layer 42 is stacked. This forms a stacked body 40A. The insulating layer 202 is a sacrificial layer that is replaced with the conductive layer 41, for example, by performing a replacement process described below. The insulating layer 202 is formed, for example, from a film containing nitrogen and silicon (for example, a silicon nitride film). The insulating layer 202 is an example of a "first layer." The insulating layer 42 is an example of a "second layer."

[0077] Next, columnar structures MHA that will become memory pillars MH are formed in the stacked body 40A. First, a plurality of holes for forming the memory pillars MH are formed. Each hole for forming the memory pillars MH penetrates the stacked body 40A in the Z direction. Next, a tunnel insulating film 63, for example, is formed along the inner wall of each hole. Next, a charge trap film 62, for example, is formed along the inner wall of each hole in which the tunnel insulating film 63 is formed. After that, a block insulating film 61, for example, is formed along the inner wall of each hole in which the charge trap film 62 is formed. As a result, a memory film 51 including the block insulating film 61, the charge trap film 62, and the tunnel insulating film 63 is formed along the inner wall of each hole.

[0078] Next, the memory film 51 is removed by etching from the bottom surface of each hole in which the memory film 51 is formed. Then, by performing etching using each hole in which the memory film 51 is formed on the inner wall, the source line SL is exposed at the bottom surface of each hole. Next, for example, a channel layer 52 is formed along the inner wall of each hole in which the memory film 51 is formed. After that, for example, a material that will become the insulating core 53 is supplied into each hole in which the channel layer 52 is formed. As a result, the insulating core 53 is formed in each hole in which the channel layer 52 is formed, and a columnar structure MHA that will become the memory pillar MH is formed.

[0079] Next, the insulating core 53 disposed at the upper end of the pillar structure MHA is removed by etching. After that, the upper end of the pillar structure MHA is filled with, for example, amorphous silicon and doped with impurities to form a cap portion 54. Next, an insulating layer 42 is formed on the surface of the stack 40A on which the columnar structures MHA that will become memory pillars MH are formed, opposite to the source lines SL.

[0080] Next, dividing portions ST are formed in the stacked body 40A. First, as shown in Fig. 8, etching is performed from the surface of the stacked body 40A opposite to the source lines SL, thereby forming trenches 81 that penetrate the stacked body 40A in the Z direction to reach the source lines SL and extend in the X direction. Next, the source lines SL exposed in the trenches 81 are oxidized to form bottom oxide films 82.

[0081] Next, a replacement step (replacement step) is performed to replace the insulating layer 202 of the laminated body 40A with the conductive layer 41. First, the insulating layer 202 is removed by etching through the inside of the trench 81 in which the bottom oxide film 82 is formed. As a result, a space 83 communicating with the trench 81 is formed in the region inside the laminated body 40A where the insulating layer 202 was previously present.

[0082] Next, an insulating material for forming an insulating film 47 is supplied to the groove 81 from which the insulating layer 202 has been removed by etching, and the insulating film 47 is formed along the inner surface of the groove 81 from which the insulating layer 202 has been removed by etching and the inner surface of the space 83 connected to the groove 81. Next, a metal material for forming a barrier metal film 46 is supplied to the trench 81 in which the insulating film 47 is formed, and the barrier metal film 46 is formed along the inner surface of the trench 81 in which the insulating film 47 is formed and the inner surface of the space 83 connected to the trench 81.

[0083] Thereafter, a conductive material for forming the conductive portion 45 is supplied to the trench 81 in which the barrier metal film 46 has been formed. As a result, the conductive portion 45 is formed along the inner surface of the trench 81 in which the barrier metal film 46 has been formed, as shown in FIG. 9. At the same time, the space 83 communicating with the trench 81 in which the barrier metal film 46 has been formed is filled with the conductive portion 45, and the insulating layer 202 is replaced with the conductive layer 41 including the conductive portion 45, the barrier metal film 46, and the insulating film 47.

[0084] 10, the conductive portion 45 and the barrier metal film 46 formed along the inner surface of the groove 81 are removed by etching through the groove 81 formed in the conductive layer 41. At the same time, of the conductive portion 45 and the barrier metal film 46 formed in the space 83 communicating with the groove 81, a portion formed in a region close to the groove 81 is removed. As a result, a stacked body 40 is formed in which a plurality of conductive layers 41 and a plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction.

[0085] Next, as shown in FIG. 11, the stack 40 is etched to remove the insulating film 47 exposed at the bottom of the trench 81 from which the conductive portion 45 and the barrier metal film 46 have been removed, together with the bottom oxide film 82, thereby exposing the source line SL. In this embodiment, the case where the source line SL is exposed at the bottom of the trench 81 will be described as an example, but the insulating film 47 and the bottom oxide film 82 do not have to be removed, or only the insulating film 47 may be removed.

[0086] 12, an insulating material for forming a sidewall insulating film STc is supplied to the groove 81 in which the source line SL is exposed at the bottom by etching and the end of the conductive portion 45 on the groove 81 side is exposed in the space 83 communicating with the groove 81. At the same time, an insulating material for forming a sidewall insulating film STc is supplied to the surface of the stacked body 40 opposite to the source line SL (the first side in the Z direction relative to the stacked body 40).

[0087] This forms a sidewall insulating film STc (first portion) extending in the Z direction and X direction along the inner surface of the trench 81, the bottom surface of which exposes the source line SL by etching, and along the inner surface of the space 83 communicating with the trench 81. At the same time, a sidewall insulating film STc (second portion) is formed extending in the Y direction from the opening of the trench 81 (the end of the first portion on the first side in the Z direction) along the surface of the stacked body 40 opposite the source line SL. The sidewall insulating film STc is an example of a "third film." The sidewall insulating film STc can be formed by, for example, a CVD (Chemical Vapor Deposition) method.

[0088] 13, a material for forming a diffusion barrier layer STa is supplied to the trench 81 in which the sidewall insulating film STc is formed and to the surface of the stacked body 40 on which the sidewall insulating film STc is formed. This forms a diffusion barrier layer STa (first portion) along the inner surface of the trench 81 in which the sidewall insulating film STc is formed and the inner surface of the space 83 communicating with the trench 81 on which the sidewall insulating film STc is formed. At the same time, a diffusion barrier layer STa (second portion) is formed extending in the Y direction from the opening of the trench 81 (the end of the first portion on the first side in the Z direction) along the surface of the stacked body 40 opposite to the source line SL. The diffusion barrier layer STa is located inside the trench 81 on the opposite side of the sidewall insulating film STc from the conductive layer 41. The diffusion barrier layer STa is an example of a "second film." The diffusion barrier layer STa can be formed by, for example, a CVD (Chemical Vapor Deposition) method.

[0089] 14, an insulating material for forming a buried insulating film STb is supplied to the trench 81 in which the diffusion barrier layer STa is formed and to the surface of the stacked body 40 on which the sidewall insulating film STc and the diffusion barrier layer STa are formed. As a result, the trench 81 in which the diffusion barrier layer STa is formed and the space 83 communicating with the trench 81 are filled with the buried insulating film STb. At the same time, the buried insulating film STb is formed on the surface of the stacked body 40 on which the diffusion barrier layer STa is formed. The buried insulating film STb is located inside the trench 81 on the opposite side of the diffusion barrier layer STa from the conductive layer 41. The buried insulating film STb is an example of a "first film." The buried insulating film STb can be formed by, for example, a CVD (Chemical Vapor Deposition) method, a method of applying a liquid material such as polysilazane (PSZ) and then baking (annealing), or the like.

[0090] 15, the surface of the stacked body 40 on which the sidewall insulating film STc, the diffusion barrier layer STa, and the buried insulating film STb are formed is etched to expose the insulating layer 42 that forms the surface of the stacked body 40. This forms a dividing portion ST including the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc.

[0091] Next, grooves for providing the dividing portions SHE are formed in the laminate 40, and the dividing portions SHE are formed inside the grooves. Next, an insulating layer is stacked on the stacked body 40 with the dividing portion SHE formed therein, and a contact CH is formed. Next, a contact VY is formed on the stacked body 40 with the contact CH formed therein. Thereafter, a bit line BL is formed above the contact VY. Next, a wiring portion 70 is formed. The above steps complete the second chip 3. The second chip 3 is attached to the first chip 2 with the wiring section 70 facing the first chip 2. In this way, the semiconductor memory device 1 of the first embodiment is formed.

[0092] <6.1 First modified example of the method for manufacturing a semiconductor memory device> Next, a first modified example of the method for manufacturing the semiconductor memory device 1 of the first embodiment will be described. Note that the configuration other than the steps described below is the same as the configuration of the method for manufacturing the semiconductor memory device 1 of the first embodiment described above.

[0093] FIG. 16 is a cross-sectional view for explaining a first modification of the method for manufacturing the semiconductor memory device of the first embodiment. In the first modified example of the manufacturing method of the semiconductor memory device 1 of the first embodiment, the steps up to forming a diffusion barrier layer STa along the inner surface of the trench 81 in which the sidewall insulating film STc is formed and the surface of the stacked body 40 on which the sidewall insulating film STc is formed (the surface of the stacked body 40 opposite the source line SL) (see Figure 13) are performed in the same manner as the manufacturing method of the semiconductor memory device 1 of the first embodiment.

[0094] Thereafter, in the first modified example, the step of forming the buried insulating film STb is performed multiple times (for example, twice). When the step of forming the buried insulating film STb is performed multiple times, the method of forming the buried insulating film STb may be the same each time, or a different method may be used each time, or the same method may be used two or more times and different methods may be used. When the two steps of forming the buried insulating film STb are performed using different methods, for example, the buried insulating film STb may be formed using a film formation method in the first step, and the buried insulating film STb may be formed using a method of applying a liquid material in the second step.

[0095] 16(a), in the first modification, an insulating material for forming a buried insulating film STb is supplied to the trench 81 in which the diffusion barrier layer STa is formed and to the surface on which the sidewall insulating film STc and the diffusion barrier layer STa of the stacked body 40 are formed. At this time, as shown in FIG. 16(a), the entire inside of the trench 81 is not filled with the buried insulating film STb. That is, the buried insulating film STb is formed along the inner surface of the trench 81 in which the buried insulating film STb is formed and the surface on which the diffusion barrier layer STa of the stacked body 40 is formed.

[0096] 16(b), an insulating material for forming the buried insulating film STb is supplied to the trench 81 in which the buried insulating film STb is formed and to the surface of the stacked body 40 on which the buried insulating film STb is formed. As a result, the trench 81 in which the diffusion barrier layer STa is formed is filled with the buried insulating film STb. At the same time, the buried insulating film STb is formed on the surface of the stacked body 40 on which the diffusion barrier layer STa is formed.

[0097] In this embodiment, an example will be described in which the process of forming the buried insulating film STb is performed multiple times (for example, twice) using the same material, but the process of forming the buried insulating film STb may be performed using a different material each time, or may be performed using the same material only some of the times.

[0098] Thereafter, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the surface of the stacked body 40 on which the sidewall insulating film STc, the diffusion barrier layer STa, and the buried insulating film STb are formed is etched to expose the surface of the stacked body 40. As a result, a dividing portion ST including the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc is formed.

[0099] <6.2 Second Modification of the Manufacturing Method of Semiconductor Memory Device> Next, a second modified example of the method for manufacturing the semiconductor memory device 1 of the first embodiment will be described. Note that the configuration other than the steps described below is the same as the configuration of the method for manufacturing the semiconductor memory device 1 of the first embodiment described above.

[0100] 17 to 25 are cross-sectional views illustrating a second modified example of the method for manufacturing the semiconductor memory device 1 of the first embodiment. For convenience of explanation, the configuration illustrated in Fig. 17 to 25 shows a cross section of the region surrounded by line F7 of the semiconductor memory device shown in Fig. 6.

[0101] First, a sacrificial layer 90 is formed on a substrate (not shown in FIG. 17) using, for example, polysilicon. Next, an insulating layer 42 is stacked on the sacrificial layer 90, and then insulating layers 202 and 42 are stacked alternately one by one on top of that, and finally insulating layer 42 is stacked. This forms a stacked body 40A.

[0102] Next, columnar structures MHA that will become memory pillars MH are formed in the stacked body 40A. First, a plurality of holes for forming the memory pillars MH are formed. Each hole for forming the memory pillars MH penetrates the stacked body 40A in the Z direction. Next, a tunnel insulating film 63, for example, is formed along the inner wall of each hole. Next, a charge trap film 62, for example, is formed along the inner wall of each hole in which the tunnel insulating film 63 is formed. After that, a block insulating film 61, for example, is formed along the inner wall of each hole in which the charge trap film 62 is formed. As a result, a memory film 51 including the block insulating film 61, the charge trap film 62, and the tunnel insulating film 63 is formed along the inner wall of each hole.

[0103] Next, for example, a channel layer 52 is formed along the inner wall of each hole in which the memory film 51 is formed. After that, for example, a material that will become the insulating core 53 is supplied into each hole in which the channel layer 52 is formed. As a result, the insulating core 53 is formed in each hole in which the channel layer 52 is formed, and a columnar structure MHA that will become the memory pillar MH is formed.

[0104] Next, the insulating core 53 disposed at the upper end of the pillar structure MHA is removed by etching. After that, the upper end of the pillar structure MHA is filled with, for example, amorphous silicon and doped with impurities to form a cap portion 54. Next, an insulating layer 42 is formed on the surface of the laminate 40A on the side opposite to the sacrificial layer 90, on which the columnar structures MHA that will become memory pillars MH have been formed.

[0105] Next, dividing portions ST are formed in the stacked body 40A. First, as shown in Fig. 17, etching is performed from the surface of the stacked body 40A opposite the sacrificial layer 90, thereby forming trenches 81 that penetrate the stacked body 40A in the Z direction to reach the sacrificial layer 90 and extend in the X direction. Next, the sacrificial layer 90 exposed in the trenches 81 is oxidized to form a bottom oxide film 82.

[0106] Next, a replacement step (replacement step) is performed to replace the insulating layer 202 of the stacked body 40A with a conductive layer 41. First, similarly to the manufacturing method of the semiconductor memory device 1 of the first embodiment, the insulating layer 202 is removed by etching to form a space 83 communicating with the trench 81, and an insulating film 47 is formed along the inner surface of the trench 81 and the inner surface of the space 83 communicating with the trench 81. Next, similarly to the manufacturing method of the semiconductor memory device 1 of the first embodiment, a barrier metal film 46 is formed along the inner surface of the trench 81 with the insulating film 47 formed therein and the inner surface of the space 83 communicating with the trench 81, and a conductive portion 45 is formed along the inner surface of the trench 81 with the barrier metal film 46 formed therein. As a result, as shown in FIG. 18 , the space 83 communicating with the trench 81 with the barrier metal film 46 formed therein is filled with the conductive portion 45. At the same time, the insulating layer 202 is replaced with the conductive layer 41 including the conductive portion 45, the barrier metal film 46, and the insulating film 47.

[0107] Next, in a manner similar to the manufacturing method of the semiconductor memory device 1 of the first embodiment, as shown in FIG. 19, the conductive portion 45 and the barrier metal film 46 formed along the inner surface of the groove 81 are removed by etching through the groove 81 in which the conductive layer 41 is formed. Next, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the stack 40 is etched as shown in FIG. 20 to remove the insulating film 47 exposed at the bottom of the groove 81 from which the conductive portion 45 and the barrier metal film 46 have been removed, together with the bottom oxide film 82, thereby exposing the sacrificial layer 90.

[0108] Next, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, as shown in FIG. 21, a sidewall insulating film STc (first portion) extending in the Z direction and the X direction is formed, as well as a sidewall insulating film STc (second portion) extending in the Y direction from the opening of the trench 81 (the end of the first portion on the first side in the Z direction) along the surface of the stack 40 opposite the source line SL.

[0109] 22, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, a diffusion barrier layer STa (first portion) is formed along the inner surface of the trench 81 where the sidewall insulating film STc is formed and the inner surface of the space 83 communicating with the trench 81 where the sidewall insulating film STc is formed. At the same time, a diffusion barrier layer STa (second portion) is formed extending in the Y direction from the opening of the trench 81 (the end of the first portion on the first side in the Z direction) along the surface of the stacked body 40 opposite to the source line SL.

[0110] 23, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the trench 81 in which the diffusion barrier layer STa is formed and the space 83 communicating with the trench 81 are filled with a buried insulating film STb. At the same time, a buried insulating film STb is formed on the surface of the stacked body 40 on which the diffusion barrier layer STa is formed.

[0111] 24, the insulating layer 42 forming the surface of the stacked body 40 is exposed, as in the manufacturing method of the semiconductor memory device 1 of the first embodiment. As a result, a dividing portion ST including the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc is formed.

[0112] Next, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the dividing portion SHE, the contact CH, the contact VY, the bit line BL, and the wiring portion 70 are formed. The above steps complete the second chip 3. Thereafter, the second chip 3 and the first chip 2 are bonded together with the wiring section 70 of the second chip 3 facing the first chip 2.

[0113] Next, the substrate of the second chip 3 is peeled off from the surface of the second chip 3 opposite to the side where it is bonded to the first chip 2, and the sacrificial layer 90 is removed by etching. This exposes the insulating layer 42 and the memory film 51 of the columnar structure MHA on the surface (the lower surface in FIG. 25) opposite to the first chip 2 (not shown in FIG. 25) of the laminate 40. Thereafter, the memory film 51 is removed by etching, and the channel layer 52 of the columnar structure MHA is exposed, as shown in FIG. 25.

[0114] Thereafter, the source lines SL are formed on the insulating layer 42 exposed on the surface of the laminate 40 opposite to the first chip 2 and on the channel layer 52 of the columnar structure MHA using, for example, a semiconductor material containing silicon. In this way, the semiconductor memory device 1 of the first embodiment is formed.

[0115] <6.3 Third Modification of the Manufacturing Method of Semiconductor Memory Device> Next, a third modified example of the method for manufacturing the semiconductor memory device 1 of the first embodiment will be described. Note that the configuration other than the steps described below is the same as the configuration of the method for manufacturing the semiconductor memory device 1 of the first embodiment described above.

[0116] FIG. 26 is a cross-sectional view for explaining a third modification of the method for manufacturing the semiconductor memory device of the first embodiment. In the third variant of the manufacturing method of the semiconductor memory device 1 of the first embodiment, the steps up to forming a diffusion barrier layer STa along the inner surface of the trench 81 in which the sidewall insulating film STc is formed and the surface of the stack 40 in which the sidewall insulating film STc is formed (the surface of the stack 40 opposite the sacrificial layer 90) (see Figure 22) are performed in the same manner as in the second variant of the manufacturing method of the semiconductor memory device 1 of the first embodiment.

[0117] Thereafter, in the third modification, the step of forming the buried insulating film STb is performed multiple times (for example, twice) as in the first modification (see (a) in FIG. 26 and (b) in FIG. 26). Thereafter, in the third modification, similarly to the second modification of the manufacturing method of the semiconductor memory device 1 of the first embodiment, the surface of the stacked body 40 on which the sidewall insulating film STc, the diffusion barrier layer STa, and the buried insulating film STb are formed is etched to expose the surface of the stacked body 40. As a result, a dividing portion ST including the buried insulating film STb, the diffusion barrier layer STa, and the sidewall insulating film STc is formed.

[0118] <7. Advantages> The semiconductor memory device 1 of the first embodiment includes a stacked body 40 and a separating portion ST. The stacked body 40 includes a plurality of conductive layers 41 and a plurality of insulating layers 42, with the plurality of conductive layers 41 and the plurality of insulating layers 42 alternately stacked one layer at a time in the Z direction. The separating portion ST penetrates the stacked body 40 and extends in the Z direction and the X direction. The separating portion ST includes a buried insulating film STb and a diffusion barrier layer STa. The buried insulating film STb extends in the Z direction and the X direction and has insulating properties. The diffusion barrier layer STa is located between the conductive layer 41 and the buried insulating film STb in the Y direction, extends in the Z direction and the X direction, has a smaller thickness in the Y direction than the buried insulating film STb, and includes a different material from the buried insulating film STb.

[0119] Therefore, in the semiconductor memory device 1 of the first embodiment, the diffusion barrier layer STa located between the conductive layer 41 and the buried insulating film STb in the Y direction can suppress the impurities contained in the buried insulating film STb, which has a thickness in the Y direction greater than that of the diffusion barrier layer STa, from diffusing into the conductive layer 41. This can improve the reliability of the memory cell array 11 and the electrical characteristics of the semiconductor memory device 1.

[0120] In particular, when the buried insulating film STb is formed by a method of applying a liquid material such as polysilazane (PSZ) and then baking (annealing), the impurities contained in the buried insulating film STb are likely to diffuse into the conductive layer 41. Therefore, the diffusion barrier layer STa has a remarkable effect of suppressing the diffusion of the impurities contained in the buried insulating film STb into the conductive layer 41.

[0121] <8. Modified Examples of Semiconductor Memory Devices> Next, a description will be given of a modified example of the semiconductor memory device 1 of the first embodiment. Note that the configuration other than that described below is the same as that of the manufacturing method of the first embodiment described above.

[0122] <8.1 First Modification of Semiconductor Memory Device> Fig. 27 is a cross-sectional view showing a first modified example of the semiconductor memory device of the first embodiment, which is an enlarged cross-sectional view of the semiconductor memory device 1 of the first embodiment, showing an area corresponding to the area surrounded by line F7 shown in Fig. 6.

[0123] In the dividing portion ST in the semiconductor memory device 1A of the first modification, unlike the semiconductor memory device 1 of the first embodiment, the sidewall insulating film STc and the diffusion barrier layer STa include not only a first portion 91 extending in the Z direction and the X direction inside the dividing portion ST, but also a second portion 92 extending in the Y direction from an end of the first portion 91 on a first side in the Z direction (the lower side in FIG. 27 ). The second portion 92 of the sidewall insulating film STc and the diffusion barrier layer STa is arranged between the stacked body 40 and a plurality of wirings. The plurality of wirings are wirings arranged on the first side in the Z direction with respect to the stacked body 40, and include, for example, the bit line BL and wirings 71 and 72 (see FIG. 6 ).

[0124] The semiconductor memory device 1A shown in FIG. 27 can be formed, for example, by the following method. That is, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the trench 81 in which the sidewall insulating film STc and the diffusion barrier layer STa are formed and the space 83 communicating with the trench 81 are filled with the buried insulating film STb. At the same time, the steps up to forming the buried insulating film STb on the surface of the stacked body 40 on which the sidewall insulating film STc and the diffusion barrier layer STa are formed (see FIG. 14) are performed.

[0125] Next, the surface of the stacked body 40 on which the sidewall insulating film STc, the diffusion barrier layer STa, and the buried insulating film STb are formed is etched to expose the surface of the diffusion barrier layer STa. This forms the sidewall insulating film STc and the diffusion barrier layer STa, each of which includes a first portion 91 extending in the Z direction and the X direction inside the dividing portion ST, and a second portion 92 extending in the Y direction from an end of the first portion 91 on a first side in the Z direction (the lower side in FIG. 27).

[0126] 27, when wiring is arranged on a first side in the Z direction (the lower side in FIG. 27) of the stacked body 40, contacts CH and CC to be connected to the wiring are formed before the wiring is formed. The contacts CH and CC are formed after performing a step of removing, by etching, the formation regions of the contacts CH and CC and their vicinity in the X direction and Y direction of the second portion 92 of the sidewall insulating film STc and the diffusion barrier layer STa.

[0127] In the dividing portion ST in the semiconductor memory device 1A of the first modification, the sidewall insulating film STc and the diffusion barrier layer STa include a second portion 92 extending in the Y direction from an end portion on a first side in the Z direction (the lower side in FIG. 27) of the first portion 91. Therefore, for example, in the step of forming the bit line BL and the wiring 71, it is possible to suppress diffusion of impurities from the first side in the Z direction of the first portion 91 into the conductive layer 41.

[0128] <8.2 Second Modification of Semiconductor Memory Device> 28 is a plan view showing a second modification of the semiconductor memory device of the first embodiment. In FIG. 28, the insulating film 47 included in the conductive layer 41 is not shown, and the conductive portion 45 and the barrier metal film 46 integrated together are shown as the conductive layer 41.

[0129] The dividing portion ST of the semiconductor memory device 1B of the second modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. The separation portion ST of the semiconductor memory device 1B of the second variant has, when viewed from the Z direction, a first end 86A located on a first side in the Y direction (the right side in Figure 28) and a second end 86B located on a second side in the Y direction (the left side in Figure 28), which is opposite the first side.

[0130] The first end 86A includes a plurality of first arc portions 87A that are convex in the Y direction toward the outside of the dividing portion ST and adjacent in the X direction, and the second end 86B includes a plurality of second arc portions 87B that are convex in the Y direction toward the outside of the dividing portion ST and adjacent in the X direction. 28, the diffusion barrier layer STa includes a plurality of third arc portions 88A extending along the plurality of first arc portions 87A and a plurality of fourth arc portions 88B extending along the plurality of second arc portions 87B. The sidewall insulating film STc includes a plurality of fifth arc portions 89A extending along the plurality of first arc portions 87A and a plurality of sixth arc portions 89B extending along the plurality of second arc portions 87B.

[0131] In the semiconductor memory device 1B of the second modification, the dividing portion ST includes a plurality of first arc portions 87A and a plurality of second arc portions 87B, and therefore an electric field is likely to concentrate at portions 87 that protrude in a pointed shape toward the inside of the dividing portion ST in the Y direction, which are formed between adjacent first arc portions 87A and between adjacent second arc portions 87B. In the second modification, the diffusion barrier layer STa includes a plurality of third arc portions 88A and a plurality of fourth arc portions 88B, and therefore, when the diffusion barrier layer STa is formed of a material with a relatively high dielectric constant compared to the materials of the buried insulating film STb and the sidewall insulating film STc, the electric field concentration at the above-mentioned portion 87 that protrudes in a pointed shape can be alleviated.

[0132] In the semiconductor memory device 1B of the second variant, when the embedded insulating film STb and the sidewall insulating film STc are formed, for example, from a film containing silicon and oxygen, it is preferable that the diffusion barrier layer STa is formed, for example, from a material containing silicon and nitrogen, or a material containing oxygen and one or more types selected from aluminum, hafnium, and zirconium.

[0133] In the semiconductor memory device 1B of the second modification, the trenches for forming the dividing portions ST can be formed simultaneously with, for example, forming the plurality of holes for forming the memory pillars MH and / or forming the plurality of holes for forming the contacts CC. In this case, the dividing portions ST can be formed more efficiently than when a process for forming only the trenches for forming the dividing portions ST is performed separately from the process for forming the holes for forming the memory pillars MH and the process for forming the plurality of holes for forming the contacts CC.

[0134] <8.3 Third Modification of Semiconductor Memory Device> FIG. 29 is a cross-sectional view showing a third modified example of the semiconductor memory device of the first embodiment. FIG. 29 is a view for explaining portions of a semiconductor memory device 1C of the third modified example that differ from the semiconductor memory device 1 of the first embodiment. FIG. 30 is a cross-sectional view for explaining a method for manufacturing the semiconductor memory device shown in FIG. 29. In FIGS. 29 and 30, the insulating film 47 included in the conductive layer 41 is omitted, and the conductive portion 45 and the barrier metal film 46 that form the conductive layer 41 are integrated together are shown as the conductive layer 41. In addition, in FIGS. 29 and 30, the dividing portion ST embedded in the region between the insulating layers 42 where the conductive layer 41 does not exist is omitted.

[0135] The dividing portion ST of the semiconductor memory device 1C of the third modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. 29, when viewed from the X direction, the dividing portion ST of the semiconductor memory device 1C of the third modification has a first end 84A located on a first side in the Y direction (the right side in FIG. 29) and a second end 84B located on a second side in the Y direction opposite the first side (the left side in FIG. 29). Unlike the first embodiment, the dividing portion ST of the semiconductor memory device 1C of the third modification has first end 84A and second end 84B each including a portion 85 extending in the Y direction.

[0136] 29, the semiconductor memory device 1C of the third modification has a structure in which two laminated bodies 40B are stacked, each of which has a plurality of conductive layers 41 and a plurality of insulating layers 42 alternately stacked one layer at a time in the Z direction, with the outermost layer being the insulating layer 42. The laminated bodies 40B have columnar structures MHA (not shown in FIG. 29) that become memory pillars MH. A portion 85 extending in the Y direction of the first end 84A and the second end 84B is a step formed by stacking two laminated bodies 40B in which a groove for forming a dividing portion ST is formed.

[0137] The semiconductor memory device 1C of the third modified example can be formed, for example, by the method described below. That is, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, the insulating film 47 exposed at the bottom of the trench 81 from which the conductive portion 45 and the barrier metal film 46 have been removed is removed together with the bottom oxide film 82 by etching, and the source line SL is exposed (see FIG. 11). This forms the first stacked body 40B.

[0138] Furthermore, except that the source line SL is not formed, the manufacturing method is the same as that of the semiconductor memory device 1 of the first embodiment, and the steps up to removing the insulating film 47 exposed at the bottom of the trench 81 from which the conductive portion 45 and the barrier metal film 46 have been removed by etching (see Figure 11) are performed, and then the semiconductor substrate (not shown in Figure 11) is removed to form a second stacked body 40B having a trench 81 penetrating in the Z direction.

[0139] 30(a), the first laminate 40B and the second laminate 40B are laminated so that the grooves 81 of the first laminate 40B and the grooves 81 of the second laminate 40B partially or entirely overlap when viewed from the Z direction. As a result, grooves 85A are formed in which the grooves 81 of the first laminate 40B and the grooves 81 of the second laminate 40B are connected in the Z direction.

[0140] Next, in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, a sidewall insulating film STc extending in the Z direction and the X direction along the inner surface and bottom surface of the trench 85A and a diffusion barrier layer STa are formed in this order (see (b) in FIG. 30). 30(c), an insulating material is supplied to the trench 85A in which the sidewall insulating film STc and the diffusion barrier layer STa have been formed, whereby the trench 85A in which the sidewall insulating film STc and the diffusion barrier layer STa have been formed is filled with the buried insulating film STb.

[0141] The buried insulating film STb in the semiconductor memory device 1C of the third modification can be formed by, for example, a CVD (Chemical Vapor Deposition) method, a method of applying a liquid material such as polysilazane (PSZ) and then baking (annealing), etc. The method of applying a liquid material such as polysilazane (PSZ) and then baking (annealing) is preferable because it can provide good embedding properties even if the groove 85A (see FIG. 30(a)) formed by connecting the groove 81 of the first stacked body 40B and the groove 81 of the second stacked body 40B in the Z direction is narrow in the Y direction and deep in the Z direction.

[0142] When the buried insulating film STb in the semiconductor memory device 1C of the third modification is formed by applying a liquid material such as polysilazane (PSZ) and then baking (annealing), impurities contained in the buried insulating film STb are likely to diffuse into the conductive layer 41. However, in the semiconductor memory device 1C of the third modification, the dividing portion ST has a diffusion barrier layer STa. Therefore, by applying a liquid material such as polysilazane (PSZ) and then baking (annealing), it is possible to prevent impurities contained in the buried insulating film STb from diffusing into the conductive layer 41.

[0143] <8.4 Fourth Modification of Semiconductor Memory Device> 31 is a cross-sectional view showing a fourth modified example of the semiconductor memory device of the first embodiment. FIG. 31 is a diagram for explaining portions of a semiconductor memory device 1D of the fourth modified example that differ from the semiconductor memory device 1 of the first embodiment. In FIG. 31, the insulating film 47 included in the conductive layer 41 is omitted, and the conductive portion 45 and the barrier metal film 46 that form the conductive layer 41 are integrated together are shown as the conductive layer 41. Also, in FIG. 31, the dividing portion ST embedded in the region between the insulating layers 42 where the conductive layer 41 does not exist is omitted.

[0144] The dividing portion ST of the semiconductor memory device 1D of the fourth modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. 31, the dividing portion ST of the semiconductor memory device 1D of the fourth modification is located between the buried insulating film STb and the diffusion barrier layer STa in the Y direction, extends in the Z direction and the X direction, and includes a second buried insulating film STd containing a material different from that of the diffusion barrier layer STa. The second buried insulating film STd is an example of a "fourth film."

[0145] The second buried insulating film STd can be made of the same material as that used for the buried insulating film STb. In the semiconductor memory device 1D of the fourth modification, the second buried insulating film STd and the buried insulating film STb may be made of the same material or different materials.

[0146] Furthermore, the dividing portion ST of the semiconductor memory device 1D of the fourth modification is located between the buried insulating film STb and the second buried insulating film STd in the Y direction, extends in the Z direction and the X direction, and includes a second diffusion barrier layer STe containing a material different from that of the buried insulating film STb and the second buried insulating film STd. The second diffusion barrier layer STe is an example of a "fifth film."

[0147] The second diffusion barrier layer STe can be made of the same material as that used for the diffusion barrier layer STa. In the semiconductor memory device 1D of the fourth modification, the second diffusion barrier layer STe and the diffusion barrier layer STa may be made of the same material or different materials. When the second diffusion barrier layer STe and the diffusion barrier layer STa are made of different materials, the second diffusion barrier layer STe and the diffusion barrier layer STa can suppress the diffusion of multiple types of impurities from the buried insulating film STb to the conductive layer 41.

[0148] The dividing portion ST of the semiconductor memory device 1D of the fourth modification can be formed by, for example, the method described below. That is, in the same manner as in the method for forming the buried insulating film STb in the first method of manufacturing the semiconductor memory device 1 of the first embodiment, a second buried insulating film STd is formed along the inner surface of the trench 81 in which the diffusion barrier layer STa is formed and the surface on which the sidewall insulating film STc and diffusion barrier layer STa of the stacked body 40 are formed (the surface of the stacked body 40 opposite the source line SL) (see Figure 16(a)).

[0149] Thereafter, a second diffusion barrier layer STe extending in the Z direction and the X direction along the inner surface of the trench 81 is formed in the same manner as in the method for forming the diffusion barrier layer STa in the method for manufacturing the semiconductor memory device 1 of the first embodiment. Thereafter, the trench 81 in which the second diffusion barrier layer STe has been formed is filled with the buried insulating film STb in the same manner as in the first modified example of the method for manufacturing a semiconductor memory device.

[0150] The semiconductor memory device 1D of the fourth modification has the diffusion barrier layer STa and the second diffusion barrier layer STe, and therefore can suppress the impurities contained in the buried insulating film STb and the second diffusion barrier layer STe from diffusing into the conductive layer 41. This can improve the reliability of the memory cell array 11 and the electrical characteristics of the semiconductor memory device 1.

[0151] <8.5 Fifth Modification of Semiconductor Memory Device> Fig. 32 is a cross-sectional view showing a fifth modified example of the semiconductor memory device of the first embodiment. Fig. 32 is a diagram for explaining portions of a semiconductor memory device 1E of the fifth modified example that differ from the semiconductor memory device 1 of the first embodiment. In Fig. 32, the insulating film 47 included in the conductive layer 41 is omitted, and the conductive portion 45 and the barrier metal film 46 that form the conductive layer 41 are integrated together are shown as the conductive layer 41. Also, in Fig. 32, the dividing portion ST embedded in the region between the insulating layers 42 where the conductive layer 41 does not exist is omitted.

[0152] The dividing portion ST of the semiconductor memory device 1E of the fifth modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. As shown in FIG. 32, the separation portion ST of the semiconductor memory device 1E of the fifth variant is located between the buried insulating film STb and the diffusion barrier layer STa in the Y direction, extends in the Z direction and the X direction, and includes a second diffusion barrier layer STe containing a material different from that of the diffusion barrier layer STa.

[0153] The second diffusion barrier layer STe can be made of the same material as that used for the diffusion barrier layer STa. In the semiconductor memory device 1E of the fifth modification, the second diffusion barrier layer STe and the diffusion barrier layer STa are made of different materials. Therefore, the second diffusion barrier layer STe and the diffusion barrier layer STa can suppress the diffusion of multiple types of impurities from the buried insulating film STb to the conductive layer 41.

[0154] The dividing portion ST of the semiconductor memory device 1E of the fifth modification can be formed by, for example, the method described below. That is, after forming a diffusion barrier layer STa in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment, a second diffusion barrier layer STe is formed using a material different from the diffusion barrier layer STa in the same manner as in the manufacturing method of the semiconductor memory device 1 of the first embodiment.

[0155] <8.6 Sixth Modification of Semiconductor Memory Device> Fig. 33 is a cross-sectional view showing a sixth modified example of the semiconductor memory device of the first embodiment. Fig. 33 is a diagram for explaining portions of a semiconductor memory device 1F of the sixth modified example that differ from the semiconductor memory device 1 of the first embodiment. In Fig. 33, the insulating film 47 included in the conductive layer 41 is omitted, and the conductive portion 45 and the barrier metal film 46 that form the conductive layer 41 are integrated together are shown as the conductive layer 41. Also, in Fig. 33, the dividing portion ST embedded in the region between the insulating layers 42 where the conductive layer 41 does not exist is omitted.

[0156] The dividing portion ST of the semiconductor memory device 1F of the sixth modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. As shown in FIG. 33, the dividing portion ST of the semiconductor memory device 1F of the sixth modified example is located inside the buried insulating film STb in the Y direction, extends in the Z direction and the X direction, and includes a conductive layer STf containing a material different from that of the buried insulating film STb. The conductive layer STf is formed of, for example, silicon doped with impurities. The conductive layer STf may be formed of, for example, amorphous silicon or silicon germanium (GeSi), which is silicon doped with germanium.

[0157] The dividing portion ST of the semiconductor memory device 1F of the sixth modification can be formed by, for example, the following method. That is, in the same manner as the method for forming the buried insulating film STb in the first method of manufacturing the semiconductor memory device 1 of the first embodiment, the buried insulating film STb is formed along the inner surface of the trench 81 in which the diffusion barrier layer STa is formed and the surface on which the sidewall insulating film STc and diffusion barrier layer STa of the stacked body 40 are formed (the surface of the stacked body 40 opposite the source line SL) (see Figure 16(a)). Thereafter, instead of the material that becomes the buried insulating film STb in the first modified example of the method for manufacturing a semiconductor memory device, a material that becomes the conductive layer STf is used to fill the trench 81 in which the buried insulating film STb has been formed with the conductive layer STf.

[0158] <8.7 Seventh Modification of Semiconductor Memory Device> Fig. 34 is a cross-sectional view showing a seventh modification of the semiconductor memory device of the first embodiment. Fig. 34 is a diagram for explaining portions of a semiconductor memory device 1G of the seventh modification that differ from the semiconductor memory device 1 of the first embodiment. In Fig. 34, the insulating film 47 included in the conductive layer 41 is omitted, and the conductive portion 45 and the barrier metal film 46 that form the conductive layer 41 are integrated together are shown as the conductive layer 41. Also, in Fig. 34, the dividing portion ST embedded in the region between the insulating layers 42 where the conductive layer 41 does not exist is omitted.

[0159] The dividing portion ST of the semiconductor memory device 1G of the seventh modification includes a buried insulating film STb, a diffusion barrier layer STa, and a sidewall insulating film STc, similar to the dividing portion ST of the semiconductor memory device 1 of the first embodiment. As shown in Figure 34, the separation portion ST of the semiconductor memory device 1G of the seventh modified example has a sidewall insulating film STc whose thickness in the Y direction becomes thinner toward one side in the Z direction relative to the stacked body 40 (the lower side in Figure 34), and a buried insulating film STb whose thickness in the Y direction becomes thicker toward one side in the Z direction relative to the stacked body 40.

[0160] Fig. 35 is a cross-sectional view for explaining the advantage of Modification 7. The dividing portion 95 in the semiconductor memory device shown in Fig. 35 has a sidewall insulating film 95a corresponding to the sidewall insulating film STc of the semiconductor memory device 1G of Modification 7, and a buried insulating film 95b corresponding to the buried insulating film STb of the semiconductor memory device 1E of Modification 5. In the dividing portion ST of the semiconductor memory device shown in FIG. 35, the thicknesses of the buried insulating film 95b and the sidewall insulating film 95a in the Y direction become thicker toward one side in the Z direction relative to the stacked body 40 (the lower side in FIG. 34).

[0161] 35, a cavity 96 is formed in the center of the buried insulating film 95b in the Y direction in the dividing portion ST. When the cavity 96 is formed in the dividing portion ST, the strength of the dividing portion ST decreases. Furthermore, impurities may diffuse from the cavity 96 formed in the dividing portion ST into the conductive layer 41, which may reduce the reliability of the memory cell array 11.

[0162] In contrast, in the dividing portion ST of the semiconductor memory device 1G of the seventh modification, the thickness of the sidewall insulating film STc in the Y direction becomes thinner toward one side in the Z direction relative to the stacked body 40 (the lower side in FIG. 34 ), and the thickness of the buried insulating film STb in the Y direction becomes thicker toward one side in the Z direction relative to the stacked body 40. Therefore, after the diffusion barrier layer STa is formed along the inner surface of the sidewall insulating film STc, the embeddability of the buried insulating film STb formed along the inner surface of the diffusion barrier layer STa is improved. Therefore, in the semiconductor memory device 1G of the seventh modification, cavities are less likely to be formed in the buried insulating film STb. Therefore, according to the semiconductor memory device 1G of the seventh modification, it is possible to prevent a decrease in strength of the dividing portion ST and diffusion of impurities from the cavities into the conductive layer 41 due to the formation of cavities in the buried insulating film STb.

[0163] Although one embodiment and multiple examples have been described above, the embodiment and examples are not limited to the above examples.

[0164] According to at least one embodiment described above, the semiconductor memory device includes a stacked body and a dividing portion. The stacked body includes a plurality of conductive layers and a plurality of insulating layers, the plurality of conductive layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction. The dividing portion penetrates the stacked body and extends in the first direction and a second direction intersecting the first direction. When a direction intersecting the first direction and the second direction is defined as a third direction, the dividing portion includes a first film and a second film. The first film extends in the first direction and the second direction and has insulating properties. The second film is located between the conductive layer and the first film in the third direction, extends in the first direction and the second direction, has a smaller thickness in the third direction than the first film, and includes a different material from the first film. This configuration can improve the electrical characteristics of the semiconductor memory device.

[0165] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0166] 1...Semiconductor memory device 40...Laminate 41...Conductive layer 42...insulating layer 45...Conductive part 46...Barrier metal film 47...insulating film CC: Contact ST: Divided section STa...Diffusion barrier layer STb...buried insulating film STc: Sidewall insulating film

Claims

1. a laminate including a plurality of conductive layers and a plurality of insulating layers, the plurality of conductive layers and the plurality of insulating layers being alternately stacked one by one in a first direction; a dividing portion that penetrates the laminate and extends in the first direction and a second direction that intersects with the first direction; Equipped with When a direction intersecting the first direction and the second direction is defined as a third direction, The dividing portion is a first film extending in the first direction and the second direction and having insulating properties; a second film located between the plurality of conductive layers and the first film in the third direction, extending in the first direction and the second direction, having a smaller thickness in the third direction than the first film, and containing a different material from the first film; Including, Semiconductor memory device.

2. a third film located between the plurality of conductive layers and the second film in the third direction, extending in the first direction and the second direction, having insulating properties, and containing a material different from that of the second film; 2. The semiconductor memory device according to claim 1.

3. The thickness of the third film in the third direction is 5 nm to 10 nm.

3. The semiconductor memory device according to claim 2.

4. the second film contains silicon and nitrogen; 3. The semiconductor memory device according to claim 1.

5. the second film comprises aluminum, hafnium, zirconium, or titanium; 3. The semiconductor memory device according to claim 1.

6. When viewed from the second direction, the dividing portion has a first end portion located on a first side in the third direction and a second end portion located on a second side in the third direction opposite to the first side, 3. The semiconductor memory device according to claim 1, wherein one or both of said first end and said second end includes a portion extending in said third direction.

7. When viewed from the first direction, the dividing portion has a first end portion located on a first side in the third direction and a second end portion located on a second side in the third direction opposite to the first side, the first end portion includes a plurality of first arc portions each of which is convex toward an outside of the dividing portion in the third direction and which are adjacent to each other in the second direction; the second end portion includes a plurality of second arc portions each of which is convex toward an outside of the dividing portion in the third direction and which are adjacent to each other in the second direction; the second film includes a plurality of third arc portions along the plurality of first arc portions and a plurality of fourth arc portions along the plurality of second arc portions; 3. The semiconductor memory device according to claim 1.

8. further comprising a plurality of wirings arranged on a first side of the stacked body in the first direction; the second film includes a first portion extending in the first direction and the second direction inside the dividing portion, and a second portion extending in the third direction from an end of the first portion on the first side in the first direction and disposed between the stacked body and the plurality of wirings, 3. The semiconductor memory device according to claim 1.

9. a thickness of the third film in the third direction that decreases toward one side in the first direction with respect to the stacked body; 3. The semiconductor memory device according to claim 2, wherein the thickness of said first film in said third direction increases toward one side in said first direction relative to said stacked body.

10. a fourth film located between the first film and the second film in the third direction, extending in the first direction and the second direction, and containing a material different from that of the second film; 3. The semiconductor memory device of claim 1, further comprising: a fifth film located between the first film and the fourth film in the third direction, extending in the first direction and the second direction, and containing a material different from that of the first film and the fourth film.

11. forming a laminate by alternately stacking the first layers and the second layers in a first direction; a groove is formed that penetrates the laminate in the first direction and extends in a second direction that intersects with the first direction; replacing the first layer with a conductive layer by a replacement step using the groove; forming a second film extending in the first direction and the second direction along an inner surface of the groove; forming an insulating first film inside the groove, the first film being located on the opposite side of the conductive layer with respect to the second film, and extending in the first direction and the second direction; This includes: When a direction intersecting the first direction and the second direction is defined as a third direction, the second film has a smaller thickness in the third direction than the first film and contains a different material from the first film; A method for manufacturing a semiconductor memory device.

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