Ceramic electronic component and method of manufacturing the same

Abstract

To provide a ceramic electronic component capable of suppressing reduction in the continuity rate of an internal electrode layer, and to provide a method of manufacturing the same.SOLUTION: A ceramic electronic component includes a laminated chip in which dielectric layers and internal electrode layers including Ni as a main phase are alternately laminated, wherein at least one of the dielectric layers includes a secondary phase including Si at an interface with the adjacent internal electrode layer, and the internal electrode layer adjacent to the dielectric layer including the secondary phase includes a layer including one or more additive elements of Au, Pt, Cu, Fe, Cr, Zn, and In at a portion in contact with the secondary phase at the interface.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Multilayer ceramic capacitors are manufactured by printing a metal paste made primarily of Ni powder onto a dielectric green sheet made primarily of a dielectric material such as barium titanate, followed by lamination, compression bonding, cutting, binder removal, firing, and application of external electrodes. To meet market demand for smaller, higher-capacity multilayer ceramic capacitors, there is a demand for thinner internal electrode layers and higher lamination density, as well as thinner dielectric layers.

[0003] In order to suppress internal defects such as cracks during the simultaneous firing of ceramic dielectric layers and metal internal electrode layers, a secondary phase composed of liquid phase components such as Si, which acts as a sintering aid, is introduced into the dielectric layers in addition to the dielectric material, which is the main phase, to design the microstructure and electrical properties (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-123698 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the internal electrode layers, discontinuities are likely to occur at contact points with the secondary phase due to the sintering promotion effect of liquid phase sintering.

[0006] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that can suppress a decrease in the continuity ratio of internal electrode layers, and a method for manufacturing the same. [Means for solving the problem]

[0007] The ceramic electronic component according to the present invention comprises a laminated chip in which dielectric layers and internal electrode layers having Ni as a main phase are alternately stacked, and at least one of the dielectric layers comprises a secondary phase containing Si at the interface with an adjacent internal electrode layer, and the internal electrode layer adjacent to the dielectric layer having the secondary phase comprises a layer containing one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In at a location in contact with the secondary phase at the interface.

[0008] In the ceramic electronic component, in the internal electrode layer adjacent to the dielectric layer including the secondary phase, the total amount of the additional elements relative to Ni may be 0.01 at % or more and 5 at % or less.

[0009] In the ceramic electronic component, the layer containing the additional element may be a single metal, an alloy, or an oxide of the additional element.

[0010] In the ceramic electronic component, the ratio (thickness of the secondary phase / thickness of the layer containing the additive element) in the stacking direction of the dielectric layers and the internal electrode layers may be 0.1 or more and 3 or less.

[0011] In the ceramic electronic component, the dielectric layer may have a thickness of 0.5 μm or less.

[0012] In the ceramic electronic component, when a STEM-EDS line analysis is performed in the stacking direction of the dielectric layers and the internal electrode layers, a peak of Si concentration may appear in the secondary phase, and a peak of the concentration of the additional element may appear in the layer containing the additional element.

[0013] In the ceramic electronic component, the internal electrode layer adjacent to the dielectric layer including the secondary phase may have a thickness of 0.05 μm or more and 0.4 μm or less.

[0014] In the ceramic electronic component, the dielectric layer may contain barium titanate.

[0015] The method for producing a ceramic electronic component according to the present invention includes the steps of: forming a laminate unit by forming an internal electrode pattern of Ni paste containing one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In on a dielectric green sheet containing a sintering aid containing SiO2; forming a laminate by stacking a plurality of the laminate units; and firing the laminate, wherein the conditions for the firing step are adjusted so that in at least one of the dielectric layers obtained by firing the dielectric green sheet, a secondary phase containing Si is formed at the interface with an adjacent internal electrode layer obtained by firing the internal electrode pattern, and a layer containing the additive element is formed in the adjacent internal electrode layer at a location in contact with the secondary phase. [Effects of the Invention]

[0016] According to the present invention, it is possible to provide a ceramic electronic component capable of suppressing a decrease in the continuity ratio of internal electrode layers, and a method for manufacturing the same. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 1A and 1B are diagrams illustrating secondary phases formed in a dielectric layer. [Figure 5] FIG. 10 is a diagram showing a continuity rate. [Figure 6] 1A and 1B are diagrams illustrating layers containing additional elements. [Figure 7] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 8] 1(a) and 1(b) are diagrams illustrating the lamination process. [Figure 9] FIG. 1 shows the positions where STEM-EDS line analysis was performed. [Figure 10] 1(a) to 1(c) show the results of STEM-EDS line analysis of the multilayer ceramic capacitor of Example 1. [Figure 11] 1(a) to 1(c) show the results of STEM-EDS line analysis of the multilayer ceramic capacitor of Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings.

[0019] (First embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 in accordance with the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0020] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 whose main phase is Ni are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in a laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered with a cover layer 13. The cover layer 13 is primarily composed of a ceramic material. For example, the material of the cover layer 13 may be made of the same primarily ceramic material as the dielectric layers 11.

[0021] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.110 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.1 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0022] The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sry Ti 1-z Zr z At least one of the following can be selected and used: O3 (0≦x≦1, 0≦y≦1, 0≦z≦1). 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate zirconate.

[0023] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0024] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0025] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0026] The laminated structure of the dielectric layers 11 and the internal electrode layers 12 can be obtained by firing multiple laminated units, each of which is made by printing a metal paste, primarily made of Ni powder, on a dielectric green sheet. Therefore, the ceramic dielectric layers 11 and the metal internal electrode layers 12 are simultaneously fired. To suppress internal defects, such as cracks, that tend to occur during the simultaneously firing process, a sintering aid containing Si is added to the dielectric green sheets. The sintering aid becomes liquid during firing, causing liquid-phase sintering and promoting the sintering of the ceramic, the primary component of the dielectric layers 11. This liquid phase becomes a secondary phase after firing.

[0027] FIG. 4 is a diagram illustrating a main phase 17 and a secondary phase 18 formed in the dielectric layer 11. As illustrated in FIG. 4, the main phase 17 and the secondary phase 18 are formed in the dielectric layer 11. The main phase 17 is the grains of the ceramic that is the main component of the dielectric layer 11. The secondary phase 18 is formed at the grain boundaries of the main phase 17 and at the interface between the dielectric layer 11 and the internal electrode layer 12. The secondary phase 18 is a phase generated in the dielectric layer 11 by firing a sintering aid, and is mainly composed of, for example, SiO2 or at least one of SiO2 and B2O3. At the locations of the internal electrode layer 12 that contact the secondary phase 18, discontinuity is likely to occur due to the sintering promotion effect of liquid phase sintering, which may cause a decrease in continuity.

[0028] Fig. 5 is a diagram showing the continuity ratio. As shown in Fig. 5, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, . . . , Ln of the metal parts are measured and summed, and the ratio of the metal parts, ΣLn / L0, can be defined as the continuity ratio of that layer.

[0029] The multilayer ceramic capacitor 100 according to this embodiment has a structure that suppresses a decrease in the continuity ratio of the internal electrode layers 12. First, as illustrated in FIG. 6, at least one of the dielectric layers 11 has a secondary phase 18 at the interface between the dielectric layer 11 and the internal electrode layer 12.

[0030] The internal electrode layer 12 includes a layer 19 containing one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In at a location in contact with the secondary phase 18 at the interface between the dielectric layer 11 and the internal electrode layer 12. The layer 19 is a thin layer that appears on the surface of the internal electrode layer 12, and is a layer in which a peak appears in the concentration of the additive element when STEM-EDS line analysis is performed along the stacking direction. The layer 19 may be a single metal, alloy, or oxide of one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In. The provision of the layer 19 causes pinning at the interface, thereby suppressing the sintering promotion effect at the contact interface with the secondary phase 18, which exists as a liquid phase during firing. This suppresses spheroidization and discontinuity of the internal electrode layer 12, and thereby suppresses a decrease in the continuity of the internal electrode layer 12. The layer 19 may cover the entire interface between the dielectric layer 11 and the internal electrode layer 12, or may cover at least a part of the interface.

[0031] For example, Au, Pt, and Cu have higher ionization energies than Ni, so layer 19 containing at least one of Au, Pt, and Cu suppresses atomic diffusion that occurs during sintering and also suppresses the sintering promotion effect at the contact interface with secondary phase 18. Fe, Cr, Zn, and In form oxides or composite oxides that are more stable than Ni, so layer 19 containing at least one of Fe, Cr, Zn, and In inhibits the reaction in which metallic Ni dissolves into secondary phase 18 and suppresses the sintering promotion effect.

[0032] If the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In in the internal electrode layer 12 is small, the sintering promotion effect at the contact interface with the secondary phase 18 may not be sufficiently suppressed. Therefore, it is preferable to set a lower limit for the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In in the internal electrode layer 12. For example, in the internal electrode layer 12, the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In is preferably 0.01 at% or more, more preferably 0.05 at% or more, and even more preferably 0.1 at% or more, when Ni is 100 at%. Note that metals that are not added among Au, Pt, Cu, Fe, Cr, Zn, and In are not included in the total amount. Therefore, when only Au is added to the internal electrode layer 12, the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In refers to the amount of Au.

[0033] On the other hand, if the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In in the internal electrode layers 12 is large, problems may occur, such as the diffusion of these elements into the dielectric layers 11, oxidation of the internal electrode layers 12, and a non-negligible effect on the sinterability of the internal electrode layers 12. Therefore, it is preferable to set an upper limit on the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In in the internal electrode layers 12. For example, in the internal electrode layers 12, the total amount of Au, Pt, Cu, Fe, Cr, Zn, and In is preferably 5 at% or less, more preferably 3 at% or less, and even more preferably 1 at% or less, when Ni is taken as 100 at%.

[0034] The thickness of each dielectric layer 11 is 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less, or 0.6 μm or less. Here, if the dielectric layers 11 are thin, the restraining force of the dielectric layers 11 during sintering is reduced, making the internal electrode layers 12 more likely to become spheroidized. Therefore, in a configuration in which the dielectric layers 11 are thin, the effect of suppressing a decrease in the continuity ratio of the internal electrode layers 12 of this embodiment is significantly achieved. For example, when the dielectric layers 11 are 0.5 μm or less, the effect of this embodiment is significantly achieved. The thickness of the dielectric layers 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a scanning electron microscope (SEM), measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value of all the measurement points.

[0035] In a configuration in which the internal electrode layers 12 are thin, the effect of suppressing a decrease in the continuity ratio of the internal electrode layers 12 of this embodiment is significantly achieved. For example, when the thickness of each internal electrode layer 12 is 0.4 μm or less, 0.6 μm or less, or 0.8 μm or less, the effect of this embodiment is significantly achieved. On the other hand, if the internal electrode layers 12 are too thin, the thickness ratio of the layers 19 to the thickness of the internal electrode layers 12 becomes high, which may result in an increase in ESR (equivalent series resistance), oxidation of the internal electrode layers 12, and the influence of the sinterability of the internal electrode layers 12 becoming non-negligible. Therefore, the thickness of each internal electrode layer 12 is preferably 0.05 μm or more, more preferably 0.1 μm or more, and even more preferably 0.15 μm or more. The thickness of the internal electrode layers 12 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with an SEM, measuring the thickness at 10 points for each of 10 different internal electrode layers 12, and deriving the average value of all the measurement points.

[0036] If the thickness ratio (thickness of secondary phase 18 / thickness of layer 19) between the dielectric layer 11 and the internal electrode layer 12 in the lamination direction is large, the amount of liquid phase in the system will increase relatively, and there is a risk that the pinning action at the interface will be difficult to maintain. Therefore, it is preferable to set an upper limit to the thickness ratio. For example, the thickness ratio is preferably 3 or less, more preferably 2 or less, and even more preferably 1.5 or less. On the other hand, if the thickness ratio is small, the dielectric layer may not be able to absorb the shrinkage stress associated with sintering of the internal electrode layer, which occurs at a lower temperature, and cracks may occur. Therefore, it is preferable to set a lower limit to the thickness ratio. For example, the thickness ratio is preferably 0.1 or more, more preferably 0.3 or more, and even more preferably 0.5 or more.

[0037] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0038] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0039] The resulting ceramic powder is then mixed with a specific additive compound depending on the intended purpose. Examples of additive compounds include oxides of magnesium (Mg), manganese (Mn), vanadium (V), Cr, rare earth elements (Y, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon. Of these, SiO2 primarily functions as a sintering aid.

[0040] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0041] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0042] Next, as illustrated in Fig. 8(a), internal electrode patterns 53 are formed on the dielectric green sheet 52. In Fig. 8(a), as an example, four layers of internal electrode patterns 53 are formed at predetermined intervals on the dielectric green sheet 52. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is defined as a lamination unit.

[0043] Ni paste is used for the internal electrode pattern 53. The Ni paste contains Ni powder and an organometallic complex or fine powder of at least one additive element selected from Au, Pt, Cu, Fe, Cr, Zn, and In. Powder of an alloy of the additive element and Ni may also be used. Ni powder coated on the surface of the additive element may also be used. The effective metal concentration of the additive element is preferably 0.01 at% or more and 5 at% or less, assuming that Ni is 100 at%. The film formation method may be printing, sputtering, vapor deposition, plating, or the like.

[0044] Next, while peeling off the dielectric green sheet 52 from the substrate 51, the lamination units are laminated as shown in FIG. 8(b).

[0045] Next, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are laminated on top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of Figure 8(b), cutting is performed along the dotted lines. The cover sheet 54 may have the same components as the dielectric green sheet 52, or may contain a different additive compound.

[0046] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping, and the ceramic laminate was heated in an atmosphere with an oxygen partial pressure of 10 -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0047] The layer 19 can be formed by adjusting firing conditions such as the firing temperature, the rate of temperature rise up to the firing temperature, and the atmosphere during the firing process. It is important that the layer 19 is formed on the surface layer of the internal electrode layer 12 before the liquid phase component containing SiO2 as a sintering aid comes into contact with the internal electrode material mainly composed of Ni and the sintering promoting effect is realized. For this reason, a firing profile is provided in which a temperature rise rate range of 50°C / min or less is set for 3 minutes or more, or a temperature keep period (a period of holding at the same temperature) of 1 minute or more is set in a temperature range (for example, a temperature range of 1000°C or less) lower than the temperature range in which SiO2 as a sintering aid melts and a liquid phase begins to form.

[0048] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0049] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0050] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0051] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0052] Example 1 A 1.0mm x 0.5mm x 0.5mm multilayer chip was fabricated by stacking laminated units printed with Ni paste containing Ni powder on a dielectric green sheet containing barium titanate, pressing, cutting, removing the binder, and firing. The dielectric layers were 0.8μm thick, the internal electrode layers were 0.6μm thick, and the number of dielectric and internal electrode layers was 470. In addition to the dielectric material (main phase), an appropriate amount of SiO2 powder was blended as a sintering aid. Au source was also added to the Ni paste. The amount of Au was 1at% when Ni was 100at%.

[0053] Example 2 In Example 2, the conditions were the same as those in Example 1, except that the thickness of the internal electrode layer was set to 0.5 μm.

[0054] Example 3 In Example 3, the conditions were the same as those in Example 1, except that the thickness of the internal electrode layer was set to 0.4 μm.

[0055] Example 4 In Example 4, a Pt source was added to the Ni paste instead of the Au source. The Pt content was 1 at% when Ni was 100 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0056] Example 5 In Example 5, a Cu source was added to the Ni paste instead of the Au source. When Ni was 100 at%, the Cu content was 1 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0057] Example 6 In Example 6, an Fe source was added to the Ni paste instead of an Au source. The Fe content was 1 at% when Ni was 100 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0058] Example 7 In Example 7, a Cr source was added to the Ni paste instead of an Au source. The Cr content was 1 at% when Ni was 100 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0059] Example 8 In Example 8, a Zn source was added to the Ni paste instead of an Au source. The amount of Zn was 1 at% when Ni was 100 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0060] Example 9 In Example 9, an In source was added to the Ni paste instead of an Au source. The amount of In was 1 at% when Ni was 100 at%. The thickness of the internal electrode layer was 0.4 μm. The other conditions were the same as those in Example 1.

[0061] (Comparative Example 1) In Comparative Example 1, the Au source was not added to the Ni paste, but the other conditions were the same as those in Example 1.

[0062] (Comparative Example 2) In Comparative Example 2, no Au source was added to the Ni paste, and the thickness of the internal electrode layer was set to 0.5 μm. The other conditions were the same as those in Example 1.

[0063] (Comparative Example 3) In Comparative Example 3, no Au source was added to the Ni paste, and the thickness of the internal electrode layer was set to 0.4 μm. The other conditions were the same as those in Example 1.

[0064] STEM-EDS line analysis was performed on the interface between the dielectric layer and the internal electrode layer for each of Examples 1 to 9 and Comparative Examples 1 to 3. For Examples 1 to 9, a layer containing an additive element was confirmed on the internal electrode layer side, and it was confirmed that the layer was in contact with the secondary phase on the dielectric layer side.

[0065] Fig. 9 is a diagram showing the positions where STEM-EDS line analysis was performed on the multilayer ceramic capacitor of Example 1. As shown in Fig. 9, line analysis was performed from the dielectric layer toward the internal electrode layer near the interface between the dielectric layer and the internal electrode layer, at a location where the secondary phase and the layer containing the additive element contact.

[0066] 10(a) to 11(c) show the results of STEM-EDS line analysis of the multilayer ceramic capacitor of Example 1. FIG. 10(a) shows the measured concentration of O (oxygen). FIG. 10(b) shows the measured concentration of Ti. FIG. 10(c) shows the measured concentration of Ni. FIG. 11(a) shows the measured concentration of Ba. FIG. 11(b) shows the measured concentration of Au. FIG. 11(c) shows the measured concentration of Si. In FIGS. 10(a) to 11(c), the dotted lines represent the interfaces between the dielectric layers 11 and the internal electrode layers 12.

[0067] As shown in Figure 10(a), the O (oxygen) concentration drops sharply at the interface. This is thought to be because the oxygen concentration is low in the internal electrode layers. As shown in Figure 10(b), the Ti concentration drops sharply at the interface. This is thought to be because Ti is mainly contained in the barium titanate in the dielectric layers, and the Ti concentration is low in the internal electrode layers. As shown in Figure 10(c), the Ni concentration increases sharply at the interface. This is thought to be because Ni is mainly contained in the internal electrode layers, and the Ni concentration is low in the dielectric layers. As shown in Figure 11(a), the Ba concentration drops sharply at the interface. This is thought to be because Ba is mainly contained in the barium titanate in the dielectric layers, and the Ba concentration is low in the internal electrode layers.

[0068] As shown in Figures 11(b) and 11(c), Au and Si concentration peaks appeared near the interface. The Au concentration peak was located closer to the internal electrode layer than the interface. This is thought to be due to the formation of an Au-containing layer on the internal electrode layer side at the interface. The Si concentration peak was located closer to the dielectric layer than the interface. This is thought to be due to the formation of a secondary phase on the dielectric layer side at the interface. The Si content at the top of the Au peak was higher than the average Si content in the dielectric layer. In addition, the Au content at the top of the Si peak was higher than the average Au content in the internal electrode layer. The Si ratio (at%) in the secondary phase in contact with the Au-containing layer was more than 1 at% higher than the average Si content (at%) in the dielectric layer.

[0069] In Examples 2 to 9, as in Example 1, peaks of the additive element concentration and peaks of the Si concentration appeared near the interface. The peak of the additive element concentration was located closer to the internal electrode layer than the interface. This is thought to be because a layer containing the additive element was formed on the internal electrode layer side at the interface. The peak of the Si concentration was located closer to the dielectric layer than the interface. This is thought to be because a secondary phase was formed on the dielectric layer side at the interface. The Si content at the additive element peak top position was higher than the average level of Si content in the dielectric layer. In addition, the additive element content at the Si peak top position was higher than the average level of additive element content in the internal electrode layer. In each Example, the layer containing the additive element is the region where the concentration of the additive element is highest, that is, the region showing the position of the peak of the additive element, within a range of 15 nm on the internal electrode layer side and the dielectric layer side, respectively, based on the interface, as shown in Figure 11(b). In each example, as shown in FIG. 11(c), the secondary phase containing Si is the region where the concentration of Si is highest, that is, the region showing the position of the peak of Si, within a range of 15 nm on the internal electrode layer side and on the dielectric layer side, based on the interface.

[0070] In Comparative Examples 1 to 3, no layer containing an additional element was observed.

[0071] The thickness of the secondary phase in the stacking direction / the thickness of the layer containing the additive element was measured at the interface between the dielectric layer and the internal electrode layer for each of Examples 1 to 9. The ratio was 0.73 for Example 1, 0.96 for Example 2, 1.10 for Example 3, 1.04 for Example 4, 1.09 for Example 5, 1.14 for Example 6, 1.12 for Example 7, 0.99 for Example 8, and 0.93 for Example 9.

[0072] The continuity ratio of the internal electrode layers was measured for each of the multilayer ceramic capacitors of Examples 1 to 9 and Comparative Examples 1 to 3. The continuity ratio of the internal electrode layers was measured by SEM observation (magnification 5000x, average of four fields of view) of the cross-sectional polished surface near the center of the chip. The continuity ratio ratio was measured for the same thickness in the Examples and Comparative Examples. The results are shown in Table 1. Compared to the continuity ratio of Comparative Example 1, the continuity ratio of Example 1 was 1.05 times. Compared to the continuity ratio of Comparative Example 2, the continuity ratio of Example 2 was 1.14 times. Compared to the continuity ratio of Comparative Example 3, the continuity ratio of Example 3 was 1.17 times, the continuity ratio of Example 4 was 1.26 times, the continuity ratio of Example 5 was 1.16 times, the continuity ratio of Example 6 was 1.17 times, the continuity ratio of Example 7 was 1.26 times, the continuity ratio of Example 8 was 1.17 times, and the continuity ratio of Example 9 was 1.17 times. From the above results, it was found that, under the condition that the thickness of the internal electrode layer is the same, the continuity ratio of the internal electrode layer is improved by bringing a layer containing an additive element into contact with the secondary phase. [Table 1]

[0073] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0074] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 17 Main phase 18 Secondary phase 19 Layer containing additional elements 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. The laminated chip is provided with dielectric layers and internal electrode layers having Ni as a main phase stacked alternately, the dielectric layer contains Si; the internal electrode layer adjacent to the dielectric layer includes a layer containing one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In; A ceramic electronic component characterized in that a concentration peak of Si exists within a range of 15 nm on the dielectric layer side in the thickness direction from the interface between the dielectric layer and the adjacent internal electrode layer, and a concentration peak of the additive element exists within a range of 15 nm on the internal electrode layer side.

2. 2. The ceramic electronic component according to claim 1, wherein the total amount of the additive elements relative to Ni in the internal electrode layers is 0.01 at % or more and 5 at % or less.

3. 3. The ceramic electronic component according to claim 1, wherein the layer containing the additional element is a single metal, an alloy, or an oxide of the additional element.

4. 4. The ceramic electronic component according to claim 1, wherein the dielectric layer has a thickness of 0.5 μm or less.

5. 5. The ceramic electronic component according to claim 1, wherein the internal electrode layers have a thickness of 0.05 μm or more and 0.4 μm or less.

6. 6. The ceramic electronic component according to claim 1, wherein the dielectric layer contains barium titanate.

7. SiO ２ forming an internal electrode pattern of a Ni paste containing one or more additive elements selected from Au, Pt, Cu, Fe, Cr, Zn, and In on a dielectric green sheet containing a sintering aid containing the compound (I), thereby forming a laminate unit; forming a laminate by stacking a plurality of the lamination units; and firing the laminate, a method for manufacturing a ceramic electronic component, characterized in that conditions for the firing step are adjusted so that a concentration peak of Si exists within a range of 15 nm on the dielectric layer side in a thickness direction from an interface between a dielectric layer obtained by firing the dielectric green sheet and an adjacent internal electrode layer obtained by firing the internal electrode pattern, and a concentration peak of the additive element exists within a range of 15 nm on the internal electrode layer side.

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