Control circuit, power supply circuit, and electronic device

Abstract

The loss in the power supply circuit is reduced while suppressing an increase in the starting voltage and an increase in the input voltage that enables an output voltage to be output as a set voltage. [Solution] A control circuit (CNT1) is configured to be used as part of a switched capacitor converter (11) having a plurality of switch elements (M1 to M4) and at least one capacitor (CFLY) and configured to generate a second voltage from a first voltage. The control circuit includes a mode switching circuit (MS1) configured to switch between a first mode and a second mode. The first mode is a mode in which switching control of the plurality of switch elements is stopped and the second voltage is set to a voltage with a value that can be considered the same as the first voltage. The second mode is a mode in which switching control of the plurality of switch elements is performed and the second voltage is set to a voltage with a value lower than the first voltage.

Description

[Technical Field]

[0001] The present disclosure relates to a control circuit, a power supply circuit, and an electronic device. [Background technology]

[0002] BACKGROUND ART Linear power supply circuits have been widely known in the past (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-112963

[0004] [overview] In recent years, power supply circuits have become increasingly powerful, and there are an increasing number of cases where power loss in power supply circuits becomes a problem.

[0005] The loss in a linear power supply circuit can be calculated by multiplying the difference between the input voltage and the output voltage by the output current. Losses in a linear power supply circuit cause heat generation.

[0006] The control circuit disclosed herein is configured to be used as part of a switched-capacitor converter including a plurality of switch elements and at least one capacitor, and configured to generate a second voltage from a first voltage. The control circuit includes a mode switching circuit configured to switch between a first mode and a second mode. The first mode is a mode in which switching control of the plurality of switch elements is stopped and the second voltage is set to a voltage with a value that can be considered the same as the first voltage. The second mode is a mode in which switching control of the plurality of switch elements is performed and the second voltage is set to a voltage with a value lower than the first voltage.

[0007] The power supply circuit disclosed in this specification comprises a switched capacitor converter having the control circuit configured as described above, the plurality of switch elements, and the at least one capacitor, and a linear power supply circuit configured to generate a third voltage from the second voltage.

[0008] The electronic device disclosed in this specification includes a power supply circuit having the above configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a power supply circuit according to a first comparative example. [Figure 2] FIG. 2 is a perspective view of the appearance of the semiconductor integrated circuit device. [Figure 3] FIG. 3 is a diagram showing the relationship between input voltage and loss. [Figure 4] FIG. 4 shows the relationship between the input voltage and the output voltage when the linear power supply circuit is used alone. [Figure 5] FIG. 5 is a diagram showing the relationship between the input voltage, the intermediate voltage, and the output voltage in the power supply circuit according to the first comparative example. [Figure 6] FIG. 6 is a diagram showing the configuration of a power supply circuit according to a second comparative example. [Figure 7] FIG. 7 is a diagram showing the configuration of the power supply circuit according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing the state of a MOS transistor serving as a switch element. [Figure 9] FIG. 9 is a diagram showing the state of a MOS transistor serving as a switch element. [Figure 10] FIG. 10 is a diagram showing a first modified example of the mode switching circuit. [Figure 11] FIG. 11 is a diagram showing a second modified example of the mode switching circuit. [Figure 12] FIG. 12 is a diagram showing a third modified example of the mode switching circuit. [Figure 13] FIG. 13 is a diagram showing a fourth modified example of the mode switching circuit. [Figure 14] FIG. 14 is a diagram showing the relationship between the input voltage, the intermediate voltage, and the output voltage in the power supply circuit according to the first embodiment. [Figure 15] FIG. 15 is a diagram showing the relationship between the input voltage and the loss in the power supply circuit according to the first embodiment. [Figure 16] FIG. 16 is a diagram showing the configuration of a power supply circuit according to the second embodiment. [Figure 17] FIG. 17 is a diagram showing the relationship between the input voltage, the intermediate voltage, and the output voltage in the power supply circuit according to the second embodiment. [Figure 18] FIG. 18 is a diagram showing the configuration of a power supply circuit according to the third embodiment. [Figure 19] FIG. 19 is a diagram showing the configuration of a power supply circuit according to the fourth embodiment. [Figure 20] FIG. 20 is a diagram showing the load regulation characteristics of an intermediate voltage. [Figure 21] FIG. 21 is a diagram showing the relationship between the input voltage, the intermediate voltage, and the output voltage in the power supply circuit according to the fourth embodiment. [Figure 22] FIG. 22 is a diagram showing the configuration of a power supply circuit according to the fifth embodiment. [Figure 23] FIG. 23 is a diagram showing the configuration of a power supply circuit according to the sixth embodiment. [Figure 24] FIG. 24 is a diagram showing the time transition of the input voltage, intermediate voltage, and output voltage. [Figure 25] FIG. 25 is a diagram showing the configuration of a power supply circuit according to the seventh embodiment. [Figure 26] FIG. 26 is a diagram showing a first configuration example of the power supply circuit according to the eighth embodiment. [Figure 27] FIG. 27 is a diagram showing a second configuration example of the power supply circuit according to the eighth embodiment. [Figure 28] FIG. 28 is a diagram showing a third configuration example of the power supply circuit according to the eighth embodiment. [Figure 29] FIG. 29 is a perspective view of the exterior of the vehicle. [Figure 30] FIG. 30 is a diagram showing a first modified example of a switched capacitor converter. [Figure 31] FIG. 31 is a diagram showing a second modified example of the switched capacitor converter.

[0010] [Detailed explanation] In this specification, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, a P-channel MOSFET will be referred to as a PMOS transistor, and an N-channel MOSFET will be referred to as an NMOS transistor.

[0011] In this specification, a constant voltage means a voltage that is constant under ideal conditions, but in reality it is a voltage that may fluctuate slightly due to temperature changes, etc. In this specification, constant voltages with different signs each mean a constant voltage of a different value.

[0012] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0013] <First Comparative Example> Fig. 1 is a diagram showing the configuration of a power supply circuit according to a first comparative example. The power supply circuit 100A shown in Fig. 1 includes a switched capacitor converter 10A and a linear power supply circuit 20. The linear power supply circuit 20 is provided in a subsequent stage of the switched capacitor converter 10A.

[0014] The switched-capacitor converter 10A is configured to generate an intermediate voltage VMID from an input voltage VIN. The linear power supply circuit 20 is configured to generate an output voltage VOUT from the intermediate voltage VMID.

[0015] The switched capacitor converter 10A includes a switching control circuit SC1, signal processing circuits SP1 to SP4, PMOS transistors M1 and M2 each functioning as a switch element, NMOS transistors M3 and M4 each functioning as a switch element, an input capacitor CIN, a flying capacitor CFLY, and an intermediate capacitor CMID.

[0016] The input voltage VIN is applied to a first terminal of the input capacitor CIN and the source of the PMOS transistor M1. The second terminal of the input capacitor CIN is connected to the ground potential. The input voltage VIN is smoothed by the input capacitor CIN. The drain of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and the first terminal of the flying capacitor CFLY. The drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M3, the first terminal of the intermediate capacitor CMID, and the source of the PMOS transistor Q1 (described later). The source of the NMOS transistor M3 is connected to the drain of the NMOS transistor M4 and the second terminal of the flying capacitor CFLY. The source of the NMOS transistor M4 and the second terminal of the intermediate capacitor CMID are connected to the ground potential.

[0017] The switching control circuit SC1 generates control signals S1 to S4. The switching control circuit SC1 outputs a HIGH level control signal S1 when turning on the PMOS transistor M1, and outputs a LOW level control signal S1 when turning off the PMOS transistor M1. The switching control circuit SC1 outputs a HIGH level control signal S2 when turning on the PMOS transistor M2, and outputs a LOW level control signal S2 when turning off the PMOS transistor M2. The switching control circuit SC1 outputs a HIGH level control signal S3 when turning on the NMOS transistor M3, and outputs a LOW level control signal S3 when turning off the NMOS transistor M3. The switching control circuit SC1 outputs a HIGH level control signal S4 when turning on the NMOS transistor M4, and outputs a LOW level control signal S4 when turning off the NMOS transistor M4.

[0018] Each of the signal processing circuits SP1 to SP4 includes a level shifter and a driver. The signal processing circuit SP1 level-shifts, logically inverts, and power-amplifies the control signal S1 to generate a gate signal G1 and supplies it to the gate of the PMOS transistor M1. The signal processing circuit SP2 level-shifts, logically inverts, and power-amplifies the control signal S2 to generate a gate signal G2 and supply it to the gate of the PMOS transistor M2. The signal processing circuit SP3 level-shifts and power-amplifies the control signal S3 to generate a gate signal G3 and supply it to the gate of the NMOS transistor M3. The signal processing circuit SP4 level-shifts and power-amplifies the control signal S4 to generate a gate signal G4 and supply it to the gate of the NMOS transistor M4.

[0019] The first state and the second state are repeated by the switching control of the switching control circuit SC1, and an intermediate voltage VMID that is half the input voltage VIN is generated.

[0020] In the first state, the PMOS transistor M1 and the NMOS transistor M3 are turned on, and the PMOS transistor M2 and the NMOS transistor M4 are turned off, so that the flying capacitor CFLY and the intermediate capacitor CMID are connected in series.

[0021] In the second state, the PMOS transistor M1 and the NMOS transistor M3 are turned off, and the PMOS transistor M2 and the NMOS transistor M4 are turned on, thereby connecting the flying capacitor CFLY and the intermediate capacitor CMID in parallel.

[0022] The linear power supply circuit 20 includes a PMOS transistor Q1 that functions as a variable resistor, an output capacitor COUT, resistors R1 and R2, a reference voltage source REF1, and an error amplifier AMP1.

[0023] The intermediate voltage VMID output from the switched capacitor converter 10A is applied to the source of the PMOS transistor Q1. The drain of the PMOS transistor Q1 is connected to a first terminal of a resistor R1, a first terminal of an output capacitor COUT, and a first terminal of a load LD. The second terminal of the resistor R1 is connected to a first terminal of a resistor R2 and a non-inverting input terminal of an error amplifier AMP1. The positive terminal of a reference voltage source REF1 is connected to an inverting input terminal of the error amplifier AMP1. The output terminal of the error amplifier AMP1 is connected to the gate of the PMOS transistor Q1. The second terminal of the output capacitor COUT, the second terminal of the resistor R2, the negative terminal of the reference voltage source REF1, and the second terminal of the load LD are connected to ground potential.

[0024] The output voltage VOUT, which is the drain voltage of the PMOS transistor Q1, is a voltage dropped from the intermediate voltage VMID by the source-drain voltage of the PMOS transistor Q1. The output voltage VOUT is smoothed by the output capacitor COUT.

[0025] A voltage divider circuit formed by resistors R1 and R2 generates a divided voltage of the output voltage VOUT and supplies it to the non-inverting input terminal of the error amplifier AMP1.

[0026] The error amplifier AMP1 generates an error signal according to the error between the divided voltage of the output voltage VOUT and the reference voltage output from the reference voltage source REF1, and supplies the error signal to the gate of the PMOS transistor Q1.

[0027] An output voltage VOUT output from the linear power supply circuit 20 is applied to a first terminal of the load LD.

[0028] The PMOS transistors M1 and M2, the NMOS transistors M3 and M4, the switching control circuit SC1, the signal processing circuits SP1 to SP4, the PMOS transistor Q1, the resistors R1 and R2, the reference voltage source REF1, and the error amplifier AMP1 are mounted on, for example, a semiconductor integrated circuit device IC1 shown in FIG. 2.

[0029] The input capacitor CIN, the flying capacitor CFLY, the intermediate capacitor CMID, and the output capacitor COUT are external components of the semiconductor integrated circuit device IC1.

[0030] The semiconductor integrated circuit device IC1 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the semiconductor integrated circuit device IC1 from the housing. The semiconductor integrated circuit device IC1 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the semiconductor integrated circuit device IC1 and the type of housing for the semiconductor integrated circuit device IC1 shown in FIG. 2 are merely examples, and can be designed as desired.

[0031] FIG. 3 shows the relationship between input voltage V and losses when current IOUT flowing through load LD1 is fixed. Characteristic line T1 shows the relationship between input voltage V and losses when linear power supply circuit 20 is used alone. When linear power supply circuit 20 is used alone, input voltage V is applied to the source of PMOS transistor Q1. Characteristic line T2 shows the relationship between input voltage V and losses in power supply circuit 100A. Because intermediate voltage VMID supplied to linear power supply circuit 20 of power supply circuit 100A is half of input voltage V, losses in power supply circuit 100A can be reduced to roughly half of the losses when linear power supply circuit 20 is used alone.

[0032] However, in power supply circuit 100A, intermediate voltage VMID supplied to linear power supply circuit 20 of power supply circuit 100A is half of input voltage VIN, so compared to when linear power supply circuit 20 is used alone, the input voltage at which the circuit can operate, i.e., starting voltage Vopr, and the input voltage Vmin at which the set output voltage VOUT can be output, each need to be twice as large (see Figures 4 and 5). Note that Figure 4 shows the relationship between input voltage VIN and output voltage YOUT when linear power supply circuit 20 is used alone. Also, Figure 5 shows the relationship between input voltage VIN and intermediate voltage VMID and output voltage VOUT in power supply circuit 100A.

[0033] <Second Comparative Example> Fig. 6 is a diagram showing the configuration of a power supply circuit according to a second comparative example. In Fig. 6, the same components as those in Fig. 1 are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0034] The power supply circuit 100B shown in FIG. 6 has a configuration in which the switched capacitor converter 10A in the power supply circuit 100A shown in FIG. 1 is replaced with a DC / DC converter 10B.

[0035] The DC / DC converter 10B is configured to generate an intermediate voltage VMID from an input voltage VIN.

[0036] The DC / DC converter 10B includes a switching control circuit SC2, signal processing circuits SP5 and SP6, a PMOS transistor M5 that functions as a switch element, an NMOS transistor M6 that functions as a switch element, an input capacitor CIN, a coil L1, and an intermediate capacitor CMID.

[0037] The input voltage VIN is applied to a first end of the input capacitor CIN and the source of the PMOS transistor M5. The second end of the input capacitor CIN is connected to the ground potential. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M6 and a first end of the coil. The second end of the coil is connected to a first end of the intermediate capacitor CMID and the source of the PMOS transistor Q1. The source of the NMOS transistor M2 and the second end of the intermediate capacitor CMID are connected to the ground potential.

[0038] The switching control circuit SC2 generates control signals S5 and S6. The switching control circuit SC2 outputs a high-level control signal S1 when turning on the PMOS transistor M5, and outputs a low-level control signal S1 when turning off the PMOS transistor M5. The switching control circuit SC2 outputs a high-level control signal S6 when turning on the NMOS transistor M6, and outputs a low-level control signal S6 when turning off the NMOS transistor M6.

[0039] The signal processing circuits SP5 and SP6 each include a level shifter and a driver. The signal processing circuit SP5 level-shifts, logically inverts, and power-amplifies the control signal S5 to generate a gate signal G5 and supplies it to the gate of the PMOS transistor M5. The signal processing circuit SP6 level-shifts and power-amplifies the control signal S6 to generate a gate signal G6 and supply it to the gate of the NMOS transistor M6.

[0040] The PMOS transistor M5 and the NMOS transistor M6 are turned on / off complementarily by the switching control of the switching control circuit SC1. When the on-duty of each of the control signals S5 and S6 is 50%, an intermediate voltage VMID that is 1 / 2 of the input voltage VIN is generated.

[0041] The PMOS transistor M5, NMOS transistor M6, switching control circuit SC2, signal processing circuits SP5 and SP6, PMOS transistor Q1, resistors R1 and R2, reference voltage source REF1, and error amplifier AMP1 are mounted on a semiconductor integrated circuit device.

[0042] The input capacitor CIN, the coil L1, the intermediate capacitor CMID, and the output capacitor COUT are external components of the semiconductor integrated circuit device.

[0043] Although the power supply circuit 100B has fewer switch elements than the power supply circuit 100A, the inclusion of the coil L1 makes it inferior to the power supply circuit 100A in terms of space saving and cost reduction. The switch elements do not require a high on-resistance, can be made small, and can be built into a semiconductor integrated circuit device. Therefore, the disadvantage of the power supply circuit 100B, which requires the coil L1, outweighs the advantage of being able to reduce the number of switch elements.

[0044] First Embodiment Fig. 7 is a diagram showing the configuration of the power supply circuit according to the first embodiment. In Fig. 7, the same parts as in Fig. 1 are given the same reference numerals, and detailed explanations will be omitted.

[0045] 7 has a configuration in which the switched capacitor converter 10A in the power supply circuit 100A shown in FIG. 1 is replaced with a switched capacitor converter 11. That is, the power supply circuit 101 includes the switched capacitor converter 11 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 11.

[0046] The switched capacitor converter 11 has a configuration in which the switching control circuit SC1 in the switched capacitor converter 10A shown in Fig. 1 is replaced with a control circuit CNT1. Note that the switched capacitor converter 11 may not be provided with an input capacitor CIN.

[0047] The PMOS transistors M1 and M2, NMOS transistors M3 and M4, control circuit CNT1, signal processing circuits SP1-SP4, PMOS transistor Q1, resistors R1 and R2, reference voltage source REF1, and error amplifier AMP1 are mounted, for example, on a semiconductor integrated circuit device IC1 shown in FIG. 2. The power supply circuit 101 does not necessarily have to include a single semiconductor integrated circuit device. For example, a first semiconductor integrated circuit device including the PMOS transistors M1 and M2, NMOS transistors M3 and M4, control circuit CNT1, and signal processing circuits SP1-SP4, and a second semiconductor integrated circuit device including the PMOS transistor Q1, resistors R1 and R2, reference voltage source REF1, and error amplifier AMP1 may be provided. Furthermore, for example, the semiconductor integrated circuit device including the control circuit CNT1 does not necessarily have to include the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4.

[0048] The control circuit CNT1 includes a mode switching circuit MS1 and a switching control circuit SC3.

[0049] The mode switching circuit MS1 is configured to switch between a pass-through mode and an SCC (Switched Capacitor Converter) mode. The pass-through mode is a mode in which switching control of the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4 is stopped, and the intermediate voltage VMID is set to a voltage value that can be regarded as the same as the input voltage VIN. The SCC mode is a mode in which switching control of the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4 is performed, and the intermediate voltage VMID is set to a value lower than the input voltage VIN (1 / 2 of the input voltage VIN in this embodiment).

[0050] The mode switching circuit MS1 includes a constant voltage source VS1 and a comparator COMP1.

[0051] The comparator COMP1 outputs a HIGH level comparison result signal if the input voltage VIN is equal to or lower than the constant voltage V1 output from the constant voltage source VS1. When the switching control circuit SC3 receives a HIGH level comparison result signal, it enters the pass-through mode.

[0052] If the input voltage VIN is greater than the constant voltage V1 output from the constant voltage source VS1, the comparator COMP1 outputs a LOW level comparison result signal. When the switching control circuit SC3 receives a LOW level comparison result signal, it enters the SCC mode.

[0053] In the pass-through mode, the switching control circuit SC3 fixes the PMOS transistor M1 on, fixes the PMOS transistor M2 on, fixes the NMOS transistor M3 off, and fixes the NMOS transistor M4 either on or off, as shown in Fig. 8. When the NMOS transistor M4 is fixed on, the flying capacitor CFLY functions as a capacitor that stabilizes the input voltage VIN.

[0054] In the SCC mode, the switching control circuit SC3 controls the switching of the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4, as shown in Fig. 8. This generates an intermediate voltage VMID that is half the input voltage VIN. More specifically, the switching control of the switching control circuit SC3 repeatedly switches between the first state ST1 and the second state ST2, generating the intermediate voltage VMID that is half the input voltage VIN.

[0055] 9, in the first state ST1, the PMOS transistor M1 and the NMOS transistor M3 are turned on, and the PMOS transistor M2 and the NMOS transistor M4 are turned off, thereby connecting the flying capacitor CFLY and the intermediate capacitor CMID in series.

[0056] 9, in the second state ST2, the PMOS transistor M1 and the NMOS transistor M3 are turned off, and the PMOS transistor M2 and the NMOS transistor M4 are turned on, thereby connecting the flying capacitor CFLY and the intermediate capacitor CMID in parallel.

[0057] The comparator COMP1 of the mode switching circuit MS1 may be configured not to directly detect the input voltage VIN, that is, the comparator COMP1 of the mode switching circuit MS1 may be configured to indirectly detect the input voltage VIN by detecting a voltage that depends on the input voltage VIN.

[0058] 10 to 13 show examples of the mode switching circuit MS1 when the comparator COMP1 is configured to indirectly detect the input voltage VIN. Note that the configuration of the mode switching circuit MS1 when the comparator COMP1 is configured to indirectly detect the input voltage VIN is not limited to the examples of FIGS. 10 to 13.

[0059] The mode switching circuit MS1 shown in FIG. 10 includes resistors R3 and R4, a constant voltage source VS1A that outputs a constant voltage VS1A, and a comparator COMP1.

[0060] The mode switching circuit MS1 shown in FIG. 11 includes an NMOS transistor Q2 having a gate to which a constant voltage VCLAMP is applied, resistors R3 and R4, a constant voltage source VS1B that outputs a constant voltage VS1B, and a comparator COMP1.

[0061] The mode switching circuit MS1 shown in FIG. 12 includes an NMOS transistor Q2 having a gate to which a constant voltage VCLAMP is applied, a constant current source CS1 that outputs a constant current, a constant voltage source VS1C that outputs a constant voltage VS1C, and a comparator COMP1.

[0062] The mode switching circuit MS1 shown in FIG. 13 includes resistors R3 and R4, an error amplifier AMP2, a PMOS transistor Q3, a resistor R5, a constant voltage source VS1D that outputs a constant voltage VS1D, and a comparator COMP1.

[0063] 14 is a diagram showing the relationship between the input voltage VIN and the intermediate voltage VMID and output voltage VOUT in the power supply circuit 101. When the input voltage VIN is equal to or lower than the constant voltage V1, the power supply circuit 101 enters pass-through mode, and the intermediate voltage VMID becomes a voltage that can be considered to be the same as the input voltage VIN. As a result, the power supply circuit 101 can suppress an increase in the starting voltage Vopr and an increase in the input voltage Vmin that allows the output voltage VOUT to be output at the set voltage.

[0064] FIG. 15 shows the relationship between input voltage V and loss in power supply circuit 101. Characteristic line T1 shows the relationship between input voltage V and loss when linear power supply circuit 20 is used alone. When linear power supply circuit 20 is used alone, input voltage V is applied to the source of PMOS transistor Q1. Characteristic line T2 shows the relationship between input voltage V and loss in power supply circuit 100A shown in FIG. 1. Characteristic line T3 shows the relationship between input voltage V and loss in power supply circuit 101.

[0065] When the input voltage V is greater than the constant voltage V, the power supply circuit 101 enters the SCC mode, and the intermediate voltage VM is half the input voltage V. As a result, in the SCC mode, the loss in the power supply circuit 101 can be reduced to roughly half of the loss when the linear power supply circuit 20 is used alone.

[0066] As is clear from Figures 14 and 15, if the value of constant voltage V1 is set appropriately, power supply circuit 101 can perform the same power reduction operation as when linear power supply circuit 20 is used alone, and can suppress the maximum loss to the same level as power supply circuit 100A shown in Figure 1.

[0067] Second Embodiment Fig. 16 is a diagram showing the configuration of a power supply circuit according to the second embodiment. In Fig. 16, the same parts as in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0068] 16 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in Fig. 7 is replaced with a switched capacitor converter 12. In other words, the power supply circuit 102 includes the switched capacitor converter 12 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 12.

[0069] The switched capacitor converter 12 has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in Fig. 7 is replaced with a control circuit CNT2. The control circuit CNT2 has a configuration in which the mode switching circuit MS1 in the control circuit CNT1 shown in Fig. 7 is replaced with a mode switching circuit MS2.

[0070] The mode switching circuit MS2 includes a constant voltage source VS1 and a comparator COMP2 having a hysteresis function.

[0071] When the input voltage VIN changes from less than or equal to the constant voltage V1 to greater than the constant voltage V1, the comparator COMP2 switches the level of the comparison result signal from LOW to HIGH.

[0072] When the input voltage VIN drops from a state greater than the constant voltage (V1-α) to a state less than the constant voltage (V1-α), the comparator COMP2 switches the level of the comparison result signal from HIGH to LOW. Note that the constant voltage (V1-α) is lower than the constant voltage V1.

[0073] FIG. 17 is a diagram showing the relationship between the input voltage VIN and the intermediate voltage VMID and output voltage VOUT in the power supply circuit 102.

[0074] When switching between pass-through mode and SCC mode, there is a risk of noise being generated in constant voltage source VS1 due to the influence of fluctuations in input voltage VIN and intermediate voltage VMID. To prevent unnecessary switching between pass-through mode and SCC mode due to the adverse influence of this noise, it is preferable to provide hysteresis for switching between pass-through mode and SCC mode, as in this embodiment.

[0075] <Third embodiment> Fig. 18 is a diagram showing the configuration of a power supply circuit according to embodiment 3. In Fig. 18, the same components as those in Fig. 16 are given the same reference numerals, and detailed description thereof will be omitted.

[0076] 18 has a configuration in which the switched capacitor converter 12 in the power supply circuit 102 shown in FIG. 16 is replaced with a switched capacitor converter 13. That is, the power supply circuit 103 includes the switched capacitor converter 13 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 13.

[0077] The switched capacitor converter 13 has a configuration in which the control circuit CNT2 in the switched capacitor converter 12 shown in Fig. 16 is replaced with a control circuit CNT3. The control circuit CNT3 has a configuration in which the mode switching circuit MS2 in the control circuit CNT2 shown in Fig. 16 is replaced with a mode switching circuit MS3.

[0078] The mode switching circuit MS3 is configured to provide a delay in mode switching, and includes a constant voltage source VS1, a comparator COMP2 having a hysteresis function, and a delay circuit DLY1.

[0079] The delay circuit DLY1 delays the comparison result signal output from the comparator COMP2 and supplies the delayed signal to the switching control circuit SC3.

[0080] In the power supply circuit 103, a delay is provided in the mode switching, thereby preventing unnecessary switching between the pass-through mode and the SCC mode due to the adverse effects of noise.

[0081] In this embodiment, the delay circuit DLY1 is provided downstream of the comparator COMP2 having a hysteresis function, but the signal transmission time of the comparison result signal may be controlled within the switching control circuit SC3 without providing the delay circuit DLY1.

[0082] Moreover, instead of the comparator COMP2 having a hysteresis function, a comparator without a hysteresis function may be used.

[0083] In addition, a delay may be provided for both mode switching from pass-through mode to SCC mode and mode switching from SCC mode to pass-through mode, or a delay may be provided for only one of mode switching from pass-through mode to SCC mode and mode switching from SCC mode to pass-through mode.

[0084] <Fourth embodiment> Fig. 19 is a diagram showing the configuration of a power supply circuit according to embodiment 4. In Fig. 19, the same components as those in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0085] 19 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in FIG. 7 is replaced with a switched capacitor converter 14. That is, the power supply circuit 104 includes the switched capacitor converter 14 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 14.

[0086] The switched capacitor converter 14 has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in FIG. 7 is replaced with a control circuit CNT4.

[0087] The control circuit CNT4 includes a mode switching circuit MS4 and a switching control circuit SC4.

[0088] The mode switching circuit MS4 is configured to switch from the pass-through mode to the SCC mode and from the SCC mode to the pass-through mode in response to different voltages. More specifically, the mode switching circuit MS4 is configured to switch from the pass-through mode to the SCC mode in response to the input voltage VIN and to switch from the SCC mode to the pass-through mode in response to the intermediate voltage VMID.

[0089] The mode switching circuit MS4 includes constant voltage sources VS1 and VS2, and comparators COMP1 and COMP3.

[0090] Comparator COMP1 outputs a HIGH level comparison result signal if the input voltage VIN is equal to or less than the constant voltage V1 output from constant voltage source VS1, and outputs a LOW level comparison result signal if the input voltage VIN is greater than the constant voltage V1 output from constant voltage source VS1.

[0091] Comparator COMP3 outputs a HIGH level comparison result signal if intermediate voltage VMID is equal to or less than the constant voltage V2 output from constant voltage source VS2, and outputs a LOW level comparison result signal if intermediate voltage VMID is greater than the constant voltage V2 output from constant voltage source VS2.

[0092] The switching control circuit SC4 controls the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4 so as to switch from the pass-through mode to the SCC mode when the level of the comparison result signal output from the comparator COMP1 switches from HIGH to LOW.

[0093] The switching control circuit SC4 controls the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4 so as to switch from the SCC mode to the pass-through mode when the level of the comparison result signal output from the comparator COMP3 switches from the LOW level to the HIGH level.

[0094] In switched capacitor converter 14, when intermediate voltage VMIN has the load regulation characteristics shown in FIG. 20, intermediate voltage VMIN decreases in response to an increase in current IOUT flowing through load LD1 even if input voltage VIN does not change.

[0095] Therefore, if switching from SCC mode to pass-through mode is also performed in response to input voltage VIN, the constant voltage V1 will be set relatively high, taking into account the drop in intermediate voltage VMIN due to the load regulation characteristics. On the other hand, if switching from SCC mode to pass-through mode is performed in response to intermediate voltage VMID, as in this embodiment, switching from SCC mode to pass-through mode becomes possible at the intermediate voltage VMID that is optimal for linear power supply circuit 20, as shown in Figure 21. As a result, when intermediate voltage VMIN is given the load regulation characteristics shown in Figure 20, power supply circuit 103 can achieve lower loss than power supply circuit 101.

[0096] In this embodiment, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, in this embodiment, a comparator having a hysteresis function may be used instead of the comparator COMP3. Also, a delay may be provided for each comparison result signal.

[0097] Fifth Embodiment Fig. 22 is a diagram showing the configuration of a power supply circuit according to embodiment 5. In Fig. 22, the same parts as in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0098] 22 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in FIG. 7 is replaced with a switched capacitor converter 15. That is, the power supply circuit 105 includes the switched capacitor converter 15 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 15.

[0099] The switched capacitor converter 15 has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in FIG. 7 is replaced with a control circuit CNT5.

[0100] The control circuit CNT5 has a configuration in which the mode switching circuit MS1 in the control circuit CNT1 shown in FIG. 7 is replaced with a mode switching circuit MS5.

[0101] The mode switching circuit MS5 has a configuration in which the constant voltage source VS1 in the mode switching circuit MS1 shown in FIG. 7 is replaced with a variable voltage source VVS1.

[0102] The variable voltage source VVS1 adjusts the value of the variable voltage VV1 in accordance with information about the current IOUT detected by the current detection sensor SNS1, and supplies the variable voltage VV1 to the non-inverting input terminal of the comparator COMP1. This allows the power supply circuit 105 to achieve the same effects as the power supply circuit 104.

[0103] In the configuration shown in FIG. 22, the current detection sensor SNS1 is provided on the input side of the linear power supply circuit 20, but it may also be provided on the output side of the linear power supply circuit 20 or the output side of the switched capacitor converter 15.

[0104] The current detection sensor SNS1 includes a mirror PMOS transistor that forms a current mirror circuit in combination with a PMOS transistor Q1. The size of the mirror PMOS transistor is made smaller than the size of the PMOS transistor Q1, and the mirror current flowing through the mirror PMOS transistor is made smaller than the current IOUT flowing through the load LD1.

[0105] Furthermore, unlike this embodiment, instead of adjusting the value of the variable voltage VV1 in accordance with the information on the current IOUT detected by the current detection sensor SNS1, the input voltage VIN may be converted at a conversion ratio in accordance with the information on the current IOUT detected by the current detection sensor SNS1 and supplied to the inverting input terminal of the comparator COMP1.

[0106] In this embodiment, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, a delay may be provided for the comparison result signal.

[0107] Sixth Embodiment Fig. 23 is a diagram showing the configuration of a power supply circuit according to embodiment 6. In Fig. 23, the same parts as in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0108] 23 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in FIG. 7 is replaced with a switched capacitor converter 16. That is, the power supply circuit 106 includes the switched capacitor converter 16 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 16.

[0109] The switched capacitor converter 16 has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in FIG. 7 is replaced with a control circuit CNT6.

[0110] The control circuit CNT6 has a configuration in which the mode switching circuit MS1 in the control circuit CNT1 shown in FIG. 7 is replaced with a mode switching circuit MS6.

[0111] The mode switching circuit MS6 has a configuration in which a switch SW1, a constant voltage source VS1', a comparator COMP4, and a constant voltage source VS3 are added to the mode switching circuit MS1 shown in FIG.

[0112] The mode switching circuit MS6 adjusts the value of the constant voltage supplied to the non-inverting input terminal of the comparator COMP1 in accordance with the output voltage VOUT. Specifically, when the comparator COMP4 determines that the output voltage VOUT is lower than the constant voltage V3 output from the constant voltage source VS3, the switch SW1 selects the constant voltage V1' output from the constant voltage source VS1' and supplies it to the non-inverting input terminal of the comparator COMP1. The constant voltage V1' is lower than the constant voltage V1. On the other hand, when the comparator COMP4 determines that the output voltage VOUT is not lower than the constant voltage V3 output from the constant voltage source VS3, the switch SW1 selects the constant voltage V1 output from the constant voltage source VS1 and supplies it to the non-inverting input terminal of the comparator COMP1.

[0113] This widens the range in which the power supply circuit 106 operates in SCC mode when the output voltage VOUT is low, for example, during startup or when the output is short-circuited as shown in FIG. 24, thereby enabling the power supply circuit 106 to reduce losses when the output voltage VOUT is low.

[0114] In this embodiment, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, a delay may be provided for the comparison result signal.

[0115] Seventh Embodiment Fig. 25 is a diagram showing the configuration of a power supply circuit according to embodiment 7. In Fig. 25, the same components as those in Fig. 19 are given the same reference numerals, and detailed description thereof will be omitted.

[0116] 25 has a configuration in which the switched capacitor converter 14 in the power supply circuit 104 shown in FIG. 19 is replaced with a switched capacitor converter 17. That is, the power supply circuit 107 includes the switched capacitor converter 17 and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 17.

[0117] The switched capacitor converter 17 has a configuration in which the control circuit CNT4 in the switched capacitor converter 14 shown in FIG. 19 is replaced with a control circuit CNT7.

[0118] The control circuit CNT7 has a configuration in which the mode switching circuit MS4 in the control circuit CNT4 shown in FIG. 19 is replaced with a mode switching circuit MS7.

[0119] The mode switching circuit MS7 has a configuration in which a switch SW1, a constant voltage source VS1', a switch SW2, a constant voltage source VS2', a comparator COMP4, and a constant voltage source VS3 are added to the mode switching circuit MS4 shown in FIG.

[0120] The power supply circuit 107 is configured by combining the power supply circuit 104 according to the fourth embodiment shown in FIG. 19 and the power supply circuit 106 according to the sixth embodiment shown in FIG.

[0121] In the power supply circuit 107, both the value of the constant voltage supplied to the non-inverting input terminal of the comparator COMP1 and the value of the constant voltage supplied to the non-inverting input terminal of the comparator COMP1 are adjusted in accordance with the output voltage VOUT, but only one of the value of the constant voltage supplied to the non-inverting input terminal of the comparator COMP1 and the value of the constant voltage supplied to the non-inverting input terminal of the comparator COMP1 may be adjusted in accordance with the output voltage VOUT.

[0122] In this embodiment, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, a comparator having a hysteresis function may be used instead of the comparator COMP2. Also, a delay may be provided for each comparison result signal.

[0123] Eighth Embodiment Fig. 26 is a diagram showing a first configuration example of a power supply circuit according to Embodiment 8. In Fig. 26, the same components as those in Fig. 19 are given the same reference numerals, and detailed description thereof will be omitted.

[0124] The power supply circuit 108A shown in Fig. 26 has a configuration in which the switched capacitor converter 14 in the power supply circuit 104 shown in Fig. 19 is replaced with a switched capacitor converter 18A. That is, the power supply circuit 108A includes the switched capacitor converter 18A and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 18A.

[0125] The switched capacitor converter 18A has a configuration in which the control circuit CNT4 in the switched capacitor converter 14 shown in FIG. 19 is replaced with a control circuit CNT8A.

[0126] The control circuit CNT8A has a configuration in which the mode switching circuit MS4 in the control circuit CNT4 shown in FIG. 19 is replaced with a mode switching circuit MS8A.

[0127] The mode switching circuit MS8A differs from the mode switching circuit MS4 shown in FIG. 19 in that the comparator COMP2 compares the intermediate voltage VMID with a voltage obtained by offsetting the output voltage VOUT by a constant voltage source VS4, but is otherwise similar to the mode switching circuit MS4 shown in FIG. 19.

[0128] The power supply circuit 108A shown in FIG. 26 has the same effects as the power supply circuit 104 according to the fourth embodiment shown in FIG.

[0129] Fig. 27 is a diagram showing a second configuration example of the power supply circuit according to the eighth embodiment. In Fig. 27, the same components as those in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0130] The power supply circuit 108B shown in Fig. 27 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in Fig. 7 is replaced with a switched capacitor converter 18B. That is, the power supply circuit 108B includes the switched capacitor converter 18B and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 18B.

[0131] The switched capacitor converter 18B has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in FIG. 7 is replaced with a control circuit CNT8B.

[0132] The control circuit CNT8B has a configuration in which the mode switching circuit MS1 in the control circuit CNT1 shown in FIG. 7 is replaced with a mode switching circuit MS8B.

[0133] The mode switching circuit MS8B differs from the mode switching circuit MS1 shown in FIG. 7 in that the comparator COMP1 compares the input voltage VIN with a voltage obtained by offsetting the output voltage VOUT by a constant voltage source VS5, but is otherwise similar to the mode switching circuit MS1 shown in FIG. 7.

[0134] The power supply circuit 108B shown in Fig. 27 has the same effect as the power supply circuit 104 according to the fourth embodiment shown in Fig. 19. Furthermore, the power supply circuit 108B shown in Fig. 27 has the same effect as the power supply circuit 105 according to the fifth embodiment shown in Fig. 22, because the determination threshold of the comparator COMP1 naturally decreases when the output voltage VOUT is low.

[0135] Fig. 28 is a diagram showing a third configuration example of the power supply circuit according to the eighth embodiment. In Fig. 28, the same components as those in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0136] The power supply circuit 108C shown in Fig. 28 has a configuration in which the switched capacitor converter 11 in the power supply circuit 101 shown in Fig. 7 is replaced with a switched capacitor converter 18C. That is, the power supply circuit 108C includes the switched capacitor converter 18C and a linear power supply circuit 20 provided in a subsequent stage of the switched capacitor converter 18C.

[0137] The switched capacitor converter 18C has a configuration in which the control circuit CNT1 in the switched capacitor converter 11 shown in FIG. 7 is replaced with a control circuit CNT8C.

[0138] The control circuit CNT8C has a configuration in which the mode switching circuit MS1 in the control circuit CNT1 shown in FIG. 7 is replaced with a mode switching circuit MS8C.

[0139] The mode switching circuit MS8B differs from the mode switching circuit MS1 shown in FIG. 7 in that the comparator COMP1 compares the intermediate voltage VMID with a voltage obtained by offsetting the output voltage VOUT by a constant voltage source VS6, but is otherwise similar to the mode switching circuit MS1 shown in FIG. 7.

[0140] The power supply circuit 108C shown in Fig. 28 has the same effect as the power supply circuit 104 according to the fourth embodiment shown in Fig. 19. Furthermore, the power supply circuit 108C shown in Fig. 28 has the same effect as the power supply circuit 105 according to the fifth embodiment shown in Fig. 22, because the determination threshold of the comparator COMP1 naturally decreases when the output voltage VOUT is low.

[0141] In the power supply circuit 108A, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, a comparator having a hysteresis function may be used instead of the comparator COMP3. Also, a delay may be provided for each comparison result signal.

[0142] In each of the power supply circuits 108B and 108C, a comparator having a hysteresis function may be used instead of the comparator COMP1. Also, a delay may be provided for each comparison result signal.

[0143] Furthermore, the power supply circuits 108A to 108C may be modified in the same manner as in, for example, FIGS.

[0144] <Application example> Each of the power supply circuits 101-107 and 108A-108C is built into an electronic device Y mounted on a vehicle X shown in Fig. 29. Note that the mounting position of the electronic device Y in Fig. 29 may differ from the actual position for convenience of illustration. Furthermore, each of the power supply circuits 101-107 and 108A-108C is not limited to use in the automotive field, and can be built into electronic devices used in any field (automotive field, industrial machinery field, home appliance field, etc.).

[0145] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0146] For example, unless inconsistent, the details described in any of the multiple embodiments can be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0147] For example, in each of the above embodiments, an NMOS transistor may be used instead of the PMOS transistor M1. When an NMOS transistor is used instead of the PMOS transistor M1, logic inversion in the signal processing circuit SP1 becomes unnecessary.

[0148] For example, in each of the above embodiments, an NMOS transistor may be used instead of the PMOS transistor M2. Note that when an NMOS transistor is used instead of the PMOS transistor M2, logic inversion in the signal processing circuit SP2 becomes unnecessary.

[0149] For example, in each of the above embodiments, a switching element other than a MOS transistor may be used as the switching element of the switched capacitor converter, such as a bipolar transistor.

[0150] For example, in each of the above embodiments, an NMOS transistor or a bipolar transistor may be used as the output transistor of the linear power supply circuit 20 instead of the PMOS transistor Q1.

[0151] The topology of the switched capacitor converter is not limited to the above embodiments. For example, the switched capacitor converter shown in FIG. 30, the switched capacitor converter shown in FIG. 31, etc. may be used. In the switched capacitor converter shown in FIG. 30 and the switched capacitor converter shown in FIG. 31, in the SCC mode, when the control signal Φ1 is a signal instructing on, the control signal Φ2 is a signal instructing off, and when the control signal Φ1 is a signal instructing off, the control signal Φ2 is a signal instructing on.

[0152] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0153] A control circuit (CNT1) of the present disclosure is a control circuit configured to be used as part of a switched capacitor converter (11) that includes a plurality of switch elements (M1 to M4) and at least one capacitor (CFLY) and is configured to generate a second voltage from a first voltage, and includes a mode switching circuit (MS1) configured to switch between a first mode and a second mode, wherein the first mode is a mode in which switching control of the plurality of switch elements is stopped and the second voltage is set to a voltage with a value that can be considered to be the same as the first voltage, and the second mode is a mode in which switching control of the plurality of switch elements is performed and the second voltage is set to a voltage with a value lower than the first voltage (first configuration).

[0154] The control circuit of the first configuration can set the switched capacitor converter in the first mode, and therefore can suppress an increase in the starting voltage and an increase in the input voltage that enables an output voltage equal to the set voltage in a power supply circuit that includes the switched capacitor converter and a linear power supply circuit provided downstream of the switched capacitor converter.

[0155] Furthermore, the control circuit of the first configuration can set the switched capacitor converter in the second mode, thereby reducing loss in a power supply circuit including the switched capacitor converter and a linear power supply circuit provided in a subsequent stage of the switched capacitor converter.

[0156] In the control circuit of the above first configuration, the mode switching circuit may be configured (second configuration) to switch from the first mode to the second mode when the first voltage changes from below a first threshold to above the first threshold.

[0157] In the control circuit of the second configuration, the mode switching circuit may be configured to adjust the first threshold value in accordance with the output current of the switched capacitor converter (third configuration).

[0158] In the control circuit of the second or third configuration, the mode switching circuit may be configured to switch from the second mode to the first mode when the first voltage goes from a state greater than a second threshold to a state less than the second threshold, and the second threshold may be configured to be smaller than the first threshold (fourth configuration).

[0159] In the control circuit of any of the above first to third configurations, the mode switching circuit may be configured to switch from the first mode to the second mode in response to the first voltage, and to switch from the second mode to the first mode in response to the second voltage (fifth configuration).

[0160] In the control circuit of the first configuration, the mode switching circuit may be configured to switch between the first mode and the second mode in accordance with the second voltage (sixth configuration).

[0161] In the control circuit of any one of the first to sixth configurations, the mode switching circuit may be configured to provide a delay in mode switching (seventh configuration).

[0162] The power supply circuit (101 to 107, 108A to 108C) of the present disclosure has a configuration (eighth configuration) including a switched capacitor converter (11 to 17, 18A to 18C) having a control circuit of any one of the first to seventh configurations, the plurality of switch elements, and the at least one capacitor, and a linear power supply circuit (20) configured to generate a third voltage from the second voltage.

[0163] In the power supply circuit of the eighth configuration, the switched capacitor converter may be provided with the control circuit of the second configuration, and the mode switching circuit (MS6, MS7) may be configured to adjust the first threshold value according to the third voltage (ninth configuration).

[0164] In the power supply circuit of the ninth configuration, the mode switching circuit (MS7) may be configured to switch from the second mode to the first mode depending on the magnitude relationship between the second voltage and a third threshold, and to adjust the third threshold depending on the third voltage (tenth configuration).

[0165] In the power supply circuit of the eighth configuration, the switched capacitor converter may be provided with a control circuit of the first configuration, and the mode switching circuit (MS8C) may be configured to switch between the first mode and the second mode depending on the magnitude relationship between the second voltage and the third voltage (eleventh configuration).

[0166] The electronic device (Y) of the present disclosure has a configuration (twelfth configuration) that includes a power supply circuit having any one of the eighth to eleventh configurations. [Explanation of symbols]

[0167] 10A, 11-15 Switched Capacitor Converter 10B DC / DC Converter 20 Linear power supply circuit 100A, 100B, 101 to 105 Power supply circuit AMP1, AMP2 Error amplifiers CIN Input capacitor CFLY Flying Capacitor CMID Intermediate Capacitor CNT1~CNT5 control circuit COMP1 to COMP4 comparators COUT Output capacitor DLY1 delay circuit IC1 Semiconductor integrated circuit device M1, M2, M5 PMOS transistors M3, M4, M6 NMOS transistors MS1 mode switching circuit LD load Q1, Q3 PMOS transistors Q2 NMOS transistor R1~R5 Resistors REF1 Reference voltage source SC1~SC4 Switching control circuit SNS1 Current Detection Sensor SP1~SP6 signal processing circuit SW1 and SW2 switches VS1~VS5, VS1', VS2', VS1A~VS1D constant voltage source X vehicle Y Electronic equipment

Claims

1. 1. A control circuit configured for use as part of a switched capacitor converter, the switched capacitor converter comprising a plurality of switch elements and at least one capacitor, and configured to generate a second voltage from a first voltage, the control circuit comprising: a mode switching circuit configured to switch between a first mode and a second mode; the first mode is a mode in which switching control of the plurality of switch elements is stopped and the second voltage is set to a voltage having a value that can be regarded as the same as the first voltage, The second mode is a mode in which the second voltage is set to a voltage lower than the first voltage by controlling switching of the plurality of switch elements.

2. The control circuit of claim 1 , wherein the mode-switching circuit is configured to switch from the first mode to the second mode when the first voltage changes from less than or equal to a first threshold to greater than the first threshold.

3. The control circuit of claim 2 , wherein the mode-switching circuit is configured to adjust the first threshold in response to an output current of the switched-capacitor converter.

4. 3. The control circuit of claim 2, wherein the mode switching circuit is configured to switch from the second mode to the first mode when the first voltage goes from greater than a second threshold to less than or equal to the second threshold, and the second threshold is less than the first threshold.

5. The control circuit of claim 1 , wherein the mode-switching circuit is configured to switch from the first mode to the second mode in response to the first voltage and to switch from the second mode to the first mode in response to the second voltage.

6. The control circuit of claim 1 , wherein the mode switching circuit is configured to switch between the first mode and the second mode in response to the second voltage.

7. The control circuit of claim 1 , wherein the mode-switching circuit is configured to provide a delay in mode switching.

8. a switched capacitor converter including the control circuit according to any one of claims 1 to 7, the plurality of switch elements, and the at least one capacitor; a linear power supply circuit configured to generate a third voltage from the second voltage; A power supply circuit comprising:

9. The switched capacitor converter comprises a control circuit according to claim 2, The power supply circuit of claim 8 , wherein the mode switching circuit is configured to adjust the first threshold value in response to the third voltage.

10. 10. The power supply circuit according to claim 9, wherein the mode switching circuit is configured to switch from the second mode to the first mode depending on a magnitude relationship between the second voltage and a third threshold, and to adjust the third threshold depending on the third voltage.

11. The switched capacitor converter comprises a control circuit according to claim 1 , 9. The power supply circuit according to claim 8, wherein the mode switching circuit is configured to switch between the first mode and the second mode depending on the magnitude relationship between the second voltage and the third voltage.

12. An electronic device comprising the power supply circuit according to claim 8.

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