Semiconductor memory device and method of manufacturing the same

Abstract

To provide a semiconductor memory device capable of suppressing degradation of reliability due to breakage and intrusion of water, and to provide a method of manufacturing the same.SOLUTION: A semiconductor memory device according to an embodiment includes a first region and a second region. The first region includes a memory cell array including a plurality of memory cells. The second region surrounds the periphery of the first region when viewed from the first direction. The second region includes a first substrate, an insulating layer stacked on the first substrate, a conductor extending in the first direction inside the insulating layer, and a covering layer in contact with the conductive portion. The conductor includes a first conductor in contact with the covering layer at a first end, and a second conductor in contact with a second end of the first conductor opposite to the first end in the first direction. The first conductor includes a first core and a first barrier metal film covering the first core. The second end of the first conductor is covered with the first barrier metal film.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art Devices each having a plurality of circuits or elements formed thereon are bonded together to fabricate a single semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-163970 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can suppress a decrease in reliability due to damage and water intrusion. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment has a first region and a second region. The first region has a memory cell array having a plurality of memory cells. The second region surrounds the periphery of the first region when viewed from a first direction. The second region includes a first substrate, an insulating layer stacked on the first substrate, a conductor extending in the first direction within the insulating layer, and a covering layer in contact with the conductive portion. The conductor includes a first conductor contacting the covering layer at a first end, and a second conductor contacting a second end of the first conductor on the opposite side of the first end in the first direction. The first conductor includes a first core and a first barrier metal film covering the first core. The second end of the first conductor is covered with the first barrier metal film. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Figure 3] 1 is a cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 4] FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment. [Figure 5] FIG. 2 is a cross-sectional view of a portion of the memory cell array according to the first embodiment. [Figure 6] FIG. 2 is a cross-sectional view of the vicinity of a columnar body of the memory cell array according to the first embodiment. [Figure 7] FIG. 4 is another cross-sectional view of the vicinity of the columnar body of the memory cell array according to the first embodiment. [Figure 8] FIG. 2 is a cross-sectional view of a characteristic portion of the semiconductor memory device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 18] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 19] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 20] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 21] FIG. 10 is a cross-sectional view of a characteristic portion of a semiconductor memory device according to a second embodiment. [Figure 22] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 23] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 24] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 25] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 26] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 27] 10A and 10B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The semiconductor memory device of the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions are assigned the same reference numerals. Duplicate descriptions of these components may be omitted. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. In this specification, "connection" is not limited to physical connection, but also includes electrical connection.

[0008] In this application, terms are defined as follows: "Parallel," "orthogonal," or "same" may include the cases of "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. That is, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected via another element interposed therebetween. "Overlapping" is not limited to the case where multiple elements are in contact with each other, but may also include the case where multiple elements are separated (the case where the projected images of multiple elements overlap when viewed from a certain direction).

[0009] The +X direction, −X direction, +Y direction, −Y direction, +Z direction, and −Z direction are defined as follows: The +X direction is the direction in which the word lines WL, which will be described later, extend. The −X direction is the opposite direction of the +X direction. When the +X direction and the −X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction that intersects (e.g., is perpendicular to) the X direction. The +Y direction is the direction in which the bit lines BL extend. The −Y direction is the opposite direction of the +Y direction. When the +Y direction and the −Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (e.g., is perpendicular to) the X direction and the Y direction. The +Z direction is the direction from the first substrate 21, which will be described later, toward the memory cell array 11 (see FIG. 3). The −Z direction is the opposite direction of the +Z direction. When the +Z direction and the −Z direction are not distinguished, they are simply referred to as the Z direction. In this application, the +Z direction side may be referred to as the “upper” and the −Z direction side may be referred to as the “lower.” However, these expressions are used for convenience of explanation and do not define the direction of gravity. The Z direction is an example of a "first direction." Also, in the drawings described below, illustrations of configurations that are not relevant to the explanation may be omitted.

[0010] (First embodiment) 1 is a block diagram showing a portion of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 2, an address register 3, a control circuit (sequencer) 4, a driver module 5, a row decoder module 6, and a sense amplifier module 7.

[0011] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 1). A block BLK is a collection of memory cell transistors. A block BLK is used as a unit for erasing data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0012] The command register 2 holds the command CMD that the semiconductor memory device 1 receives from the host device. The address register 3 holds address information ADD that the semiconductor memory device 1 receives from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 4 controls various operations of the semiconductor memory device 1. For example, the control circuit 4 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 2.

[0013] The driver module 5 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 6 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line. The sense amplifier module 7 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 7 determines the data stored in each memory cell transistor based on the voltage of each bit line and transfers the determination result to the host device as read data DAT.

[0014] Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. Fig. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, five strings STR0 to STR4).

[0015] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes a plurality of memory cell transistors MC0 to MCn (n is an integer equal to or greater than 1), one or more drain-side select transistors ST1, and one or more source-side select transistors ST2.

[0016] In each NAND string NS, memory cell transistors MC0 to MCn are connected in series. Each memory cell transistor MC includes a control gate and a charge storage section. The control gate of the memory cell transistor MC is connected to one of word lines WL0 to WLn. Each memory cell transistor MC stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, thereby retaining data in a non-volatile manner.

[0017] The drain of the drain-side select transistor ST1 is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MCn. The control gate of the drain-side select transistor ST1 is connected to one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor ST1 is electrically connected to the row decoder module 6 via the drain-side select gate line SGD. The drain-side select transistor ST1 connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain-side select gate line SGD.

[0018] The drain of the source-side select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MCn. The source of the source-side select transistor ST2 is connected to a source line SL. The control gate of the source-side select transistor ST2 is connected to a source-side select gate line SGS. The source-side select transistor ST2 connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side select gate line SGS.

[0019] In the same block BLK, the control gates of the memory cell transistors MC0 to MCn are commonly connected to the corresponding word lines WL0 to WLn. In the same string STR, the control gate of the drain-side select transistor ST1 is commonly connected to the corresponding drain-side select gate line SGD. The control gate of the source-side select transistor ST2 is commonly connected to the source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS to which the same column address is assigned in multiple strings STR.

[0020] FIG. 3 is a cross-sectional view of a semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 includes a memory chip 10 and a circuit chip 20, which are bonded together at a bonding surface S. The memory chip 10 includes a memory cell array 11. The circuit chip 20 functions as a control circuit (logic circuit) that controls the operation of the memory chip 10. The memory chip 10 and the circuit chip 20 are electrically connected via second pads 13 and first pads 23 on the bonding surface S. The semiconductor memory device 1 shown in FIG. 1 has the memory chip 10 mounted on the circuit chip 20.

[0021] The circuit chip 20 includes a first substrate 21, an insulating layer 22, a first pad 23, a transistor 24, a wiring 25, and a via 26.

[0022] The first substrate 21 is, for example, a semiconductor substrate made of silicon or the like. The insulating layer 22 is stacked on the first substrate 21. The insulating layer 22 is an interlayer insulating film that provides insulation between multilayer wirings. The interlayer insulating film is, for example, an oxide film such as a silicon oxide film.

[0023] The first pads 23 electrically connect the memory chip 10 and the circuit chip 20 on the bonding surface S. The first pads 23 are electrically connected to, for example, a transistor 24. The transistor 24 is formed on the first substrate 21. The transistor 24 is, for example, a part of a CMOS circuit.

[0024] The wiring 25 and the via 26 are made of a conductor such as copper, tungsten, etc. The via 26 provides electrical connection between the transistor 24 and the wiring 25, between the wiring 25 and the first pad 23, or between the wirings 25 themselves.

[0025] The memory chip 10 includes a memory cell array 11, an insulating layer 12, second pads 13, wiring 15, vias 16, insulating layers 17, 18, and 19, a conductor 30, a covering layer 40, and a conductive layer 41.

[0026] The memory cell array 11 is a collection of memory cell transistors. The memory cell array 11 has a plurality of conductive layers, a plurality of insulating layers, pillars MP, and slits ST. The configuration of the memory cell array 11 will be described in detail later.

[0027] The insulating layer 12 covers the memory cell array 11. The insulating layer 12 is an interlayer insulating film that insulates between multilayer wirings. The second pads 13 are responsible for electrical connection between the memory chip 10 and the circuit chip 20 on the bonding surface S.

[0028] The second pad 13 is electrically connected to, for example, the memory cell array 11. The wiring 15 and the via 16 are made of a conductor such as copper or tungsten. The via 16 provides electrical connection between the memory cell array 11 and the wiring 15, between the wiring 15 and the second pad 13, or between the wirings 15 themselves. The insulating layers 17, 18, and 19 are made of, for example, a silicon oxide film or a silicon nitride film.

[0029] The conductors 30 extend in the Z direction. The configuration of the conductors 30 will be described in detail later. The covering layer 40 is connected across the multiple conductors 30. The covering layer 40 is, for example, a conductive layer having conductivity. The conductive layer 41 can apply a source potential from outside the semiconductor memory device 1 to the source layer BSL (see Figure 5). By arranging the conductive layers 41 evenly across the memory cell array 11, a substantially uniform source potential can be applied to the source layer BSL.

[0030] Fig. 4 is a plan view of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 has a first region R1 and a second region R2 when viewed from the Z direction. Fig. 3 is a cross-section of the semiconductor memory device 1 taken along line AA in Fig. 4.

[0031] The first region R1 is a region that overlaps with the memory cell array 11 when viewed in a plan view from the Z direction. The first region R1 has the memory cell array 11. The first region R1 has, for example, a first substrate 21, an insulating layer 12, an insulating layer 22, wiring 15, wiring 25, vias 16, vias 26, a first pad 23, a second pad 13, the memory cell array 11, insulating layers 17, 18, and 19, and a conductive layer 41. The first region R1 is called the memory cell array region and is a region for storing data.

[0032] The second region R2 surrounds the first region R1 when viewed from the Z direction. The second region R2 includes, for example, a first substrate 21, insulating layers 12 and 22, wiring 15 and 25, vias 16 and 26, a first pad 23, a second pad 13, a conductor 30, insulating layers 17 and 18, insulating layers 19, and a covering layer 40.

[0033] The second region R2 is referred to as an edge seal region. The second region R2 includes one or more edge seals ES. The edge seal ES is formed in a ring shape surrounding the first region R1 when viewed in the Z direction. The edge seal ES includes, for example, wiring 15, wiring 25, via 16, via 26, first pad 23, second pad 13, and conductor 30. The edge seal ES penetrates the insulating layer 12 and the insulating layer 22 in the Z direction. The edge seal ES prevents, for example, moisture from entering the memory cell array 11 from the surroundings. The edge seal ES prevents, for example, cracks from forming toward the memory cell array 11. The edge seal ES includes, for example, a conductive material such as copper or tungsten. The edge seal ES can dissipate (neutralize) electric charges generated during and after manufacturing to the first substrate 21 (ground).

[0034] The memory cell array 11 in the first region R1 will now be described in detail. As shown in Figure 4, the memory cell array 11 has a memory cell region 11m and a staircase region 11s. The staircase region 11s is located at the edge of the memory cell region 11m. The memory cell region 11m is sandwiched or surrounded by the staircase region 11s.

[0035] The memory cell region 11m is divided in the Y direction by a plurality of slits ST and a plurality of slits SHE. Each of the slits ST is formed from the staircase region 11s on the first end side in the X direction of the memory cell array 11, through the memory cell region 11m, to the staircase region on the second end side. The slits SHE are formed at least in the memory cell region 11m. The slits SHE are shallower than the slits ST and are formed substantially parallel to the slits ST. The slits SHE electrically separate the conductive layer (word line) for each drain-side select gate line SGD. The inside of the slits ST is filled with, for example, a conductor or an insulator. The inside of the slits SHE is filled with, for example, an insulator.

[0036] The portion of the memory cell array 11 sandwiched between two slits ST is a block BLK. Each of the blocks BLK corresponds to each of the blocks BLK0 to BLK(k-1) in FIGS. 1 and 2. The portion of the memory cell array 11 sandwiched between the slit ST and the slit SHE is called a finger. By dividing the drain-side select gate line SG1 into fingers, a specific finger in the block BLK can be selected by the drain-side select gate line SG1 when writing and reading data.

[0037] 5 is a cross-sectional view of a portion of the memory cell array 11 according to the first embodiment. The memory cell array 11 includes a plurality of conductive layers 51, a plurality of insulating layers 52, a source layer BSL, a plurality of pillars MP, and slits ST. The conductive layers 51 and the insulating layers 52 are alternately stacked. The source layer BSL includes a conductive material such as doped polysilicon. The slits ST are filled with a conductive material such as copper or tungsten.

[0038] The plurality of conductive layers 51 extend in the X and Y directions, respectively. The conductive layers 51 are, for example, tungsten or polysilicon doped with impurities. The number of conductive layers 51 is arbitrary. The conductive layers 51 become the drain-side select gate lines SGD, word lines WL, and source-side select gate lines SGS. Each of these drain-side select gate lines SGD, word lines WL, and source-side select gate lines SGS is exposed in the staircase region 11s of the memory cell array 11 and connected to a contact plug. Here, the conductive layer 51 located farthest from the first substrate 21 among the plurality of conductive layers 51 is referred to as the first conductive layer 51A.

[0039] The multiple insulating layers 52 extend in the X direction and the Y direction, respectively. The insulating layers 52 include, for example, silicon oxide. The insulating layers 52 are located between the conductive layers 51 and the source layers BSL and between adjacent conductive layers 51 in the Z direction. The insulating layers 52 insulate adjacent conductive layers 51. The number of insulating layers 52 is determined by the number of conductive layers 51.

[0040] There are a plurality of pillars MP in the memory cell array 11. Each pillar MP extends in the Z direction. Each pillar MP penetrates, for example, a plurality of conductive layers 51, a plurality of insulating layers 52, and a source layer BSL in the Z direction. The pillar MP has, for example, a circular or elliptical shape when viewed from the Z direction.

[0041] The pillars MP include, for example, first pillars MP1, second pillars MP2, and connection portions JC1.

[0042] The first pillar MP1 is in contact with the source layer BSL. The first pillar MP1 extends in the Z direction within the memory cell array 11. For example, the widths of the first pillar MP1 in the X and Y directions gradually increase from the top to the bottom.

[0043] The second columnar body MP2 is in contact with the contact plug and extends in the Z direction within the memory cell array 11. For example, the widths of the second columnar body MP2 in the X and Y directions gradually increase from the top to the bottom.

[0044] The connecting portion JC1 is located between the first columnar member MP1 and the second columnar member MP2. The connecting portion JC1 joins the first columnar member MP1 and the second columnar member MP2. The widths of the connecting portion JC1 in the X and Y directions are larger than the widths of the first columnar member MP1 and the second columnar member MP2 in the X and Y directions, respectively.

[0045] Here, an example has been shown in which the pillars MP have a first pillar MP1, a second pillar MP2, and a connecting portion JC1, but the shape of the pillars MP is not limited to this example. For example, the pillars MP may be pillars that are connected in the Z direction and do not have a connecting portion JC1. Furthermore, for example, the pillars MP may have multiple connecting portions at different positions in the Z direction, with the multiple pillars being connected in the Z direction by the connecting portions. The shape of the pillars MP varies depending on the manufacturing process of the memory cell array 11. For example, a pillar MP having a first pillar MP1, a second pillar MP2, and a connecting portion JC1 can be obtained by forming the memory cell array 11 in two stages, one pillar at a time.

[0046] Fig. 6 is a cross-sectional view of the vicinity of a pillar MP of the memory cell array according to the first embodiment. Fig. 7 is another cross-sectional view of the vicinity of a pillar MP of the memory cell array according to the first embodiment. Fig. 7 is a cross-section of the pillar MP taken along the conductive layer 51.

[0047] Each pillar MP has, in order from the inside, a core 53, a semiconductor body 54, and a memory film 55. The pillar MP is formed in the memory hole MH.

[0048] The core 53 extends in the Z direction and has a columnar shape. The core 53 includes, for example, silicon oxide. The core 53 is located inside the semiconductor body 54.

[0049] The semiconductor body 54 extends in the Z direction. The semiconductor body 54 is connected to the source layer BSL. The semiconductor body 54 covers the outer surface of the core 53. The semiconductor body 54 includes, for example, silicon. The silicon is, for example, polysilicon obtained by crystallizing amorphous silicon.

[0050] The memory film 55 extends in the Z direction. The memory film 55 covers the outer surface of the semiconductor body 54. The memory film 55 is located between the inner surface of the memory hole MH and the outer surface of the semiconductor body 54. The memory film 55 includes, for example, a tunnel insulating film 56 and a charge storage film 57. The tunnel insulating film 56 and the charge storage film 57 are located closer to the semiconductor body 54 in this order.

[0051] The tunnel insulating film 56 is located between the charge storage film 57 and the semiconductor body 54. The tunnel insulating film 56 includes, for example, silicon oxide or a combination of silicon oxide and silicon nitride. The tunnel insulating film 56 is a potential barrier between the semiconductor body 54 and the charge storage film 57.

[0052] The charge storage film 57 is located between each of the insulating layer 52 and the conductive layer 51 and the tunnel insulating film 56. The charge storage film 57 includes, for example, silicon nitride. The portions where the charge storage film 57 intersects with each of the plurality of conductive layers 51 function as memory cells. The memory cells retain data based on the presence or absence of charge or the amount of charge stored in the portions (charge storage portions) where the charge storage film 57 intersects with the plurality of conductive layers 51. The charge storage portions are located between each of the conductive layers 51 and the semiconductor body 54 and are surrounded by an insulating material.

[0053] A block insulating film 51a and a barrier film 51b may be provided between each conductive layer 51 and the insulating layer 52, and between each conductive layer 51 and the memory film 55. The block insulating film 51a suppresses back tunneling, which is a phenomenon in which charges return from the conductive layer 51 to the memory film 55. The block insulating film 51a is, for example, a silicon oxide film, a metal oxide film, or a laminated film in which multiple insulating films are laminated. An example of a metal oxide is aluminum oxide. The barrier film 51b is, for example, titanium nitride or a laminated film of titanium nitride and titanium.

[0054] The pillars MP may have a cover insulating film 58 between each insulating layer 52 and the charge storage film 57. The cover insulating film 58 contains, for example, silicon oxide. The cover insulating film 58 protects the charge storage film 57 from etching during processing. The cover insulating film 58 may be omitted, or a portion of the cover insulating film 58 may be left between the conductive layer 51 and the charge storage film 57 and used as a block insulating film.

[0055] 8 is a cross-sectional view of a characteristic portion of the semiconductor memory device according to the first embodiment, and is an enlarged cross-sectional view of the vicinity of the conductor 30 in the second region R2.

[0056] The conductor 30 extends in the Z direction within the insulating layer 12 of the memory chip 10. The conductor 30 includes a first conductor 31 and a second conductor 32.

[0057] The first end e1 of the first conductor 31 contacts the covering layer 40. The first end e1 is the upper end of the first conductor 31. The second end e2 of the first conductor 31 contacts the second conductor 32. The second end e2 is the end of the first conductor 31 opposite the first end e1 in the Z direction and is the lower end of the first conductor 31. The second end e2 is, for example, closer to the first substrate 21 than the first conductive layer 51A (see FIG. 5). The first conductive layer 51A is the conductive layer 51 in the memory cell array 11 that is located farthest from the first substrate 21. Furthermore, when the pillar MP has a first pillar MP1, a connection portion JC1, and a second pillar MP2 as shown in FIG. 5, the second end e2 may be at the same height as the connection portion JC1.

[0058] The first conductor 31 includes a first core 35 and a first barrier metal film 36. The first core 35 includes a conductive material such as copper or tungsten. The first core 35 may include the same metal as a second core 38 (described later), or may include a different material from the second core 38. The first core 35 is formed at a different time from the second core 38 during the manufacturing process, and therefore can be freely designed regardless of the material that makes up the second core 38.

[0059] The first barrier metal film 36 covers the outer periphery of the first core 35. The first barrier metal film 36 covers, for example, the side and bottom surfaces of the first core 35. The second end e2 of the first conductor 31 is covered with the first barrier metal film 36. The first barrier metal film 36 is, for example, titanium nitride or a laminated structure film of titanium nitride and titanium. The first barrier metal film 36 improves adhesion between the first core 35 and the insulating layer 12.

[0060] The second conductor 32 includes a second core 38 and a second barrier metal film 39. The periphery of the second conductor 32 may be covered with an insulating film 33. The insulating film 33 may be, for example, silicon oxide. The second conductor 32 may contain the same metal as the first conductor 31, or may contain a different metal.

[0061] The second core 38 includes a conductive material such as copper or tungsten. The second barrier metal film 39 covers the outer periphery of the second core 38. The second barrier metal film 39 covers, for example, the side and top surfaces of the second core 38. The first end e3 of the second conductor 32 is covered with the second barrier metal film 39. The first end e3 of the second conductor 32 is the top end of the second conductor 32. The second barrier metal film 39 is, for example, titanium nitride or a laminated structure film of titanium nitride and titanium.

[0062] The first end e3 of the second conductor 32 contacts the second end e2 of the first conductor 31. A portion of the second end e2 of the first conductor 31 may be recessed in the Z direction with respect to the XY plane. That is, the height position of the outer periphery and the central portion of the second end e2 in the Z direction may differ. The first end e3 of the second conductor 32 may fit into the recess (central portion). The first end e3 of the second conductor 32 may be located farther from the first substrate 21 in the Z direction than at least a portion of the second end e2 of the first conductor 31. For example, the first end e3 of the second conductor 32 may be located higher than at least a portion of the second end e2 of the first conductor 31. The circumferential length of the second end e2 of the first conductor 31 may be longer than the circumferential length of the first end e3 of the second conductor 32.

[0063] The covering layer 40 is connected to, for example, the first ends e1 of one or more of the conductors 30. The covering layer 40 is formed, for example, in openings formed in the insulating layers 17, 18, and 19. The insulating layer 19 shown in FIG. 8 has a three-layer structure of a polysilicon layer 19A, a silicon oxide layer 19B, and a polysilicon layer 19C. A protective layer 45 may be formed in the opening to cover the side surface of the opening. The protective layer 45 is, for example, silicon oxide.

[0064] Next, a method for manufacturing the semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is fabricated by bonding together a memory chip 10 and a circuit chip 20. Figures 9 to 20 are cross-sectional views for explaining the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0065] The memory chip 10 and the circuit chip 20 are fabricated separately. As shown in FIG. 9, the circuit chip 20 is obtained by stacking a first laminate L1 on a first substrate 21. The first laminate L1 includes, for example, a first pad 23 and a transistor 24. The first pad 23 and the transistor 24 are covered with an insulating layer 22 and are electrically connected to each other by wiring 25 and vias 26. The first laminate L1 is fabricated by repeating film formation for each layer and processing using photolithography or the like for each layer on a layer-by-layer basis. Well-known methods can be used for the film formation and processing methods. A plurality of first pads 23 are exposed on the bonding surface S of the circuit chip 20 opposite the first substrate 21.

[0066] The memory chip 10 is obtained by stacking a second laminate L2 (see FIG. 16) on a second substrate 61. The manufacturing process of the second laminate L2 will be described in detail with reference to FIGS.

[0067] First, as shown in Fig. 10, intermediate layers 62 and 63 are laminated on a second substrate 61. The intermediate layer 62 is a layer that will become the insulating layer 19, and the intermediate layer 63 is a layer that will become the insulating layer 18. Next, the conductors 30 and the memory cell array 11 are formed at different positions on the intermediate layer 63. The memory cell array 11 can be fabricated by performing the steps of forming a laminate in which insulating layers 52 and sacrificial layers are alternately laminated, forming pillars MP and slits ST that penetrate the laminate, and replacing the sacrificial layers with conductive layers 51 via the slits ST.

[0068] The formation of the conductor 30 will be described in detail below. Figures 11 to 15 show the vicinity of the slit ST of the memory cell array 11 in correspondence with the vicinity of the portion where the conductor 30 is formed. In Figures 11 to 15, the left side of the figure is an enlarged view of the vicinity of the slit ST, and the right side of the figure is an enlarged view of the vicinity of the portion where the conductor 30 is formed.

[0069] 11, the slit ST is formed in a stacked body including a polysilicon layer 63C, a silicon oxide layer 63B, a sacrificial layer 59A, a silicon oxide layer 63D, a polysilicon layer 63A, a plurality of insulating layers 52, and a plurality of sacrificial layers 59B. The slit ST extends from the first surface S1 of the stacked body to the silicon oxide layer 63B.

[0070] The first opening H1 for forming the conductor 30 is formed at a different position from the slit ST in the same XY plane. The first opening H1 is formed in the second region R2 surrounding the first region R1 in which the memory cell array 11 is formed, as viewed from the Z direction. In the second region R2, an insulating layer 12 is stacked on the polysilicon layer 63C, the silicon oxide layer 63B, and the polysilicon layer 63A. The first opening H1 penetrates the insulating layer 12 in the Z direction. The first opening H1 reaches from the first surface S1 of the stack to the silicon oxide layer 63B.

[0071] Next, as shown in FIG. 12, the silicon oxide layer 63B, the silicon oxide layer 63D, and the sacrificial layer 59A are dissolved through the slit ST, and then a source layer BSL is formed. The silicon oxide layer 63B near the first opening H1 is not dissolved but left as is. Next, a sacrificial layer 74 is formed in the first opening H1. The sacrificial layer 74 is an example of a first sacrificial layer. The sacrificial layer 74 is filled after an oxide film 73 is formed inside the first opening H1. The sacrificial layer 74 is obtained by filling the first opening H1 with a material to become the sacrificial layer up to the top surface of the insulating layer 12 and then removing a portion of it. Simultaneously with the formation of the oxide film 73 and the sacrificial layer 74, an oxide film 71 and a sacrificial layer 72 are formed in the slit ST. The oxide film 73 and the oxide film 71 are formed by, for example, CVD (chemical vapor deposition), and the sacrificial layer 74 and the sacrificial layer 72 are formed by, for example, CVD. The sacrificial layer 72 is an example of a third sacrificial layer. The oxide films 71 and 73 are made of, for example, silicon oxide, and the sacrificial layers 72 and 74 are made of amorphous silicon.

[0072] Specifically, the sacrificial layer 74 is obtained by the following procedure. A mask M is formed to cover the upper part of the slit ST. The mask M is not formed on the first opening H1. A portion of the filler material (amorphous silicon) filled in the first opening H1 is removed through the opening in the mask M. By removing a portion of the filler material, the sacrificial layer 74 is obtained, which fills the first opening H1 partway in the depth direction.

[0073] Next, as shown in FIG. 13, a sacrificial layer 76 is further formed on the sacrificial layer 74 inside the first opening H1. The sacrificial layer 76 is an example of a second sacrificial layer. The sacrificial layer 76 is filled after an oxide film 75 is formed inside the first opening H1. The oxide film 75 is made of, for example, silicon oxide, and the sacrificial layer 76 is made of amorphous silicon. Then, the mask M formed on the stacked body is removed.

[0074] 14, the oxide film 75 and the sacrificial layer 76 are removed. In the same step as this, the oxide film 71 and the sacrificial layer 72 in the slits ST are removed. Also, each of the sacrificial layers 59B is replaced with a conductive layer 51 through the slits SL.

[0075] Next, as shown in FIG. 15 , an insulating film 77 and a conductor 78 are formed in this order in the slit ST. The insulating film 77 is made of, for example, silicon oxide. The conductor 78 is made of, for example, tungsten. A barrier metal film 79 may be present between the insulating film 77 and the conductor 78. At the same time, an insulating film 33 and a second conductor 32 are formed in this order in the area where the sacrificial layer 76 has been removed. The second conductor 32 has a second core 38 and a second barrier metal film 39. The second conductor 32 extends to the first surface of the sacrificial layer 74.

[0076] Next, second pads 13 are fabricated, which are electrically connected to the conductors 30 and the pillars MP of the memory cell array 11. The conductors 30 and the memory cell array 11 are electrically connected to the second pads 13 by wiring 15 and vias 16. The second stack L2 is fabricated by repeating film formation for each layer and processing using photolithography or the like for each layer. Well-known methods can be used for film formation and processing. A plurality of second pads 13 are exposed on the bonding surface S of the memory chip 10 opposite the second substrate 61. Then, as shown in FIG. 16, the second stack L2 is turned upside down.

[0077] Next, the first laminate L1 and the second laminate L2 are bonded together at the bonding surface S so that the first pads 23 and the second pads 13 are connected.

[0078] Next, the formation of the conductor 30 will be further described. This will be described in detail below. In Figures 17 to 20, the vicinity of the slit ST of the memory cell array 11 and the vicinity of the portion where the conductor 30 is formed are shown in correspondence with each other.

[0079] 17, by turning the second stacked body L2 upside down, the sacrificial layer 74 is present above the second conductor 32. Next, as shown in FIG. 18, after the second substrate 61 is peeled off, a second opening H2 is formed that reaches the second surface of the sacrificial layer 74. By forming the second opening H2, a part of the sacrificial layer 74 is exposed. Furthermore, by forming the second opening H2, the polysilicon layer 63A becomes the polysilicon layer 19A, the silicon oxide layer 63B becomes the silicon oxide layer 19B, the polysilicon layer 63C becomes the polysilicon layer 19C, and the intermediate layer 62 becomes the insulating layer 18.

[0080] Next, as shown in FIG. 19, the oxide film 73 and the sacrificial layer 74 are removed from the second opening H2. The oxide film 73 and the sacrificial layer 74 are removed in different processes from the sacrificial layers 72 and 74 formed in the slit ST. Next, a first barrier metal film 36 and a first core 35 are laminated in this order in the area from which the oxide film 73 and the sacrificial layer 74 have been removed, thereby forming the first conductor 31. Because the first conductor 31 is formed at a different time from the second conductor 32, the material constituting the first conductor 31 can be freely set regardless of the material constituting the second conductor 32. Furthermore, a protective layer 45 is formed in the second opening H2 to cover the side surfaces of the second opening H2.

[0081] 20, an insulating layer 17 is laminated so as to cover the second opening H2 and the protective layer 45. Next, an opening is provided in the insulating layer 17 at a portion that overlaps with the first conductor 31 when viewed from the Z direction, and a covering layer 40 is formed. The covering layer 40 is connected to the first conductor 31. A conductive layer 41 is also formed above the slit ST. Through the above steps, the semiconductor memory device 1 according to this embodiment is fabricated. The manufacturing process shown here is an example, and other processes may be inserted between each process.

[0082] The conductor 30 has a large aspect ratio in the Z direction, with a length greater than its width in the X and Y directions. If the conductor 30 with such a high aspect ratio structure is formed all at once, it may tilt relative to the Z direction. This tilting of the conductor 30 may result in a gap at the connection between the contact plug and the conductor 30. Specifically, a gap formed of a material other than metal may form in a portion of the edge seal ES extending in the Z direction. This gap may serve as a path for moisture or cracks to penetrate, potentially reducing the reliability of the semiconductor memory device 1. In contrast, in the manufacturing method of the semiconductor memory device 1 according to this embodiment, the conductor 30 with a high aspect ratio structure is fabricated in two stages. Therefore, tilting of the conductor 30 with a high aspect ratio structure during the manufacturing process can be suppressed. If the conductor 30 is not tilted, no gap will form at the connection between the conductor 30 and the contact plug, resulting in a highly reliable semiconductor memory device 1.

[0083] (Second embodiment) 21 is a cross-sectional view of a characteristic portion of the semiconductor memory device according to the second embodiment. FIG. 21 is an enlarged cross-sectional view of the vicinity of the conductor 30A in the second region R2. In the semiconductor memory device according to the second embodiment, the shape of the conductor 30A is different from that of the conductor 30. In the semiconductor memory device according to the second embodiment, the same components as those in the semiconductor memory device according to the first embodiment are assigned the same reference numerals and will not be described.

[0084] The conductor 30A extends in the Z direction within the insulating layer 12 of the memory chip 10. The conductor 30A includes a first conductor 31A and a second conductor 32A. The first conductor 31A differs from the first conductor 31 according to the first embodiment only in its shape, and is otherwise configured similarly to the first conductor 31. The second conductor 32A differs from the second conductor 32 according to the first embodiment only in its shape, and is otherwise configured similarly to the second conductor 32.

[0085] A first end e1 of the first conductor 31A contacts the covering layer 40. The first end e1 is the upper end of the first conductor 31A. A second end e2 of the first conductor 31A contacts the second conductor 32A. The second end e2 is, for example, closer to the first substrate 21 than the first conductive layer 51A (see FIG. 5). The first conductive layer 51A is the conductive layer 51 in the memory cell array 11 that is located farthest from the first substrate 21.

[0086] The first end e3 of the second conductor 32A contacts the second end e2 of the first conductor 31A. A portion of the second end e2 of the first conductor 31A may be recessed in the Z direction with respect to the XY plane. The first end e3 of the second conductor 32A may fit into the recess (central portion). The first end e3 of the second conductor 32A may be located farther from the first substrate 21 in the Z direction than at least a portion of the second end e2 of the first conductor 31A. For example, the first end e3 of the second conductor 32A may be located above at least a portion of the second end e2 of the first conductor 31A. The perimeter of the second end e2 of the first conductor 31A may be longer than the perimeter of the first end e3 of the second conductor 32A. The perimeter of the second conductor 32A may increase with increasing distance from the first end e3. For example, the width of the second conductor 32A may increase as it moves away from the first end e3.

[0087] Next, a method for manufacturing a semiconductor memory device according to the second embodiment will be described. The method for manufacturing a semiconductor memory device according to the second embodiment is the same as the method for manufacturing a semiconductor memory device according to the first embodiment in that the memory chip 10 and the circuit chip 20 are manufactured separately. The method for manufacturing the circuit chip 20 is the same as the method for manufacturing a semiconductor memory device according to the first embodiment, and therefore a description thereof will be omitted.

[0088] Next, a method for manufacturing the memory chip 10 will be described. In the method for manufacturing the semiconductor memory device according to the second embodiment, the method for manufacturing the memory cell array 11 of the memory chip 10 is the same as that for the semiconductor memory device according to the first embodiment. In the method for manufacturing the semiconductor memory device according to the second embodiment, the method for manufacturing the conductor 30A is different from that for manufacturing the conductor 30 according to the first embodiment. This point will be described in detail using Figures 22 to 27. Figures 22 to 27 illustrate the vicinity of the slit ST of the memory cell array 11 in correspondence with the vicinity of the portion where the conductor 30A is formed. In Figures 22 to 27, the left side of the figure is an enlarged view of the vicinity of the slit ST, and the right side is an enlarged view of the vicinity of the portion where the conductor 30A is formed.

[0089] The first opening H1 for forming the conductor 30A is formed at a different position from the slit ST in the same plane. The first opening H1 is formed in the second region R2 surrounding the first region R1 in which the memory cell array 11 is formed, as viewed from the Z direction. In the second region R2, an insulating layer 12 is stacked on the polysilicon layer 63C, the silicon oxide layer 63B, and the polysilicon layer 63A. The first opening H1 penetrates the insulating layer 12 in the Z direction. The first opening H1 reaches from the first surface S1 of the stack to the silicon oxide layer 63B.

[0090] As shown in FIG. 22, a sacrificial layer 74 is filled inside the first opening H1. The sacrificial layer 74 is filled after an oxide film 73 is formed inside the first opening H1. The sacrificial layer 74 fills the first opening H1 up to partway in the depth direction. A protective layer 81 is formed on the sacrificial layer 74 inside the first opening H1. The protective layer 81 is, for example, silicon oxide.

[0091] 23, the oxide film 71 and the sacrificial layer 72 in the slit ST are removed. Each of the sacrificial layers 59B is replaced with a conductive layer 51 through the slit SL. The sacrificial layer 74 in the first opening H1 is protected by the protective layer 81 and is therefore not removed in the same step as the step of removing the sacrificial layer 72 in the slit ST. An insulating film 77 and a conductor 78 are formed in this order in the slit ST from which the oxide film 71 and the sacrificial layer 72 have been removed. A barrier metal film 79 may be formed between the insulating film 77 and the conductor 78.

[0092] Next, as shown in FIG. 24 , a contact plug CP is formed that reaches the conductor 78 in the slit ST. The contact plug CP has a core 82 and a barrier metal film 83. The core 82 is made of a conductive material such as copper or tungsten, and the barrier metal film 83 is made of titanium nitride or a laminated film of titanium nitride and titanium, for example. In addition, in the same process as forming the contact plug CH, a second conductor 32A is formed that reaches the first surface of the sacrificial layer 74. The second conductor 32A penetrates the protective layer 81 and reaches the first surface of the sacrificial layer 74. The second conductor 32A has a second core 38 and a second barrier metal film 39.

[0093] Next, similarly to the method for manufacturing the semiconductor memory device according to the first embodiment, the first laminate L1 and the second laminate L2 are bonded together at the bonding surface S so that the first pads 23 and the second pads 13 are connected. Fig. 25 is a diagram obtained by turning Fig. 24 upside down. By turning the second laminate L2 upside down, the sacrificial layer 74 is located above the second conductors 32A.

[0094] 26, a second opening H2 is formed that reaches the second surface of the sacrificial layer 74. By forming the second opening H2, a part of the sacrificial layer 74 is exposed.

[0095] Next, the oxide film 73 and the sacrificial layer 74 are removed from the second opening H2. A first barrier metal film 36 and a first core 35 are sequentially stacked in the area from which the oxide film 73 and the sacrificial layer 74 have been removed, thereby forming the first conductor 31A. Because the first conductor 31A is formed at a different time from the second conductor 32A, the material constituting the first conductor 31A can be freely set regardless of the material constituting the second conductor 32A.

[0096] Next, as shown in FIG. 27, a protective layer 45, an insulating layer 17, and a covering layer 40 are formed in the same manner as in the manufacturing method of the semiconductor memory device according to the first embodiment. The covering layer 40 is connected to the first conductor 31A. A conductive layer 41 is also formed above the slit ST. Through the above steps, the semiconductor memory device according to this embodiment is manufactured. The manufacturing process shown here is an example, and other processes may be inserted between each step.

[0097] In the manufacturing method of the semiconductor memory device according to the second embodiment, the conductor 30A with a high aspect ratio structure is fabricated in two stages. This prevents the conductor 30A with a high aspect ratio structure from tilting during the manufacturing process. In the semiconductor memory device according to the second embodiment, the second conductor 32A is fabricated in the same process as the contact plug CH. Therefore, it is difficult to increase the length of the second conductor 32A in the Z direction compared to the second conductor 32 in the semiconductor memory device according to the first embodiment. This increases the aspect ratio of the first conductor 31A in the Z direction, which may cause the first conductor 31A to tilt relative to the Z direction. Even in this case, the coverage area of ​​the coating layer 40 in the X and Y directions is sufficiently large relative to the area of ​​the top end of the first conductor 31A. Therefore, even if the first conductor 31A tilts relative to the Z direction, no gaps are formed between the coating layer 40 and the first conductor 31A. Gaps can be a path for moisture and cracks to penetrate. However, preventing these gaps can sufficiently prevent a decrease in the reliability of the semiconductor memory device.

[0098] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0099] 1. Semiconductor memory device 11 Memory Cell Array 12, 17, 18, 19, 22 Insulating layer 13 Second Pad 21 First board 23 First Pad 24 transistors 30, 30A conductor 31, 31A First conductor 32, 32A Second conductor 33 Insulating film 35 First Core 36 First barrier metal film 38 Second Core 39 Second barrier metal film 40 Covering layer 41 Conductive layer 45 Protective layer 72, 74, 76 81 Protective layer e1, e3 1st end e2 2nd end ES Edge Seal H1 1st opening H2 2nd opening JC1 connection L1 First laminate L2 2nd laminate MH Memory Hole MP columnar body MP1 1st columnar body MP2 2nd columnar body R1 1st area R2 2nd area ST slit

Claims

1. a first region having a memory cell array having a plurality of memory cells; and a second region surrounding the first region when viewed from a first direction; the second region includes a first substrate, an insulating layer stacked on the first substrate, a conductor extending in the first direction inside the insulating layer, and a covering layer in contact with the conductor; the conductor includes a first conductor contacting the coating layer at a first end, and a second conductor contacting a second end of the first conductor on the opposite side of the first end in the first direction, the first conductor includes a first core and a first barrier metal film covering the first core; The second end of the first conductor is covered with the first barrier metal film.

2. 2. The semiconductor memory device according to claim 1, wherein a perimeter of said second end of said first conductor is longer than a perimeter of a first end of said second conductor that is in contact with said first conductor.

3. 2. The semiconductor memory device according to claim 1, wherein a first end of the second conductor that contacts the first conductor is located farther from the first substrate in the first direction than at least a portion of the second end of the first conductor.

4. 2. The semiconductor memory device according to claim 1, wherein said first conductor comprises the same metal as said second conductor.

5. 2. The semiconductor memory device according to claim 1, wherein said first conductor comprises a metal different from that of said second conductor.

6. the memory cell array includes a stack having a plurality of conductive layers and a plurality of insulating layers; 2. The semiconductor memory device according to claim 1, wherein the second end of the first conductor is closer to the first substrate than a first conductive layer of the plurality of conductive layers that is located farthest from the first substrate.

7. the memory cell array includes a stacked body having a plurality of conductive layers and a plurality of insulating layers, and a columnar body extending in the first direction inside the stacked body; the pillars include first pillars extending in the first direction, second pillars extending in the first direction, and connection portions between the first pillars and the second pillars; 2. The semiconductor memory device according to claim 1, wherein said second end of said first conductor is at the same height as said connecting portion in said first direction.

8. the second conductor includes a second core and a second barrier metal film covering the second core; 2. The semiconductor memory device according to claim 1, wherein a first end of said second conductor in contact with said first conductor is covered with said second barrier metal film.

9. forming a first stack on a first substrate, the first stack including a transistor and a first pad electrically connected to the transistor; a second laminate is fabricated on a second substrate, the second laminate being formed with a memory cell array, an insulating layer covering the memory cell array, and a second pad connected to the memory cell array; forming a first opening penetrating the insulating layer in a first direction in a second region surrounding a first region in which the memory cell array is formed as viewed from a first direction; forming a first sacrificial layer inside the first opening; forming a conductor inside the first opening and extending to a first surface of the first sacrificial layer; bonding the first laminate and the second laminate together so as to connect the first pad and the second pad; peeling the second substrate from the second laminate, and forming a second opening that reaches a second surface of the first sacrificial layer opposite to the first surface; a first sacrificial layer formed on the first insulating film and a first core formed on the second insulating film; a first sacrificial layer formed on the first insulating film and a first core formed on the second insulating film;

10. 10. The method for manufacturing a semiconductor memory device according to claim 9, wherein said first sacrificial layer is filled up to a depth of said first opening.

11. further forming a second sacrificial layer on the first surface of the first sacrificial layer inside the first opening; 10. The method for manufacturing a semiconductor memory device according to claim 9, wherein the conductor is formed in the portion from which the second sacrificial layer has been removed, the conductor reaching the first surface of the first sacrificial layer.

12. further forming a protective layer on the first surface of the first sacrificial layer inside the first opening; The method for manufacturing a semiconductor memory device according to claim 9 , wherein the conductor is formed so as to penetrate the protective layer and reach the first surface of the first sacrificial layer.

13. forming a slit penetrating the memory cell array in the first direction; forming a third sacrificial layer inside the slit; 10. The method for manufacturing a semiconductor memory device according to claim 9, wherein the first sacrificial layer and the third sacrificial layer are removed in different steps.

14. further forming a second sacrificial layer on the first surface of the first sacrificial layer inside the first opening; forming a slit penetrating the memory cell array in the first direction; forming a third sacrificial layer inside the slit; 10. The method for manufacturing a semiconductor memory device according to claim 9, wherein the second sacrificial layer and the third sacrificial layer are removed in the same step.

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