Inverter device

Abstract

This suppresses the impulse-like surge voltage generated between the gate and source of the upper arm switching element during the switching of the lower arm switching element. [Solution] The gate and source of the upper arm switching element 111 are connected via an upper arm gate capacitor 141, and the gate and source of the lower arm switching element 112 are connected via a lower arm gate capacitor 142. The capacitance of the upper arm gate capacitor 141 is greater than the capacitance of the lower arm gate capacitor 142. The product of the resistance of the upper arm gate resistor 131 connecting the upper arm gate drive signal output unit 121 and the gate of the upper arm switching element 111, and the capacitance of the upper arm gate capacitor 141 is approximately equal to the product of the resistance of the lower arm gate resistor 132 connecting the lower arm gate drive signal output unit 122 and the gate of the lower arm switching element 112, and the capacitance of the lower arm gate capacitor 142.

Description

[Technical Field]

[0001] This invention relates to an inverter device. [Background technology]

[0002] Patent Document 1 describes that a gate resistor is connected between the switching element of the inverter circuit and the gate drive circuit (gate drive signal output section), and a gate capacitor is connected between the gate and emitter of the switching element. Patent Document 2 describes an upper arm switching element and a lower arm switching element of an inverter circuit. Furthermore, Patent Document 2 describes a first gate drive circuit that outputs a control signal to the upper arm switching element and a second gate drive circuit that outputs a control signal to the lower arm switching element. In addition, Patent Document 2 states that the first gate drive circuit includes a gate resistor and a gate capacitor. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2009-303472 [Patent Document 2] Japanese Patent Publication No. 2021-5984 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] By the way, in the technology described in Patent Document 2, the first gate drive circuit and the second gate drive circuit have the same structure.

[0005] Through diligent research, the present inventors have discovered that if a first gate drive circuit having a gate resistor and a gate capacitor and a second gate drive circuit having a gate resistor and a gate capacitor have the same structure, as described in Patent Document 2, an impulse-like surge voltage is generated between the gate and source of the upper arm switching element when the lower arm switching element is switched, and this surge voltage may cause the upper arm switching element to switch incorrectly (i.e., both the upper arm switching element and the lower arm switching element may switch).

[0006] In view of the above, the present invention aims to provide an inverter device that can suppress impulse-like surge voltages generated between the gate and source of the upper arm switching element when the lower arm switching element is switched. [Means for solving the problem]

[0007] One aspect of the present invention is an inverter device comprising an upper arm switching element, a lower arm switching element, an upper arm gate drive signal output unit, a lower arm gate drive signal output unit, an upper arm gate resistor, a lower arm gate resistor, an upper arm gate capacitor, and a lower arm gate capacitor, wherein the first terminal of the upper arm gate drive signal output unit is connected to the gate of the upper arm switching element via the upper arm gate resistor, the second terminal of the upper arm gate drive signal output unit is connected to the source or emitter of the upper arm switching element, the first terminal of the lower arm gate drive signal output unit is connected to the gate of the lower arm switching element via the lower arm gate resistor, the second terminal of the lower arm gate drive signal output unit is connected to the source or emitter of the lower arm switching element, the gate of the upper arm switching element and the source or emitter of the upper arm switching element are connected via the upper arm gate capacitor, and the gate of the lower arm switching element and the source or emitter of the lower arm switching element are connected via the lower arm gate capacitor Connected via a lower, the capacitance C1 of the upper arm gate capacitor is greater than the gate parasitic capacitance Cp1 of the upper arm switching element, the capacitance C2 of the lower arm gate capacitor is greater than the gate parasitic capacitance Cp2 of the lower arm switching element, the capacitance C1 of the upper arm gate capacitor is greater than the capacitance C2 of the lower arm gate capacitor, the product of the resistance R1 of the upper arm gate resistor and the capacitance C1 of the upper arm gate capacitor is greater than the product of the resistance R2 of the lower arm gate resistor and the lower arm gate capacitor The upper arm gate resistor is approximately equal to the product with capacitance C2, and is an external gate resistor provided separately from the upper arm switching element and the upper arm gate drive signal output unit; the lower arm gate resistor is an external gate resistor provided separately from the lower arm switching element and the lower arm gate drive signal output unit; the upper arm gate capacitor is an external gate capacitor that is intentionally inserted separately from the upper arm switching element and the upper arm gate drive signal output unit; and the lower arm gate capacitor isThis inverter device includes an external gate capacitor that is intentionally inserted separately from the lower arm switching element and the lower arm gate drive signal output section.

[0008] In an inverter device according to one aspect of the present invention, the capacitance C1 of the upper arm gate capacitor may be greater than the maximum value within the tolerance range of the manufacturing variation of the capacitance C2 of the lower arm gate capacitor.

[0009] In an inverter device according to one aspect of the present invention, the capacitance C1 of the upper arm gate capacitor may be larger than the capacitance C2 of the lower arm gate capacitor to the extent that the impulse-like surge voltage generated between the gate and source or emitter of the upper arm switching element during switching of the lower arm switching element is suppressed.

[0010] One aspect of the present invention is an inverter device comprising an upper arm switching element, a lower arm switching element, an upper arm gate drive signal output unit, a lower arm gate drive signal output unit, an upper arm gate resistor, a lower arm gate resistor, and an upper arm gate capacitor, wherein the first terminal of the upper arm gate drive signal output unit is connected to the gate of the upper arm switching element via the upper arm gate resistor, the second terminal of the upper arm gate drive signal output unit is connected to the source or emitter of the upper arm switching element, the first terminal of the lower arm gate drive signal output unit is connected to the gate of the lower arm switching element via the lower arm gate resistor, the second terminal of the lower arm gate drive signal output unit is connected to the source or emitter of the lower arm switching element, and the gate of the upper arm switching element and the source or emitter of the upper arm switching element are connected via the upper arm gate capacitor, and the upper arm The inverter device is such that the capacitance C1 of the upper-arm gate capacitor is greater than the gate parasitic capacitance Cp1 of the upper-arm switching element, the capacitance C1 of the upper-arm gate capacitor is greater than the gate parasitic capacitance Cp2 of the lower-arm switching element, the product of the resistance R1 of the upper-arm gate resistor and the capacitance C1 of the upper-arm gate capacitor is approximately equal to the product of the resistance R2 of the lower-arm gate resistor and the gate parasitic capacitance Cp2 of the lower-arm switching element, the upper-arm gate resistor is an external gate resistor provided separately from the upper-arm switching element and the upper-arm gate drive signal output unit, the lower-arm gate resistor is an external gate resistor provided separately from the lower-arm switching element and the lower-arm gate drive signal output unit, and the upper-arm gate capacitor is an external gate capacitor that is intentionally inserted separately from the upper-arm switching element and the upper-arm gate drive signal output unit.

[0011] In the inverter device according to one aspect of the present invention, the capacitance C1 of the upper arm gate capacitor may be larger than the gate parasitic capacitance Cp2 of the lower arm switching element to such an extent that an impulse-like surge voltage generated between the gate and the source or emitter of the upper arm switching element during the switching of the lower arm switching element is suppressed.

Advantages of the Invention

[0012] According to the present invention, it is possible to suppress an impulse-like surge voltage generated between the gate and the source of the upper arm switching element during the switching of the lower arm switching element.

Brief Description of the Drawings

[0013] [Figure 1] It is a circuit diagram showing a first example of the inverter device 1 of the first embodiment. [Figure 2] It is a diagram for explaining an impulse-like surge voltage generated between the gate and the source of the upper arm switching element during the switching of the lower arm switching element in a conventional general inverter device. [Figure 3] It is a circuit diagram showing a first example of the inverter device 1 of the second embodiment. [Figure 4] It is a diagram showing a circuit of an example corresponding to the inverter device 1 of the second embodiment shown in FIG. 3. [Figure 5] It is a diagram showing a simulation result such as the voltage VGS_H between the gate and the source of the upper arm switching element in the circuit shown in FIG. 4. [Figure 6] It is a diagram showing a circuit of a comparative example corresponding to a conventional inverter device. [Figure 7] It is a diagram showing a simulation result such as the voltage VGS_H between the gate and the source of the upper arm switching element in the circuit shown in FIG. 6.

Modes for Carrying Out the Invention

[0014] Hereinafter, embodiments of the inverter device of the present invention will be described with reference to the drawings.

[0015] <First Embodiment> FIG. 1 is a circuit diagram showing a first example of the inverter device 1 of the first embodiment.

[0016] In the example shown in FIG. 1, the inverter device 1 includes an upper-arm switching element 111, a lower-arm switching element 112, an upper-arm gate drive signal output unit 121, a lower-arm gate drive signal output unit 122, an upper-arm gate resistor 131, a lower-arm gate resistor 132, an upper-arm gate capacitor 141, a lower-arm gate capacitor 142, an upper-arm discharge resistor 151, a lower-arm discharge resistor 152, and a DC bus voltage source 16.

[0017] In the example shown in FIG. 1, the upper-arm switching element 111 and the lower-arm switching element 112 are MOSFETs having a gate, a drain, and a source. However, in other examples, the upper-arm switching element 111 and the lower-arm switching element 112 may be switching elements other than MOSFETs, such as IGBTs having a gate, a collector, and an emitter, for example.

[0018] In the example shown in FIG. 1, the upper-arm gate drive signal output unit 121 and the lower-arm gate drive signal output unit 122 are constituted by an IC (integrated circuit). However, in other examples, the upper-arm gate drive signal output unit 121 and the lower-arm gate drive signal output unit 122 may be constituted by a circuit other than an IC, such as a circuit having discrete components, for example.

[0019] In the example shown in FIG. 1 (the first example of the inverter device 1 of the first embodiment), the inverter device 1 includes the upper-arm discharge resistor 151 and the lower-arm discharge resistor 152. However, in other examples (the second example of the inverter device 1 of the first embodiment), the inverter device 1 may not include the upper-arm discharge resistor 151 and the lower-arm discharge resistor 152.

[0020] In the example shown in Figure 1, the first terminal 121A of the upper arm gate drive signal output unit 121 is connected to the gate G1 of the upper arm switching element 111 via the upper arm gate resistor 131. The second terminal 121B of the upper arm gate drive signal output unit 121 is connected to the source S1 of the upper arm switching element 111. The drain D1 of the upper arm switching element 111 is connected to the positive terminal of the DC bus voltage source 16.

[0021] In the example where the upper arm switching element 111 is an IGBT having a gate, collector, and emitter, the second terminal 121B of the upper arm gate drive signal output unit 121 may be connected to the emitter of the upper arm switching element 111.

[0022] In the example shown in Figure 1, the first terminal 122A of the lower arm gate drive signal output unit 122 is connected to the gate G2 of the lower arm switching element 112 via the lower arm gate resistor 132. The second terminal 122B of the lower arm gate drive signal output unit 122 is connected to the source S2 of the lower arm switching element 112. Furthermore, the source S2 of the lower arm switching element 112 is connected to the negative terminal of the DC bus voltage source 16. The drain D2 of the lower arm switching element 112 is connected to the source S1 of the upper arm switching element 111.

[0023] In the example where the lower arm switching element 112 is an IGBT having a gate, collector, and emitter, the second terminal 122B of the lower arm gate drive signal output unit 122 may be connected to the emitter of the lower arm switching element 112.

[0024] In the example shown in Figure 1, the gate G1 of the upper arm switching element 111 and the source S1 of the upper arm switching element 111 are connected via the upper arm gate capacitor 141.

[0025] In an example where the upper arm switching element 111 is an IGBT having a gate, collector, and emitter, the gate G1 of the upper arm switching element 111 and the emitter of the upper arm switching element 111 may be connected via the upper arm gate capacitor 141.

[0026] In the example shown in Figure 1, the gate G2 of the lower arm switching element 112 and the source S2 of the lower arm switching element 112 are connected via the lower arm gate capacitor 142.

[0027] In an example where the lower arm switching element 112 is an IGBT having a gate, collector, and emitter, the gate G2 of the lower arm switching element 112 and the emitter of the lower arm switching element 112 may be connected via the lower arm gate capacitor 142.

[0028] In the example shown in Figure 1, the gate G1 of the upper arm switching element 111 and the source S1 of the upper arm switching element 111 are connected via the upper arm discharge resistor 151.

[0029] In an example where the upper arm switching element 111 is an IGBT having a gate, collector, and emitter, the gate G1 of the upper arm switching element 111 and the emitter of the upper arm switching element 111 may be connected via the upper arm discharge resistor 151.

[0030] In the example shown in Figure 1, the gate G2 of the lower arm switching element 112 and the source S2 of the lower arm switching element 112 are connected via the lower arm discharge resistor 152.

[0031] In an example where the lower arm switching element 112 is an IGBT having a gate, collector, and emitter, the gate G2 of the lower arm switching element 112 and the emitter of the lower arm switching element 112 may be connected via the lower arm discharge resistor 152.

[0032] Through diligent research, the inventors have discovered that if the upper arm gate drive signal output unit 121, upper arm gate resistor 131, and upper arm gate capacitor 141 and the lower arm gate drive signal output unit 122, lower arm gate resistor 132, and lower arm gate capacitor 142 are made to have the same structure (more specifically, if the parameters of the upper arm gate resistor 131 and upper arm gate capacitor 141 are symmetrical with the parameters of the lower arm gate resistor 132 and lower arm gate capacitor 142), an impulse-like (spike-like) surge voltage is generated between the gate G1 and source S1 of the upper arm switching element 111 when the lower arm switching element 112 is switched, and there is a risk that the upper arm switching element 111 may switch incorrectly due to this surge voltage (that is, both the upper arm switching element 111 and the lower arm switching element 112 may switch).

[0033] Figure 2 is a diagram illustrating the impulse-like surge voltage generated between the gate and source of the upper arm switching element during switching of the lower arm switching element in a conventional general inverter device.

[0034] As shown in Figure 2, the spike-like surge voltages that are mixed into the waveform of the gate voltage Vgs of the upper arm switching element are superimposed on the waveform of the gate voltage Vgs of the upper arm switching element as the lower arm switching element switches. If a spike-like surge voltage that mixes into the waveform of the gate voltage Vgs of the upper arm switching element exceeds the gate threshold voltage of the upper arm switching element, the upper arm switching element may switch incorrectly, potentially causing a short circuit between the upper and lower arms. During the dead time period when the upper arm switching element switches (turns off) and both the upper and lower arm switching elements are in the off state, current flows back through the upper arm switching element in the reverse direction. As a result, the voltage Vds between the drain and source of the upper arm switching element remains approximately 0V. However, as soon as the dead time period ends, the lower arm switching element switches, and the current that was recirculating through the upper arm switching element switches from the upper arm to the lower arm (that is, it flows from the drain to the source of the lower arm switching element without recirculating through the upper arm switching element). At the same time, a DC bus voltage is applied to the upper arm switching element, which was previously off, and the voltage between the drain and source of the lower arm switching element becomes approximately 0V.

[0035] Thus, when the lower arm switching element switches immediately after the dead time ends, the voltage Vds between the drain and source of the upper arm switching element rises sharply from approximately 0V to the DC bus voltage, as shown in the upper right graph of Figure 2. Such a sharp change in the voltage Vds between the drain and source of the upper arm switching element causes a noise current (inoise) to be injected into the gate of the upper arm switching element through the feedback capacitance Cr present between the drain and gate of the upper arm switching element. That is, the noise current (=Cr × dVds / dt) flows into the gate of the upper arm switching element through the feedback capacitance Cr. An external upper arm gate resistor is connected between the gate of the upper arm switching element and the upper arm gate drive signal output section. Therefore, when noise current passes through the external upper arm gate resistor, a spike-like surge voltage is superimposed on the waveform of the gate voltage Vgs applied to the upper arm switching element by the upper arm gate drive signal output section.

[0036] In the example shown in Figure 1, measures described later are taken to suppress the impulse-like surge voltage generated between the gate G1 and source S1 of the upper arm switching element 111 when the lower arm switching element 112 is switched.

[0037] In the example shown in Figure 1, the capacitance C1 of the upper arm gate capacitor 141 is greater than the gate parasitic capacitance Cp1 of the upper arm switching element 111. The capacitance C2 of the lower arm gate capacitor 142 is greater than the gate parasitic capacitance Cp2 of the lower arm switching element 112. The capacitance C1 of the upper arm gate capacitor 141 is greater than the capacitance C2 of the lower arm gate capacitor 142.

[0038] In detail, in the example shown in Figure 1, the capacitance C1 of the upper arm gate capacitor 141 is greater than the maximum value within the manufacturing tolerance range (e.g., "±10%") of the capacitance C2 of the lower arm gate capacitor 142 (e.g., "design value of capacitance C2 of the lower arm gate capacitor 142 + 10%"). More specifically, the capacitance C1 of the upper arm gate capacitor 141 is greater than the capacitance C2 of the lower arm gate capacitor 142 to the extent that the impulse-like surge voltage generated between the gate G1 and source S1 of the upper arm switching element 111 during the switching of the lower arm switching element 112 is suppressed. In an example where the upper arm switching element 111 and the lower arm switching element 112 are IGBTs having a gate, collector, and emitter, the capacitance C1 of the upper arm gate capacitor 141 is greater than the capacitance C2 of the lower arm gate capacitor 142 to the extent that the impulse-like surge voltage generated between the gate and emitter of the upper arm switching element 111 when the lower arm switching element 112 is switched is suppressed.

[0039] In the example shown in Figure 1, the product of the resistance value R1 of the upper arm gate resistor 131 and the capacitance C1 of the upper arm gate capacitor 141 (R1 × C1) is approximately equal to the product of the resistance value R2 of the lower arm gate resistor 132 and the capacitance C2 of the lower arm gate capacitor 142 (R2 × C2). In other words, the resistance value R1 of the upper arm gate resistor 131 is smaller than the resistance value R2 of the lower arm gate resistor 132. In the example shown in Figure 1, the resistance R1 of the upper arm gate resistor 131 is 2 [Ω], the capacitance C1 of the upper arm gate capacitor 141 is 1 [μF], the resistance R2 of the lower arm gate resistor 132 is 20 [Ω], and the capacitance C2 of the lower arm gate capacitor 142 is 0.1 [μF]. However, in other examples, the resistance R1 of the upper arm gate resistor 131, the capacitance C1 of the upper arm gate capacitor 141, the resistance R2 of the lower arm gate resistor 132, and the capacitance C2 of the lower arm gate capacitor 142 may differ from the values ​​shown in Figure 1.

[0040] In other words, in the example shown in Figure 1, the upper arm gate resistor 131 is an external gate resistor provided separately from the upper arm switching element 111 and the upper arm gate drive signal output unit 121. The lower arm gate resistor 132 is an external gate resistor provided separately from the lower arm switching element 112 and the lower arm gate drive signal output unit 122. The upper arm gate capacitor 141 is an external gate capacitor that is intentionally inserted separately from the upper arm switching element 111 and the upper arm gate drive signal output unit 121. The lower arm gate capacitor 142 is an external gate capacitor that is intentionally inserted separately from the lower arm switching element 112 and the lower arm gate drive signal output unit 122.

[0041] In the example shown in Figure 1, an external upper-arm gate capacitor 141 is inserted between the gate G1 and source S1 of the upper-arm switching element 111. As a result, noise current entering the gate G1 of the upper-arm switching element 111 through the feedback capacitance Cr present between the drain D1 and gate G1 of the upper-arm switching element 111 is absorbed by the upper-arm gate capacitor 141. Although the upper arm gate capacitor 141 is charged by noise current, the voltage across the upper arm gate capacitor 141 rises slowly despite the charging by noise current because the upper arm gate capacitor 141 has capacitance. As a result, the spike-like surge voltage superimposed on the waveform of the gate voltage Vgs of the upper arm switching element 111 is suppressed, and its peak value is also reduced. In the example shown in Figure 1, because an external upper arm gate capacitor 141 is inserted into the upper arm, it is necessary to match the time constant of the lower arm. Therefore, the resistance value R1 of the upper arm gate resistor 131 is made smaller than the resistance value R2 of the lower arm gate resistor 132, by the amount of the upper arm gate capacitor 141.

[0042] For example, in conventional inverter devices, such as the technology described in Patent Document 2, the same components are used as the upper arm switching element and the lower arm switching element, so the upper arm gate drive circuit and the lower arm gate drive circuit have the same structure (the parameters of the upper arm gate drive circuit and the lower arm gate drive circuit are symmetrical).

[0043] On the other hand, in the example shown in Figure 1, the parameters of the upper arm gate drive circuit and the lower arm gate drive circuit are asymmetrical in order to suppress the impulse-like surge voltage that occurs between the gate and source of the upper arm switching element when the lower arm switching element is switched, which occurs when the parameters of the upper arm gate drive circuit and the lower arm gate drive circuit are symmetrical as in conventional inverter devices. Therefore, in the example shown in Figure 1, it is possible to suppress the spike-shaped surge voltage superimposed on the gate drive signal of the upper arm switching element 111 simultaneously with the switching of the lower arm switching element 112. As a result, surge voltages exceeding the gate withstand voltage of the upper arm switching element 111 will not enter the G1 gate of the upper arm switching element 111, and the upper arm switching element 111 can be switched safely.

[0044] <Second Embodiment> Figure 3 is a circuit diagram showing a first example of the inverter device 1 of the second embodiment.

[0045] In the example shown in Figure 3, the inverter device 1 includes an upper arm switching element 111, a lower arm switching element 112, an upper arm gate drive signal output unit 121, a lower arm gate drive signal output unit 122, an upper arm gate resistor 131, a lower arm gate resistor 132, an upper arm gate capacitor 141, an upper arm discharge resistor 151, a lower arm discharge resistor 152, and a DC bus voltage source 16.

[0046] In the example shown in Figure 3 (the first example of the inverter device 1 of the second embodiment), the inverter device 1 is equipped with an upper arm discharge resistor 151 and a lower arm discharge resistor 152. However, in other examples (the second example of the inverter device 1 of the second embodiment), the inverter device 1 may not be equipped with an upper arm discharge resistor 151 and a lower arm discharge resistor 152.

[0047] In the example shown in Figure 3, the first terminal 121A of the upper arm gate drive signal output unit 121 is connected to the gate G1 of the upper arm switching element 111 via the upper arm gate resistor 131. The second terminal 121B of the upper arm gate drive signal output unit 121 is connected to the source S1 of the upper arm switching element 111. The drain D1 of the upper arm switching element 111 is connected to the positive terminal of the DC bus voltage source 16. The first terminal 122A of the lower arm gate drive signal output unit 122 is connected to the gate G2 of the lower arm switching element 112 via the lower arm gate resistor 132. The second terminal 122B of the lower arm gate drive signal output unit 122 is connected to the source S2 of the lower arm switching element 112. Furthermore, the source S2 of the lower arm switching element 112 is connected to the negative terminal of the DC bus voltage source 16. The drain D2 of the lower arm switching element 112 is connected to the source S1 of the upper arm switching element 111. The gate G1 and source S1 of the upper arm switching element 111 are connected via the upper arm gate capacitor 141.

[0048] The gate G1 of the upper arm switching element 111 and the source S1 of the upper arm switching element 111 are connected via the upper arm discharge resistor 151. The gate G2 of the lower arm switching element 112 and the source S2 of the lower arm switching element 112 are connected via the lower arm discharge resistor 152.

[0049] In the example shown in Figure 3, measures described later are taken to suppress the impulse-like surge voltage generated between the gate G1 and source S1 of the upper arm switching element 111 when the lower arm switching element 112 is switched.

[0050] In the example shown in Figure 3, the capacitance C1 of the upper arm gate capacitor 141 is greater than the gate parasitic capacitance Cp1 of the upper arm switching element 111. Furthermore, the capacitance C1 of the upper arm gate capacitor 141 is greater than the gate parasitic capacitance Cp2 of the lower arm switching element 112.

[0051] In detail, in the example shown in Figure 3, the capacitance C1 of the upper arm gate capacitor 141 is greater than the gate parasitic capacitance Cp2 of the lower arm switching element 112 to the extent that the impulse-like surge voltage generated between the gate G1 and source S1 of the upper arm switching element 111 during switching of the lower arm switching element 112 is suppressed.

[0052] In the example shown in Figure 3, the product of the resistance value R1 of the upper arm gate resistor 131 and the capacitance C1 of the upper arm gate capacitor 141 (R1 × C1) is approximately equal to the product of the resistance value R2 of the lower arm gate resistor 132 and the gate parasitic capacitance Cp2 of the lower arm switching element 112 (R2 × Cp2). In other words, the resistance value R1 of the upper arm gate resistor 131 is smaller than the resistance value R2 of the lower arm gate resistor 132. In the example shown in Figure 3, the resistance R1 of the upper arm gate resistor 131 is 2 [Ω], the capacitance C1 of the upper arm gate capacitor 141 is 1 [μF], the resistance R2 of the lower arm gate resistor 132 is 20 [Ω], and the gate parasitic capacitance Cp2 of the lower arm switching element 112 is 0.1 [μF]. However, in other examples, the resistance R1 of the upper arm gate resistor 131, the capacitance C1 of the upper arm gate capacitor 141, the resistance R2 of the lower arm gate resistor 132, and the gate parasitic capacitance Cp2 of the lower arm switching element 112 may differ from the values ​​shown in Figure 3.

[0053] In other words, in the example shown in Figure 3, the upper arm gate resistor 131 is an external gate resistor provided separately from the upper arm switching element 111 and the upper arm gate drive signal output unit 121. The lower arm gate resistor 132 is an external gate resistor provided separately from the lower arm switching element 112 and the lower arm gate drive signal output unit 122. The upper arm gate capacitor 141 is an external gate capacitor that is intentionally inserted separately from the upper arm switching element 111 and the upper arm gate drive signal output unit 121.

[0054] In the example shown in Figure 3, unlike conventional inverter devices where the upper arm gate drive circuit and the lower arm gate drive circuit have the same structure, the upper arm gate drive circuit and the lower arm gate drive circuit have different structures in order to suppress the impulse-like surge voltage that occurs between the gate and source of the upper arm switching element when the lower arm switching element is switched. Therefore, in the example shown in Figure 3, it is possible to suppress the spike-shaped surge voltage superimposed on the gate drive signal of the upper arm switching element 111 simultaneously with the switching of the lower arm switching element 112. As a result, surge voltages exceeding the gate withstand voltage of the upper arm switching element 111 will not enter the G1 gate of the upper arm switching element 111, and the upper arm switching element 111 can be switched safely.

[0055] [Examples] Figure 4 shows the circuit of an embodiment corresponding to the inverter device 1 of the second embodiment shown in Figure 3 (i.e., the upper arm gate drive circuit and the lower arm gate drive circuit are asymmetrical). Figure 5 shows the voltage V between the gate and source of the upper arm switching element in the circuit shown in Figure 4. GS_H This figure shows the simulation results, etc. Specifically, Figure 5(A) shows the voltage V between the gate and source of the upper arm switching element in the circuit shown in Figure 4. GS_H The simulation results are shown in Figure 5(B), where the voltage V between the gate and source of the lower arm switching element in the circuit shown in Figure 4 is shown. GS_L The simulation results are shown in Figure 5(C), where the voltage V between the drain and source of the upper arm switching element in the circuit shown in Figure 4 is shown. DS_H The simulation results are shown in Figure 5(D), where the voltage V between the drain and source of the lower arm switching element in the circuit shown in Figure 4 is shown. DS_L The simulation results are shown. In the circuit of the embodiment shown in Figure 4, the resistance value of resistor "R3", which corresponds to the upper arm gate resistor 131 shown in Figure 3, is set to 1 [Ω], the resistance value of resistor "R2", which corresponds to the lower arm gate resistor 132 shown in Figure 3, is set to 10 [Ω], and the capacitance of capacitor "C1", which corresponds to the upper arm gate capacitor 141 shown in Figure 3, is set to 4.7 [μF].

[0056] Figure 6 shows a comparative example circuit corresponding to a conventional inverter device (i.e., the upper arm gate drive circuit and the lower arm gate drive circuit are symmetrical). Figure 7 shows the voltage V between the gate and source of the upper arm switching element in the circuit shown in Figure 6. GS_H This figure shows the simulation results, etc. Specifically, Figure 7(A) shows the voltage V between the gate and source of the upper arm switching element in the circuit shown in Figure 6. GS_H The simulation results are shown in Figure 7(B), where the voltage V between the gate and source of the lower arm switching element in the circuit shown in Figure 6 is shown. GS_Lshows the simulation results. FIG. 7(C) shows the voltage V between the drain and source of the upper arm switching element in the circuit shown in FIG. 6 DS_H shows the simulation results. FIG. 7(D) shows the voltage V between the drain and source of the lower arm switching element in the circuit shown in FIG. 6 DS_L of the simulation results. In the circuit of the comparative example shown in FIG. 6, the resistance value of the resistor "R3" corresponding to the upper arm gate resistor is set to 10 [Ω], and the resistance value of the resistor "R2" corresponding to the lower arm gate resistor is set to 10 [Ω].

[0057] In the circuit of the comparative example in which the upper arm gate drive circuit and the lower arm gate drive circuit shown in FIG. 6 are symmetric, as shown by the broken-line ellipse in FIG. 7(A), an impulse-like surge voltage is generated between the gate and source of the upper arm switching element when the lower arm switching element switches (turns on), and also when the lower arm switching element switches (turns off), an impulse-like surge voltage is generated between the gate and source of the upper arm switching element. On the other hand, in the circuit of the embodiment corresponding to the inverter device 1 of the second embodiment shown in FIG. 4 (the upper arm gate drive circuit and the lower arm gate drive circuit are asymmetric), as shown by the broken-line ellipse in FIG. 5(A), the impulse-like surge voltage generated between the gate and source of the upper arm switching element when the lower arm switching element switches (turns on) can be suppressed, and the impulse-like surge voltage generated between the gate and source of the upper arm switching element when the lower arm switching element switches (turns off) can be suppressed.

[0058] As described above, the embodiments of the inverter device of the present invention have been described with reference to the drawings. However, the inverter device of the present invention is not limited to the above-described embodiments, and appropriate changes can be made without departing from the spirit of the present invention. The configurations of each example of the above-described embodiments may be combined as appropriate.

Explanation of Reference Numerals

[0059] 1...Inverter device, 111...Upper arm switching element, G1...Gate, S1...Source, D1...Drain, 112...Lower arm switching element, G2...Gate, S2...Source, D2...Drain, 121...Upper arm gate drive signal output section, 121A...First terminal, 121B...Second terminal, 122...Lower arm gate drive signal output section, 122A...First terminal, 122B...Second terminal, 131...Upper arm gate resistor, 132...Lower arm gate resistor, 141...Upper arm gate capacitor, 142...Lower arm gate capacitor, 151...Upper arm discharge resistor, 152...Lower arm discharge resistor, 16...DC bus voltage source

Claims

1. An inverter device comprising an upper arm switching element, a lower arm switching element, an upper arm gate drive signal output unit, a lower arm gate drive signal output unit, an upper arm gate resistor, a lower arm gate resistor, an upper arm gate capacitor, and a lower arm gate capacitor, The first terminal of the upper arm gate drive signal output unit is connected to the gate of the upper arm switching element via the upper arm gate resistor. The second terminal of the upper arm gate drive signal output unit is connected to the source or emitter of the upper arm switching element. The first terminal of the lower arm gate drive signal output unit is connected to the gate of the lower arm switching element via the lower arm gate resistor. The second terminal of the lower arm gate drive signal output unit is connected to the source or emitter of the lower arm switching element. The gate of the upper arm switching element and the source or emitter of the upper arm switching element are connected via the upper arm gate capacitor. The gate of the lower arm switching element and the source or emitter of the lower arm switching element are connected via the lower arm gate capacitor. The capacitance C1 of the upper arm gate capacitor is greater than the gate parasitic capacitance Cp1 of the upper arm switching element. The capacitance C2 of the lower arm gate capacitor is greater than the gate parasitic capacitance Cp2 of the lower arm switching element. The capacitance C1 of the upper arm gate capacitor is greater than the capacitance C2 of the lower arm gate capacitor. The product of the resistance value R1 of the upper arm gate resistor and the capacitance C1 of the upper arm gate capacitor is approximately equal to the product of the resistance value R2 of the lower arm gate resistor and the capacitance C2 of the lower arm gate capacitor. The upper arm gate resistor is an external gate resistor provided separately from the upper arm switching element and the upper arm gate drive signal output unit. The lower arm gate resistor is an external gate resistor provided separately from the lower arm switching element and the lower arm gate drive signal output unit. The upper arm gate capacitor is an external gate capacitor that is intentionally inserted separately from the upper arm switching element and the upper arm gate drive signal output section. The lower arm gate capacitor is an external gate capacitor that is intentionally inserted separately from the lower arm switching element and the lower arm gate drive signal output section. Inverter device.

2. The capacitance C1 of the upper arm gate capacitor is greater than the maximum value within the tolerance range for manufacturing variations of the capacitance C2 of the lower arm gate capacitor. The inverter device according to claim 1.

3. The capacitance C1 of the upper arm gate capacitor is greater than the capacitance C2 of the lower arm gate capacitor to such an extent that the impulse-like surge voltage generated between the gate and source or emitter of the upper arm switching element during switching of the lower arm switching element is suppressed. The inverter device according to claim 2.

4. An inverter device comprising an upper arm switching element, a lower arm switching element, an upper arm gate drive signal output unit, a lower arm gate drive signal output unit, an upper arm gate resistor, a lower arm gate resistor, and an upper arm gate capacitor, The first terminal of the upper arm gate drive signal output unit is connected to the gate of the upper arm switching element via the upper arm gate resistor. The second terminal of the upper arm gate drive signal output unit is connected to the source or emitter of the upper arm switching element. The first terminal of the lower arm gate drive signal output unit is connected to the gate of the lower arm switching element via the lower arm gate resistor. The second terminal of the lower arm gate drive signal output unit is connected to the source or emitter of the lower arm switching element. The gate of the upper arm switching element and the source or emitter of the upper arm switching element are connected via the upper arm gate capacitor. The capacitance C1 of the upper arm gate capacitor is greater than the gate parasitic capacitance Cp1 of the upper arm switching element. The capacitance C1 of the upper arm gate capacitor is greater than the gate parasitic capacitance Cp2 of the lower arm switching element. The product of the resistance value R1 of the upper arm gate resistor and the capacitance C1 of the upper arm gate capacitor is approximately equal to the product of the resistance value R2 of the lower arm gate resistor and the gate parasitic capacitance Cp2 of the lower arm switching element. The upper arm gate resistor is an external gate resistor provided separately from the upper arm switching element and the upper arm gate drive signal output unit. The lower arm gate resistor is an external gate resistor provided separately from the lower arm switching element and the lower arm gate drive signal output unit. The upper arm gate capacitor is an external gate capacitor that is intentionally inserted separately from the upper arm switching element and the upper arm gate drive signal output section. Inverter device.

5. The capacitance C1 of the upper arm gate capacitor is greater than the gate parasitic capacitance Cp2 of the lower arm switching element to such an extent that the impulse-like surge voltage generated between the gate and source or emitter of the upper arm switching element during switching is suppressed. The inverter device according to claim 4.

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