Semiconductor equipment

Abstract

To provide a semiconductor device that is less susceptible to changes in electrical characteristics due to miniaturization. [Solution] An acid comprising a first region and a pair of second regions facing each other across the first region A semiconductor film, a gate insulating film provided on the oxide semiconductor film, and provided on the gate insulating film The first region is c-axis oriented and has a first electrode superimposed on the first region. A non-single-crystal oxide semiconductor region having a crystalline portion, and a pair of second regions are dopants A semiconductor device characterized by being an oxide semiconductor region that includes and has multiple crystalline parts. That is the case.

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using an oxide semiconductor.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor in this specification is a semiconductor device, and an electric optical device, a semiconductor circuit, and an electronic device including the transistor are all included in the semiconductor device.

Background Art

[0003] Many of the transistors used in flat panel displays typified by liquid crystal display devices and light emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon formed on a glass substrate or polycrystalline silicon. Further, transistors using such silicon semiconductors are also used in integrated circuits (ICs) and the like.

[0004] Techniques for using metal oxides exhibiting semiconductor characteristics in transistors instead of the above silicon semiconductors have attracted attention. In this specification, metal oxides exhibiting semiconductor characteristics are referred to as "oxide semiconductors".

[0005] For example, as the oxide semiconductor, techniques for fabricating a transistor using a Zn - O - based metal oxide or an In - Ga - Zn - O - based metal oxide and using the transistor as a switching element of a pixel of a display device and the like have been disclosed (see Patent Document 1 and Patent Document 2).

[0006] Further, in a transistor using an oxide semiconductor, a highly conductive oxide semiconductor containing nitrogen is provided as a buffer layer between the source region and the drain region, and between the source electrode and the drain electrode.​​ By providing a conductor, the contact resistance between the oxide semiconductor and the source and drain electrodes is reduced. A technology for reducing resistance has been disclosed (see Patent Document 3).

[0007] Furthermore, in a top-gate transistor containing an oxide semiconductor, the channel formation region A technique for forming the source region and drain region in a self-aligned manner is disclosed (non (See Patent Document 1). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2010-135774 [Non-patent literature]

[0009] [Non-Patent Document 1] Jae Chul Park et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure” IEDM2009, pp191-194 [Overview of the project] [Problems that the invention aims to solve]

[0010] In order to increase the integration density of integrated circuits using transistors, miniaturization of transistors is necessary. It is essential.

[0011] Generally, in the miniaturization of transistors using silicon semiconductors, extremely short channel lengths The compressed transistor exhibits variations in electrical characteristics, such as a negative threshold voltage fluctuation. This phenomenon occurs. Suppressing this phenomenon is important for miniaturizing transistors using silicon semiconductors. This is one of the challenges.

[0012] Furthermore, transistors using oxide semiconductors are superior to transistors using silicon. It is known that the off-current is small at room temperature, and this is because carriers generated by thermal excitation This is thought to be because there are few A, meaning the carrier density is low. Even in transistors using cyanoacrylate materials, shortening the channel length can reduce the threshold voltage. Fluctuations and other changes may occur.

[0013] Therefore, one aspect of the present invention provides a semiconductor device that is less susceptible to changes in electrical characteristics due to miniaturization. The task is to accomplish this. [Means for solving the problem]

[0014] In a transistor using an oxide semiconductor, the electrical characteristics due to miniaturization of the transistor To suppress fluctuations, the oxide semiconductor film containing the channel formation region contains a region containing a dopant. The goal is to create a region. Specifically, a pair of regions containing a dopant and a ch The channel-forming region is provided. In this way, the gas generated in the drain region is... Furthermore, in order to mitigate the electric field applied to the channel formation region, fluctuations in the threshold voltage, etc. The effects caused by shortening the length can be reduced. In this specification, the dopant and This term refers to the elements and impurities added to an oxide semiconductor film that includes a channel-forming region.

[0015] Furthermore, the above oxide semiconductor film is non-single crystal, and more specifically, the ab-plane of the non-single crystal is perpendicular to the ab-plane. When viewed from the front, the atomic arrangement is triangular, hexagonal, equilateral triangle, or regular hexagonal. It has a structure in which, when viewed from a direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are layered. It includes crystalline portions arranged in a manner. In this specification, an oxide semiconductor having said crystalline portions is referred to as CAA C-OS(C Axis Aligned Crystalline Oxide Se We will call this channel formation region CAAC-O By using S, the irradiation of visible light or ultraviolet light, as well as the addition of heat and bias, This suppresses fluctuations in the electrical characteristics of transistors and improves the reliability of semiconductor devices. ru.

[0016] Furthermore, the region containing the above-mentioned dopant is an oxide semiconductor having multiple crystalline parts, mainly polycrystalline. It is composed of a body region. Thus, even in the region containing the above dopant, multiple bonds By creating an oxide semiconductor region with a crystalline structure, fluctuations in the electrical characteristics of the transistor are suppressed. It is possible.

[0017] In other words, one aspect of the present invention comprises a first region and a pair of second regions facing each other across the first region A region and an oxide semiconductor film including, a gate insulating film provided on the oxide semiconductor film, and gate The first electrode is provided on an insulating film and superimposed on a first region, and the first region is , a non-single-crystal oxide semiconductor region having c-axis oriented crystalline parts, and a pair of second regions A semiconductor device that is an oxide semiconductor region containing a dopant and having multiple crystalline parts. be.

[0018] Furthermore, the region containing the above dopant is located on an oxide semiconductor region having multiple crystalline parts, with a c-axis A non-single-crystal oxide semiconductor region having an oriented crystalline portion may be provided.

[0019] The above oxide semiconductor film is an acid containing two or more elements selected from In, Ga, Sn, and Zn. It is preferable to use a synthetic semiconductor film.

[0020] Furthermore, the semiconductor device has a second electrode and a second region electrically connected to a pair of second regions. It has three electrodes.

[0021] A pair of second regions use the first electrode as a mask and allow the dopant to pass through the gate insulating film. By adding it, it can be formed into a self-aligned state. A pair of second regions are small The first region functions as both a source region and a drain region, and is a channel-forming region. By providing a pair of second regions containing dopants at both ends, the electric field applied to the first region is This can be mitigated, such as by shortening the channel length, due to fluctuations in the transistor threshold voltage. This can reduce the effects that result from it.

[0022] Furthermore, a sidewall insulating film is provided on the side surface of the first electrode, and the first electrode is used as a mask. By passing the dopant through the sidewall insulating film, a pair of second regions A pair of third regions with lower dopant concentrations than the main region can be formed in a self-aligned manner. .

[0023] In other words, the pair of third regions function as channel-forming regions, and the pair of third regions A pair of second regions are formed between the two regions. The pair of second regions have a higher dopant concentration than the pair of third regions. The regions function as source and drain regions. A pair of second regions are used to dopane. The pair of third regions with low concentrations are regions that relax the electric field applied to the channel formation region, that is, This functions as an electric field relaxation region. By providing an electric field relaxation region in this way, This reduces the effects caused by shortening the channel length, such as fluctuations in the threshold voltage of the DISTRA. This is possible. In addition, both the pair of second regions and the pair of third regions have multiple crystalline parts. It is composed of oxide semiconductor regions.

[0024] Therefore, another aspect of the present invention is a first region and a pair of second regions facing each other across the first region. The region, and a pair of third regions provided between the first region and the pair of second regions, An oxide semiconductor film containing an oxide semiconductor film, a gate insulating film provided on the oxide semiconductor film, and on the gate insulating film It has a first electrode provided therein and superimposed on the first region, and the first region is c-axis arranged A non-single-crystal oxide semiconductor region having a oriented crystalline portion, comprising a pair of second regions and a pair The third region is an oxide semiconductor region containing a dopant and having multiple crystalline parts. Furthermore, the dopant concentrations in the pair of second regions are higher than the dopant concentrations in the pair of third regions. It is a semiconductor device.

[0025] Furthermore, both the pair of second regions and the pair of third regions are oxide semiconductors having multiple crystalline parts. A non-single-crystal oxide semiconductor region having c-axis oriented crystalline portions is provided on the conductive region. That's fine.

[0026] For example, the dopants added to the pair of second regions and the pair of third regions are Group 15 elements. Or boron. For example, the dopant may be phosphorus, arsenic, and antimony, and One or more elements selected from boron, contained in a pair of second regions and a pair of third regions. The dopant concentration achievable is 5×10 18 cm -3 or more and 1×10 22 cm -3 or less, which is preferable. Furthermore, the dopant concentration in the pair of second regions is 5×10 20 cm -3 or more and 1×10 2 2 cm -3 or less, and the dopant concentration in the pair of third regions is 5×10 18 cm -3 or more and 5 ×10 21 cm -3 or less, which is even more preferable.

[0027] Also, the transistor according to one aspect of the present invention is a transistor having a top gate structure, and the second electrode and the third electrode may have a top contact structure in which they contact the upper surface of the pair of second regions , or may have a bottom contact structure in which they contact the lower surface of the pair of second regions.

[0028] In the above, when adding a dopant to the oxide semiconductor film including the channel formation region, the dopant may be added without passing through the gate insulating film using the first electrode as a mask. For example, the range where the gate insulating film is formed may be only on the first region.

[0029] Also, when the gate insulating film is formed of an oxide insulating film and the sidewall insulating film is formed from a nitride insulating film, due to the difference in the etching rates of the nitride insulating film and the oxide insulating film, the gate insulating film (the oxide insulating film) functions as an etching stopper when forming the sidewall insulating film (the nitride insulating film), and excessive etching of the oxide semiconductor film in contact with the lower surface of the gate insulating film can be suppressed. As a result, the gate insulating film is the first ​​The structure remains on one region, a pair of second regions, and a pair of third regions.

[0030] Furthermore, when both the sidewall insulating film and the gate insulating film are made of oxide insulating film, the oxidation By utilizing the difference in etching rates between the insulating film and the first electrode, a pair of second regions and The gate insulating film provided on a pair of third regions can be etched. As a result, the gate insulating film remains on the first region. [Effects of the Invention]

[0031] According to one aspect of the present invention, a semiconductor device is provided that is less susceptible to changes in electrical characteristics due to miniaturization. It is possible. [Brief explanation of the drawing]

[0032] [Figure 1] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 2] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 3] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 4] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 5] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 6] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 7] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] A cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 9] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 10] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 12] A top view and a cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 13] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] A cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 15] A cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 16] A cross-sectional view showing an example of a semiconductor device according to one aspect of the present invention. [Figure 17] A diagram showing the structure of an oxide semiconductor after dopant addition. [Figure 18] A diagram showing the electronic state of an oxide semiconductor before and after the addition of a dopant. [Figure 19] This figure shows a cross-sectional TEM image of an oxide semiconductor after dopant addition. [Figure 20] A diagram showing an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 21] A diagram showing an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 22] A diagram showing an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 23] A diagram showing an example of a circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 24] A diagram showing a block diagram illustrating a specific example of a CPU, and a diagram showing a part of that block diagram. [Modes for carrying out the invention]

[0033] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. Not limited to the present invention, the form and details thereof may not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the parameters can be modified in various ways. Therefore, the present invention is described below. The description of this embodiment is not limited to the information provided below. In the diagrammatic structure, the same reference numeral is used for parts that are identical or have similar functions, but different numerals are used for different parts. This is used consistently across all surfaces, and its repeated use will be omitted from further explanation.

[0034] In each figure described herein, the size, film thickness, or region of each component is clearly indicated. It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. .

[0035] Furthermore, the terms "first," "second," "third," etc. used in this specification are used to avoid confusion of constituent elements. This is attached to the number and does not limit it numerically. Therefore, for example, "the first" can be written as " This can be explained by replacing it with "the second" or "the third," etc., as appropriate.

[0036] In this specification, the term "film" refers to a CVD method (including plasma CVD, etc.) Alternatively, by sputtering or other methods, the entire surface of the surface to be formed is formed, and the entire surface of the surface to be formed is formed The surface formed on the surface after processing related to the manufacturing process of a semiconductor device, and the used Yes, they are.

[0037] The functions of "source" and "drain" are used when employing transistors with different polarities, or in circuits. The direction of the current may change during operation, which can cause the current to switch positions. In the details, the terms "source" and "drain" can be used interchangeably. Let's assume that.

[0038] (Embodiment 1) In this embodiment, the structure and fabrication method of a transistor, which is one aspect of the present invention, This will be explained using Figures 1 through 8.

[0039] <Structure and characteristics of transistor 100> Figure 1(A) is a top view of transistor 100. Note that in Figure 1(A), the base insulation... The edge film 102, gate insulating film 111, and interlayer insulating film 117 are not shown for convenience.

[0040] As shown in Figure 1(A), the first electrode 113 is connected to a first region 105 (not shown) and a pair of second regions It is provided on an oxide semiconductor film 103 that includes regions 123a and 123b. And the second The electrode 119a, through the opening 116a, of the pair of second regions 123a and 123b The third electrode 119b is in contact with 123b via the opening 116b, respectively. It is provided. In addition, the second electrode 119a and the third electrode 119b are a pair of second Since it is in contact with the upper surfaces of regions 123a and 123b respectively, transistor 100 is This is a transistor with a top gate structure and a top contact structure.

[0041] Figure 1(B) is a cross-sectional view of transistor 100 between points A and B. From Figure 1(B), A base insulating film 102 is provided on the substrate 101, and on the base insulating film 102, the first region An oxide semiconductor film 103 is provided, which includes region 105 and a pair of second regions 123a and 123b. The pair of second regions 123a and 123b face each other via the first region 105. It is provided as such.

[0042] A gate insulating film 111 is provided on the oxide semiconductor film 103. A first electrode 113 is provided, which is superimposed on the first region 105.

[0043] An interlayer insulating film 117 is provided on the gate insulating film 111 and the first electrode 113. ru.

[0044] The second electrode 119a and the third electrode 119b are gate-insulated as shown in Figure 1(B). A pair of openings 116a and 116b provided in the film 111 and the interlayer insulating film 117 It is provided in contact with the second regions 123a and 123b. The gate insulating film 111 is It is provided adjacent to the first region 105 and the pair of second regions 123a and 123b. .

[0045] Oxide semiconductor film 1 comprising a first region 105 and a pair of second regions 123a, 123b 03 is a metal oxide containing two or more elements selected from In, Ga, Sn, and Zn. Furthermore, the metal oxide has a band gap of 2 eV or more, preferably 2.5 eV or more. Preferably, it is 3 eV or higher. In this way, metal oxides with a wide band gap are By using this method, the off-current of transistor 100 can be reduced.

[0046] Furthermore, in transistor 100, the first region 105 functions as a channel formation region. ru.

[0047] The first region 105 is CAAC-OS as described above. As mentioned above, CAAC- OS is a non-single crystal, and when viewed from a direction perpendicular to the ab-plane of the non-single crystal, it is triangular or It has a hexagonal, or equilateral triangular or regular hexagonal atomic arrangement, and from a direction perpendicular to the c-axis Observe the oxide semiconductor containing crystalline regions where metal atoms are arranged in layers or where metal atoms and oxygen atoms are arranged in layers. It refers to the body.

[0048] Furthermore, while CAAC-OS is not a single crystal, it is not formed solely from amorphous material. Furthermore, although CAAC-OS contains crystalline regions, the boundary between one crystalline region and another is not clearly defined. Sometimes it's impossible to separate them.

[0049] Some of the oxygen in CAAC-OS may be replaced with nitrogen. The c-axis of each individual crystal portion that makes up the structure is in a specific direction (for example, the substrate on which CAAC-OS is formed). They may be aligned perpendicular to the surface, the surface or film surface of CAAC-OS, or the interface. The normal to the ab plane of each individual crystal part that makes up CAAC-OS is in a certain direction (for example, CAA (Direction perpendicular to the substrate surface where C-OS is formed, the surface or film surface of CAAC-OS, or the interface, etc.) It's okay to stay.

[0050] CAAC-OS can be a conductor, a semiconductor, or an insulator, depending on its composition. They exist. Also, depending on their composition, they can be transparent or opaque to visible light. They might do that.

[0051] Furthermore, the hydrogen concentration in the first region 105 is 5 × 10⁵ 18 cm -3 Less than 1 × 10 18 cm -3 The following is more preferable: 5 x 10 17 cm -3 More preferably, 1 × 1 0 16 cm -3 The following is true: The first region 105, which is the channel-forming region, is CAAC-OS Furthermore, transistor 100, in which the hydrogen concentration is reduced, is used before and after light irradiation and BT (Gate / Thermal Bias) The threshold voltage fluctuation is small before and after the stress test. It possesses stable electrical characteristics and can be considered a highly reliable transistor.

[0052] The pair of second regions 123a and 123b contain a dopant and have a plurality of crystalline portions. This is an oxide semiconductor region. The pair of second regions 123a and 123b are dopants, One or more elements selected from arsenic, antimony, and boron are added. ru.

[0053] The pair of second regions 123a and 123b contain a dopant and have a plurality of crystalline portions. Because it is an oxide semiconductor region, if a pair of second regions 123a and 123b are, If CAAC-OS does not contain dopants, similar to region 105 (oxide semi) Compared to the case where all of the conductive film 103 is CAAC-OS without dopants, It has high conductivity. In other words, the resistive component of the oxide semiconductor film 103 in the channel direction is reduced. This allows us to increase the on-current of transistor 100.

[0054] Therefore, the pair of second regions 123a and 123b have an conductivity of 0.1 S / cm or more and 1000 The conductivity should be less than or equal to S / cm, preferably between 10 S / cm and 1000 S / cm. If the ratio is too low, the on-current of transistor 100 will decrease. Also, the pair of second To increase the conductivity of regions 123a and 123b, increasing the dopant concentration will result in... While it is possible to increase carrier density, increasing dopant concentration too much can lead to a pair of problems. This may reduce the conductivity of the second regions 123a and 123b.

[0055] Therefore, the dopant concentrations in the pair of second regions 123a and 123b are 5 × 10⁻¹⁰. 18 cm - 3 The above 1 x 10 22 cm -3The following is preferable. Also, the operation of transistor 100 In the process of adding the dopant during the manufacturing process, the first electrode 113 functions as a mask. The first region 105 and the pair of second regions 123a and 123b are formed in a self-aligned manner. .

[0056] A pair of second regions 123a and 123b are at least in transistor 100. It functions as a channel region and a drain region. A pair of second regions 123a, 123b are channeled. By providing them at both ends of the first region 105 of the channel-forming region, the first region which is the channel-forming region The electric field applied to region 105 can be mitigated.

[0057] In detail, a pair of second regions 123a and 123b are formed in the first region 105 of the channel-forming region. By providing them at both ends, the curvature of the band ends in the channel formed in the first region 105 This shows the effect of reducing the threshold voltage. Therefore, transistor 100 has a negative threshold voltage. This reduces the effects caused by shortening the channel length, such as fluctuations in direction.

[0058] Then, the pair of second regions 123a and 123b are the second electrode 119a and the third electrode Because the contact resistance with 119b is reduced, the on-current of transistor 100 is increased. It is possible.

[0059] <Method for manufacturing transistor 100> Next, the method for fabricating transistor 100 will be explained using Figures 2 to 4.

[0060] There are no major restrictions on the material of the substrate 101, but it must be at least strong enough to withstand subsequent heat treatment. It must have a certain degree of heat resistance. For example, glass substrates, ceramic substrates, quartz substrates, A sapphire substrate or the like may be used as the substrate 101. Alternatively, silicon or silicon carbide may be used. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to apply substrates, SOI substrates, etc., and semiconductor elements are provided on these substrates. The resulting product may be used as the substrate 101.

[0061] Alternatively, a flexible substrate may be used as the substrate 101. A transistor is provided on the flexible substrate. In this case, the transistor may be fabricated directly on a flexible substrate, or it may be fabricated on another substrate. After fabricating the transistor, it may be peeled off and transferred to a flexible substrate. In order to peel off the peel and transfer it to the flexible substrate, the peel must be removed between the other substrate and the transistor. It would be good to create an area that is easy to access.

[0062] First, a base insulating film 102 is formed on the substrate 101. The base insulating film 102 is made of the following materials. It is used to form a single-layer structure or a laminated structure.

[0063] Furthermore, the material for the undercoat insulating film 102 may be silicon oxide, gallium oxide, or a An oxide insulating film such as luminium, or silicon nitride, or aluminum nitride, etc. Nitride insulating film, or silicon oxide nitride, aluminum oxide nitride, or silicon oxide nitride An insulating film selected from the available materials can be used. Note that the base insulating film 102 will be formed later. It is preferable that the portion in contact with the oxide semiconductor film 103 contains oxygen. "Silicon oxide" refers to a material whose composition contains more nitrogen than oxygen, and is an acid "Silicon nitride" refers to a material whose composition contains more oxygen than nitrogen.

[0064] Aluminum nitride films, aluminum oxide nitride films, and silicon nitride films have high thermal conductivity. Therefore, by using it in the underlayer insulating film 102, the heat dissipation of the transistor 100 is improved. It is possible.

[0065] Furthermore, in the fabrication of transistor 100, alkali metals such as Li and Na are impurities. Therefore, it is preferable to reduce the content. Impurities such as alkali metals in the substrate 101 When using a glass substrate containing alkali metals, the underlying insulating film 102 is used to prevent the intrusion of alkali metals. Therefore, it is preferable to form the above-mentioned nitride insulating film.

[0066] The underlayer insulating film 102 can be formed by sputtering, CVD, coating, or other methods. There is no limit to the thickness of the underlayer insulating film 102, but the thickness of the underlayer insulating film 102 should be 50 nm or more. It is preferable that the underlayer insulating film 102 contains impurities from the substrate 101 (for example, L In addition to preventing the diffusion of alkali metals such as i and Na, the manufacturing process of transistor 100 To prevent the substrate 101 from being etched by the etching process in the process, Because they exist.

[0067] Furthermore, the underlying insulating film 102 is acidic in the portion that comes into contact with the oxide semiconductor film 103 that will be formed later. Since it is preferable to include an element, the underlying insulating film 102 is used, which releases oxygen when heated. A membrane may be used. Note that "oxygen is released by heating" refers to TDS (Thermal Desorption Spectroscopy (temperature-controlled desorption gas spectroscopy) analysis, The amount of oxygen released, converted to oxygen atoms, is 1.0 × 10⁻⁶. 18 cm -3 Preferably 3.0× 10 20 cm-3 This means that it is as described above.

[0068] The following describes a method for quantifying the amount of oxygen released by converting it to oxygen atoms using TDS analysis.

[0069] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. Therefore, insulation The amount of gas released can be measured by using the integral value of the membrane spectrum and the reference value of the standard sample. It can be calculated. The reference value of a standard sample is the product of the spectra of a sample containing a given atom. This is the ratio of the density of atoms to the fractional value.

[0070] For example, the TDS analysis results of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and From the TDS analysis results of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) can be found using formula 1. This can be done. Here, the entire spectrum detected at mass number 32 obtained by TDS analysis Let's assume it originates from an oxygen molecule. CH3OH has a mass number of 32, but is it possible that it exists? We will not consider this here as it has a low probability. Also, the isotope of the oxygen atom with mass number 17 Regarding oxygen atoms and oxygen molecules containing oxygen atoms with a mass number of 18, the abundance ratio in nature It is not considered because the amount is extremely small.

[0071]

number

[0072] N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integral value of the spectrum when the sample is analyzed using TDS. Here, the reference value of the standard sample is N H2 / S H2 Let's assume that. SO2 This is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. (See details of Equation 1.) For further information, please refer to Japanese Patent Publication No. 6-275697. Note that the numerical values ​​for the amount of oxygen released are as described above. This was done using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Denshi Kagaku Co., Ltd., and standard testing was performed. As a material, 1 x 10 16 cm -3 The values ​​were measured using a silicon wafer containing hydrogen atoms. be.

[0073] Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released is determined. Even if they are present, it can still be estimated.

[0074] Note N O2 This is the amount of oxygen molecules released. In insulating films, when converted to oxygen atoms, The amount of oxygen released is twice the amount of oxygen molecules released.

[0075] As an example of a film that releases oxygen upon heating, silicon oxide (SiO₂) has an excess of oxygen. X (x> 2)) There is silicon oxide (SiO₂) with an excess of oxygen. X (x>2)) refers to the number of silicon atoms. It contains more than twice the amount of oxygen atoms per unit volume of silicon. The number of atoms and the number of oxygen atoms were measured using the Rutherford backscattering method.

[0076] By using a film that releases oxygen upon heating as the underlying insulating film 102, the oxide semiconductor that will be formed later will be able to Oxygen is supplied to the conductive film 103, and the interface between the underlying insulating film 102 and the oxide semiconductor film 103 The charge can be reduced. Therefore, the charge that may be generated due to the operation of transistor 100 can be reduced. Trap can be suppressed at the interface between the ground insulating film 102 and the oxide semiconductor film 103, ZISTA100 can be made into a transistor with minimal degradation of electrical characteristics.

[0077] Next, an oxide semiconductor, which is CAAC-OS in all regions, is placed on the underlying insulating film 102. A film 130 is formed.

[0078] As a method for forming an oxide semiconductor film 130 that is CAAC-OS in all regions For example, there are two types of methods: (1) One method is to form an oxide semiconductor film. (2) Another method is to perform the process once while heating the substrate, and (3) another method is to use an oxide semiconductor. The film formation process is divided into two stages, with heat treatment performed after each stage to form an oxide semiconductor film. This is the method.

[0079] First, we will explain the case where the oxide semiconductor film 130 is formed by method (1).

[0080] An oxide semiconductor film 130 is formed on the substrate insulating film 102 while heating the substrate 101 (Figure See 2(A). Note that the oxide semiconductor film 130 was produced by sputtering, molecular beam epitaxy. The oxide semiconductor film may be formed by the following methods: atomic layer deposition or pulsed laser deposition. The thickness of 130 is 10 nm to 100 nm, preferably 10 nm to 30 nm. You should put it below.

[0081] The oxide semiconductor film 130 contains two or more metals selected from In, Ga, Zn, and Sn. Oxide materials can be used. For example, the quaternary metal oxide In-Sn-Ga-Zn- O-based materials, and ternary metal oxides such as In-Ga-Zn-O and In-Sn-Z nO-based materials, In-Al-Zn-O-based materials, Sn-Ga-Zn-O-based materials, Al -Ga-Zn-O type materials, Sn-Al-Zn-O type materials, and binary metal oxides In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-M gO-based materials, Sn-Mg-O-based materials, In-Mg-O-based materials, In-Ga-O-based materials Materials such as indium oxide, tin oxide, and zinc oxide can be used. Here, for example, In-Ga-Zn-O materials are composed of indium (In), gallium (Ga), and zinc (Z). This means an oxide containing n), and the composition ratio is not particularly specified. Also, In and Ga It may also contain elements other than Zn. In this case, with respect to the stoichiometric ratio of the oxide semiconductor film, An excess of oxygen is preferable. This is because an excess of oxygen can lead to oxygen deficiencies in the oxide semiconductor film. This can suppress the generation of carriers.

[0082] When using an In-Ga-Zn-O system material as the oxide semiconductor film 130, In, Ga As an example of a metal oxide target containing Zn, In2O3:Ga2O3:ZnO Some have a composition ratio of =1:1:1 [molar ratio]. Furthermore, In2O3:Ga2 A target with a composition ratio of O3:ZnO=1:1:2 [molar ratio], In2O3:G A target having a composition ratio of a2O3:ZnO=1:1:4 [molar ratio], or In A target having a composition ratio of 2O3:Ga2O3:ZnO=2:1:8 [molar ratio] It can also be used.

[0083] For example, when using an In-Zn-O based material as the oxide semiconductor film 130, In terms of atomic ratio, In / Zn = 0.5 to 50, preferably In / Zn = 1 to 20. More preferably, In / Zn = 1.5 or more and 15 or less. The atomic ratio of In to Zn is determined before By setting the range as described above, the field-effect mobility of transistor 100 can be improved. Here, when the atomic ratio of the compound is In:Zn:O=X:Y:Z, Z>1.5X+Y and That would be preferable.

[0084] As an oxide semiconductor film, the chemical formula is InMO3(ZnO) m Materials represented by (m>0) are used. It may be. Here, M is one or more golds selected from Ga, Al, Mn, and Co. It indicates the group element. For example, as M, Ga, Ga and Al, Ga and Mn or Ga You may also use terms like "Co".

[0085] Furthermore, the temperature at which the substrate 101 is heated should be between 150°C and 450°C. The substrate temperature should be between 200°C and 350°C. By increasing the heating temperature of the substrate 101 during the manufacturing process, the proportion of the crystalline portion relative to the amorphous portion is increased. It can be a CAAC-OS with a high proportion.

[0086] Next, we will explain the case where the oxide semiconductor film 130 is formed by method (2).

[0087] The substrate 101 is placed on the underlay insulating film 102 while maintaining the substrate temperature at 200°C to 400°C. A first layer of oxide semiconductor film is formed, under the atmosphere of nitrogen, oxygen, noble gas, or dry air. A heat treatment is performed at a temperature of 550°C or higher but below the substrate strain point. This heat treatment removes the oxide layer of the first layer. C-axis oriented crystals (including plate-like crystals) are formed in the region including the surface of the semiconductor film. Then, the second oxide semiconductor film is formed to be thicker than the first oxide semiconductor film. After that, A heat treatment is performed at a temperature of 550°C or higher and below the substrate strain point, and the c-axis oriented bond is formed in the region including the surface. Using the first layer of oxide semiconductor film, in which crystals (including plate-like crystals) are formed, as a seed for crystal growth, the second layer The oxide semiconductor film of the eye is grown upwards. Note that the first layer of oxide semiconductor film and the second layer The oxide semiconductor film of the eye uses a metal oxide material that can be applied to the oxide semiconductor film 130 described above. It is sufficient if it is present. Furthermore, it is preferable to form the first oxide semiconductor film with a thickness of 1 nm to 10 nm. It seems so.

[0088] Using the sputtering method, an oxide semiconductor film 130 is formed by either method (1) or method (2). When forming the film, the hydrogen concentration in the oxide semiconductor film 130 is reduced as much as possible. Preferred. To reduce the hydrogen concentration, the atmosphere supplied to the processing chamber of the sputtering apparatus As a gas, it is a highly purified noble gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. (Typically, argon), oxygen, and mixed gases of noble gases and oxygen are used as appropriate. The exhaust from the treatment chamber is provided by a cryopump with high water exhaust capacity and a hydrogen pump with high hydrogen exhaust capacity. A sputter ion pump can be used in combination with this system.

[0089] By doing so, an oxide semiconductor film 130 with reduced hydrogen contamination is formed. This can be done. Furthermore, even when using the above sputtering apparatus, the oxide semiconductor film 130 is less than [a small amount]. It is formed by containing nitrogen. For example, by secondary ion mass spectrometry (SIMS). Oxide semiconductor film 13 measured by ion mass spectrometry The nitrogen concentration at 0 is 5 × 10⁻⁶ 18 cm -3 It will be less than.

[0090] Furthermore, the underlying insulating film 102 and the oxide semiconductor film 130 may be formed continuously under vacuum. For example, hydrogen-containing impurities adhering to the surface of the substrate 101 are treated with heat or plasma After removal by processing, the underlying insulating film 102 is formed without exposure to the atmosphere, and then exposed to the atmosphere. The oxide semiconductor film 130 may be formed without exposure. In this way, the substrate 1 The hydrogen-containing impurities adhering to the surface of 01 are reduced, and the substrate 101 and the underlying insulating film 102 This suppresses the adhesion of atmospheric components to the interface between the underlying insulating film 102 and the oxide semiconductor film 130. Yes, it is possible. As a result, a transistor 100 with good electrical characteristics and high reliability can be manufactured. It is possible.

[0091] When forming or after forming the oxide semiconductor film 130, the oxygen of the oxide semiconductor film 130 A charge can be generated due to a defect. Generally, oxygen vacancies in oxide semiconductors can generate electric charge. A portion of the oxygen deficiency acts as a donor, generating electrons, which are carriers. In other words, transistor 10 Even at 0, some of the oxygen vacancies in the oxide semiconductor film 130 become donors and carriers. The generation of electrons causes the threshold voltage of transistor 100 to fluctuate in the negative direction. In the oxide semiconductor film 130, the generation of the electron occurs between the oxide semiconductor film 130 and the underlying insulating film. This is particularly noticeable in oxygen deficiencies that occur near the interface with the border film 102.

[0092] Therefore, after forming the oxide semiconductor film 130, the first heat treatment is performed, and the oxide semiconductor film 13 Forms 1 (see Figure 2(B)).

[0093] The first heat treatment involves heating the oxide semiconductor film 130 with hydrogen (containing water, hydroxyl groups, or hydrides). It releases oxygen, and also releases some of the oxygen contained in the underlying insulating film 102, thus releasing the oxide semiconductor Oxygen is diffused within the film 130 and near the interface between the underlying insulating film 102 and the oxide semiconductor film 130. To cause this to happen. In other words, the first heat treatment is performed at the interface between the underlying insulating film 102 and the oxide semiconductor film 130. The oxygen vacancies in the energy levels and oxide semiconductor film 130 are reduced, resulting in the completed transistor 100. The effect of carrier trapping at the interface between the oxide semiconductor film 103 and the underlying insulating film 102 is reduced. Therefore, the first heating treatment is performed when the threshold voltage of transistor 100 is It can suppress fluctuations in the negative direction.

[0094] Furthermore, not only a portion of the oxygen vacancies in the oxide semiconductor film 130, but also in the oxide semiconductor film 130 The hydrogen also acts as a donor, generating electrons, which are carriers. The first heating treatment generates the oxide semi The conductive film 130 has a reduced hydrogen concentration and becomes a highly purified oxide semiconductor film 131. The hydrogen concentration of the oxide semiconductor film 131 is 5 × 10⁻⁶. 18 cm -3 Less than 1 × 10 18 cm -3 The following is more preferable: 5 x 10 17 cm -3 More preferably, 1 × 1 0 16 cm -3 The following applies. Note that the hydrogen concentration in the oxide semiconductor film 131 is determined by the secondary ionic state. Secondary Ion Mass Spectrometer (SIMS) This is measured by y).

[0095] The first heat treatment sufficiently reduces the hydrogen concentration, resulting in high purity, and also provides sufficient oxygen. By using an oxide semiconductor film 131 that has been supplied and has reduced defect levels caused by oxygen deficiency. This allows us to reduce the off-current of transistor 100. Specifically, at room temperature (25°C) The off-current at °C (here, the value per unit channel width (1 μm)) is 100 Hz (1 zA (zeptoampere) is 1 × 10⁻¹⁰ -21 A) Preferably, it should be 10zA or less. Alkali metals such as Li and Na are impurities, so it is preferable to keep their content low. Furthermore, 2 × 10 in the oxide semiconductor film 131 16 cm -3 Preferably, 1 × 10 15 cm -3 The following concentrations are preferable. Furthermore, alkaline earth metals are also impurities. It is preferable to reduce the content.

[0096] The temperature of the first heat treatment is 150°C or higher and below the substrate strain point temperature, preferably 250°C or higher. The temperature should be 50°C or lower, more preferably 300°C to 450°C, and the atmosphere should be oxidizing or inactive. The process is carried out in an oxidizing atmosphere. Here, an oxidizing atmosphere is defined as an oxidizing gas such as oxygen, ozone, or oxygen nitride. This refers to an atmosphere containing 10 ppm or more of s. Furthermore, an inert atmosphere is defined as an atmosphere containing the aforementioned oxidizing gases. This refers to an atmosphere with a concentration of less than 10 ppm, and which is otherwise filled with nitrogen or a noble gas. Processing time The heating time should be between 3 minutes and 24 hours. Heat treatment exceeding 24 hours is preferable as it leads to a decrease in productivity. do not have.

[0097] There are no special limitations on the heating device used for the first heat treatment, and the heat from a heat source such as a resistance heating element is used. The device may include an apparatus for heating the object to be processed by conduction or thermal radiation. For example, an electric device. Furnaces, GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Anneal) devices, etc. A Thermal Anneal (LRTA) device can be used. The LRTA device uses a halogen Xenon lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high voltage Due to the radiation of light (electromagnetic waves) emitted from lamps such as sodium lamps and high-pressure mercury lamps, It is a device that heats the object to be processed. The GRTA device is a device that performs heat treatment using high-temperature gas. It is placed there.

[0098] Next, a resist mask is formed on the oxide semiconductor film 131 by a photolithography process. Using the resist mask, the oxide semiconductor film 131 is etched into a desired shape, forming island-like structures. An oxide semiconductor film 132 is formed (see Figure 2(C)). Note that the resist mask is In addition to the photography process, inkjet methods, printing methods, etc., can be used as appropriate. Etching is performed so that the edges of the island-shaped oxide semiconductor film 132 become tapered. It is preferable to do so. By making the edges of the island-shaped oxide semiconductor film 132 tapered, In the subsequent manufacturing process of transistor 100, the coating properties of the formed film are improved. This allows for the film to break, preventing breakage. The tapered shape recedes the resist mask. It can be formed by etching while simultaneously allowing the material to be formed.

[0099] The etching process in this step can be performed by dry etching or wet etching. This can be done, and these can be combined. The etching solution used for wet etching and For example, a solution of phosphoric acid, acetic acid, and nitric acid, ammonia hydrogen peroxide (31% by weight hydrogen peroxide:2 A solution such as 8% by weight ammonia water:water (5:2:2 by volume ratio) can be used. ITO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0100] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4, etc., are preferred.

[0101] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S)) F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and these gases can be mixed with noble gases such as helium (He) and argon (Ar). Gases with added sulfites, etc., can be used.

[0102] As for dry etching, parallel plate type RIE (Reactive Ion Etching) Methods such as the ng method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. Checking conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode, Adjust the electrode temperature on the substrate side as appropriate.

[0103] Next, a gate insulating film 111 is formed on the oxide semiconductor film 132. This is formed as a single-layer or multilayer structure using a material applicable to the underlying insulating film 102. Furthermore, the thickness of the gate insulating film 111 is 1 nm or more and 300 nm or less, more preferably 5 nm. It is best to set the wavelength between 50 nm and 60 nm.

[0104] Also, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-added hafnium silicate (HfSi x O y N z (x> 0, y>0, z>0), hafnium aluminate (HfAl x O y (x>0, y>0) High-k materials such as ) can be used. High-k materials have a high dielectric constant. Therefore, for example, it has the same gate insulating film capacity as when a silicon oxide film is used as the gate insulating film. While maintaining this, the thickness of the physical gate insulating film can be increased. Therefore, gate-lea The current can be reduced. Furthermore, the gate insulating film 111 is made of the high-k material in a single-layer structure. It may be used as such, or it may be used as a laminated structure with a material that can be applied to the underlying insulating film 102.

[0105] Furthermore, it is preferable that the portion in contact with the oxide semiconductor film 132 contains oxygen. Furthermore, the gate insulating film 111 may be an oxide insulating film or a film that releases oxygen upon heating. It is preferable.

[0106] After forming the gate insulating film 111, a second heat treatment is performed to form an island-shaped oxide semiconductor film 140 This forms (see Figure 2(D)). The second heat treatment involves hydrogen ( It releases water (containing hydroxyl groups or hydrides) and the underlying insulating film 102 and gate It releases some of the oxygen contained in the insulating film 111, and in the oxide semiconductor film 132, the underlying insulating film 10 Near the interface between 2 and the oxide semiconductor film 132, and between the oxide semiconductor film 132 and the gate insulating film 1 Oxygen can be diffused near the interface with 11. In other words, the second heat treatment is oxide Oxygen vacancies in the semiconductor film 132, interface states between the underlying insulating film 102 and the oxide semiconductor film 132, Furthermore, the interface state between the oxide semiconductor film 132 and the gate insulating film 111 can be reduced. .

[0107] The conditions and apparatus for the second heat treatment are appropriately configured to match the conditions and apparatus applicable to the first heat treatment. Use it.

[0108] Furthermore, the second heat treatment may be performed in conjunction with the first heat treatment, but the first heat treatment and By performing both the first and second heat treatments, the above interface states and the above oxygen deficiencies can be efficiently reduced. It is possible.

[0109] Next, a conductive film is applied to the gate insulating film 111 using a conductive material that can be applied to the first electrode 113. Form 112 (see Figure 3(A)). The thickness of the conductive film 112 is determined by the electrical conductivity of the conductive material described below. The optimal setting can be determined appropriately, taking into account factors such as air resistance and the time required for the manufacturing process. For example, 10nm It is sufficient to form it at a wavelength of 500 nm or less.

[0110] Conductive materials applicable to the first electrode 113 include aluminum, titanium, chromium, nickel, From copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten The conductive material is a single metal or an alloy in which it is the main component. Using materials, it is formed as a single-layer or multi-layer structure. For example, aluminum containing silicon A single-layer structure of aluminum film, a double-layer structure with a titanium film laminated on an aluminum film, and a tungsten film. A two-layer structure with a titanium film laminated on top, and a copper film laminated on top of a copper-magnesium-aluminum alloy film. It has a two-layer structure, a titanium film and an aluminum film layered on top of the titanium film, and further... There is a three-layer structure or the like in which a titanium film is formed on it. In addition, a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

[0111] Next, a resist mask is formed on the conductive film 112 by a photolithography process, and using the resist mask, the conductive film 112 is etched into a desired shape to form the first electrode 113 (see Fig. 3(B)). The first electrode 113 may be configured to function as at least a gate electrode and also as a gate wiring. Note that the resist mask can be appropriately formed by an inkjet method, a printing method, or the like in addition to the photolithography process, and the etching can be appropriately dry etching or wet etching similar to that when processing the oxide semiconductor film 130. <( <(

[0112] Also, the conductive films that become the gate insulating film 111 and the first electrode 113 are preferably formed continuously without being exposed to the atmosphere.

[0113] Also, between the first electrode 113 and the gate insulating film 111, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, a Sn-O film containing nitrogen, an In-O film containing nitrogen, a metal nitride film (InN, ZnN, etc.) are preferably provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and in the electrical characteristics of the transistor 100, the threshold voltage can be made positive, and the transistor 100 can be made a so-called normally-off transistor. For example, when using an In-Ga-Zn-O film containing nitrogen, at least A higher nitrogen concentration than oxide semiconductor film 140, specifically 7 atomic percent or more of In-Ga-Zn- O membrane is used.

[0114] Next, the oxide semiconductor film 140 is subjected to a process of adding the dopant 150 (see Figure 3(C)). ).

[0115] The dopant 150 to be added shall be a Group 15 element or boron, specifically phosphorus, arsenic, and One or more selected from antimony and boron. As a method for adding dopant 150 to conductive film 140, ion doping or ion doping is used. The implantation method can be used.

[0116] By using ion doping or ion implantation, dopant 1 The doping depth (doping region) of 50 becomes easier to control, and the dopant 15 is added to the oxide semiconductor film 140. It is possible to add zero with high precision. Furthermore, ion doping or ion implantation methods are available. When adding dopant 150 by the tapping method, the substrate 101 is heated while the dopant is added. That's good too.

[0117] The process of adding the dopant 150 to the oxide semiconductor film 140 may be performed multiple times. When the process of adding dopant 150 to oxide semiconductor film 140 is performed multiple times, The element T150 can be the same element in all multiple processes, or it can be changed each time the process is completed. stomach.

[0118] When adding the dopant 150 to the oxide semiconductor film 140, the first electrode 113 is used as a mask. The dopant 150 functions in the oxide semiconductor film 140 in the region overlapping with the first electrode 113. No substance is added, and a first region 105, which becomes a channel-forming region, is formed.

[0119] Furthermore, the area to which Dopant 150 was added was damaged by the addition of Dopant 150. Crystallinity is reduced, resulting in an amorphous region. By adjusting the amount of dopant 150 added, This reduces the amount of damage and prevents the formation of completely amorphous regions. Yes, it is possible. In other words, the region to which dopant 150 is added is at least the same as the first region 105. This region has a large proportion of amorphous areas. It is better not to make it a completely amorphous region for the next step. This is preferable because crystallization by the third heat treatment can be easily carried out.

[0120] Next, after adding dopant 150, a third heat treatment is performed. As a result, the region to which dopant 150 is added contains the dopant and multiple crystalline parts It can be made into a pair of second regions 123a and 123b, which are oxide semiconductor regions having (See Figure 3(D)).

[0121] The pair of second regions 123a and 123b function as the source region and drain region. Furthermore, an oxide semiconductor having multiple crystalline portions which are a pair of second regions 123a and 123b. The region is different from the first region 105, which is CAAC-OS. Furthermore, the third heat treatment This can also improve the crystallinity of CAAC-OS, which is the first region 105.

[0122] The temperature of the third heat treatment is 450°C or higher and below the substrate strain point temperature, preferably 650°C or higher. The temperature should be kept below the plate strain point, and the process should be carried out under reduced pressure, an oxidizing atmosphere, or an inert atmosphere. In this case, the oxidizing atmosphere is defined as an oxidizing gas such as oxygen, ozone, or oxygen nitride at a concentration of 10 ppm or higher. refers to the atmosphere it contains. The inert atmosphere means that the aforementioned oxidizing gas is less than 10 ppm, and in addition, it refers to an atmosphere filled with nitrogen or a noble gas. The treatment time is 1 hour to 24 hours and is set as such. Heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity.

[0123] The heating device used for the third heat treatment can be the device applicable to the first heat treatment and the second heat treatment.

[0124] Thus, with the first electrode 113 as a mask, the dopant 150 is added to the oxide semiconductor film 14 0, and then, by performing the third heat treatment, the first region 105 that becomes the channel formation region and the pair of second regions 123a and 123b that become the source region and the drain region can be formed in self - alignment.

[0125] Next, an insulating film that becomes the interlayer insulating film 117 is formed on the gate insulating film 111 and the first electrode 113, and a resist mask is formed on the insulating film that becomes the interlayer insulating film 117 by a photolithography process. Using the resist mask for etching, openings 116a and 116b are formed (see Fig. 4(A)). Note that the resist mask can be appropriately formed by an inkjet method, a printing method, etc. in addition to the photolithography process, and the etching can appropriately use dry etching or wet etching similar to when processing the oxide semiconductor film 130.

[0126] For the interlayer insulating film 117, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film or a silicon nitride film can be used and formed by a sputtering method, a CVD method, etc. At this time ​​​Therefore, it is preferable to use a film that does not easily release oxygen when heated for the interlayer insulating film 117. This is to prevent a decrease in the conductivity of the pair of second regions 123a and 123b. This involves using the CVD method, with silane gas as the main material, and nitrogen oxide gas, nitrogen gas, and hydrogen gas. The film can be formed by mixing appropriate source gases from noble gases. Also, the substrate temperature should be kept below 300°C. The temperature should be kept below 550°C. Using the CVD method minimizes oxygen release during heating. It can be formed into a membrane.

[0127] Next, through the openings 116a and 116b, it comes into contact with a pair of second regions 123a and 123b. A conductive film is formed in this manner, and a resist mask is applied to the conductive film by a photolithography process. A resist mask is formed, and the conductive film is etched using the resist mask, and the second electrode 119a and Then the third electrode 119b is formed (see Figure 4(B)). Note that the second electrode 119a and The third electrode 119b can be formed in the same manner as the first electrode 113.

[0128] The second electrode 119a and the third electrode 119b each have at least the source electrode and It functions as both a drain electrode and a source and drain wire. .

[0129] Based on the above, transistor 100 can be manufactured.

[0130] <Modification 1 of transistor 100> Furthermore, the third heat treatment is performed at a temperature of 550°C or higher but below the substrate strain point temperature, and in an oxidizing atmosphere. And within a pair of second regions 123a, 123b, there are multiple dopants 150 and On oxide semiconductor regions 109a and 109b having crystalline parts, a dopant 150 is provided. , and forming non-single-crystal oxide semiconductor regions 107a and 107b having c-axis oriented crystalline portions. It is possible.

[0131] In this case, the top view of the completed transistor 160 is shown in Figure 5(A). Furthermore, Figure Figure 5(B) shows a cross-sectional view of 5(A) between A and B.

[0132] A pair of second regions 123a and 123b of transistor 160 contain dopant 150. Furthermore, non-single-crystal oxide semiconductor regions 107a, 107b having c-axis oriented crystalline portions, and an oxide semiconductor region 109a having a dopant 150 and a plurality of crystalline portions. , is composed of 109b (see Figure 5(B)). Note that oxide semiconductor region 107a, The dopant concentrations in 107b and the oxide semiconductor regions 109a and 109b are the same.

[0133] Furthermore, the second electrode 119a and the third electrode 119b are separated by openings 116a and 116b. It is in contact with oxide semiconductor regions 107a and 107b. Other aspects of transistor 160 The configuration is the same as that of transistor 100.

[0134] Furthermore, when the third heat treatment is performed for 1 hour under the above conditions, the oxide semiconductor region 107a, 107b is a pair of second regions 123a, from the upper surface of 123b to the pair of second regions 123a , at least 2 nm is formed in the direction of the lower surface of 123b. Also, a third process is carried out under the above conditions. By increasing the heat treatment time, the oxide semiconductor regions 107a and 107b can be thickened. It can be formed.

[0135] And in transistors 100 and 160, a pair of second regions 123a, The only difference is the configuration of 123b; the explanation for transistor 100 is the same as for transistor 16. This also applies to 0.

[0136] In transistor 160 as well, the band in the channel formed in the first region 105 It shows the effect of reducing the curvature at the ends, and transistor 160 has a threshold voltage in the negative direction. The effects caused by shortening the channel length, such as fluctuations, can be reduced. Furthermore, a pair The second regions 123a and 123b are in contact with the second electrode 119a and the third electrode 119b. The contact resistance and the resistance component in the channel direction of the pair of second regions 123a and 123b are Because it is reduced, the on-current of transistor 160 can be increased.

[0137] Furthermore, transistor 160 has a pair of second regions 123a and 123b which are oxide semiconductor regions. Since these are regions 107a, 107b and oxide semiconductor regions 109a, 109b, let's assume that Compared to the case where the pair of second regions 123a and 123b are amorphous regions, the time before and after light irradiation If the threshold voltage fluctuation before and after the BT (gate thermal bias) stress test is small, It is a well-considered and reliable transistor.

[0138] <Modification of transistor 100, part 2> When forming the first electrode 113 in the method for fabricating transistor 100, the gate insulating film 111 By etching simultaneously, the first region 105 of the oxide semiconductor film 103 is etched. An insulating film 121 can be provided.

[0139] In this case, the top view of the completed transistor 170 is shown in Figure 6(A). Furthermore, Figure Figure 6(B) shows a cross-sectional view of 6(A) between A and B. Top view structure of transistor 170 This is similar to transistor 100, and is a top-gate structure and top-contact structure transistor. He is a genista.

[0140] Furthermore, the shape of the gate insulating film 111 differs between transistor 100 and transistor 170. They are only different; the explanation for transistor 100 also applies to transistor 170. It will be done.

[0141] In transistor 170 as well, the band in the channel formed in the first region 105 It shows the effect of reducing the curvature at the ends, and transistor 170 has a threshold voltage in the negative direction. The effects caused by shortening the channel length, such as fluctuations, can be reduced. Furthermore, a pair The second regions 123a and 123b are in contact with the second electrode 119a and the third electrode 119b. The contact resistance and the resistance component in the channel direction of the pair of second regions 123a and 123b are Because it is reduced, the on-current of transistor 170 can be increased.

[0142] Furthermore, the transistor 170 has a pair of second regions 123a and 123b having multiple crystalline portions. Since it is an oxide semiconductor region, if the pair of second regions 123a and 123b are amorphous Compared to cases in a qualitative area, the pre- and post-light irradiation and BT (gate thermal bias) stress tests The threshold voltage fluctuation before and after the test is considered small, indicating a highly reliable transistor. ru.

[0143] The method for fabricating transistor 170 will be explained using Figures 3, 7, and 8. Transistor 170 operates up to the step of forming the conductive film 112 (see Figure 3(A)). It is the same as the Ta100.

[0144] After forming the conductive film 112, the conductive film 112 and the gate insulating film 111 are etched. By doing this, the first electrode 113 and the first region of the oxide semiconductor film 103 that is later formed A gate insulating film 121 can be formed superimposed only on region 105 (see Figure 7(A)). ).

[0145] Furthermore, since the gate insulating film 121 is in contact only with the first region 105, the oxide semiconductor film 1 It is not provided along the shape (step) of 40. In other words, the gate insulating film 121 is There are no parts that overcome the step in the oxide semiconductor film 140. Therefore, the completed transistor In the ZISTA 170 as well, the gate insulating film 121 overcomes the step of the oxide semiconductor film 103. Because there is no part that is broken, leakage current caused by breaks in the gate insulating film 121 is reduced. Furthermore, the breakdown voltage of the gate insulating film 121 can be increased. Even when the material is thinned to nearly 5nm, transistor 170 can still be operated. Oh, by thinning the gate insulating film 121, the effects caused by shortening the channel length are... This can reduce noise and increase the operating speed of the transistor.

[0146] Furthermore, transistor 170 has no portion where the gate insulating film 121 crosses over a step. Therefore, the parasitic capacitance that occurs between the first electrode 113 and the pair of second regions 123a and 123b Almost none. Therefore, even when the channel length of transistor 170 is reduced, This can reduce fluctuations in the threshold voltage.

[0147] From this point onward, the same process as for transistor 100 is performed to form transistor 170. This can be done. Furthermore, in transistor 170, the process of adding dopant 150 is Unlike transistor 100, the first electrode 113 is used as a mask, and the oxide semiconductor film 14 The 0 will be added with some of it exposed (see Figure 7(B)).

[0148] As in transistor 170, a portion of the oxide semiconductor film 140 is exposed, and the dopant When adding 150, the method of adding dopant 150 is ion doping or Other methods besides ion implantation can also be used. For example, the raw material to be added Plasma is generated in a gas atmosphere containing elements, and the additive (here, oxide semiconductor film 1) is used. 40) is a plasma treatment in which the plasma is irradiated. Examples of equipment include dry etching equipment, plasma CVD equipment, and high-density plasma CVD equipment. These can be used. Furthermore, the plasma treatment can be performed while heating the substrate 101. good.

[0149] Furthermore, in transistor 170, a third addition is performed after adding dopant 150. By performing the heat treatment at a temperature above 550°C but below the substrate strain point temperature, and in an oxidizing atmosphere, dopant is produced. The oxide semiconductor regions 109a and 109b, which contain 150 and have multiple crystalline parts, are located on top of the oxide semiconductor region 109a and 109b. Non-single-crystal oxide semiconductor region containing -Pant 150 and having c-axis oriented crystalline portion A pair of second regions 123a, 123b are formed, provided with 107a, 107b. It is possible (see Figure 8). Note that the symbols in Figure 8 refer to transistor 100 (see Figure 1), Corresponding to the codes of transistor 160 (see Figure 5) and transistor 170 (see Figure 6). do.

[0150] Thus, in one aspect of the disclosed invention, the problems associated with miniaturization can be resolved. As a result, it becomes possible to significantly reduce the size of the transistor. By making the size sufficiently small, the area occupied by the semiconductor device becomes smaller, thus reducing the semiconductor The number of components in the device increases. This reduces the manufacturing cost per semiconductor device. Furthermore, since semiconductor devices are miniaturized while maintaining equivalent functionality, if the size is kept to a similar level... This makes it possible to realize semiconductor devices with even greater functionality. Also, the channel length By reducing the size, it is also possible to obtain benefits such as faster operation and lower power consumption. In other words, disclosure In one aspect of the invention, miniaturization of transistors using oxide semiconductors is achieved. And it is possible to obtain various effects associated with this. Note that this embodiment is not applicable to other embodiments. The form of application and the examples can be combined as appropriate.

[0151] (Embodiment 2) In this embodiment, the structure and manufacturing method of transistor 200, which is another aspect of the present invention, are described. This will be explained using Figures 9 to 14. Transistor 200 is described in Embodiment 1. Compared to the transistor 100 shown above, the sidewall insulating film is located on the end face of the first electrode 113. 215 is provided, and the first region 105 and a pair of second regions of the oxide semiconductor film 103 A pair of third regions 223a and 223b are provided between regions 123a and 123b. The matter is different.

[0152] Furthermore, transistor 200 is another embodiment of the present invention and will be described in Embodiment 1. The same principles apply to this embodiment as well.

[0153] <Structure and characteristics of transistor 200> Figure 9(A) is a top view of transistor 200. Note that in Figure 9(A), the base insulation... The edge film 102, gate insulating film 111, and interlayer insulating film 117 are not shown for convenience.

[0154] From Figure 9(A), the first electrode 113 is located in the first region 105 (not shown) and a pair of second regions Including regions 123a, 123b, and a pair of third regions 223a, 223b (not shown). It is provided on the oxide semiconductor film 103. Sidewall insulation is provided on the side surface of the first electrode 113. A border film 215 is provided. The second electrode 119a and the third electrode 119b are provided on a pair of second regions 123a, 123b via openings 116a, 116b Furthermore, the second electrode 119a and the third electrode 119b are located in a pair of second regions 12 It is in contact with the top surfaces of 3a and 123b. Transistor 200 has a top gate structure and is top It is a transistor with a contact structure.

[0155] Figure 9(B) is a cross-sectional view of transistor 200 between points A and B. From Figure 9(B), A base insulating film 102 is provided on the substrate 101, and on the base insulating film 102, the first region Region 105, a pair of second regions 123a, 123b and a pair of third regions 223a, 22 An oxide semiconductor film 103 containing 3b is provided. A pair of second regions 123a, 123 b is provided opposite via the first region 105. A pair of third regions 223a, 2 23b is provided between the first region 105 and the pair of second regions 123a and 123b. It is.

[0156] A gate insulating film 111 is provided on the oxide semiconductor film 103. A first electrode 113 is provided superimposed on the first region 105. Sidewall insulating films 215 are provided in contact with both sides of 3.

[0157] On the gate insulating film 111, the first electrode 113, and the sidewall insulating film 215, interlayer An insulating film 117 is provided.

[0158] The second electrode 119a and the third electrode 119b are openings provided in the interlayer insulating film 117 It is provided in contact with a pair of second regions 123a and 123b via 116a and 116b. The gate insulating film 111 consists of a first region 105 and a pair of second regions 123a, 12 It is in contact with 3b and a pair of third regions 223a and 223b.

[0159] The ends of the second electrode 119a and the third electrode 119b may be tapered, The end of the first electrode 113 is preferably vertical. The structure is vertical, and an insulating film that will become the sidewall insulating film 215 is formed on the first electrode 113. Furthermore, by performing highly anisotropic etching, the sidewall insulating film 215 is formed. Because it is possible.

[0160] Furthermore, as will be explained in more detail later, Figures 9(A) and 9(B) show a pair of third regions 223a , 223b is in the region where the oxide semiconductor film 103 overlaps with the sidewall insulating film 215. It is in contact with the sidewall insulating film 215 and the gate of the first electrode 113. At least a portion of the region other than the area in contact with the insulating film 111 has a curved shape.

[0161] The oxide semiconductor film 103 is selected from In, Ga, Sn, and Zn, as in Embodiment 1. The metal oxide contains two or more elements and has a wide band gap. This allows us to reduce the off-current of transistor 200.

[0162] Furthermore, in transistor 200, the first region 105 functions as a channel formation region. Furthermore, it is CAAC-OS and has a reduced hydrogen concentration. Therefore, Transis The Ta200 was used before and after light irradiation and before and after BT (gate thermal bias) stress testing. Furthermore, due to the small fluctuation in threshold voltage, it has stable electrical characteristics and is a highly reliable transistor. He can be called a star.

[0163] The pair of second regions 123a and 123b are the same as in Embodiment 1, and if the pair of second regions Regions 123a and 123b are CAACs that do not contain dopants, similar to the first region 105. -If it is OS (all oxide semiconductor film 103 does not contain dopants CAAC- It has higher conductivity compared to the case of OS. Also, a pair of third regions 223a, 223b In this region as well, it contains a dopant, similar to the pair of second regions 123a and 123b, and The power is high. In other words, the resistive component in the channel direction of the oxide semiconductor film 103 is reduced. This allows for an increase in the on-current of transistor 200.

[0164] Furthermore, in transistor 200, a pair of second regions 123a, 123b and a pair The conductivity and dopant concentration of the third regions 223a and 223b are the same as in Embodiment 1. This is within a certain range, and increasing the dopant concentration too much will reduce conductivity, which can lead to problems. The ON current of the 200 converter decreases.

[0165] Therefore, a pair of second regions 123a, 123b and a pair of third regions 223a, 223 The dopant concentration of b is 5 × 10 18 cm -3 The above 1 x 10 22 cm -3 The following This is preferable. Furthermore, the dopant concentrations of a pair of second regions 123a and 123b are a pair The dopant concentrations are higher in the third region 223a and 223b. Specifically, the pair of second regions The dopant concentrations in regions 123a and 123b are 5 × 10⁻⁶. 20 cm -3 The above 1 x 10 22 cm -3 The following dopant concentrations were set for the pair of third regions 223a and 223b: 5 × 10⁻¹⁰ 18 cm -3 The above 5 x 10 21 cm -3 It is preferable to keep the concentration of these dopants below a certain level. The difference in degree is because transistor 200 is provided with a sidewall insulating film 215. Self-alignment is formed during the dopant addition process.

[0166] Transistor 200 has a pair of second regions 123a and 123b, and the second region 123 Between a and the first region 105, the third region 22 of the pair of third regions 223a and 223b 3a is set up with a third region 223b between the second region 123b and the first region 105. By doing so, the electric field applied to the first region 105 can be mitigated. A pair of second regions Regions 123a and 123b function as the source region and drain region, respectively. The third regions 223a and 223b function as electric field relaxation regions.

[0167] In detail, of the pair of second regions 123a and 123b, the second region 123a and the first region Between region 105, of the pair of third regions 223a and 223b, the third region 223a is the second By providing a third region 223b between region 123b and the first region 105, There is almost no bending of the band edges in the channel formed in the first region 105. Therefore, transistor 200 is affected when the threshold voltage fluctuates in the negative direction, etc. The effects caused by shortening the flannel length can be reduced.

[0168] Then, the pair of second regions 123a and 123b are the second electrode 119a and the third electrode The reduced contact resistance with 119b increases the on-current of transistor 200. It is possible.

[0169] <Method for fabricating transistor 200> Next, the method for fabricating transistor 200 will be explained using Figures 2, 3, and 10. ru.

[0170] Regarding the fabrication method of transistor 200, oxygen is diffused and the hydrogen concentration is sufficiently reduced. The process of forming the oxide semiconductor film 140 and the gate insulating film 111 (Figure 2(D)) (corresponding process), and conductive material applicable to the first electrode 113 on the oxide semiconductor film 140. Up to the step of forming the conductive film 112 using the material (the step corresponding to Figure 3(A)), Since it is the same as Zista 100, you can refer to Embodiment 1.

[0171] Next, a photolithography process is performed to form a resist mask on the conductive film 112, The first electrode 113 is formed by etching using a resist mask (see Figure 10(A)). (Illuminate). The etching is performed so that the end of the first electrode 113 has a vertical shape, as described above. Therefore, it is preferable to perform highly anisotropic etching. As for highly anisotropic etching conditions It is preferable that the selectivity ratio of the conductive film 112 to the resist mask is extremely high.

[0172] Next, the oxide semiconductor film 140 is subjected to a process of adding dopant 150 (first dopant addition). The process is carried out (see Figure 10(B)). Note that in the first dopant addition process, The types of dopant 150 (elements to be added) and the method of adding dopant 150 are as follows: This is the same as form 1.

[0173] In the first dopant doping treatment, the first electrode 113 functions as a mask, and the dopant The 150 passes through the gate insulating film 111 and is added to the oxide semiconductor film 140. Then, oxide semiconductor regions 214a and 214b to which dopant 150 is added are formed. Furthermore, since it is not added to the region overlapping with the first electrode 113 of the oxide semiconductor film 140, Region 105 of 1 is formed.

[0174] Next, a sidewall insulating film 215 is formed. The sidewall insulating film 215 is formed under the substrate insulating film. It is formed of either the edge film 102 or the gate insulating film 111 as described above.

[0175] Transistor 200 has a first region 105, a pair of second regions 123a, 123b and In either of the pair of third regions 223a and 223b, the gate insulating film 111 They are provided in contact with each other. To achieve this structure, the gate insulating film 111 and the side wall The insulating film 215 can be an insulating film with a different etching rate. When forming the sidewall insulating film 215, the gate insulating film 111 is etched to stop It can function as a part. The gate insulating film 111 can be used as an etching stopper. By using this method, excessive etching of the oxide semiconductor film 140 can be suppressed. Furthermore, the etching endpoint (endpoint) when forming the sidewall insulating film 215 The gate can also be easily detected. Furthermore, the gate insulating film 111 functions as an etching stopper. By doing so, the width of the sidewall insulating film 215 (sidewall insulating film 2 in Figure 9(B) The width of the area where 15 is in contact with the gate insulating film 111 becomes easier to control. A pair of third regions The ranges of regions 223a and 223b are determined by the width of the sidewall insulating film 215. Increasing the size of the third pair of regions 223a and 223b will increase the channel formation region. The electric field applied to a certain first region 105 can be relaxed.

[0176] First, a sidewall insulating film 215 and An insulating film 114 is formed (see Figure 10(C)). The insulating film 114 is the underlayer insulating film 102 Alternatively, it can be formed in the same manner as the gate insulating film 111, and nitrogen as described in Embodiment 1. It is preferable to use any of the ionized insulating films. Furthermore, the thickness of the insulating film 114 is not particularly limited. However, the appropriate material should be selected considering the coverage of the shape of the first electrode 113.

[0177] The sidewall insulating film 215 is formed by etching the insulating film 114. The etching is a highly anisotropic etching, and the sidewall insulating film 215 is an insulating film 1 By performing a highly anisotropic etching process in step 14, a self-aligned structure can be formed. Here, dry etching is preferred as the highly anisotropic etching method, for example, As a chugging gas, trifluoromethane (CHF3), octafluorocyclobutane ( Fluorine-containing gases such as C4F8 and tetrafluoromethane (CF4) can be used. Even if you add noble gases such as helium (He) or argon (Ar) or hydrogen (H2) Good. Furthermore, as a dry etching method, a high-frequency voltage is applied to the substrate, and reactive ions are used. It is preferable to use the etching method (RIE method).

[0178] Furthermore, the dopant concentrations in the pair of third regions 223a and 223b that are formed later are on the side Corresponding to the thickness of the wall insulating film 215, a pair of third regions 223a and 223b The thickness of the sidewall insulating film 215 is adjusted so that the dopant concentration is as described above. To determine this, we need to decide the thickness of the first electrode 113. Note that the sidewall insulating film 21 The thickness of 5 refers to the sidewall insulating film 215 in contact with the gate insulating film 111. This refers to the area from the surface to the highest point of the surface in contact with the first electrode 113.

[0179] Furthermore, the range of the pair of third regions 223a and 223b is the width of the sidewall insulating film 215. The width of the sidewall insulating film 215 is determined in accordance with the thickness of the first electrode 113. Therefore, the range of the pair of third regions 223a and 223b becomes the desired range. Next, we need to determine the thickness of the first electrode 113.

[0180] Next, the process of adding dopant 150 to oxide semiconductor regions 214a and 214b (second The dopant addition process is performed (see Figure 10(D)). Note that there are 150 types of dopants (addition). The method for adding the elements and dopant 150 is the same as in Embodiment 1.

[0181] In the second dopant doping treatment as well, the first electrode 113 functions as a mask, and the dopant The 150 passes through the gate insulating film 111 and the sidewall insulating film 215, and oxide It is added to semiconductor regions 214a and 214b. The added dopant 150 is From the region where the additive passes only through the gate insulating film 111, the gate insulating film 111 and the side The region where the additive passes through the Dowall insulating film 215 is smaller. Therefore, the oxide semiconductor A dopant concentration difference can be self-aligned between body regions 214a and 214b.

[0182] In this embodiment as well, the region to which dopant 150 is added is the region to which dopant 150 is added The added damage reduces crystallinity, resulting in an amorphous region. Amount of dopant 150 to add. By adjusting these factors, the amount of damage can be reduced and it can be prevented from becoming a completely amorphous region. It can also be formed in such a way. In other words, the region to which dopant 150 is added is at least the This means that the proportion of amorphous regions is greater than that of region 105. Preventing the formation of the crystalline region facilitates crystallization during the subsequent third heat treatment. ,preferable.

[0183] Next, a third heat treatment is performed, similar to the process for manufacturing transistor 100, and dopant 15 The region to which 0 is added is an oxide semiconductor region containing a dopant and having multiple crystalline parts. A pair of second regions 123a, 123b and a pair of third regions 223a, 223 b can be used (see Figure 10(E)). Note that the heating conditions and processing for the third heat treatment may vary. The heating device is the same as described in Embodiment 1.

[0184] In this way, the first electrode 113 is used as a mask, and the dopant 150 is applied to the oxide semiconductor film 14 By adding to 0 and then performing a third heat treatment, the first region which becomes the channel-forming region is formed. 105 and a pair of second regions 123a, 123b which will be the source region and drain region. A pair of third regions 223a and 223b, which become electric field relaxation regions, are formed in a self-aligned manner. It is possible to do so.

[0185] Subsequently, the interlayer insulating film 117 is formed in the same manner as the manufacturing process for transistor 100, and the gate insulating film is formed. Openings 116a and 116b are formed in the edge film 111 and the interlayer insulating film 117, and opening 116 a, 116b, and a second electrode 119a in contact with a pair of second regions 123a, 123b and a third electrode 119b is formed. Note that the interlayer insulating film 117, openings 116a, 11 The steps of forming 6b, the second electrode 119a and the third electrode 119b are performed in Embodiment 1. This is similar to the previous explanation.

[0186] Based on the above, transistor 200 can be fabricated (see Figure 9).

[0187] Furthermore, the above refers to the first dopant addition treatment and the second dopant addition treatment, Two dopant addition treatments were performed. However, before the first dopant addition treatment... Then, a sidewall insulating film 215 is formed, and then, to achieve the desired dopant concentration... A dopant doping treatment may be performed to form the transistor 200. Pant concentration refers to the pair of second regions 123a, 123b and one pair of transistors 200. These are the dopant concentrations in the third region, 223a, and 223b.

[0188] <Modification 1 of Transistor 200> Furthermore, the third heat treatment is performed at a temperature of 550°C or higher but below the substrate strain point temperature, and in an oxidizing atmosphere. And within a pair of second regions 123a, 123b, there are multiple dopants 150 and On oxide semiconductor regions 109a and 109b having crystalline parts, a dopant 150 is provided. , and forming non-single-crystal oxide semiconductor regions 107a and 107b having c-axis oriented crystalline portions. This can be achieved, and in a pair of third regions 223a, 223b, dopant 150 A dopant is placed on oxide semiconductor regions 209a and 209b that contain and have multiple crystalline parts. Non-single-crystal oxide semiconductor region 207a containing 150 and having a c-axis oriented crystalline portion , 207b can be formed.

[0189] In this case, a top view of the completed transistor 260 is shown in Figure 11(A). Furthermore, Figure 11(B) shows a cross-sectional view of the section between A and B in Figure 11(A).

[0190] A pair of second regions 123a and 123b of transistor 260 contain dopant 150. Furthermore, non-single-crystal oxide semiconductor regions 107a, 107b having c-axis oriented crystalline portions, and an oxide semiconductor region 109a having a dopant 150 and a plurality of crystalline portions. , is composed of 109b (see Figure 11(B)). Note that oxide semiconductor region 107a The dopant concentrations in 107b and the oxide semiconductor regions 109a and 109b are the same.

[0191] Furthermore, the pair of third regions 223a and 223b of transistor 260 are dopant 150 Non-single-crystal oxide semiconductor regions 207a, 20 having a c-axis oriented crystalline portion and including Oxide semiconductor region 2 comprising 7b and dopant 150, and having a plurality of crystalline portions. It consists of 09a and 209b (see Figure 11(B)).

[0192] As described above, the pair of third regions 223a and 223b are the pair of second regions 123a, Since the dopant concentration is lower than that of 123b, the oxide semiconductor regions 207a and 207b are The oxide semiconductor regions 209a and 209b are oxide semiconductor regions 107a and 107b and The dopant concentration is lower in the oxide semiconductor region 10⁹a and 10⁹b. The dopant concentrations in regions 207a and 207b and oxide semiconductor regions 209a and 209b are the same. That is the case.

[0193] Furthermore, the second electrode 119a and the third electrode 119b are separated by openings 116a and 116b. It is in contact with oxide semiconductor regions 107a and 107b. Other aspects of transistor 260 The configuration is the same as that of transistor 160.

[0194] Furthermore, when the third heat treatment is performed for 1 hour under the above conditions, the oxide semiconductor region 107a, 107b is a pair of second regions 123a, from the upper surface of 123b to the pair of second regions 123a , at least 2 nm is formed in the direction of the lower surface of 123b. Also, a third process is carried out under the above conditions. By increasing the heat treatment time, the oxide semiconductor regions 107a and 107b can be thickened. It can be formed.

[0195] And in transistors 200 and 260, a pair of second regions 123a, The only difference is the configuration of 123b and the pair of third regions 223a, 223b, The explanation relating to transistor 200 also applies to transistor 260.

[0196] In transistor 260 as well, the band in the channel formed in the first region 105 It shows the effect of reducing the curvature at the ends, and transistor 260 has a threshold voltage in the negative direction. The effects caused by shortening the channel length, such as fluctuations, can be reduced. Furthermore, the second Contact between electrode 119a and the third electrode 119b and the pair of second regions 123a and 123b The resistance can be reduced, and the on-current of transistor 260 can be increased.

[0197] Furthermore, transistor 260 has a pair of second regions 123a and 123b which are oxide semiconductor regions. Since these are regions 107a, 107b and oxide semiconductor regions 109a, 109b, let's assume that Compared to the case where the pair of second regions 123a and 123b are amorphous regions, the time before and after light irradiation If the threshold voltage fluctuation before and after the BT (gate thermal bias) stress test is small, It is a well-considered and reliable transistor.

[0198] <Modification 2 of Transistor 200> When forming the first electrode 113 in the method for fabricating transistor 200, the gate insulating film 111 By etching simultaneously, the first region 105 of the oxide semiconductor film 103 is etched. An insulating film 121 can be provided.

[0199] In this case, the top view of the completed transistor 270 is shown in Figure 12(A). Furthermore, Figure 12(B) shows a cross-sectional view between A and B in Figure 12(A). Above transistor 270 The surface structure is the same as transistor 200, with a top gate structure and a top contact structure. It is a transistor.

[0200] Furthermore, transistors 200 and 270 have different gate insulating film shapes. Furthermore, the explanation relating to transistor 200 also applies to transistor 270. .

[0201] Therefore, in transistor 270 as well, in the channel formed in the first region 105 This shows the effect of reducing the bending of the band edge, and transistor 270 has a threshold voltage of This reduces the effects caused by shortening the channel length, such as fluctuations in the negative direction. The second electrode 119a and the third electrode 119b and a pair of second regions 123a, 123 This reduces the contact resistance with b and increases the on-current of transistor 270. It is possible.

[0202] Furthermore, the transistor 270 has a pair of second regions 123a and 123b having multiple crystalline portions. Since it is an oxide semiconductor region, if the pair of second regions 123a and 123b are amorphous Compared to cases in a qualitative area, the pre- and post-light irradiation and BT (gate thermal bias) stress tests The threshold voltage fluctuation before and after the test is considered small, indicating a highly reliable transistor. ru.

[0203] The method for fabricating transistor 270 will be explained using Figures 3, 13, and 14. Transistor 270 is a transistor up to the step of forming the conductive film 112 (see Figure 3(A)). It is similar to the Zista 100.

[0204] After forming the conductive film 112, the conductive film 112 and the gate insulating film 111 are etched. And the first electrode 113 and the first region 105 of the oxide semiconductor film 103 that is formed later. A gate insulating film 121 can be formed that is superimposed only on the top (see Figure 13(A)).

[0205] Furthermore, since the gate insulating film 121 is in contact only with the first region 105, the oxide semiconductor film 1 It is not provided along the shape (step) of 40. In other words, the gate insulating film 121 is There are no parts that overcome the step in the oxide semiconductor film 140. Therefore, the completed transistor In the ZISTA 270 as well, the gate insulating film 121 overcomes the step of the oxide semiconductor film 103. Because there is no part that is broken, leakage current caused by breaks in the gate insulating film 121 is reduced. Furthermore, the breakdown voltage of the gate insulating film 121 can be increased. Even when the material is thinned to nearly 5nm, the transistor 270 can still be operated. Oh, by thinning the gate insulating film 121, the effects caused by shortening the channel length are... This can reduce noise and increase the operating speed of the transistor.

[0206] Furthermore, transistor 270 has no portion where the gate insulating film 121 crosses over a step. Therefore, the first electrode 113 and a pair of second regions 123a, 123b and a pair of third regions 2 There is almost no parasitic capacitance between 23a and 223b. Therefore, transistor 27 A value of 0 can reduce threshold voltage fluctuations even when the channel length is reduced. .

[0207] Next, the first dopant addition procedure is performed (see Figure 13(B)). The process can be carried out in the same manner as for transistor 200. By the first dopant doping process Then, oxide semiconductor regions 214a and 214b with dopant 150 added are formed. .

[0208] Next, an insulating film 114, which will become the sidewall insulating film 215, is formed (see Figure 13(C)). The insulating film 114 is formed in the same manner as the underlayer insulating film 102 or the gate insulating film 111. This can be achieved, and the oxide insulating film or nitride insulating film described in Embodiment 1 is one of them. Furthermore, there are no particular limitations on the thickness of the insulating film 114, but the coverage of the shape of the first electrode 113 is important. You should take that into consideration and make the appropriate choice.

[0209] Similar to transistor 200, the sidewall is formed by etching the insulating film 114. An insulating film 215 is formed. Details of the etching process can be found above.

[0210] Furthermore, the thickness of the sidewall insulating film 215 is determined in the sidewall insulating film 215, From the surface in contact with the oxide semiconductor film 140 which will become the oxide semiconductor film 103, the first electrode 1 This refers to the area up to the highest point of the surface in contact with 13. And then, the pair of third regions 22 that are formed later. The dopant concentrations of 3a and 223b correspond to the thickness of the sidewall insulating film 215. Therefore, the dopant concentrations of the pair of second regions 123a and 123b are determined at transistor 200. The thickness of the sidewall insulating film 215, and furthermore, the first electrode 11, are such that the values ​​described are obtained. All you need to do is determine the thickness of 3.

[0211] Furthermore, the range of the pair of second regions 123a and 123b is the width of the sidewall insulating film 215. (For example, the sidewall insulating film 215 in Figure 12(B) is in contact with the oxide semiconductor film 103) It is determined by the width of the area where it is located. The range of the pair of second regions 123a and 123b is enlarged. This reduces the electric field applied to the first region 105.

[0212] The width of the sidewall insulating film 215 corresponds to the thickness of the first electrode 113, The first electrode 11 is positioned such that the range of the pair of second regions 123a and 123b becomes the desired range. All you need to do is determine the thickness of 3.

[0213] Next, a second dopant doping process is performed. Note that in transistor 270, dopant The process of adding 150 differs from that of transistor 200 in that it masks the first electrode 113. The region where the film is added passing through the sidewall insulating film 215 and the oxide semiconductor film 140 There are regions where the material is added while partially exposed (see Figure 13(D)).

[0214] As in transistor 270, a portion of the oxide semiconductor film 140 is exposed, and the dopant When adding 150, the method of adding dopant 150 is ion doping or Other methods besides ion implantation can be used. For example, the raw material to be added Plasma is generated in a gas atmosphere containing elements, and the additive (here, oxide semiconductor film 1) is used. 40) is a plasma treatment in which the plasma is irradiated. Examples of equipment include dry etching equipment, plasma CVD equipment, and high-density plasma CVD equipment. These can be used. Furthermore, the plasma treatment can be performed while heating the substrate 101. good.

[0215] Subsequently, transistor 270 is fabricated by performing the same process as for transistor 200. This can be done (see Figure 12).

[0216] Furthermore, similar to transistor 200, before the first dopant doping process, side war A thin insulating film 215 is formed, and then dopants are added to achieve the desired dopant concentration. The transistor 270 may be formed by performing a process.

[0217] Furthermore, in transistor 270, a third addition is performed after adding dopant 150. By performing the heat treatment at a temperature above 550°C but below the substrate strain point temperature, and in an oxidizing atmosphere, dopant is produced. The oxide semiconductor regions 109a and 109b, which contain 150 and have multiple crystalline parts, are located on top of the oxide semiconductor region 109a and 109b. Non-single-crystal oxide semiconductor region containing -Pant 150 and having c-axis oriented crystalline portion A pair of second regions 123a, 123b are formed, provided with 107a, 107b. It is possible (see Figure 14). Note that the symbols in Figure 14 represent transistor 200, This corresponds to the codes of the zista 260 and transistor 270.

[0218] Thus, in one aspect of the disclosed invention, the problems associated with miniaturization can be resolved. As a result, it becomes possible to significantly reduce the size of the transistor. By making the size sufficiently small, the area occupied by the semiconductor device becomes smaller, thus reducing the semiconductor The number of components in the device increases. This reduces the manufacturing cost per semiconductor device. Furthermore, since semiconductor devices are miniaturized while maintaining equivalent functionality, if the size is kept to a similar level... This makes it possible to realize semiconductor devices with even greater functionality. Also, the channel length By reducing the size, it is also possible to obtain benefits such as faster operation and lower power consumption. In other words, disclosure By one aspect of the invention, miniaturization of transistors using oxide semiconductors is achieved. This makes it possible to obtain various effects associated with it. Note that this embodiment is not applicable to other embodiments. The form and examples can be combined as appropriate.

[0219] (Embodiment 3) In this embodiment, the structure and manufacturing method of a transistor, which is another aspect of the present invention, are described below. This will be explained using Figures 15 and 16.

[0220] The transistor described in this embodiment is the same as the transistor 100 described in Embodiment 1. In comparison, the second electrode 119a and the third electrode 119b are a pair of oxide semiconductor films. The difference is that it is in contact with the lower surfaces of regions 123a and 123b. In other words, in this embodiment The transistor shown is a top-gate and bottom-contact transistor. Furthermore, a cross-sectional view of the transistor with the top gate structure and bottom contact structure is shown. This is shown in Figure 15(A).

[0221] Furthermore, all transistors described in Embodiment 1 and Embodiment 2 are also included in the Top It can be made into a transistor with a bottom gate structure and a bottom contact structure. For example, In transistors 160 and 170, the top gate structure and bottom gate structure are also used. It can be made into a contact structure. Transistor 160 has a top gate structure and a bottom gate structure. Figure 15(B) shows a cross-sectional view of a transistor with a contact structure, with transistor 170 at the top. Figure 15(C) shows a cross-sectional view of a transistor with a bottom gate structure and bottom contact structure. vinegar.

[0222] Furthermore, transistor 200 has a top gate structure and a bottom contact structure. Figure 16(A) shows a cross-sectional view of the transistor, with transistor 260 having a top gate structure and a bottom gate structure. Figure 16(B) shows a cross-sectional view of a transistor with a contact structure, with transistor 270 at the top. Figure 16(C) shows a cross-sectional view of a transistor with a bottom gate structure and bottom contact structure. vinegar.

[0223] In Figures 15(A) to 15(C) and Figures 16(A) to 16(C), each reference numeral is: Transistor 100, transistor 160 and transistor 170, and transistor Since it corresponds to the codes of transistor 200, transistor 260, and transistor 270. For explanations of each reference numeral, please refer to the descriptions of Embodiment 1 and Embodiment 2 as appropriate. Furthermore, not only with respect to each reference numeral, but also what has been explained in Embodiment 1 and Embodiment 2 is relevant here. This also applies to the embodiments.

[0224] Furthermore, the transition shown in Figures 15(A) to 15(C) and Figures 16(A) to 16(C) The method for manufacturing the transistors involves rearranging the order of the manufacturing steps for each corresponding transistor. This can be done. For example, the process of forming the second electrode 119a and the third electrode 119b can be performed as follows: This process is performed after the step of forming the underlayer insulating film 102, and thereafter, the transistor 100, the transistor Transistor 160 and transistor 170, as well as transistors 200 and 260 and in the manufacturing process of transistor 270, the second electrode 119a and the third electrode 11 All steps except for the step of forming 9b should be carried out in order.

[0225] Note that in the transistors shown in Figures 15(C) and 16(C), the oxide semiconductor film 1 03 is a pair of second regions 123a, 123 as shown in Figures 15(B) and 16(B). b is an oxide semiconductor region 109a containing dopant 150 and having multiple crystalline portions. , a non-single crystal having a c-axis oriented crystalline portion containing dopant 150 on 109b. Configurations that provide oxide semiconductor regions 107a and 107b, or a pair of third regions 223a and 2 23b is an oxide semiconductor region 20 containing dopant 150 and having multiple crystalline portions. 9a and 209b have a non-single crystalline portion containing dopant 150 and having a c-axis oriented crystalline portion. A configuration may also be provided in which oxide semiconductor regions 207a and 207b of the crystal are provided. A cross-sectional view of the Zista is not shown.

[0226] Thus, in one aspect of the disclosed invention, the problems associated with miniaturization can be resolved. As a result, it becomes possible to significantly reduce the size of the transistor. By making the size sufficiently small, the area occupied by the semiconductor device becomes smaller, thus reducing the semiconductor The number of components in the device increases. This reduces the manufacturing cost per semiconductor device. Furthermore, since semiconductor devices are miniaturized while maintaining equivalent functionality, if the size is kept to a similar level... This makes it possible to realize semiconductor devices with even greater functionality. Also, the channel length By reducing the size, it is also possible to obtain benefits such as faster operation and lower power consumption. In other words, disclosure By one aspect of the invention, miniaturization of transistors using oxide semiconductors is achieved. This makes it possible to obtain various effects associated with it. Note that this embodiment is not applicable to other embodiments. It can be combined with other forms as appropriate.

[0227] (Embodiment 4) In this embodiment, the source region of the transistor shown in Embodiments 1 to 3 The dopant-added region functions as both a drain region and an electric field relaxation region. In this, the binding state of the dopant and the oxidation of the region to which the dopant is added. The electronic states of semiconductor materials will be explained with reference to Figures 17 and 18.

[0228] For example, in transistor 100, a pair of second regions which are regions containing a dopant. Regions 123a and 123b have higher conductivity than the first region 105, which does not contain the dopant.

[0229] This increase in conductivity is due to the oxide semiconductor constituting the pair of second regions 123a and 123b. It is expected that carriers will be generated in the oxide semiconductor due to the addition of a pant. can.

[0230] Therefore, in this embodiment, in an oxide semiconductor with a dopant-added structure, first principles First-Principles Molecular Dynamic Bonding state and electronic state of the oxide semiconductor by s:FPMD calculation and structural optimization calculation The state will be explained. The oxide semiconductor is an In-Ga-Zn-O type metal oxide. To simplify the above calculations, we assume that the In-Ga-Zn-O metal oxide is amorphous. (Hereafter referred to as a-IGZO). Furthermore, the dopant is a phosphorus (P) atom.

[0231] The above calculations were performed on α-IGZO with one phosphorus atom placed (added). Specifically, α-IGZO has 84 atoms per unit cell, and its composition ratio is In:Ga:Zn: The ratio of atoms is O=1:1:1:4, and the density is 5.9 g / cm³. -3 The lattice constant is a This assumes that b=c=1.02nm and α=β=γ=90°.

[0232] Furthermore, the calculation program used to perform the above calculations was a first-principles quantitative analysis program from Accelrys. The child dynamics program CASTEP was used. The functional used was GGA-PBE, and the pseudopotential The Ultrasoft was used for each component. The cutoff energy was 260 eV (DO In S-calculations, the energy is 380 eV, and the number of k points is 1 × 1 × 1. FPMD calculations use NVT ensemble. The calculation was performed using a bulldozer at a temperature of 1500K. The total calculation time was 0.3 ps, with a time step size of 1.0 fs. That is the case.

[0233] The initial structure in the above calculation and the final structure after the above calculation are shown in Figure 17. Figure 17(A) Figure 17(B) shows the initial structure, and Figure 17(B) shows the final structure. The initial structure is, This is equivalent to a structure in which phosphorus atoms are placed at arbitrary positions compared to a-IGZO. The structure refers to the structure after the above calculations have been performed, that is, the structure after structural optimization. The final structure after the optimization process is the transistor described in Embodiments 1 to 3. In this context, it corresponds to the structure of the oxide semiconductor region containing the dopant.

[0234] As shown in Figure 17(A), the phosphorus atom in the initial structure is one of the elements that make up α-IGZO. It is assumed that it is placed (added) in between. In Figure 17, the black circles represent oxygen atoms. The white circles represent metal atoms (In atoms, Zn atoms, or Ga atoms), and the gray circles represent phosphorus atoms. It represents

[0235] Based on the above calculations, the phosphorus atom in the final structure is "bonded to one Zn atom" and "bonded to two acids It forms a single bond with an elementary atom, and a double bond with one oxygen atom. In other words, phosphorus atom It is coordinated to the Zn atom while bonded to the oxygen atom (see Figure 17(B)).

[0236] Furthermore, the fact that the metal atom to which the phosphorus atom is bonded is a Zn atom is from the perspective of bond energy. This can be explained by:

[0237] The bond energy between a Zn atom and an oxygen atom is different from that of other metal atoms (In atoms and Ga atoms). Since the bond energy between the Zn atom and the oxygen atom is lower than that of the oxygen atom, the bond between the Zn atom and the oxygen atom is different from other bonds. It can be said that this bond is more easily broken than other bonds. Therefore, after structural optimization, the phosphorus atom is located around the periphery. It is thought that the oxygen atom will coordinate to the Zn atom. However, this does not mean that the phosphorus atom This indicates that it is most likely to bond with a Zn atom, and that the phosphorus atom will bond. The metal atoms are not limited to Zn atoms; they may also be other metal atoms that make up α-IGZO.

[0238] Next, Figure 18 shows the density of states diagram for the structure after structural optimization. Figure 18(A) shows the phosphorus atom. This is a density of states diagram for a-IGZO without the addition of (addition of) the substance. Also, see Figure 18(B). This involves arranging (adding) phosphorus atoms, and the resulting a-IGZO after structural optimization (corresponding to Figure 17(B)). This is a density of states diagram in ). The solid line in Figure 18(B) represents the arrangement (addition) of phosphorus atoms. Furthermore, the dashed line in Figure 18(B) represents the total density of states of a-IGZO after structural optimization. This shows the partial density of states of phosphorus atoms in the optimized α-IGZO. Figures 18(A) and 1. In both 8(B), the horizontal axis represents energy [eV], and the vertical axis represents the density of states in the structure after structural optimization. This represents [states / eV]. Note that either Figure 18(A) or Figure 18(B) is shown. In the density of states diagram, the energy origin is also taken at the Fermi level.

[0239] From Figure 18(A), the α-IGZO without phosphorus atoms in the total density of states is The lumino level coincides with the upper end of the valence band, and the conduction band is formed on the band gap. It is.

[0240] From Figure 18(B), the aI after optimizing the structure and arranging phosphorus atoms in the total density of states Since the Fermi level of GZO is within the conduction band, the a-IGZO It can be said that this is generated by the carrier. Furthermore, within the band gap of the a-IGZO, It can be seen that an energy level for the phosphorus atom is also being created.

[0241] From the above, when a dopant is added to an oxide semiconductor, It can be understood that a carriage is generated.

[0242] The configurations and methods shown in this embodiment are similar to those shown in other embodiments and examples. It can be used in combination with other elements as appropriate.

[0243] (Embodiment 5) In this embodiment, the transistor shown in any of Embodiments 1 to 3 is used. Let's explain an example of a semiconductor device.

[0244] Figure 20(A) shows the circuit diagram of a memory element (hereinafter also referred to as a memory cell) that constitutes a semiconductor device. An example is shown. The memory cell uses a material other than an oxide semiconductor in the channel formation region. Transistor 1160 and transistor 1162 using an oxide semiconductor as the channel formation region That's how it's structured.

[0245] The transistor 1162, which uses an oxide semiconductor in the channel formation region, follows the above embodiment. It can be made that way.

[0246] As shown in Figure 20(A), the gate electrode of transistor 1160 and transistor 116 It is electrically connected to either the source electrode or the drain electrode of the two. What are the wiring (1st Line: also called the source line) and the source electrode of the transistor 1160? , electrically connected, the second wiring (2nd Line: also called bit line) and the transistor The drain electrode of the TA1160 is electrically connected. And the third wiring (3rd Line (also called the first signal line) and the source electrode or drain of transistor 1162 The other electrode is electrically connected to the fourth wire (4th Line: also known as the second signal line). The gate electrode of transistor 1162 is electrically connected to the gate electrode.

[0247] Transitions using materials other than oxide semiconductors, such as single-crystal silicon, in the channel formation region Because transistor 1160 is capable of sufficiently high-speed operation, by using transistor 1160, It is possible to perform tasks such as reading stored data at high speed. Furthermore, oxide semiconductors are used as channels. The transistor 1162 used in the formation region has a smaller off-current compared to the transistor 1160. It has the characteristic of being such that by turning off transistor 1162 This makes it possible to maintain the potential of the gate electrode of transistor 1160 for an extremely long period of time. It is Noh.

[0248] By taking advantage of the characteristic that the potential of the gate electrode of transistor 1160 can be maintained, the following can be achieved: It is possible to write, store, and read information.

[0249] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 1162 turns on is set to turn on transistor 1162. This allows the potential of the third wiring to be applied to the gate electrode of transistor 1160. (Writing). After that, the potential of the fourth wire is set to the power at which transistor 1162 is in the off state. As a result, by turning off transistor 1162, transistor 1160 The potential of the gate electrode is maintained (held).

[0250] The off-current of transistor 1162 is smaller than that of transistor 1160, so The potential of the gate electrode of the 1160 is maintained for a long time. For example, a transistor If the potential of the gate electrode of transistor 1160 is the potential that turns on transistor 1160, then The transistor 1160 will remain in the ON state for an extended period of time. The potential of the gate electrode of transistor 1160 is the potential that turns transistor 1160 off. If transistor 1160 remains in the off state for an extended period of time, this will be achieved.

[0251] Next, we will explain how to read the information. As mentioned above, when transistor 1160 is ON When the state is maintained as either the "on" or "off" state, a predetermined potential (low potential) is applied to the first wiring. When this occurs, the potential of the second wiring depends on whether transistor 1160 is on or off. It takes different values. For example, when transistor 1160 is ON, the first wiring The potential of the second wiring will decrease relative to the potential of the first wiring. Also, transistor 1160 When the device is in the off state, the potential of the second wire does not change.

[0252] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. By doing so, information can be extracted.

[0253] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is controlled when transistor 1162 is ON. To achieve this potential, transistor 1162 is turned ON. This allows the third wiring to A potential (a potential related to new information) is applied to the gate electrode of transistor 1160. After that, the potential of the fourth wire is set to the potential at which transistor 1162 is in the off state. By turning off ZISTA 1162, the new information will be retained.

[0254] Thus, the memory cell relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices containing memory cells is achieved.

[0255] Furthermore, Figure 20(B) shows an example of a circuit diagram for a memory cell that is an advanced version of the memory cell shown in Figure 20(A). This will be shown.

[0256] The memory cell 1100 shown in Figure 20(B) has a first wiring SL (source line) and a second wiring BL (bit line), third wiring S1 (first signal line), and fourth wiring S2 (second signal line) And the fifth wiring WL (word wire), and transistor 1164 (the first transistor), Transistor 1161 (second transistor) and transistor 1163 (third transistor) It consists of transistor 1164 and transistor 1163. Furthermore, materials other than oxide semiconductors are used in the channel formation region, and transistor 1161 is acid A synthetic semiconductor is used in the channel formation region.

[0257] Here, the gate electrode of transistor 1164 and the source electrode of transistor 1161 It is electrically connected to one of the drain electrodes. Also, the first wiring SL and the transistor The source electrode of transistor 1164 is electrically connected to the drain of transistor 1164. The electrode and the source electrode of transistor 1163 are electrically connected. Wiring BL 2 and the drain electrode of transistor 1163 are electrically connected, and the third The wiring S1 and the other of the source electrode or drain electrode of transistor 1161 are electrically connected. The fourth wiring S2 is connected to the gate electrode of transistor 1161, and the gate electrode of transistor 1161 is electrically connected to it. The fifth wiring WL and the gate electrode of transistor 1163 are electrically connected. ru.

[0258] Next, I will explain the operation of the circuit in detail.

[0259] When writing to memory cell 1100, set the first wiring SL to 0V and the fifth wiring WL to Set the voltage to 0V, the second wire BL to 0V, and the fourth wire S2 to 2V. Write data "1" to this location. In this case, set the third wire S1 to 2V, and when writing data "0", set the third wire S1 to 0V. At this time, transistor 1163 is in the off state and transistor 1161 is in the on state. Yes. Furthermore, when writing is complete, before the potential of the third wiring S1 changes, the fourth Set wiring S2 to 0V and turn off transistor 1161.

[0260] As a result, after writing data "1", the gate electrode of transistor 1164 is connected to the Node.js. The potential of node A (hereinafter referred to as node A) is approximately 2V, and after writing data "0", the potential of node A is approximately The voltage becomes 0V. Node A accumulates a charge corresponding to the potential of the third wiring S1, but the transistor The off-current of the ZISTA 1161 is a transistor that uses single-crystal silicon in the channel formation region. Compared to that, it is small, and the potential of the gate electrode of transistor 1164 is maintained for a long time. ru.

[0261] Next, when reading the memory cell, set the first wiring SL to 0V and the fifth wiring WL to 2V. V, the fourth wire S2 is set to 0V, the third wire S1 is set to 0V, and it is connected to the second wire BL. The read circuit is set to the operating state. At this time, transistor 1163 is ON, The STA1161 will be turned off.

[0262] If the data is "0," meaning node A is at approximately 0V, then transistor 1164 is in the off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. On the other hand, data If node A is at approximately 2V, then transistor 1164 is ON. Therefore, the resistance between the second wiring BL and the first wiring SL will be low. The readout circuit is memo The data "0" and "1" can be read from the difference in the resistance state of the recell. The second wiring BL was set to 0V when connected, but it is charged to a floating state or a potential above 0V. It's okay if it's floating. The third wire S1 was set to 0V during reading, but it's floating. It is also acceptable if it is charged to a potential of 0V or higher.

[0263] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltages mentioned above are just examples. The operating voltage is such that when the data is "0", transistor 1 Transistor 164 is in the off state, and transistor 1164 is in the on state when the data is "1". Also, transistor 1161 is ON during writing and OFF at other times. If you select it so that the transistor 1163 turns ON when reading out, That's fine. In particular, instead of 2V, you can use the power supply potential VDD of the surrounding logic circuits.

[0264] In this embodiment, for the sake of ease of understanding, we will explain the smallest memory unit (1 bit) memory cell. As revealed, the configuration of memory cells is not limited to this. Multiple memory cells can be appropriately configured. They can also be connected to form more advanced semiconductor devices. For example, multiple of the above memory cells can be connected. Using these, it is possible to construct NAND and NOR type semiconductor devices. Wiring configuration Furthermore, the figures are not limited to Figures 20(A) and 20(B), and can be modified as appropriate.

[0265] Figure 21 shows a block of a semiconductor device according to one embodiment of the present invention having an m × n bit memory capacity. The circuit diagram is shown.

[0266] The semiconductor device shown in Figure 21 has m fifth wirings WL(1) to WL(m) and m fourth wirings Wiring S2(1)~S2(m) and n second wirings BL(1)~BL(n) and n The third wiring S1(1)~S1(n) and multiple memory cells 1100(1,1)~110 The numbers 0(m, n) are arranged in a matrix of m rows x n columns (m and n are natural numbers). It also has a memory cell array 1110. It also has a second wiring BL and a third wiring S1 The drive circuit 1111 that connects to the fourth wiring S2 and the drive circuit that connects to the fifth wiring WL It has peripheral circuits such as path 1113 and read circuit 1112. Other peripheral circuits include A fresh circuit or similar may be provided.

[0267] Let's consider memory cell 1100(i, j) as a representative of each memory cell. Here, memory cells Lu1100(i, j) (where i is an integer between 1 and m, and j is an integer between 1 and n) is the second Wiring BL(j), third wiring S1(j), fifth wiring WL(i) and fourth wiring S2( i) and the first wiring are connected respectively. The first wiring has the first wiring potential Vs The following is given: Also, the second wiring BL(1)~BL(n) and the third wiring S1(1 )~S1(n) is connected to the drive circuit 1111 and the read circuit 1112, and the fifth wiring WL(1) ~WL(m) and the fourth wiring S2(1)~S2(m) are connected to the drive circuit 1113 respectively. It continues.

[0268] The operation of the semiconductor device shown in Figure 21 will be explained. In this configuration, line by line writing and Perform a read operation.

[0269] When writing to memory cells 1100(i,1) to 1100(i,n) in the i-th row, Set the wiring potential Vs of wire 1 to 0V, the fifth wiring WL(i) to 0V, and the second wiring BL(1)~BL( Let n) be 0V and the fourth wiring S2(i) be 2V. At this time, transistor 1161 is The state is as follows. The third wiring S1(1)~S1(n) is the column where data "1" is written, which is 2V The column to which the data "0" is written will be set to 0V. Furthermore, when writing is complete, the third distribution Before the potential of lines S1(1) to S1(n) changes, set the fourth wire S2(i) to 0V, Turn off transistor 1161. Also, the unselected fifth wire WL is 0V, unselected. The fourth wire S2 is set to 0V.

[0270] As a result, the gate voltage of transistor 1164 of the memory cell that wrote data "1" The potential of the node connected to the pole (hereinafter referred to as Node A) is approximately 2V, and the data "0" is written. The potential at node A of the memory cell becomes approximately 0V (see Figures 20(B) and 21). The potential of node A in the unselected memory cell remains unchanged.

[0271] To read memory cells 1100(i,1) to 1100(i,n) in the i-th row, Set the potential of the first wiring Vs to 0V, the fifth wiring WL(i) to 2V, and the fourth wiring S2(i) to 0V. The third wiring S1(1)~S1(n) is set to 0V, and the second wiring BL(1)~BL(n) The connected read circuit is put into operation. In the read circuit, for example, the resistance of the memory cell is... Based on the difference in the resistance state, the data "0" or "1" can be read. Note that the 5th non-selected state The wiring WL is set to 0V, and the unselected fourth wiring S2 is also set to 0V. Note that the second wiring during writing... Although BL is set to 0V, it is acceptable for it to be in a floating state or charged to a potential above 0V. The third wiring S1 was set to 0V during reading, but it may be in a floating state or at a potential of 0V or higher. It's okay if it's electrified.

[0272] Note that the definitions of data "1" and data "0" are for convenience only, and they could be reversed. Furthermore, the operating voltages mentioned above are just examples. The operating voltage is such that when the data is "0", transistor 1 Transistor 164 is in the off state, and transistor 1164 is in the on state when the data is "1". Also, transistor 1161 is ON during writing and OFF at other times. If you select it so that the transistor 1163 turns ON when reading out, That's fine. In particular, instead of 2V, you can use the power supply potential VDD of the surrounding logic circuits.

[0273] The configurations and methods shown in this embodiment are similar to those shown in other embodiments and examples. It can be used in combination with other elements as appropriate.

[0274] (Embodiment 6) In this embodiment, an example of a circuit diagram of a memory cell having a capacitive element is shown. Figure 22(A) shows The memory cell 1170 shown has a first wiring SL, a second wiring BL, a third wiring S1, and a fourth wiring BL Wiring S2, the fifth wiring WL, transistor 1171 (the first transistor), and It consists of a transistor 1172 (the second transistor) and a capacitive element 1173. Transistor 1171 uses a material other than an oxide semiconductor in the channel formation region, The Rangista 1172 uses an oxide semiconductor in the channel formation region.

[0275] Here, the gate electrode of transistor 1171 and the source electrode of transistor 1172 One of the drain electrodes and one of the electrodes of the capacitive element 1173 are electrically connected. Furthermore, the first wiring SL and the source electrode of transistor 1171 are electrically connected. The second wiring BL and the drain electrode of transistor 1171 are electrically connected, The wiring S1 of 3 and the other of the source electrode or drain electrode of transistor 1172 are connected by electricity. The fourth wire S2 and the gate electrode of transistor 1172 are electrically connected. The fifth wiring WL and the other electrode of the capacitive element 1173 are electrically connected. Yes, they are.

[0276] Next, I will explain the operation of the circuit in detail.

[0277] When writing to memory cell 1170, set the first wiring SL to 0V and the fifth wiring WL to Set the voltage to 0V, the second wire BL to 0V, and the fourth wire S2 to 2V. Write data "1" to this location. In this case, set the third wire S1 to 2V, and when writing data "0", set the third wire S1 to 0V. At this time, transistor 1172 will be in the ON state. Then, before the potential of the third wiring S1 changes, the fourth wiring WL is set to 0V, and the transistor Turn off the Ta1172.

[0278] As a result, after writing data "1", it is connected to the gate electrode of transistor 1171. The potential of node A (hereinafter referred to as node A) is approximately 2V, and after writing data "0", the potential of node A The voltage becomes approximately 0V.

[0279] When reading from memory cell 1170, set the first wiring SL to 0V and the fifth wiring WL to With 2V, the fourth wire S2 set to 0V, the third wire S1 set to 0V, and connected to the second wire BL. The readout circuit is set to the operating state. At this time, transistor 1172 is in the off state. .

[0280] The state of transistor 1171 when the fifth wiring WL is set to 2V will be explained. The potential of node A, which determines the state of the inverter 1171, is the capacitance between the fifth wiring WL and node A. C1 and the capacitance C2 between the gate electrode-source electrode and the drain electrode of transistor 1171 To depend on.

[0281] Note that the third wiring S1 was set to 0V during reading, but it may be floating or at a potential of 0V or higher. It's fine if it's charged. Data "1" and data "0" are definitions for convenience, and the opposite is true. That's fine.

[0282] The potential of the third wire S1 during writing is such that transistor 1172 is in the off state after writing. Furthermore, when the potential of the fifth wiring WL is 0V, transistor 1171 is in the off state. Within the box, select the potentials for data "0" and "1" respectively. The fifth wiring WL power during reading... In the case of data "0", transistor 1171 is turned off, and in the case of data "1", You should select the transistor 1171 so that it is turned ON. Also, transistor 11 The threshold voltage of 71 is just one example. Within the range that does not change the state of transistor 1171 as described above. Any threshold value is acceptable as long as it's within the specified range.

[0283] Furthermore, a selection transistor having a first gate electrode and a second gate electrode, and a capacitance element Figure 22(B) shows an example of a NOR-type semiconductor memory device that uses memory cells with children. I will explain.

[0284] A semiconductor device according to one aspect of the present invention, shown in Figure 22(B), has row I (where I is a natural number greater than or equal to 2) J A memory cell array with multiple memory cells arranged in a matrix in columns (where J is a natural number) It possesses the characteristics of (i).

[0285] The memory cell array shown in Figure 22(B) has i rows (where i is a natural number greater than or equal to 3) and j columns (where j is greater than or equal to 3). Multiple memory cells 1180 arranged in a matrix (a natural number of ), and i word lines W L (word line WL_1 to word line WL_i) and i capacitance lines CL (capacitance line CL_1 to To the capacity line CL_i) and i gate lines BGL (gate line BGL_1 to gate line BGL _i), j bit lines BL (bit line BL_1 to bit line BL_j), and source line It is equipped with an SL (steam locomotive).

[0286] Furthermore, each of the multiple memory cells 1180 (memory cell 1180(M,N)(however A transistor (also called a transistor) is a natural number between 1 and j (where N is a natural number between 1 and j) and a natural number between 1 and i (where M is a natural number between 1 and i). 1181(M,N), capacitive element 1183(M,N), and transistor 1182(M,N ) and are provided.

[0287] In addition, in semiconductor memory devices, the capacitive element comprises a first capacitive electrode, a second capacitive electrode, and The capacitive element is composed of a dielectric layer superimposed on a first capacitive electrode and a second capacitive electrode. Charge is accumulated in accordance with the voltage applied between the first capacitive electrode and the second capacitive electrode. .

[0288] Transistor 1181(M,N) is an N-channel transistor, and has a source electrode and a dotted It has a rain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device, transistor 1181 is not necessarily an N-channel transistor. You don't have to.

[0289] One of the source and drain electrodes of transistor 1181(M,N) is connected to bit line B The first gate electrode of transistor 1181(M,N) is connected to L_N, and the word line W The second gate electrode of transistor 1181(M,N) is connected to L_M, and gate wire B Connected to GL_M. Source electrode and drain electrode of transistor 1181(M,N) By configuring one of the poles to be connected to the bit line BL_N, selective processing is performed for each memory cell. The data can be read from there.

[0290] Transistor 1181(M,N) is a selected transistor in memory cell 1180(M,N). It functions as a zista (radioactive marker).

[0291] As for transistor 1181(M,N), an oxide semiconductor is used in the channel formation region. A transistor can be used.

[0292] Transistor 1182(M,N) is a P-channel transistor. In the form of semiconductor memory, transistor 1182 is not necessarily a P-channel type transistor You don't have to make it a standard.

[0293] One of the source and drain electrodes of transistor 1182(M,N) is connected to the source line S Connected to L, the other of the source and drain electrodes of transistor 1182(M,N) It is connected to the bit line BL_N, and the gate electrode of transistor 1182(M,N) is It is connected to the source electrode and the other of the drain electrode of the lampistor 1181(M,N).

[0294] Transistor 1182(M,N) is an output transistor in memory cell 1180(M,N). It functions as a transistor. For example, the transistor 1182(M,N) can be used in single-phase configuration. A transistor can be used that uses crystalline silicon in the channel formation region.

[0295] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M, and the capacitance element The second capacitive electrode of transistor 1183(M,N) is the source electrode of transistor 1181(M,N). And it is connected to the other side of the drain electrode. Note that the capacitive element 1183(M,N) is a retaining capacitor It functions as a quantity.

[0296] The voltages of each word line WL_1 through WL_i are, for example, controlled by a decoder. It is controlled by a dynamic circuit.

[0297] The voltages of bit lines BL_1 through BL_j are, for example, controlled by a decoder. It is controlled by a dynamic circuit.

[0298] The voltages of capacitance lines CL_1 to CL_i are, for example, the number of times a decoder is used for driving. It is controlled by the road.

[0299] The voltages of gate lines BGL_1 through BGL_i are, for example, the gate line drive cycle. It is controlled using roads.

[0300] The gate line drive circuit is, for example, a diode and a first capacitive electrode which is the anode of the diode. It consists of a circuit equipped with a capacitive element electrically connected to the gate line BGL.

[0301] By adjusting the voltage of the second gate electrode of transistor 1181, The threshold voltage of 181 can be adjusted. Therefore, it functions as a selector transistor. The threshold voltage of transistor 1181 is adjusted, and in the off state, transistor 118 The current flowing between the source and drain electrodes of 1 can be minimized. This allows for a longer data retention period in memory circuits. Also, the data writing... Because the voltage required for insertion and readout can be lower than that of conventional semiconductor devices, It can reduce power consumption.

[0302] This embodiment connects to a transistor using an oxide semiconductor as the channel formation region. Because it is possible to maintain the potential of the node for an extremely long period of time, low power consumption By applying force, it is possible to create memory cells that can write, retain, and read information. In the memory cell array shown in Figure 22(B), instead of memory cell 1180, The memory cell 1170 shown in Figure 22(A) can be used. Install the appropriate wiring to match the RU1170.

[0303] The configurations and methods shown in this embodiment are similar to those shown in other embodiments and examples. It can be used in combination with other elements as appropriate.

[0304] (Embodiment 7) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment is described below. This will be explained with reference to Figure 23.

[0305] Figure 23(A) shows what is known as DRAM (Dynamic Random Access). An example of a semiconductor device with a configuration equivalent to memory is shown. Figure 23(A) shows the memory The Luar Array 1120 has a configuration in which multiple memory cells 1130 are arranged in a matrix. Furthermore, the memory cell array 1120 has m first wirings and n second wirings. It has a wire. In this embodiment, the first wiring is called the bit wire BL, and the second is The wiring is called the word line (WL).

[0306] The memory cell 1130 is composed of a transistor 1131 and a capacitive element 1132. The gate electrode of transistor 1131 is connected to the first wiring (word line WL). It is. Also, one of the source electrode or drain electrode of transistor 1131 is the second distribution It is connected to the line (bit line BL) and the source electrode or drain of transistor 1131. The other electrode of the capacitor is connected to one of the electrodes of the capacitive element. It is connected to the capacitance line CL and a constant potential is applied. Transistor 1131 has the The transistor shown in the embodiment is applied.

[0307] The transistor that uses an oxide semiconductor as the channel formation region as shown in the previous embodiment is Compared to transistors using single-crystal silicon in the channel formation region, the off-current is smaller. It has the following characteristics. For this reason, it is recognized as a so-called DRAM, as shown in Figure 23(A). When this transistor is applied to a semiconductor device, it is possible to obtain a substantially non-volatile memory. It is possible.

[0308] Figure 23(B) shows what is known as SRAM (Static Random Access Module). An example of a semiconductor device with a configuration equivalent to a memory cell is shown. Figure 23(B) shows a memory cell. The array 1140 has a configuration in which multiple memory cells 1150 are arranged in a matrix. This is possible. Also, the memory cell array 1140 has a first wiring BL, a second wiring BLB ( It has an inverting bit line, a third wiring WL, a power line Vdd, and a ground potential line Vss.

[0309] Memory cell 1150 consists of a first transistor 1151, a second transistor 1152, and Transistor 3 1153, Transistor 4 1154, Transistor 5 1155 , and a sixth transistor 1156. The first transistor 1151 and the second Transistor 1152 functions as a selection transistor. Also, the third transistor Of transistors 1153 and the fourth transistor 1154, one is an n-channel type transistor ( Here, the fourth transistor is 1154, and the other is a p-channel transistor (here Next is the third transistor 1153). In other words, the third transistor 1153 and the The CMOS circuit is composed of 4 transistors 1154. Similarly, the 5th transistor The CMOS circuit is composed of transistor 1155 and the sixth transistor 1156. .

[0310] First transistor 1151, second transistor 1152, fourth transistor 115 4. The sixth transistor 1156 is an n-channel type transistor, and is in the form of the previous implementation. The transistor shown in the diagram can be applied. The third transistor 1153 and The fifth transistor, 1155, is a p-channel type transistor, and is made of a material other than oxide semiconductors. The material (for example, single-crystal silicon) is used in the channel formation region.

[0311] The configurations and methods shown in this embodiment are similar to those shown in other embodiments and examples. It can be used in combination with other elements as appropriate.

[0312] (Embodiment 8) A CPU that uses at least a portion of transistors with oxide semiconductors in the channel formation region. A Central Processing Unit (Central Processing Unit) can be configured.

[0313] Figure 24(A) is a block diagram showing the specific configuration of the CPU. The PU has an arithmetic logic unit (ALU) on board 1190. nit)1191, ALU controller 1192, instruction decoder 1193 Interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8. Rewritable ROM1199 and ROM interface (ROM I / F) It has 1189. The substrate 1190 is a semiconductor substrate, SOI substrate, glass substrate, etc. Yes. ROM1199 and ROM I / F1189 may be placed on separate chips. Of course. The CPU shown in Figure 24(A) is merely one example of a simplified configuration, and the actual CPU is different. U has a wide variety of configurations depending on its intended use.

[0314] Instructions input to the CPU via the Bus I / F1198 are processed by the instruction decoder. The signal is input to DA 1193, decoded, and then interrupted by the ALU controller 1192. Controller 1194, Register Controller 1197, Timing Controller 119 It is entered into field 5.

[0315] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0316] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates CLK2, and the clock signal CLK2 is used by the various types described above. To supply power to the circuit.

[0317] In the CPU shown in Figure 24(A), a memory element (memory cell) is provided in register 1196. The memory element (memory cell) of register 1196 is provided with the following features: The memory elements (memory cells) described in Form 7 can be used.

[0318] In the CPU shown in Figure 24(A), the register controller 1197 is ALU1191 Following the instructions, select a hold operation in register 1196. That is, register In the memory element of Ta 1196, data retention is performed by a phase inversion element, or capacity The register controller 1197 selects whether to use an element to retain data. If data retention by a transfer element is selected, the data is transferred to the memory element in register 1196. Power supply voltage is supplied. If data retention in the capacitive element is selected, the capacitance Data is rewritten to the element, and power voltage is supplied to the memory element in register 1196. It can be stopped.

[0319] Regarding power shutdown, as shown in Figure 24(B) or Figure 24(C), the memory element group and the power A switching element is installed between nodes where the source potential VDD or power supply potential VSS is provided. This can be done by doing so. The following is a description of the circuits in Figures 24(B) and 24(C). To do so.

[0320] Figures 24(B) and 24(C) show switches that control the supply of power potential to the memory elements. The memory circuit structure includes a transistor in which an oxide semiconductor is used as the channel formation region. Here is an example of success.

[0321] The memory device shown in Figure 24(B) consists of a switching element 1141 and multiple memory elements 1142. It has a group of memory elements 1143. Specifically, each memory element 1142 has the above-mentioned actual The memory elements described in the form of the installation can be used. The memory element group 1143 has Each memory element 1142 receives a high-level power supply potential V via a switching element 1141. DD is supplied. Furthermore, each memory element 1142 of the memory element group 1143 has, The potential of the signal IN and the potential of the low-level power supply VSS are provided.

[0322] In Figure 24(B), the switching element 1141 is an oxide semiconductor channel formation region. It uses a transistor, and the signal given to the gate electrode of the transistor Switching is controlled by SigA.

[0323] Note that in Figure 24(B), the switching element 1141 has only one transistor. While it indicates a configuration, it is not particularly limited and may have multiple transistors. When element 1141 has multiple transistors that function as switching elements The above-mentioned transistors may be connected in parallel or in series. Furthermore, a combination of series and parallel connections is also acceptable.

[0324] Furthermore, in Figure 24(B), the switching element 1141 controls the memory element group 1143. The supply of a high-level power supply potential VDD to each memory element 1142 is controlled, Even when the supply of a low-level power supply potential VSS is controlled by the switching element 1141, good.

[0325] Furthermore, Figure 24(C) shows that each memory element 1142 of the memory element group 1143 has a switch. A low-level power supply potential VSS is supplied to the memory device via the 1141 element. Here is an example. The switching element 1141 controls each memory element of the memory element group 1143. The supply of a low-level power potential VSS to 1142 can be controlled.

[0326] Between the memory element group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed to temporarily stop the CPU's operation and cut off the power supply voltage, It is possible to retain data even while power consumption is reduced. Specifically In terms of this, for example, when a personal computer user uses an input device such as a keyboard, Even when you stop inputting information, you can stop the CPU from operating, thereby consuming It can reduce power consumption.

[0327] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays. [Examples]

[0328] In this embodiment, the cross-sectional structure of an oxide semiconductor film with dopant added will be described.

[0329] This section describes the method for fabricating oxide semiconductor films, which are dopant additives. First, glass A 300 nm silicon oxide film was formed on the substrate by sputtering.

[0330] Next, an oxide semiconductor film of an In-Ga-Zn-O system material (hereinafter referred to as IGZ) is placed on the silicon oxide film. A film (O) was formed by sputtering. In this example, the composition ratio was In2O3: Using a target with a molar ratio of Ga2O3:ZnO=1:1:2, an argon flow The volume is set to 30 sccm, the oxygen flow rate to 15 sccm, and the substrate temperature to 400°C, with a thickness of 3 A 0 nm IGZO film was formed. Furthermore, the IGZO film formed under these conditions is the same as in Embodiment 1. This is the CAAC-OS described in Embodiment 3.

[0331] Next, in order to release the hydrogen from the formed IGZO film, the heating temperature was set to 450°C, and nitrogen was added. The treatment was performed under controlled conditions for one hour.

[0332] Next, dopants were added to the heated IGZO film using the ion implantation method. In this example, the dopant is a phosphate ion (31P + ) and set the acceleration voltage to 20kV, and add Quantity 1×10 16 cm -2 It was added to the IGZO film as such.

[0333] Next, the IGZO film to which the dopant (phosphate ion) was added was heated to a temperature of 650°C. Then, a heat treatment was performed for 1 hour. In this example, the process is carried out after the addition of the dopant. In the heat treatment, the IGZO film treated under a nitrogen atmosphere was designated as Sample 1, and under an oxygen atmosphere... The IGZO film obtained using this method will be designated as Sample 2.

[0334] Transmission Electron Microscope Cross-sectional TEM observation of sample 1 and sample 2 was performed using e:TEM). Note that the comparative example and TEM was also used for IGZO films that were not heat-treated after dopant addition. Then, the cross-section was observed. Figure 19(A) shows the cross-sectional TEM image of the comparative example, and Figure 19(B) Figure 19(C) shows a cross-sectional TEM image of sample 1, and Figure 19(C) shows a cross-sectional TEM image of sample 2. Figures 19(A) to 19(C) are cross-sectional TEM images observed at a magnification of 8 million times.

[0335] No lattice image is observed in Figure 19(A), and the electron diffraction pattern of the comparative example (not shown) is also not shown. The pattern was a halo pattern. This confirmed that the comparative example was amorphous.

[0336] Figure 19(B) shows a lattice pattern, confirming that sample 1 contains crystalline portions. The electron diffraction pattern of sample 1 (not shown) was obtained at the position where the electron beam was irradiated. Therefore, there were different diffraction patterns. In particular, in Figure 19(B), the control of the IGZO film Where the last part differed, the crystal orientation was different. Therefore, sample 1 has multiple crystals. It was confirmed that it possesses a division.

[0337] Figure 19(C) shows a lattice pattern, confirming that sample 2 contains crystalline regions. It was determined that IG It was confirmed that the region including the surface of the ZO film is a crystalline portion having c-axis orientation. Furthermore, Since the crystalline portion having c-axis orientation is non-single crystal, the region including the surface of the IGZO film is CA It can be said that it is AC-OS, and at least 2 nm was formed from the surface of the IGZO film. Furthermore, except for the region containing the surface of the IGZO film, it has multiple crystalline parts, similar to sample 1. This was confirmed.

[0338] Based on the above, by performing a heat treatment after adding a dopant to the oxide semiconductor film, multiple It was confirmed that an oxide semiconductor film having a crystalline portion can be formed. Furthermore, the heat treatment Depending on the atmosphere, the region including the surface of the oxide semiconductor film to be formed is non-single crystal and c It has been confirmed that an oxide semiconductor (CAAC-OS) containing axially oriented crystalline regions can be formed. came. [Explanation of Symbols]

[0339] 100 transistors 101 circuit board 102 Underlying insulating film 103 Oxide semiconductor film 105 The first area 107a Oxide semiconductor region 107b Oxide semiconductor region 109a Oxide semiconductor region 109b Oxide semiconductor region 111 Gate Insulator 112 Conductive film 113 First electrode 116a opening 116b opening 117 Interlayer insulating film 119a Second electrode 119b Third electrode 121 Gate Insulator 123a Second area 123b Second area 130 Oxide semiconductor film 131 Oxide semiconductor film 132 Oxide semiconductor film 140 Oxide semiconductor film 150 Dopant 160 transistors 170 transistors 200 transistors 207a Oxide semiconductor region 207b Oxide semiconductor region 209a Oxide semiconductor region 209b Oxide semiconductor region 214a Oxide semiconductor region 214b Oxide semiconductor region 215 Sidewall Insulation Film 223a Third area 223b Third area 260 transistors 270 transistors 1100 cell cells 1110 memory cell array 1111 Drive Circuit 1112 Readout Circuit 1113 Drive Circuit 1120 memory cell array 1130 memory cells 1131 Transistors 1132 Capacitive element 1140 memory cell array 1141 Switching element 1142 memory element 1143 Memory element group 1150 memory cells 1151 Transistors 1152 transistors 1153 Transistors 1154 Transistors 1155 Transistor 1156 Transistors 1160 transistors 1161 transistors 1162 transistors 1163 Transistors 1164 transistors 1170 cell cells 1171 transistors 1172 transistors 1173 Capacitive element 1180 memory cells 1181 Transistors 1182 transistors 1183 Capacitive element 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM

Claims

[Claim 1] An oxide semiconductor film comprising a first region and a pair of second regions facing each other across the first region, A gate insulating film provided on the oxide semiconductor film, It has a first electrode provided on the gate insulating film and superimposed on the first region, The first region is a non-single-crystal oxide semiconductor region having a c-axis oriented crystalline region, The second region is an oxide semiconductor region containing a dopant and having a plurality of crystalline regions, The second region is provided with a non-single-crystal oxide semiconductor region containing a dopant and having c-axis oriented crystalline region on an oxide semiconductor region containing the dopant and having a plurality of crystalline regions. The device has a second electrode and a third electrode electrically connected to the pair of second regions, The second electrode and the third electrode are in contact with the upper surface of the pair of second regions. The gate insulating film is provided on the first region and the pair of second regions of the semiconductor device.

Images