Memory system

Abstract

To provide a memory system that suppresses performance degradation caused by training operations. [Solution] The memory system controller is capable of performing either a first write operation or a second write operation. The first write operation includes a data-in operation and a program operation. The data-in operation is the operation of transferring data to the memory device by a data signal and a data strobe signal, and storing the data captured by the latch circuit in the memory device in a buffer circuit. In the second write operation, the controller performs the data-in operation, acquires the data captured by the latch circuit by the data-in operation, and obtains the number of error bits contained in the acquired data. Furthermore, the controller determines whether to perform a training operation or skip it depending on the number of error bits.

Description

Technical Field

[0001] This embodiment relates to a memory system.

Background Art

[0002] A memory system includes a controller and a memory chip, and data transfer is performed between the controller and the memory chip. In order to speed up the data transfer, it has been considered to apply an Un-matched DQS architecture to the receiving circuit of the data transfer. According to the Un-matched DQS architecture, in the receiving circuit, a delay circuit is provided only in the path of the data strobe signal among the path of the data signal and the path of the data strobe signal. Then, by adjusting the delay circuit, the timing of the data strobe signal with respect to the data signal is adjusted. The adjustment of the delay circuit is referred to as a training operation.

[0003] The delay time of the delay circuit can vary due to various factors such as temperature changes. When the Un-matched DQS architecture is applied, the training operation is required relatively frequently.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a memory system that suppresses performance degradation caused by the training operation.

Means for Solving the Problem

[0006] According to one embodiment, a memory system includes a memory device and a controller. The memory device includes a first terminal to which a data signal is input, a second terminal to which a data strobe signal is input, a receiving circuit, a memory cell array, and a buffer circuit disposed between the memory cell array and the receiving circuit. The receiving circuit includes a latch circuit that captures data from the data signal based on the data strobe signal and a delay circuit disposed between the second terminal and the latch circuit. The controller is connected to the memory device via the first terminal and the second terminal. The controller is capable of performing any one of a first write operation and a second write operation. The first write operation includes a data-in operation and a program operation. In the data-in operation, the controller transfers first data, which is data to be written, to the memory device by using the data signal and the data strobe signal, and causes the memory device to store the first data captured by the latch circuit in the buffer circuit. In the program operation, the controller causes the memory device to store the first data stored in the buffer circuit in the memory cell array. In the second write operation, the controller performs the data-in operation, acquires the first data captured by the latch circuit and stored in the buffer circuit by the data-in operation, and acquires the number of error bits included in the acquired first data. In the second write operation, the controller further performs a training operation to adjust the delay time of the delay circuit when the number of error bits is greater than a first threshold, and performs the program operation without performing the training operation when the number of error bits is less than the first threshold.

Brief Description of the Drawings

[0007] [Figure 1] A diagram showing a configuration example of a memory system according to the first embodiment. [Figure 2] A diagram showing a configuration example of each memory chip according to the first embodiment. [Figure 3]A diagram showing the circuit configuration of a block according to the first embodiment. [Figure 4] A diagram showing an example of the configuration of a signal processing circuit as a receiving circuit according to the first embodiment. [Figure 5] A diagram illustrating the training motion according to the first embodiment. [Figure 6] A diagram illustrating an example of a latch test operation according to the first embodiment. [Figure 7] A diagram showing an example of a latch test operation according to the first embodiment. [Figure 8] A flowchart illustrating an example of the operation of the controller according to the first embodiment. [Figure 9] A diagram illustrating an example of the timing of training movements according to the first embodiment. [Figure 10] A diagram showing an example of the operation before and after a latch test operation according to a modified example of the first embodiment. [Figure 11] A diagram illustrating an example of the timing of the latch test light operation according to the second embodiment. [Figure 12] A flowchart illustrating an example of the operation of the controller according to the second embodiment. [Modes for carrying out the invention]

[0008] The memory system according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) Figure 1 shows an example configuration of a memory system according to the first embodiment. As shown in Figure 1, the memory system 1 is connectable to a host 2. The host 2 is an information processing device such as a server, personal computer, or mobile terminal. The memory system 1 functions as an external storage device for the host 2. The host 2 can send access requests, such as read requests or write requests, to the memory system 1.

[0010] The memory system 1 comprises one or more memory chips 100, a controller 200, and a temperature sensor 300. The memory chips 100 operate based on instructions from the controller 200. The memory chips 100 are, for example, NAND flash memory. In this embodiment, the memory system 1 comprises one or more memory chips 100, such as memory chips 100_0 and 100_1. The number of memory chips 100 in the memory system 1 is not limited to two. If the memory system 1 comprises multiple memory chips 100, the multiple memory chips 100 may be housed in a single package.

[0011] Note that the memory chip 100 is an example of a memory device.

[0012] The temperature sensor 300 detects temperature. The temperature detected by the temperature sensor 300 is used by the CPU 203 for various control functions.

[0013] Each memory chip 100 is equipped with multiple memory cell transistors, and can store data nonvolatilically in the multiple memory cell transistors. The memory chip 100 is connected to the controller 200 by a memory bus 400. The memory bus 400 includes signal lines used for sending and receiving data signals, control signals, and status signals. The memory chip 100 transfers, for example, an 8-bit wide data signal DQ<7:0> to and from the controller 200. The bit width of the data signal DQ is not limited to 8 bits. In addition to data, commands and addresses are transferred as the data signal DQ<7:0>. The memory chip 100 receives control signals from the controller 200 and sends status signals to the controller 200. The status signals include a ready-busy signal RyBy.

[0014] The control signals include the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, a pair of read enable signals RE and REn, a pair of data strobe signals DQS and DQSn, and the write protect signal WPn. The "n" at the end of the signal code indicates that the signal is operated in negative logic. Whether each signal operates in negative or positive logic can be arbitrarily designed.

[0015] The chip enable signal CEn is a signal used to enable the memory chip 100 that is to be accessed. The chip enable signal CEn is input individually to each of the two memory chips 100_1 and 100_2. Signals DQ<7:0>, DQS, DQSn, CLE, ALE, WEn, RE, REn, and WPn are input commonly to the two memory chips 100_1 and 100_2. The memory chip 100 that has been enabled by the chip enable signal CEn can perform operations corresponding to these commonly input signals.

[0016] The pair of data strobe signals DQS and DQSn are signals that instruct the destination to capture the data transmitted by the data signal DQ<7:0>. Of the controller 200 and the memory chip 100, the source of the data signal DQ<7:0> can transmit the pair of data strobe signals DQS and DQSn. That is, the pair of data strobe signals DQS and DQSn can be transmitted from the controller 200 to the memory chip 100, or from the memory chip 100 to the controller 200.

[0017] The command latch enable signal CLE indicates that the data signal DQ<7:0> is a command. The address latch enable signal ALE indicates that the data signal DQ<7:0> is an address. The write enable signal WEn instructs the memory chip 100 to capture the command or address transmitted by the data signal DQ<7:0>. The pair of read enable signals RE and REn instruct the memory chip 100 to output the data signal DQ<7:0>. The memory chip 100 can delay the input pair of read enable signals RE and REn and output them as a pair of data strobe signals DQS and DQSn. The write protect signal WPn instructs the memory chip 100 to prohibit the execution of program operations and erase operations.

[0018] The ready / busy signal RyBy indicates whether the memory chip 100 is in a ready state (Ry) or a busy state (By). The ready state (Ry) means that the memory chip 100 is in a state where it can receive commands from the controller 200.

[0019] Note that the configuration of the memory bus 400 is not limited to the example described above. The types and number of signals that the memory bus 400 can transfer are arbitrary, as long as it can transfer data signals DQ<7:0> and data strobe signals DQS and DQSn.

[0020] Hereafter, we will describe the data strobe signal DQS as a representative of the pair of data strobe signals DQS and DQSn, and omit the explanation of the data strobe signal DQSn. Also, the data signal DQ<7:0> will be abbreviated as data signal DQ.

[0021] The controller 200 can command the memory chip 100 to perform various operations based on requests from the host 2, etc.

[0022] The controller 200 includes a host interface (I / F) circuit 201, RAM (random access memory) 202, a CPU 203, a buffer memory 204, a memory interface (I / F) circuit 205, and an ECC (error correction code) circuit 206. The controller 200 may be configured as, for example, a System-On-a-Chip (SoC). The controller 200 may also be configured as an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). The controller 200 may be composed of multiple chips. Each function of the controller 200 may be implemented by a processor running software (firmware), dedicated hardware circuitry, or a combination thereof.

[0023] The host interface (I / F) circuit 201 is connected to host 2 via a bus compliant with, for example, the SATA (Serial Advanced Technology Attachment) standard, the SAS (Serial Attached SCSI) standard, or the PCI (Peripheral Components Interconnect) Express® standard. The host interface circuit 201 is responsible for communication between controller 200 and host 2.

[0024] The memory interface circuit 205 is connected to each memory chip 100 via the memory bus 400. The memory interface circuit 205 is responsible for communication between the controller 200 and the memory chips 100.

[0025] The CPU 203 controls the operation of the controller 200.

[0026] RAM 202 is used as a work area for the CPU 203. Buffer memory 204 temporarily holds data sent to and output from the memory chip 100. RAM 202 and buffer memory 204 may be composed of, for example, DRAM (dynamic random access memory), SRAM (static random access memory), or a combination thereof. RAM 202 may be located outside the controller 200.

[0027] The ECC circuit 206 performs encoding using error correction codes on the data transmitted to the memory chip 100. Furthermore, the ECC circuit 206 detects and corrects errors in the data by decoding the encoded data received from the memory chip 100. The ECC circuit 206 may be located within the memory interface circuit 205.

[0028] Figure 2 shows an example of the configuration of each memory chip 100 according to the first embodiment.

[0029] The memory chip 100 includes a signal processing circuit 101, a control circuit 103, a command register 104, an address register 105, a status register 106, a voltage generation circuit 107, a column buffer 109, a column decoder 110, a data register 111, a sense amplifier 112, a memory cell array 113, a row address buffer decoder 114, and a row address decoder 115.

[0030] The signal processing circuit 101 includes a latch circuit 120. The latch circuit 120 captures the data signal DQ transferred from the controller 200 at the timing of the toggle of the data strobe signal DQS transferred from the controller 200.

[0031] Furthermore, the signal processing circuit 101 receives a control signal. Based on the received control signal, the signal processing circuit 101 determines whether the data signal DQ transferred from the controller 200 is a command, an address, or data.

[0032] The signal processing circuit 101 distributes and stores the command, address, and data, which have been transferred as data signals DQ and taken into the latch circuit 120, into the command register 104, the address register 105, and the data register 111, respectively.

[0033] The address stored in address register 105 includes the row address and the column address. The row address is sent to the row address buffer decoder 114. The column address is sent to the column buffer 109.

[0034] The control circuit 103 is a state transition circuit (state machine) that transitions states based on control signals. Control signals are input to the control circuit 103 via the signal processing circuit 101. The control circuit 103 controls the operation of the entire memory chip 100 based on various control signals and commands stored in the command register 104.

[0035] The control circuit 103 generates status information indicating the state of operation control or the result of operation control, and stores the status information in the status register 106. The control circuit 103 outputs the status information stored in the status register 106 in response to a status read command from the controller 200.

[0036] The signal processing circuit 101, under the control of the control circuit 103, transitions the state of the ready / busy signal RyBy between the ready state (Ry) and the busy state (By).

[0037] The memory cell array 113 has a configuration in which multiple memory cell transistors are arranged. Each of the multiple memory cell transistors is connected to a bit line BL and a word line WL. Data received from the host 2 is stored in the memory cell array 113.

[0038] The memory cell array 113 has multiple block BLKs. All data stored in a block BLK is erased all at once. The operation of erasing all data stored in a block BLK is referred to as the erase operation.

[0039] Figure 3 shows the circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. A block BLK has, for example, four string units SU0 to SU3. Each string unit SU contains a plurality of memory strings 140.

[0040] Each of the memory strings 140 includes, for example, 14 memory cell transistors MT (MT0 to MT13) and selection transistors ST1 and ST2. The 14 memory cell transistors MT (MT0 to MT13) are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The number of memory cell transistors MT in the memory string 140 is not limited to 14. Each memory cell transistor MT comprises a control gate and a charge storage layer to hold data non-volatile. The memory cell transistor MT may be of the MONOS type with an insulating film in the charge storage layer, or of the FG type with a conductive film in the charge storage layer.

[0041] The gates of the selection transistor ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 are connected in common to, for example, the selection gate line SGS. The gates of the selection transistor ST2 in each of the string units SU0 to SU3 may be connected to different selection gate lines SGS0 to SGS3 (not shown) for each string unit SU. The control gates of the memory cell transistors MT0 to MT13 within the same block BLK are connected in common to the word lines WL0 to WL13, respectively.

[0042] The drains of the selection transistor ST1 of each memory string 140 within the string unit SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number greater than or equal to 2). Furthermore, the bit lines BL connect one memory string 140 within each string unit SU to multiple blocks BLK. Additionally, the sources of each selection transistor ST2 are connected to the source line SL.

[0043] In other words, a string unit SU is a collection of memory strings 140 connected to different bit lines BL and the same selection gate line SGD. A block BLK is a collection of multiple string units SU that share a common word line WL. And a memory cell array 113 is a collection of multiple block BLK that share a common bit line BL.

[0044] When the controller 200 instructs the write of data, the threshold voltage of the memory cell transistor MT is set to the state corresponding to the data. This operation is referred to as the program operation. When the controller 200 instructs the read of data, the state of the threshold voltage of the memory cell transistor MT is determined, and the determined state is converted into data. This operation is referred to as the sense operation.

[0045] Program and sense operations are performed collectively on memory cell transistors MT connected to a single word line WL in a single string unit SU. The group of memory cell transistors MT selected collectively during program and sense operations is denoted as a memory cell group MCG. The collection of 1-bit memory areas of multiple memory cell transistors MT that are written (or read) by a program operation on a single memory cell group MCG is denoted as a page.

[0046] The number of pages provided by a single memory cell group (MCG) depends on the number of bits of data that can be stored in each memory cell transistor (MT). If K is the number of bits of data stored in each memory cell transistor (MT), then a single memory cell group (MCG) can provide K pages. Hereafter, as an example, a single memory cell group (MCG) provides three pages. The data stored in one of the three pages provided by a single memory cell group (MCG) will be referred to as lower page data, the data stored in another page as middle page data, and the data stored in the remaining page as upper page data.

[0047] Let's return to the explanation in Figure 2.

[0048] The data register 111 stores data that is written by program operations. Additionally, the data register 111 stores data read from the memory cell array 113 by sense operations.

[0049] The data register 111 is an example of a buffer circuit placed between the signal processing circuit 101 and the memory cell array 113.

[0050] The data to be written, transferred from the controller 200, is captured by the latch circuit 120 of the signal processing circuit 101 and stored in the data register 111. Then, the data to be written stored in the data register 111 is stored in the memory cell array 113 by program operation. The operation in which the controller 200 transfers the data to be written to the memory chip 100, and the memory chip 100 stores the data to be written to the data register 111 via the latch circuit 120, is referred to as the data-in operation. Hereafter, the operation including the data-in operation and program operation will be referred to as the write operation.

[0051] Data read from the memory cell array 113 by a sense operation is stored in the data register 111. Some or all of the data stored in the data register 111 is transferred to the controller 200 via the signal processing circuit 101. The operation of transferring the data stored in the data register 111 to the controller 200 is referred to as a data-out operation. Furthermore, the operation including both the sense operation and the data-out operation is referred to as a read operation.

[0052] The voltage generation circuit 107 generates various voltages necessary for accessing the memory cell array 113 (program operation, sense operation, and erase operation) based on the power input to the Vcc terminal (not shown). The voltage generation circuit 107 then supplies the generated voltages to the sense amplifier 112, the memory cell array 113, and the low-address decoder 115, respectively.

[0053] The row-address decoder 115, column decoder 110, and sense amplifier 112 perform access to the memory cell array 113 (program operation, sense operation, and erase operation) based on control by the control circuit 103.

[0054] Next, the more detailed configuration of the signal processing circuit 101 will be described. The signal processing circuit 101 functions as a receiving circuit that receives the data signal DQ.

[0055] Figure 4 shows an example of the configuration of a signal processing circuit 101 as a receiving circuit according to the first embodiment. As shown in this figure, the signal processing circuit 101 includes a latch circuit 120, a driver 121, a driver 122, and a delay circuit 123.

[0056] The memory chip 100 has a terminal T to which the data signal DQ is input from the memory interface circuit 205. DQ Then, the data strobe signal DQS is input to terminal T from the memory interface circuit 205. DQS It includes terminal T. DQ This is an example of the first terminal. Terminal T DQS This is an example of a second terminal.

[0057] Terminal T DQS Between the latch circuit 120 and the terminal T, the driver 121 and the delay circuit 123 are arranged. DQS The data strobe signal DQS input to terminal T is input to the latch circuit 120 via driver 121 and delay circuit 123 in that order. DQ A driver 122 is positioned between the terminal T and the latch circuit 120. DQ The data signal DQ input to the device is input to the latch circuit 120 via the driver 122. The latch circuit 120 acquires data from the data signal DQ input to it, based on the data strobe signal DQS input to it.

[0058] Thus, the signal processing circuit 101 as a receiving circuit has an Un-matched DQS architecture configuration in which the delay circuit 123 is provided only in the path of the data strobe signal DQS, out of the paths of the data signal DQ and the data strobe signal DQS.

[0059] The delay time of the delay circuit 123 is adjusted by the training operation. The training operation according to the first embodiment will be explained with reference to Figure 5.

[0060] Part (A) of Figure 5 shows the boundary of the memory chip 100 (i.e., terminal TDQS , T DQ ) shows the waveforms of the data strobe signal DQS and the data signal DQ. Part (B) of FIG. 5 shows the waveforms of the data strobe signal DQS and the data signal DQ in the latch circuit 120.

[0061] Here, it is assumed that the latch circuit 120 is configured to capture data from the data signal DQ at the timings of both the rising edge and the falling edge of the data strobe signal DQS. The latch circuit 120 may be configured to capture data at the timing of either the rising edge or the falling edge of the data strobe signal DQS.

[0062] The controller 200 toggles the data strobe signal DQS the number of times corresponding to the total size of the data transferred as the data signal DQ so that the data transferred as the data signal DQ can be captured. Therefore, among the data transferred as the data signal DQ, the edge E for capturing the 8-bit data D (denoted as data D x for simplicity) transferred at the x-th position from the beginning (where x is a numerical value) is naturally determined. The edge of the data strobe signal DQS for capturing the data D x is denoted as edge E x .

[0063] In the example shown in part (A) of FIG. 5, the timings of the edges E0, E1, E2,... of the data strobe signal DQS are significantly earlier than the timings of the transfer of the data D0, D1, D2,.... Therefore, the receiving circuit cannot capture all the data D transferred as the data signal DQ without omission.

[0064] The delay circuit 123 delays the data strobe signal DQS, allowing the latch circuit 120 to capture all data D that is transferred as data signal DQ. During training, the delay time of the data strobe signal DQS is adjusted so that the timing of each edge E0, E1, E2, ... of the data strobe signal DQS matches the timing of the center of the eye pattern of the corresponding data D. As a result, as shown in part (B) of Figure 5, the transfer timing of each data D in the latch circuit 120 matches the timing of the corresponding edge E, allowing the latch circuit 120 to capture each data D.

[0065] As mentioned above, the delay time of the delay circuit 123 can vary depending on factors such as the temperature around the delay circuit 123. Therefore, the timing of the data strobe signal DQS relative to the data signal DQ may change due to temperature changes from the ideal timing shown in part (B) of Figure 5. As the timing of the data strobe signal DQS relative to the data signal DQ shifts due to temperature changes from the ideal timing shown in part (B) of Figure 5, the number of error bits included in the transmitted data increases. For example, if data containing more error bits than the correction capability of the ECC circuit 206 is stored in the memory cell array 113, the controller 200 will not be able to read the data correctly. To prevent such a situation, a second training operation is required even after the training operation has been completed.

[0066] Regarding the Unmatched DQS architecture, some standards mention the need for repeated training. For example, according to the Toggle 5.1 standard and later established by the Joint Electron Device Engineering Council Solid State Technology Association (JEDEC), it is recommended to perform training every 25 degrees Celsius temperature change.

[0067] During training, data transfers occur numerous times between the controller 200 and the memory chip 100. During training, there are periods when the controller 200 cannot perform either write or read operations on the memory chip 100. Therefore, the performance of the memory system 1 deteriorates depending on the frequency of training operations.

[0068] In the first embodiment, even if the controller 200 detects that the temperature change exceeds a predetermined value (for example, 25 degrees Celsius), it will skip the training operation if the operation of the receiving circuit meets a predetermined criterion. The predetermined criterion is, for example, that the degree of error that occurs when the latch circuit 120 acquires data is within an acceptable range. In other words, the controller 200 detects the degree of error that occurs when the latch circuit 120 acquires data and decides whether or not to skip the training operation based on the result of the detection. The operation of detecting the degree of error that occurs when the latch circuit 120 acquires data is referred to as the latch test operation.

[0069] The controller 200 utilizes the data to be written, which is transferred from the controller 200 to the memory chip 100 during a write operation, in order to efficiently perform a latch test operation.

[0070] Figure 6 is a diagram illustrating an example of a latch test operation according to the first embodiment.

[0071] The controller 200 performs a data-in operation to transfer the lower page data from the lower page data, middle page data, and upper page data stored in the memory chip 100 (S1).

[0072] In the memory chip 100, the lower page data transferred from the controller 200 as a data signal DQ is captured in 8-bit increments by the latch circuit 120 based on the data strobe signal DQS, and the captured 8-bit lower page data is sequentially stored in the data register 111.

[0073] Next, the controller 200 performs a latch test operation. Specifically, the controller 200 first performs a data-out operation to acquire the lower page data stored in the data register 111 (S2). Then, the controller 200 uses the ECC circuit 206 to perform error correction on the lower page data acquired from the memory chip 100 by the data-out operation. Finally, the controller 200 acquires the number of errors corrected by the ECC circuit 206, i.e., the number of error bits (S3).

[0074] The number of error bits is the threshold Th err1 If greater than the threshold Th, controller 200 performs the training operation (S4-1). err1 The setting method is arbitrary. However, for example, the value must not exceed the upper limit of the number of error bits that can be corrected by the ECC circuit 206, which is the threshold Th err1 It will be set as follows.

[0075] The number of error bits is the threshold Th err1 If the value is smaller, the controller 200 skips the training operation and continues with the write operation (S4-2). In other words, the controller 200 performs a data-in operation to transfer the middle page data and upper page data, and causes the memory chip 100 to perform the program operation for the lower page data, middle page data, and upper page data.

[0076] The number of error bits is the threshold Th err1 The handling of cases where it is equal to is optional. Hereafter, the number of error bits is the threshold Th err1 If equal to the threshold Th, the number of error bits err1 The same processing as in the case of a smaller value will be performed.

[0077] The series of operations described using Figure 6 is referred to as a latch-test write operation. A write operation that does not involve a latch-test operation but includes both a data-in operation and a program operation is referred to as a normal write operation.

[0078] Normal light operation is an example of the first light operation. Latch test light operation is an example of the second light operation. Threshold Th err1 This is an example of the first threshold.

[0079] Figure 7 shows an example of a latch test operation according to the first embodiment. In this example, it is assumed that four memory chips 100_0, 100_1, 100_2, and 100_3 are connected to the memory bus 400. In this and subsequent figures, memory chips may be abbreviated as CP. The horizontal axis in parts (A) and (B) of this figure represents time.

[0080] Part (A) of Figure 7 shows that the number of error bits is determined by the latch test operation, which is the threshold Th err1 The operation in the case where a larger result was obtained is shown. First, a read operation is performed on the memory chip 100_1 during the period from time t0 to time t2. That is, the controller 200 performs the following actions on the memory chip 100_1: transferring a command to instruct a sense operation (Sense), waiting for a period tR, and performing a data out operation (Dout). The period tR indicates the period during which the sense operation is being performed on the memory chip 100.

[0081] If, at time t1, a temperature condition is met, for example, the temperature change exceeds a threshold Th1 (for example, 25 degrees Celsius), and a write operation to a certain memory chip 100 is scheduled, the controller 200 performs a latch test operation when performing the write operation to that memory chip 100. In the example shown in Figure 7, the latch test operation is performed when performing a write operation to memory chip 100_0.

[0082] Specifically, the controller 200 first performs a data-in operation (Din(Low)) to transfer the lower page data (time t2). Next, the controller 200 performs a data-out operation (Dout) to acquire the lower page data that has been taken up by the latch circuit 120 and stored in the data register 111 (time t3). The controller 200 performs error correction on the lower page data acquired by the data-out operation and obtains the number of error bits. Then, the controller 200 calculates the number of error bits and the threshold Th err1 A comparison is made with the example in part (A) of Figure 7, where the number of error bits is the threshold Th err1 Because it is larger, controller 200 performs training (time t4).

[0083] Once the training operation is complete (time t5), the controller 200 executes the following data-in operations in this order: a data-in operation to transfer lower page data (Din(Low)), a data-in operation to transfer middle page data (Din(Mid)), and a data-in operation to transfer upper page data (Din(Up)). Then, the controller 200 causes the memory chip 100_0 to execute a program operation to store the lower page data, middle page data, and upper page data into a single memory cell group MCG (time t6).

[0084] The period tPROG indicates the period during which program operation is being executed on the memory chip 100.

[0085] Part (B) of Figure 7 shows that the number of error bits is determined by the latch test operation, which is the threshold Th err1 The operation in the case where the following result was obtained is shown. Up to time t3, the same operation as in part (A) is performed. The controller 200 performs error correction on the lower page data obtained by the data out operation (Dout) at time t3 and obtains the number of error bits. Then, the controller 200 calculates the number of error bits and the threshold Th err1 A comparison is made with the number of error bits as the threshold Therr1 Therefore, the controller 200 continues the write operation. Specifically, the controller 200 performs a data-in operation (Din(Mid)) for the middle page data and a data-in operation (Din(Up)) for the upper page data (time t11). Then, the controller 200 causes the memory chip 100_0 to execute a program operation to store the lower page data, middle page data, and upper page data into a single memory cell group MCG (time t12).

[0086] In this way, the controller 200 uses the data to be written, which has been transferred to the memory chip 100, to perform a latch test operation. Therefore, the controller 200 does not need to transfer data specifically for the latch test operation to the memory chip 100 separately from the data to be written. In other words, the efficiency of the latch test operation is improved.

[0087] Figure 8 is a flowchart showing an example of the operation of the controller 200 according to the first embodiment. Note that read and erase operations are not mentioned in this description. Read and erase operations are performed as usual. The series of operations shown in this figure are performed for each memory chip 100.

[0088] First, the controller 200 sets a reference temperature value (S101). For example, in step S101, the controller 200 obtains a temperature detection value from the temperature sensor 300 and sets the obtained detection value as the reference value.

[0089] The controller 200 monitors the temperature change from a reference value to detect when the temperature change from the reference value exceeds a predetermined threshold Th1. The controller 200 periodically performs, for example, acquiring temperature detection values ​​from the temperature sensor 300, calculating the temperature change based on the acquired detection values, and comparing the calculated temperature change with the threshold Th1.

[0090] The threshold Th1 is pre-configured. For example, according to the Toggle 5.1 standard and later, the threshold Th1 is 25 degrees Celsius. The threshold Th1 may also be configurable from, for example, host 2. Note that the threshold Th1 is an example of a second threshold.

[0091] Hereafter, the temperature change from the reference value will simply be referred to as the temperature change.

[0092] If the temperature change exceeds the threshold Th1 (S102), the controller 200 determines whether the next operation to be performed is the first write operation after the temperature change exceeds the threshold Th1 (S103).

[0093] If the temperature change does not exceed the threshold Th1, the controller 200 can perform a normal light operation as a light operation. However, the processing when the temperature change reaches the threshold Th1 but does not exceed it is not limited to this. If the temperature change reaches the threshold Th1, the control may transition to step S103.

[0094] If the next operation to be performed is not the first light operation after the temperature change exceeds the threshold Th1 (S103: No), the controller 200 performs the operation as usual (S104). Then the control transitions to step S103.

[0095] If the next operation to be performed is the first light operation after the temperature change exceeds the threshold Th1 (S103: Yes), the controller 200 performs a latch test light operation.

[0096] Specifically, the controller 200 first performs a data-in operation to transfer lower page data (S105). Then, the controller 200 performs a data-out operation to retrieve the lower page data that was transferred to the memory chip 100 by the data-in operation and stored in the data register 111 of the memory chip 100 (S106).

[0097] The controller 200 obtains the number of error bits in the lower page data acquired from the memory chip 100 (S107). Then, the controller 200 calculates the number of error bits and the threshold Th err1 Compare them.

[0098] The number of error bits is the threshold Th err1 If the value is greater than (S108: Yes), the controller 200 interrupts the light operation (S109) and performs the training operation (S110). Along with performing the training operation, the controller 200 updates the reference value of the temperature change in the same manner as in step S101 (S111), and the control transitions to step S102.

[0099] The number of error bits is the threshold Th err1 If the value is not greater than (S108: No), the controller 200 continues the light operation (S112). Then the control transitions to step S111. That is, the controller 200 updates the reference value of the temperature change in the same manner as in step S101 (S111).

[0100] Figure 9 is a diagram illustrating an example of the timing of the training operation according to the first embodiment. This figure shows the time progression of the temperature change and the time progression of the number of error bits obtained when the latch test operation is performed.

[0101] At time t20, for example, the temperature reference value is set by the process in step S101 in Figure 8. Subsequently, even if the amount of temperature change exceeds the threshold Th1, the number of error bits in the latch test operation exceeds the threshold Th err1 The training operation will not be performed unless the value becomes larger. In the example shown in Figure 9, the temperature change from the set temperature reference value at time t20 exceeds the threshold Th1 at time t21. As a result, the latch test operation and the update of the temperature reference value (e.g., step S111 in Figure 8) are performed at time t21. However, at time t21, the number of error bits exceeds the threshold Th err1The following applies. Therefore, no training operation is performed at time t21. Similarly, the temperature change from the updated temperature reference value at each of times t21 to t25 exceeds the threshold Th1 at each of times t22 to t26. As a result, a latch test operation and an update of the temperature reference value (e.g., step S111 in Figure 8) are performed at each of times t22 to t26. However, at each of times t22 to t25, the number of error bits exceeds the threshold Th err1 The following applies. Therefore, no training operations are performed during the period from time t22 to t25. At time t26, the number of error bits exceeds the threshold Th err1 As it grows larger, the training movements are executed.

[0102] A technology comparable to the embodiment will be described. A technology comparable to the embodiment will be referred to as a comparative example. According to the comparative example, the training operation of the receiving circuit is executed each time the temperature change exceeds the threshold Th1. According to the comparative example, as shown in the example in Figure 9, the training operation is executed at the timings of time t21, t22, t23, t24, and t25.

[0103] In contrast, as described above, according to the first embodiment, no training operations are performed during the period from time t21 to t25, and the training operations are performed at time t26. In other words, according to the first embodiment, the frequency of training operations is reduced compared to the comparative example.

[0104] As described above, according to the first embodiment, the memory chip 100 includes a signal processing circuit 101, a data register 111 which is a buffer circuit, and a memory cell array 113. The signal processing circuit 101 includes a latch circuit 120 and a delay circuit 123, and the delay circuit 123 is connected to terminal T DQSIt is placed between the sensor and the latch circuit 120. The controller 200 monitors the temperature change based on the temperature detected by the temperature sensor 300. If the temperature change is less than the threshold Th1, the controller 200 performs a normal light operation. If the temperature change exceeds the threshold Th1, the controller 200 performs a latch test light operation for the first light operation after the temperature change exceeds the threshold Th1.

[0105] In a latch test write operation, the controller 200 performs a data input operation and a latch test operation, which retrieves the data to be written that has been taken into the latch circuit 120 by the data input operation and stored in the data register 111, and retrieves the number of error bits contained in the retrieved data. The number of error bits is the threshold Th err1 If it is greater than the threshold Th, the controller 200 performs the training operation. The number of error bits is the threshold Th err1 If the value is smaller, the controller 200 continues with the light operation (i.e., the programmed operation) without performing the training operation.

[0106] Therefore, the frequency of training operations is reduced, and latch test operations to determine whether or not to skip training operations are executed efficiently. As a result, performance degradation of memory system 1 caused by training operations is suppressed.

[0107] (modified version) The data used for the latch test operation is not limited to the data initially transferred to the memory chip 100 during the write operation (i.e., lower page data). As a variation, an example is described in which the latch test operation is performed using the data last transferred to the memory chip 100 during the write operation (i.e., upper page data).

[0108] Figure 10 shows an example of the operation before and after a latch test according to a modified version of the first embodiment. In this example, it is assumed that four memory chips 100_0, 100_1, 100_2, and 100_3 are connected to the memory bus 400. The horizontal axis in parts (A) and (B) of this figure represents time.

[0109] Part (A) of Figure 10 shows that the number of error bits is determined by the latch test operation, which is the threshold Th err1 The operation in the case where a larger result was obtained is shown. First, a read operation is performed on memory chip 100_1 during the period from time t30 to time t32.

[0110] At time t31, the temperature change exceeds the threshold Th1. Accordingly, at time t32, a write operation to memory chip 100_0 is initiated.

[0111] Specifically, the controller 200 executes the following data-in operations in this order (time t32): a data-in operation to transfer lower page data (Din(Low)), a data-in operation to transfer middle page data (Din(Mid)), and a data-in operation to transfer upper page data (Din(Up)).

[0112] Next, the controller 200 initiates a program operation on the memory chip 100_0 to store the lower page data, middle page data, and upper page data into a single memory cell group MCG (time t33). Furthermore, while initiating the program operation on the memory chip 100, the controller 200 performs a data out operation (Dout(Up)) to acquire the upper page data that has been captured by the latch circuit 120 and stored in the data register 111. The controller 200 performs error correction on the upper page data acquired by the data out operation and obtains the number of error bits. Then, the controller 200 calculates the number of error bits and the threshold Th err1 A comparison will be made.

[0113] In the example of part (A) in Figure 10, the number of error bits is the threshold Th err1 It is set to be larger. Therefore, the controller 200 interrupts the program operation of the memory chip 100 and performs the training operation (time t34).

[0114] Once the training operation is complete (time t35), the controller 200 executes the following data-in operations in this order: a data-in operation to transfer lower page data (Din(Low)), a data-in operation to transfer middle page data (Din(Mid)), and a data-in operation to transfer upper page data (Din(Up)). Then, the controller 200 causes the memory chip 100_0 to execute a program operation to store the lower page data, middle page data, and upper page data into a single memory cell group MCG (time t36).

[0115] Part (B) of Figure 10 shows that the number of error bits is determined by the latch test operation, which is the threshold Th err1 The operation in the case where the following result was obtained is shown. Until time t33, the same operation as in part (A) is performed. At time t33, the controller 200 causes the memory chip 100_0 to start a program operation to store the lower page data, middle page data, and upper page data into a single memory cell group MCG. Furthermore, the controller 200 causes the memory chip 100 to start the program operation and also performs a data out operation (Dout(Up)) to acquire the upper page data that has been taken up by the latch circuit 120 and stored in the data register 111. The controller 200 performs error correction on the upper page data acquired by the data out operation and obtains the number of error bits. Then, the controller 200 calculates the number of error bits and the threshold Th err1 A comparison will be made.

[0116] In the example of part (B) of Figure 10, the number of error bits is the threshold Th err1The following conditions are met. Therefore, the controller 200 does not execute the training operation and instead causes the memory chip 100 to continue the program operation (time t41).

[0117] In this way, the controller 200 performs the latch test operation after the data-in operation for all data to be written to the three pages is complete. This makes it possible to overlap the execution period of the data-out operation for the latch test operation with the period during which the program operation is executed. In other words, the time required for the execution of the latch test operation can be hidden by the execution of the program operation, further improving the efficiency of the latch test operation.

[0118] In the example shown in Figure 10, the execution period of the data-out operation for the latch test was included in the period during which the program operation was executed. The timing of the execution of the latch test operation and the execution of the program operation are arbitrary, as long as the execution period of the data-out operation for the latch test operation overlaps with at least a portion of the execution period of the program operation.

[0119] Furthermore, in the example shown in Figure 10, the upper page data among the three data to be written was used for the latch test operation. The data used for the latch test operation is not limited to the upper page data. The controller 200 can use any of the three data to be written for the latch test operation, as long as the data can be obtained through the data-out operation.

[0120] (Second embodiment) In the second embodiment, differences from the first embodiment will be described. Matters that are the same as in the first embodiment will be described briefly or omitted.

[0121] Figure 11 is a diagram illustrating an example of the timing of a latch test write operation according to the second embodiment. This figure shows the time progression of the temperature change and the time progression of the number of error bits obtained when the latch test operation is performed.

[0122] In the example shown in Figure 11, the temperature reference value is set (or updated) at time t50.

[0123] At time t51, the temperature change exceeds the threshold Th1. In response to the temperature change exceeding the threshold Th1, the controller 200 performs a latch test light operation during the first light operation after time t51 when the temperature change exceeded the threshold Th1 (time t52).

[0124] In the second embodiment, the number of error bits in the initial latch test write operation is less than the threshold Th err1 Even if a smaller result is obtained and the training operation is skipped, the latch test-write operation is performed at several different timings thereafter. This prevents the degree of error that occurs during data acquisition by the latch circuit 120 after the initial latch test-write operation from deviating from the acceptable range.

[0125] Specifically, in the example shown in Figure 11, the controller 200 performs a latch test light operation after a predetermined number of light operations (denoted as N times) (times t53, t54). N is, for example, an integer of 2 or more. N is set in advance. N may also be configurable from the host 2. Note that N is an example of a second setting value.

[0126] The threshold bit used for comparison with the error bit count may be the same or different for the initial latch test write operation and the latch test write operation performed every N write operations. Here, as an example, the threshold bit Th is used for the initial latch test write operation. err1 A threshold Th is used in the latch test light operation, which is performed every N light operations. err1 A threshold smaller than Th err2 This is used. In other words, in the latch test light operation performed every N light operations, the criteria for deciding when to start the training operation are made stricter compared to the first latch test light operation.

[0127] During operation under conditions of large temperature fluctuations, even if the number of error bits obtained in the latch test operation exceeds the threshold Th err1 Th err2 Even if the target is not reached, the degree of error that occurs during data acquisition by the latch circuit 120 remains at a poor level. Therefore, if operation continues for a certain period of time under conditions of large temperature changes, the training operation and the updating of the temperature reference value are forcibly performed.

[0128] Specifically, in the example shown in Figure 11, when a predetermined number of write operations (denoted as M times) are performed after the temperature change exceeds the threshold Th1, the controller 200 forcibly performs a training operation and updates the temperature reference value (time t55). M is, for example, an integer of 2 or more. M is set in advance. M may also be configurable from the host 2. Note that M is an example of a first setting value.

[0129] At time t55, the temperature reference value is updated, causing the temperature change to transition to 0. When the training operation ends (time t56), the number of error bits is suppressed compared to times t52-t55, when the system operated with a large temperature change.

[0130] Furthermore, in the second embodiment, in addition to threshold Th1, threshold Th2 may be provided as a threshold for the amount of temperature change. Threshold Th2 is greater than threshold Th1. When the amount of temperature change reaches threshold Th2, the controller 200 forcibly performs training and updates the temperature reference value. Threshold Th2 is preset. Threshold Th2 may also be configurable from host 2. Threshold Th2 is an example of a third threshold. The controller 200 may not perform training if the amount of temperature change is equal to threshold Th2, but may perform training if the amount of temperature change is greater than threshold Th2.

[0131] Figure 12 is a flowchart showing an example of the operation of the controller 200 according to the second embodiment. Note that read and erase operations are not mentioned in this description. Read and erase operations are performed as usual. The series of operations shown in this figure are performed for each memory chip 100.

[0132] First, in step S201, the same process as in step S101 shown in Figure 8 is performed. That is, the controller 200 sets a reference temperature value (S201). Then, the controller 200 monitors the temperature change and determines whether the temperature change exceeds the threshold Th1.

[0133] When the temperature change exceeds the threshold Th1 (S202), the controller 200 starts counting the number of times the write operation has been performed since the temperature change exceeded the threshold Th1 (S203).

[0134] If the temperature change does not exceed the threshold Th1, the controller 200 can perform a normal light operation. However, the processing when the temperature change reaches the threshold Th1 but does not exceed it is not limited to this. If the temperature change reaches the threshold Th1, the control may transition to step S203.

[0135] Next, the controller 200 determines whether the temperature change is less than or equal to the threshold Th1 (S204). If the temperature change is less than or equal to the threshold Th1 (S204: Yes), the controller 200 continues normal operation until the temperature change exceeds the threshold Th1 (S202).

[0136] If the temperature change is not below the threshold Th1 (S204: No), the controller 200 determines whether the temperature change is above the threshold Th2 (S205).

[0137] If the temperature change is greater than or equal to the threshold Th2 (S205: Yes), the controller 200 performs a training operation (S206). Upon the start of the training operation, the controller 200 updates the temperature change reference value in the same manner as in step S201 (S207), and the control transitions to step S202.

[0138] If the temperature change is not greater than or equal to the threshold Th2 (S205: No), the controller 200 determines whether the next light operation to be performed is the first light operation after the temperature change has exceeded the threshold Th1 (S208).

[0139] If the next light operation to be performed is the first light operation after the temperature change exceeds the threshold Th1 (S208: Yes), the controller 200 performs a latch test light operation.

[0140] Specifically, the controller 200 first performs a data-in operation to transfer lower page data (S209). Then, the controller 200 performs a data-out operation to retrieve the lower page data that was transferred to the memory chip 100 by the data-in operation and stored in the data register 111 of the memory chip 100 (S210). The controller 200 retrieves the number of error bits of the lower page data retrieved from the memory chip 100 (S211). Then, the controller 200 calculates the number of error bits and the threshold Th err1 Compare them.

[0141] The number of error bits is the threshold Th err1 If it is greater than (S212: Yes), the controller 200 interrupts the light operation (S213), and control transitions to step S206, that is, the controller 200 performs the training operation (S206).

[0142] The number of error bits is the threshold Th err1 If it is not greater than (S212: No), the controller 200 continues the light operation (S214), and the control transitions to step S204.

[0143] If the next light operation to be performed is not the first light operation after the temperature change exceeds the threshold Th1 (S208: No), the controller 200 determines whether the next light operation to be performed is the Mth light operation after the temperature change exceeds the threshold Th1 (S215).

[0144] If the next light operation to be performed is the Mth light operation after the temperature change exceeds the threshold Th1 (S215: Yes), the controller 200 performs a normal light operation (S216). Then, the control transitions to step S206, which is when the controller 200 performs a training operation (S206).

[0145] If the next light operation to be performed is not the Mth light operation after the temperature change exceeds the threshold Th1 (S215: No), the controller 200 determines whether the next operation to be performed is the Nth light operation since the previous latch test light operation (S217).

[0146] If the next operation to be performed is the Nth write operation since the previous latch test write operation (S217: Yes), the controller 200 performs the latch test write operation. However, the threshold Th err1 Instead, threshold Th err2 This is used.

[0147] Specifically, the controller 200 first performs a data-in operation to transfer lower page data (S218). Then, the controller 200 performs a data-out operation to retrieve the lower page data that was transferred to the memory chip 100 by the data-in operation and stored in the data register 111 of the memory chip 100 (S219). The controller 200 obtains the number of error bits of the lower page data obtained from the memory chip 100 (S220). Then, the controller 200 calculates the number of error bits and the threshold Th err2 Compare them.

[0148] The number of error bits is the threshold Th err2 If it is greater than (S221: Yes), the control transitions to step S213. That is, the controller 200 interrupts the light operation (S213) and performs the training operation (S206).

[0149] The number of error bits is the threshold Th err2 If it is not greater than (S221: No), the control transitions to step S214. That is, the controller 200 continues the light operation (S214).

[0150] If the next operation to be performed is not the Nth light operation since the previous latch test light operation (S217: No), the controller 200 performs a normal light operation as the next light operation (S222). Then, the control transitions to step S204.

[0151] In the example shown in Figure 12, lower page data was used in the latch test operation. However, the data used in the latch test operation is not limited to lower page data. For example, modifications of the first embodiment are also applicable to the second embodiment.

[0152] As described above, according to the second embodiment, the controller 200 performs a training operation when the number of light operations performed after the temperature change exceeds the threshold Th1 reaches M times.

[0153] During operation under conditions of large temperature fluctuations, the degree of error during data acquisition by the latch circuit 120 remains at a high level. When the number of write operations reaches M, the controller 200 forcibly executes a training operation, thereby reducing the degree of error during data acquisition by the latch circuit 120.

[0154] Furthermore, according to the second embodiment, the controller 200 performs a latch test light operation every N light operations.

[0155] Therefore, after the initial latch test write operation, it is prevented that the degree of error that occurs when acquiring data by the latch circuit 120 deviates from the acceptable range.

[0156] Furthermore, according to the second embodiment, the threshold Th used in the latch test light operation performed every N light operations is err2 This is the threshold Th used in the initial latch test light operation. err1 Smaller.

[0157] Therefore, in subsequent latch test light operations, it becomes possible to determine whether or not to perform the training operation using stricter criteria than in the initial latch test light operation.

[0158] Furthermore, according to the second embodiment, the controller 200 performs a training operation when the temperature change is greater than the threshold Th2.

[0159] In the first embodiment, the second embodiment, and its variations, the controller 200 performed a latch test write operation when the temperature change exceeded the threshold Th1. The trigger for the latch test write operation is not limited to this. For example, the delay time in the delay circuit 123 can also be varied by fluctuations in the voltage of the power supplied to the memory chip 100. Therefore, the controller 200 may perform a latch test write operation based on a trigger derived from the voltage of the power supplied to the memory chip 100.

[0160] Furthermore, examples of triggers for latch test light operation based on temperature change are specifically illustrated in Figures 8 and 12. The triggers for latch test light operation based on temperature change are not limited to these examples.

[0161] Furthermore, during the latch test operation, the controller 200 retrieves the data stored in the data register 111 by a data-out operation and obtains the number of error bits by performing error correction on the retrieved data using the ECC circuit 206. The method for obtaining the number of error bits is not limited to the method using the ECC circuit 206. For example, when the controller 200 performs a data-in operation, it may store a copy of the data to be used in the data-in operation in, for example, RAM 202. Then, during the latch test operation, the controller 200 retrieves the data stored in the data register 111 by a data-out operation and obtains the number of error bits by comparing the retrieved data with the copy previously stored in RAM 202 or the like.

[0162] As described above in the first embodiment, the second embodiment, and the modifications, the controller 200 is capable of performing either a normal light operation or a latch test light operation.

[0163] The latch test light operation improves the efficiency of the latch test operation used to determine whether or not to perform the training operation, and also reduces the frequency of training operation execution. Therefore, performance degradation caused by training operations is suppressed.

[0164] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0165] 1 Memory system, 2 Host, 100, 100_0, 100_1, 100_2, 100_3 Memory chip, 101 Signal processing circuit, 103 Control circuit, 104 Command register, 105 Address register, 106 Status register, 107 Voltage generation circuit, 109 Column buffer, 110 Column decoder, 111 Data register, 112 Sense amplifier, 113 Memory cell array, 114 Row address buffer decoder, 115 Row address decoder, 120 Latch circuit, 121, 122 Driver, 123 Delay circuit, 140 Memory string, 200 Controller, 201 Host interface circuit, 202 RAM, 203 CPU, 204 Buffer memory, 205 Memory interface circuit, 206 ECC circuit, 300 Temperature sensor, 400 Memory bus.

Claims

1. A memory device comprising: a first terminal into which a data signal is input; a second terminal into which a data strobe signal is input; a receiving circuit comprising a latch circuit for acquiring data from the data signal based on the data strobe signal and a delay circuit disposed between the second terminal and the latch circuit; a memory cell array; and a buffer circuit disposed between the memory cell array and the receiving circuit. A controller connected to the memory device via the first and second terminals, capable of performing either a first write operation including a data-in operation and a program operation, or a second write operation, Equipped with, In the aforementioned data input operation, the controller: The first data, which is the data to be written, is transferred to the memory device by the data signal and the data strobe signal. The memory device is made to store the first data acquired by the latch circuit in the buffer circuit. In the program operation described above, the controller, The memory device is made to store the first data stored in the buffer circuit in the memory cell array. In the second light operation, the controller, The aforementioned data input operation is performed, The first data, which has been taken into the latch circuit and stored in the buffer circuit by the data input operation, is acquired. The number of error bits included in the acquired first data is obtained, If the number of error bits is greater than the first threshold, a training operation is performed to adjust the delay time of the delay circuit. If the number of error bits is less than the first threshold, the program operation is executed without performing the training operation. Memory system.

2. In the second light operation, the controller, If the number of error bits is less than the first threshold, the program operation is executed without repeating the data-in operation. The memory system according to claim 1.

3. Equipped with an additional temperature sensor, The aforementioned controller, Based on the temperature detected by the temperature sensor, the amount of temperature change from the reference value is monitored. Based on the aforementioned temperature change, it is determined whether to perform the first light operation or the second light operation during the light operation. The reference value is updated in accordance with the execution of the training operation. The memory system according to claim 1.

4. Equipped with an additional temperature sensor, The aforementioned controller, Based on the temperature detected by the temperature sensor, the amount of temperature change from the reference value is monitored. If the amount of temperature change is less than the second threshold, the first light operation is performed in the light operation. If the amount of temperature change exceeds the second threshold, the second light operation is performed in the first light operation after the amount of temperature change exceeds the second threshold. The reference value is updated in accordance with the execution of the training operation. The memory system according to claim 1.

5. The controller further executes the training operation when the number of times the light operation has been performed after the temperature change exceeds the second threshold reaches a first set value. The memory system according to claim 4.

6. The controller further executes the second light operation each time the number of times the second light operation is performed after the second light operation is performed reaches a second set value. The memory system according to claim 4.

7. The value of the first threshold used in the second light operation, which is performed each time the number of light operations performed after the second light operation reaches the second setpoint, is smaller than the value of the first threshold used in the second light operation, which is performed in the first light operation after the temperature change exceeds the second threshold. The memory system according to claim 6.

8. The controller executes the training operation when the amount of temperature change is greater than the third threshold which is greater than the second threshold. The memory system according to claim 4.

9. The controller, in the second write operation, performs the acquisition of the first data during a period that overlaps at least partially with the execution period of the program operation. A memory system according to any one of claims 1 to 8.

10. The memory cell array comprises a plurality of memory cell groups, Each of the aforementioned multiple memory cell groups comprises multiple pages, The first data includes a plurality of second data, each of which is stored in a different page among the plurality of pages. In the second light operation, the controller The buffer circuit retrieves the second data to be stored in one of the pages among the plurality of second data, The number of error bits included in the acquired second data is obtained. A memory system according to any one of claims 1 to 8.

Images