Manufacturing method for chip-type electronic components

Abstract

To provide a method for manufacturing chip-type electronic components that improves yield. [Solution] The method for manufacturing this chip-type electronic component includes a base sheet forming step S01 in which a plurality of base sheets 21 are formed, a laminate forming step S02 in which the plurality of base sheets 21 are stacked to form a laminate 31, and a cutting step S03 in which the laminate 31 is cut to obtain a plurality of chip-type electronic components 1A. In the base sheet forming step S01, in each of the plurality of base sheets 21, chip regions 22 aligned in a first direction E1 are separated by slits S1 in a second direction E2 by patterning, while chip regions 22 aligned in the second direction E2 are left connected. In the cutting step S03, the laminate 31 is cut only in the first direction E1.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing chip-type electronic components.

Background Art

[0002] Patent Document 1 describes a method for manufacturing an electronic component including a step of forming a laminate having a plurality of chip regions before division, a step of cutting the laminate according to the chip regions to obtain a plurality of chips, and a step of firing the plurality of chips. In the method of Patent Document 1, in the step of cutting the laminate, since a pair of external electrodes are obtained simultaneously with the cutting of the chip regions, the step of forming the external electrodes is omitted.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing an electronic component as described above, an improvement in yield by reducing the lamination shift of the conductor pattern in the chip regions overlapping in the lamination direction when forming the laminate, or reducing the cutting shift when cutting the laminate, is an issue.

[0005] This disclosure has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a chip-type electronic component in which an improvement in yield is achieved.

Means for Solving the Problems

[0006] The gist of this disclosure is as follows.

[0007] [1] A method for manufacturing a chip-type electronic component, comprising: a base sheet forming step of forming a plurality of base sheets in which a plurality of chip regions before division are arranged in a first direction and a second direction perpendicular to the first direction, and a predetermined conductor pattern is provided in each of the plurality of chip regions; a laminate forming step of stacking the plurality of base sheets so that the plurality of chip regions overlap in the stacking direction to form a laminate; and a cutting step of cutting the laminate according to the plurality of chip regions to obtain a plurality of chip-type electronic components, wherein in the base sheet forming step, in each of the plurality of base sheets, the chip regions arranged in the first direction are separated from each other by slits in the second direction by patterning, while the chip regions arranged in the second direction are left connected; and in the cutting step, the laminate is cut only in the first direction.

[0008] In this method for manufacturing chip-type electronic components, in multiple base sheets used to form a laminate, chip regions aligned in a first direction are separated by patterning slits, while chip regions aligned in a second direction are left connected. Because the chip regions aligned in the second direction are connected, multiple chip regions can be treated as a single sheet. Therefore, compared to cases where chip regions are separated in both the first and second directions, the misalignment of conductor patterns in overlapping chip regions during the lamination process can be reduced. Furthermore, in this method for manufacturing chip-type electronic components, since the laminates aligned in the first direction are pre-separated by patterning slits, the laminates aligned in the second direction can be cut only in the first direction, allowing the laminate to be broken down into individual chip-type electronic components. Therefore, the cutting of the laminate is simplified, and cutting misalignment is reduced. As a result, this method for manufacturing chip-type electronic components improves yield.

[0009] [2] The method for manufacturing a chip-type electronic component according to [1], wherein the chip-type electronic component has an internal conductor disposed inside a body and an external electrode exposed on a part of the mounting surface of the body and a part of the end face continuous with the mounting surface, and in the body sheet forming step, the slit is formed along the edge corresponding to the end face in each of the plurality of chip regions.

[0010] The inner wall surface of the slit created by patterning is formed obliquely to the thickness direction of the base sheet. Therefore, when a slit is formed along the edge corresponding to the end face of a chip-type electronic component, a groove is formed at the end face of the final chip-type electronic component due to the stacking of the inner wall surfaces of the slit. This groove formation allows bonding materials such as solder to bite into the groove when mounting the chip-type electronic component onto other components, ensuring sufficient bonding strength. Furthermore, both the base material and the external electrode are present at the end face, and the groove is formed across the base material and the external electrode. As a result, even if the base material and electrode parts, which are made of different materials, coexist on the outer surface of the base material, stress concentration at the boundary between the base material and the electrode parts is mitigated.

[0011] [3] The chip-type electronic component comprises an internal conductor disposed inside a base body and external electrodes exposed on a part of the mounting surface of the base body and a part of the end face continuous with the mounting surface, wherein in the base body sheet forming step, the slit is formed along the edge corresponding to the mounting surface in each of the plurality of chip regions, the method for manufacturing a chip-type electronic component according to [1].

[0012] The inner wall surface of the slit created by patterning is formed obliquely to the thickness direction of the base sheet. Therefore, when a slit is formed along the edge corresponding to the mounting surface of a chip-type electronic component, a groove is formed on the mounting surface of the final chip-type electronic component due to the stacking of the inner wall surfaces of the slit. This groove formation allows bonding materials such as solder to bite into the groove when mounting the chip-type electronic component to other components, ensuring sufficient bonding strength. Furthermore, both the base material and external electrodes are present on the mounting surface, and the groove is formed across both the base material and the external electrodes. As a result, even if the base material and electrode parts, which are made of different materials, coexist on the outer surface of the base material, stress concentration at the boundary between the base material and electrode parts is mitigated.

[0013] [4] A method for manufacturing a chip-type electronic component according to any one of [1] to [3], wherein in the base sheet forming step, the plurality of chip regions belonging to a row aligned in the first direction are arranged in each of the plurality of base sheets with a displacement in the first direction relative to the plurality of chip regions belonging to a row adjacent to the first row. In this case, even if the chip regions aligned in the first direction are separated by slits made by patterning, one chip region can be made to be connected to the plurality of chip regions adjacent to that one chip region in the second direction. Therefore, the misalignment of the conductor patterns in chip regions that overlap in the stacking direction when forming a laminate can be reduced even more effectively.

[0014] [5] A method for manufacturing a chip-type electronic component according to [2] or [3], wherein in the laminate formation step, the plurality of base sheets are laminated while alternately offsetting each of the plurality of base sheets to one and the other in the first direction, in a range where at least a portion of the slits of the plurality of base sheets overlap when viewed from the lamination direction. In this case, the groove portion of the outer surface of the final obtained chip-type electronic component has irregularities formed not only on the inner wall surface of the slits due to lamination, but also on the irregularities due to the offset of the base sheets. Therefore, the bonding strength of the chip-type electronic component is further improved.

[0015] [6] A method for manufacturing a chip-type electronic component according to any one of [1] to [5], wherein in the base sheet forming step, slits in a first direction are further formed by patterning in a range in which the slits do not take on a closed shape. By forming slits in a first direction by patterning in a range in which multiple chip regions can be treated as a sheet, the portion that needs to be cut can be reduced when cutting a laminate arranged in a second direction only in the first direction. Therefore, cutting the laminate becomes easier, and cutting deviations when cutting the laminate can be reduced even more reliably. By reducing the portion that needs to be cut, the load on the blade during cutting can be reduced. This suppresses blade wear and reduces dimensional variations of chip-type electronic components obtained by fragmenting the laminate. [Effects of the Invention]

[0016] According to this disclosure, yield improvements can be achieved. [Brief explanation of the drawing]

[0017] [Figure 1] This is a schematic perspective view of a chip-type electronic component according to one embodiment of the present disclosure. [Figure 2] Figure 1 is a schematic exploded perspective view of a chip-type electronic component. [Figure 3] Figure 1 is a schematic, enlarged perspective view of the main components of a chip-type electronic component. [Figure 4] Figure 1 is a schematic, enlarged side view of the main components of the chip-type electronic component shown. [Figure 5] This is a schematic, enlarged side view of the main part showing the groove. [Figure 6] This is a schematic, enlarged perspective view of the main part of a modified chip-type electronic component. [Figure 7] Figure 6 is a schematic, enlarged side view of the main components of the chip-type electronic component shown. [Figure 8] This is a schematic enlarged side view of the main part of a chip-type electronic component relating to another modified example. [Figure 9] This flowchart shows a method for manufacturing a chip-type electronic component according to one embodiment of the present disclosure. [Figure 10] It is a schematic plan view of a green sheet formed in the green sheet forming step. [Figure 11] It is a schematic cross-sectional view of a laminate formed in the laminate forming step. [Figure 12] It is a schematic plan view of a green sheet formed in the green sheet forming step according to a modification. [Figure 13] It is a schematic cross-sectional view of a laminate formed in the laminate forming step according to a modification. [Figure 14] It is a schematic plan view of a green sheet formed in the green sheet forming step according to another modification. [Figure 15] (a) and (b) are schematic plan views of a green sheet formed in the green sheet forming step according to still another modification. [Embodiments for Carrying Out the Invention]

[0018] Hereinafter, a preferred embodiment of a method for manufacturing a chip-type electronic component according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0019] [Configuration of Chip-Type Electronic Component] FIG. 1 is a schematic perspective view of a chip-type electronic component according to an embodiment of the present disclosure. Further, FIG. 2 is a schematic exploded perspective view of the chip-type electronic component shown in FIG. 1.

[0020] The chip-type electronic component 1A shown in FIGS. 1 and 2 is a multilayer coil component such as a high-frequency inductor, for example. As shown in FIGS. 1 and 2, the chip-type electronic component 1A includes a base body 2, an internal conductor 3 disposed inside the base body 2, and a pair of external electrodes 4 (4A, 4B) disposed on the outer surface of the base body 2.

[0021] Body 2 has, for example, a rectangular parallelepiped shape. The rectangular parallelepiped shape may include a shape with chamfered corners and edges, or a shape with rounded corners and edges. The outer surface of body 2 has a pair of opposing end faces 2a, 2b, a pair of opposing side faces 2c, 2d, and a pair of opposing main faces 2e, 2f. Side face 2c is the mounting surface P of the chip-type electronic component 1A. The mounting surface P is the surface that faces other electronic components (such as a circuit board) when the chip-type electronic component 1A is mounted on those other electronic components.

[0022] For convenience, in the following explanation, the opposing directions of the end faces 2a and 2b will be referred to as the first direction D1, the opposing directions of the side faces 2c and 2d as the second direction D2, and the opposing directions of the main faces 2e and 2f as the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are orthogonal to each other and constitute a three-dimensional Cartesian coordinate system. The third direction D3 coincides with the stacking direction of the base layer 11, which will be described later. The length of the base 2 in the first direction D1 may be longer than the length of the base 2 in the second direction D2. The length of the base 2 in the second direction D2 may be approximately the same as the length of the base 2 in the third direction D3.

[0023] The base body 2 is constructed by stacking multiple base body layers 11. Here, as shown in Figure 2, the base body 2 is constructed by stacking base body layers 11a to 11h in a third direction D3. In the actual base body 2, the multiple base body layers 11a to 11h are integrated to such an extent that the boundaries between these layers are not visible. The base body layers 11a and 11h located at the stacking edges do not have the internal conductor 3 and external electrodes 4A and 4B placed on them, and are layers composed only of the base body portion. The base body layers 11a and 11h function as protective layers for the internal conductor 3 and external electrodes 4A and 4B. The base body layers 11a and 11h may consist of multiple layers. In the example in Figure 2, both base body layers 11a and 11h consist of two layers.

[0024] The base layers 11a to 11h are composed of, for example, magnetic materials (Ni-Cu-Zn ferrite materials, Ni-Cu-Zn-Mg ferrite materials, Ni-Cu ferrite materials, etc.). The magnetic materials constituting the base layers 11a to 11h may include Fe alloys, etc. The base layers 11a to 11h may also be composed of non-magnetic materials (glass ceramic materials, dielectric materials, etc.).

[0025] In the example shown in Figure 2, the internal conductor 3 is composed of coil conductors 12c to 12f and connecting conductors 13a and 13b. Examples of conductive materials that make up the internal conductor 3 include Cu and Ni. The internal conductor 3 is, for example, a sintered body of a conductive paste containing the above conductive material. The internal conductor 3 may be composed of the same conductive material as the conductive material that makes up the external electrode 4, or it may be composed of a different conductive material than the conductive material contained in the external electrode 4.

[0026] The coil conductors 12c to 12f are conductors that constitute coil C (see Figure 1). Coil conductor 12c is patterned on the base layer 11c, and coil conductor 12d is patterned on the base layer 11d. Coil conductor 12e is patterned on the base layer 11e, and coil conductor 12f is patterned on the base layer 11f. The coil conductors 12c to 12f are electrically connected to each other in a third direction D3, which is the stacking direction of the base layers 11c to 11f, and constitute coil C within the base 2.

[0027] The connecting conductors 13a and 13b are conductors that electrically connect coil C to external electrodes 4A and 4B. Connecting conductor 13a is patterned in the base layer 11c together with coil conductor 12c, and connects the end of coil conductor 12c, which forms one end of coil C, to external electrode 4A. Connecting conductor 13b is patterned in the base layer 11f together with coil conductor 12f, and connects the end of coil conductor 12f, which forms the other end of coil C, to external electrode 4B.

[0028] The external electrode 4 is a terminal electrode for electrically connecting the chip-type electronic component 1A to other electronic components. Examples of conductive materials that make up the external electrode 4 include Cu and Ni. The outer surface of the external electrode 4 may be provided with a plating layer by electroplating or electroless plating. The plating layer may be, for example, a Ni plating layer, a Sn plating layer, or an Au plating layer. The plating layer may be a single layer or multiple layers.

[0029] In this embodiment, the external electrode 4 is L-shaped when viewed from the third direction D3 and is embedded in the base body 2 flush with the outer surface of the base body 2. The external electrode 4A is provided across a part of the side surface 2c, which is the mounting surface P (the part on the end surface 2a side), and a part of the end surface 2a that is continuous with the side surface 2c. The length of the external electrode 4A in the first direction D1 on the mounting surface P is smaller than the length of the base body 2 in the first direction D1. The length of the external electrode 4A in the third direction D3 on the mounting surface P is smaller than the length of the base body 2 in the third direction D3.

[0030] The length of the external electrode 4A in the second direction D2 at the end face 2a is smaller than the length of the base body 2 in the second direction D2. The length of the external electrode 4A in the third direction D3 at the end face 2a is smaller than the length of the base body 2 in the third direction D3. Therefore, both the base body 2 and the external electrode 4A are exposed on the mounting surface P and the end face 2a.

[0031] The external electrode 4B is provided across a portion of the side surface 2c (the portion on the end face 2b side) and a portion of the end face 2b that is continuous with the side surface 2c. The length of the external electrode 4B in the first direction D1 on the mounting surface P is shorter than the length of the base body 2 in the first direction D1. The length of the external electrode 4B in the third direction D3 on the mounting surface P is shorter than the length of the base body 2 in the third direction D3. Therefore, both the base body 2 and the external electrode 4B are exposed on the mounting surface P and the end face 2b.

[0032] External electrodes 4A and 4B are constructed by stacking multiple electrode portions. As shown in Figure 2, external electrode 4A is constructed by stacking L-shaped electrode portions 14Ab to 14Ag, which are patterned on the edges of the base layers 11b to 11g on the mounting surface P side and the edge of the end surface 2a side, in a third direction D3. External electrode 4B is constructed by stacking L-shaped electrode portions 14Bb to 14Bg, which are patterned on the edges of the base layers 11b to 11g on the mounting surface P side and the edge of the end surface 2b side, in a third direction D3.

[0033] Figure 3 is a schematic, enlarged perspective view of the main components of the chip-type electronic component shown in Figure 1. Figure 4 is an enlarged side view of the main components of the chip-type electronic component shown in Figure 1. Figures 3 and 4 show the outer surface of the element 2 around the external electrode 4A, but the outer surface of the element 2 around the external electrode 4B has a similar configuration.

[0034] As shown in Figures 3 and 4, the outer surface of the base body 2 of the chip-type electronic component 1A is provided with grooves M that extend in a direction perpendicular to the stacking direction of the base body layer 11, spanning from the base body 2 to the external electrode 4. In this embodiment, the grooves M are provided in a straight line along the second direction D2 at end faces 2a and 2b. The length of the grooves M in the second direction D2 is equal to the length of the base body 2 in the second direction D2. That is, the grooves M are provided so as to connect the two ends of end faces 2a and 2b in the second direction D2.

[0035] In this embodiment, the grooves M are formed due to slits S1 (see Figure 10) provided in the base sheet 21A, described later, used in the manufacturing process of the chip-type electronic component 1A. Therefore, grooves M are provided for each base layer 11, and multiple grooves are arranged in the stacking direction of the base layers 11. Here, corresponding to the number of base layers 11a to 11h, 10 grooves extending along the second direction D2 are arranged in the third direction D3 at each of the end faces 2a and 2b.

[0036] In each of the base layers 11a to 11h, the side surface 11A corresponding to the end faces 2a and 2b is inclined with respect to a surface 11B facing the main faces 2e and 2f, as shown in Figure 5, so that the base layers 11a to 11h widen from the main face 2e side towards the main face 2f side. Each of the grooves M is defined by a surface 11B of each of the base layers 11a to 11h and a side surface 11A inclined with respect to that surface 11B, as the base layers 11a to 11h are stacked in the third direction D3.

[0037] In the example shown in Figure 5, the cross-sectional shape of the groove M is triangular with the side surface 11A as the hypotenuse. The angles of the hypotenuse in the cross-sectional shape of the groove M may be equal to or different for each groove M corresponding to each elemental layer 11a to 11h. Depending on the shape of the side surface 11A, the cross-sectional shape of the groove M may be such that the hypotenuse portion is curved in a concave or convex shape.

[0038] In the chip-type electronic component 1A having the above configuration, by forming grooves M on the outer surface of the base body 2, when mounting the chip-type electronic component 1A onto other components, bonding materials such as solder can be embedded in the grooves M, thereby ensuring sufficient bonding strength. Furthermore, in the chip-type electronic component 1A, grooves M are formed on the outer surface of the base body 2, extending from the base body 2 to the external electrodes 4A and 4B. Therefore, even if the base body portion and the electrode portion, which are made of different materials, coexist on the outer surface of the base body 2, stress concentration at the boundary between the base body portion and the electrode portion is alleviated. Thus, the chip-type electronic component 1A can achieve both the assurance of bonding strength during mounting and the alleviation of stress concentration at the boundary between the base body portion and the electrode portion.

[0039] In this embodiment, grooves M are provided for each of the base layers 11a to 11h, and multiple grooves M are arranged in the stacking direction of the base layers 11a to 11h. This allows for a higher level of both ensuring bonding strength during mounting and mitigating stress concentration at the boundary between the base portion and the electrode portion. Furthermore, grooves M for each of the base layers 11a to 11h can be easily formed by adjusting the shape of the side surface 11A of the base layers 11a to 11h that constitute the base 2.

[0040] In this embodiment, the cross-sectional shape of the groove M is defined by one surface 11B of the base layers 11a to 11h and a side surface 11A of the base layer 11 that is inclined with respect to the surface 11B. With this configuration, the groove M can be easily formed by adjusting the shape of the side surface 11A of the base layer 11.

[0041] In this embodiment, the external electrodes 4A and 4B are exposed on a portion of the mounting surface P of the base body 2 and on a portion of the end faces 2a and 2b that are continuous with the mounting surface P, and the grooves M are provided on the end faces 2a and 2b. With this configuration, a joining material such as solder can be embedded in the grooves M on the end faces 2a and 2b of the base body 2, thereby ensuring suitable joining strength.

[0042] Figure 6 is a schematic enlarged perspective view of the main part of a modified chip-type electronic component. Figure 7 is a schematic enlarged side view of the main part thereof. As shown in Figures 6 and 7, the modified chip-type electronic component 1B differs from the chip-type electronic component 1A, in that the groove M is provided on the side surface 2c (mounting surface P), while the groove M is provided on the end surfaces 2a and 2b.

[0043] More specifically, in the chip-type electronic component 1B, the groove is provided in a straight line along the first direction D1 on the mounting surface P. The length of the groove M in the first direction D1 is equal to the length of the element 2 in the first direction D1. That is, the groove M is provided so as to connect the two ends of the mounting surface P in the first direction D1.

[0044] Similar to the chip-type electronic component 1A, the grooves M are formed due to slits S1 (see Figure 12) provided in the base sheet 21B, described later, used in the manufacturing process of the chip-type electronic component 1B. Therefore, grooves M are provided for each base layer 11, and multiple grooves are arranged in the stacking direction of the base layers 11. Here, corresponding to the number of base layers 11a to 11h, 10 grooves extending along the first direction D1 are arranged in the third direction D3 on the mounting surface P.

[0045] The chip-type electronic component 1B, having the configuration described above, exhibits the same effects as the chip-type electronic component 1A, achieving both the securing of bonding strength during mounting and the mitigation of stress concentration at the boundary between the base body and the electrode portion. Furthermore, in the chip-type electronic component 1B, the external electrodes 4A and 4B are exposed on a portion of the mounting surface P of the base body 2 and on a portion of the end faces 2a and 2b continuous with the mounting surface P, and the groove M is provided on the mounting surface P. With this configuration, bonding materials such as solder can be embedded in the groove on the mounting surface P of the base body 2, thereby ensuring suitable bonding strength.

[0046] Figure 8 is a schematic enlarged side view of a key part of a chip-type electronic component according to another modified example. As shown in Figure 8, the chip-type electronic component 1C according to another modified example differs from the chip-type electronic component 1A, which does not have such offset, in that adjacent base layers 11 in the stacking direction are alternately offset with respect to the outer surface on which the grooves M are provided.

[0047] More specifically, in the chip-type electronic component 1C, odd-numbered elemental layers 11 are offset towards the end face 2a when viewed from the main surface 2e, and even-numbered elemental layers 11 are offset towards the end face 2b when viewed from the main surface 2e. The offset amount F between the elemental layer 11 offset towards the end face 2a and the elemental layer 11 offset towards the end face 2b is expressed, for example, as the distance between the leading edge of the side surface of the elemental layer 11 offset towards the end face 2a and the leading edge of the side surface 11A of the elemental layer 11 offset towards the end face 2b. The offset amount F is set within a range that maintains electrical connections between adjacent internal conductors 3 in the stacking direction, between electrode portions 14Ab to 14Ag of the external electrode 4A, and between electrode portions 14Bb to 14Bg of the external electrode 4B. In the manufacturing process, the offset amount F is set within a range smaller than the width of the slit S1 described later.

[0048] In such a chip-type electronic component 1C, in the grooves M on the outer surface (here, end faces 2a, 2b) of the base body 2, in addition to the irregularities formed by the side surface A of the base body layer 11 which is inclined with respect to one surface 11B of the base body layer 11, irregularities are further formed due to the offset of the base body layer 11. Therefore, it is possible to achieve a higher level of both ensuring bonding strength during mounting and mitigating stress concentration at the boundary between the base body and the electrode portion.

[0049] In the example shown in Figure 8, the base layers 11 are offset alternately by one layer each to the end face 2a and end face 2b sides. However, the base layers 11 may be offset alternately by multiple layers each to the end face 2a and end face 2b sides. Furthermore, the offset amounts F of each base layer 11 do not necessarily have to be the same; the offset amount F of at least one base layer 11 may differ from the offset amounts F of the other base layers 11.

[0050] In the example in Figure 8, the base layer 11 is offset to the end face 2a and end face 2b sides in a configuration where the groove M is formed on the end faces 2a and 2b, as in the chip-type electronic component 1A. However, in a configuration where the groove M is formed on the mounting surface P, as in the chip-type electronic component 1B, the base layer 11 may be offset to the side 2c (mounting surface P) side and side 2d side.

[0051] [Manufacturing method for chip-type electronic components] Figure 9 is a flowchart showing a method for manufacturing a chip-type electronic component according to one embodiment of the present disclosure. As shown in Figure 9, the method for manufacturing a chip-type electronic component according to this embodiment comprises a base sheet forming step S01, a laminate forming step S02, a cutting step S03, and a heat treatment step S04.

[0052] The base sheet formation process S01 is a process for forming a plurality of base sheets 21. As shown in Figure 10, the base sheet 21 is a sheet in which a plurality of chip regions 22 before division are arranged in a first direction E1 and a second direction E2. The chip region 22 is a region that corresponds to a base layer of a chip-type electronic component obtained after individualization. Each of the chip regions 22 is provided with a predetermined conductor pattern K that corresponds to the internal conductor 3 (coil conductors 12c to 12f, connecting conductors 13a, 13b) and the electrode portion (electrode portion 14Ab to 14Ag, electrode portion 14Bb to 14Bg) that constitutes the external electrode 4.

[0053] The base sheet 21A shown in Figure 10 is used in the manufacture of the chip-type electronic component 1A described above. In this embodiment, the base sheet 21A includes a plurality of base sheets 21a to 21h corresponding to base layers 11a to 11h. For the sake of explanation, Figure 10 shows a plan view of the base sheet 21A with the base sheets 21a to 21h superimposed. Also, in Figure 10, for the purpose of explaining the orientation of the conductor pattern K, the conductor pattern K formed by superimposing the coil conductors 12c to 12f, connecting conductors 13a and 13b, and electrode portions (electrode portions 14Ab to 14Ag, electrode portions 14Bb to 14Bg) that constitute the external electrode 4 is shown by dashed lines in each chip region 22.

[0054] The base sheets 21a and 21h are sheets corresponding to the base layers 11a and 11h, which function as protective layers, and are composed only of base material. For base sheets 21b to 21g having a conductor pattern K, patterning of the base material portion of each chip region 22 is performed using, for example, photolithography. Here, by exposing and developing the base material portion using, for example, a Cr mask, a groove pattern corresponding to the conductor pattern K is formed on the base material portion of each chip region 22. Subsequently, the conductive paste constituting the conductor pattern K is printed onto the groove pattern of the base material portion to form the conductor pattern K corresponding to each chip region 22.

[0055] As shown in Figure 10, in the base sheets 21a to 21h, multiple chip regions 22 are arranged in two dimensions with the first direction E1 as the row direction and the second direction E2 as the column direction. In the example in Figure 10, the first direction E1 is the same direction as the first direction D1 used in the explanation of the chip-type electronic component 1A, and the second direction E2 is the same direction as the second direction D2 used in the explanation of the chip-type electronic component 1A.

[0056] In the base sheets 21a to 21h, multiple chip regions 22 belonging to a row aligned in the first direction E1 are offset in the first direction E1 relative to multiple chip regions 22 belonging to adjacent rows. There are no particular restrictions on the amount of offset between multiple chip regions 22 belonging to a row and multiple chip regions 22 belonging to adjacent rows. In the example in Figure 10, the amount of offset between multiple chip regions 22 belonging to a row and multiple chip regions 22 belonging to adjacent rows is approximately half the length of the chip region 22 in the first direction E1. As a result, the multiple chip regions 22 in the base sheets 21a to 21h are arranged in a staggered pattern in the column direction.

[0057] In the base sheets 21a to 21h, slits S1 are formed by patterning. The formation of the slits S1 is performed simultaneously with the formation of the groove pattern by the photolithography method, for example, when patterning the base portion using the photolithography method. The inner wall surface Sa of the slit S1 formed by patterning using the photolithography method is formed obliquely with respect to the thickness direction of the base sheets 21a to 21h (see Figure 11). This inner wall surface Sa corresponds to the side surface 11A of the base layer 11 described above. When the base sheets 21a to 21h are viewed from the second direction D2, the cross-sectional shape of the slit S1 is a shape that widens from the exposure side to the opposite side.

[0058] In the example shown in Figure 10, the slit S1 extends in a second direction E2 along the edges 22a and 22b corresponding to the end faces 2a and 2b of the chip-type electronic component 1A that are later formed in each of the multiple chip regions 22. As a result, in the base sheets 21a to 21h, the chip regions 22 aligned in the first direction E1 are separated by the slit S1, while the chip regions 22 aligned in the second direction E2 remain connected to each other. The width of the slit S1 may be, for example, 1 μm to 50 μm, or 1 μm to 20 μm. There is no particular limit to the lower limit of the slit width. The upper limit of the slit width is set considering the width of the blade used in the cutting process S03, as it affects the number of chip-type electronic components that can be manufactured.

[0059] In this embodiment, as described above, multiple chip regions 22 belonging to a row aligned in the first direction E1 are offset in the first direction E1 relative to multiple chip regions 22 belonging to adjacent rows. Therefore, while the chip regions 22 aligned in the first direction E1 are separated by the slit S1, the chip regions 22 aligned in the second direction E2 are connected in an X-shape to the chip regions 22 offset to one side of the first direction E1 and the chip regions 22 offset to the other side of the first direction E1 (see dashed line J in Figure 10).

[0060] The laminate formation process S02 is a process of forming a laminate 31 by stacking multiple base sheets 21a to 21h. In the laminate formation process S02, a base material 32 made of a backing paper or the like is prepared as shown in Figure 11. Then, base sheets 21a to 21h are stacked on one surface of the base material 32 so that multiple chip regions 22 overlap in the stacking direction, thereby forming a laminate 31. In the laminate 31, the stacking of base sheets 21a to 21h forms a base 2, a coil C, and external electrodes 4A and 4B for each chip region 22.

[0061] In laminating the base sheets 21a to 21h, for example, each of the base sheets 21a to 21h may be formed on a substrate such as a PET film in the base sheet formation step S01. In this case, in the laminate formation step S02, the base sheets 21a to 21h are transferred onto the substrate 32 one layer at a time in a predetermined order, and the substrate is peeled off after each transfer, thereby easily forming the laminate 31.

[0062] By stacking the base sheets 21a to 21h, a stack of chip regions 33 is formed on the substrate 32, arranged in two dimensions with the first direction E1 as the row direction and the second direction E2 as the column direction, similar to the chip regions 22 of the base sheets 21a to 21h. In this embodiment, as described above, in the base sheets 21a to 21h, multiple chip regions 22 belonging to one row aligned in the first direction E1 are offset in the first direction E1 relative to multiple chip regions 22 belonging to adjacent rows. Therefore, in the multiple stacks 31 formed by stacking the base sheets 21a to 21h, multiple chip region stacks 33 belonging to one row aligned in the first direction E1 are also offset in the first direction E1 relative to multiple chip region stacks 33 belonging to adjacent rows.

[0063] In the laminate formation process S02, when the base sheets 21a to 21h formed on the substrate are transferred to the backing paper layer by layer, the front and back sides of the base sheets 21a to 21h are reversed from the time they were formed. Therefore, in the laminate 31, as shown in Figure 11, the cross-sectional shape of the slit S1 when the base sheets 21a to 21h are viewed from the second direction D2 becomes a shape that widens towards the base 32.

[0064] Each slit S1 in the base sheets 21a to 21h is stacked in the stacking direction by the stacking of the base sheets 21a to 21h, forming a slit stack Sx. The arrangement of the chip region stacks 33 in the first direction E1 and the second direction E2 maintains the arrangement of the chip regions 22 in the base sheets 21a to 21h. The chip region stacks 33 aligned in the first direction E1 are separated from each other by the slit stack Sx. The chip region stacks 33 aligned in the second direction E2 are connected in an X-shape to the chip region stack 33 shifted to one side of the first direction E1 and the chip region stack 33 shifted to the other side of the first direction E1. In each of the chip region stacks 33, along with the formation of the slit stack Sx, grooves M are formed on the surfaces that will later become the end faces 2a and 2b of the chip-type electronic component 1A. These grooves M extend in a direction perpendicular to the stacking direction of the base layer 11, spanning from the base body 2 to the external electrode 4, as shown in Figures 3 and 4.

[0065] After laminating the base sheets 21a to 21h, a step of pressing the laminate 31 in the lamination direction may be performed. For pressing the laminate 31, for example, warm isostatic pressing (WIP) or uniaxial pressing can be used. Pressing the laminate 31 makes adjacent base parts and adjacent conductor patterns K in the lamination direction tightly bonded to each other. In addition, it is possible to suppress the generation of voids caused by steps between base parts and conductor patterns K in the same layer.

[0066] The cutting step S03 is a step of cutting the laminate 31 according to a plurality of chip regions 22. In the cutting step S03, the laminate 31 is cut only in the first direction E1, for example, by a blade or laser processing. In this embodiment, in each of the plurality of chip regions 22, the laminate 31 is cut along a cutting line R that extends in the first direction E1 along the sides 22c and 22d corresponding to the sides 2c (mounting surface P) and 2d of the chip-type electronic component 1A that is formed later. As a result, the plurality of chip region laminates 33 that were previously separated in the first direction E1 by the slit laminate Sx are also separated in the second direction E2, and the plurality of chip region laminates 33 are made into individual pieces.

[0067] The heat treatment step S04 is a step in which heat treatment is applied to the individualized chip region laminate 33. In the heat treatment step S04, a binder removal treatment is performed on multiple chip region laminates 33, and then the heat treatment is carried out. The heat treatment temperature is, for example, 850°C to 900°C. After the heat treatment step S04 is carried out, electroplating or electroless plating is applied to the external electrodes 4A and 4B as needed to form a single or multiple plating layer on the outer surface of the external electrodes 4A and 4B. This makes it possible to obtain multiple of the above-described chip-type electronic components 1A.

[0068] As explained above, in this method for manufacturing chip-type electronic components, in the multiple base sheets 21a to 21h used to form the laminate 31, chip regions 22 aligned in the first direction E1 are separated by slits S1 formed by patterning, while chip regions 22 aligned in the second direction E2 are left connected. Because the chip regions 22 aligned in the second direction E2 are connected, it becomes possible to treat multiple chip regions 22 as a single sheet. Therefore, compared to the case where the chip regions 22 are separated in the first direction E1 and the second direction E2, the misalignment of the conductor pattern K in the chip regions 22 that overlap in the stacking direction when forming the laminate 31 can be reduced.

[0069] Furthermore, in this method for manufacturing chip-type electronic components, the laminates 31 aligned in the first direction E1 are separated in advance by slits S1 formed by patterning. Therefore, by cutting the laminates 31 aligned in the second direction E2 only in the first direction E1, the laminates 31 can be broken down into individual chip-type electronic components 1A. Consequently, the cutting of the laminates 31 can be simplified, and cutting misalignment during the cutting of the laminates 31 can be reduced. As a result, this method for manufacturing chip-type electronic components improves yield.

[0070] In this embodiment, in each of the multiple chip regions 22 of the base sheet 21a to 21h formed in the base sheet formation process S01, slits S1 are formed along the edges 22a and 22b corresponding to the end faces 2a and 2b of the chip-type electronic component 1A. The inner wall surface Sa of the slit S1, formed by patterning using a method such as photolithography, is formed obliquely to the thickness direction of the base sheet 21a to 21h. Therefore, when slits S1 are formed along the edges 22a and 22b corresponding to the end faces 2a and 2b of the chip-type electronic component 1A, a groove M is formed at the end faces 2a and 2b of the final chip-type electronic component 1A by the stacking of the inner wall surfaces Sa of the slit S1. In the chip-type electronic component 1A, the formation of the groove M makes it possible to ensure bonding strength during mounting and to alleviate stress concentration at the boundary between the base portion and the electrode portion.

[0071] In this embodiment, in each of the multiple base sheets 21a to 21h formed in the base sheet formation process S01, multiple chip regions 22 belonging to a row aligned in the first direction E1 are positioned offset in the first direction E1 relative to multiple chip regions 22 belonging to rows adjacent to that row. In this case, even if the chip regions 22 aligned in the first direction E1 are separated by patterning slits S1, one chip region 22 can be kept connected to multiple chip regions 22 adjacent to that chip region 22 in the second direction E2. Therefore, the stacking misalignment of the conductor pattern K in the chip regions 22 that overlap in the stacking direction when forming the laminate 31 can be reduced even more effectively.

[0072] Figure 12 is a schematic plan view of the base sheet formed in the base sheet forming process according to the modified example. The base sheet 21B shown in Figure 12 differs from the base sheet 21A shown in Figure 10 in the relationship between the orientation of the conductor pattern K and the slit S1 in the chip region 22.

[0073] The base sheet 21B is used in the manufacture of the chip-type electronic component 1B described above. In the base sheets 21a to 21h that make up the base sheet 21B, the first direction E1 is the same as the second direction D2 used in the description of the chip-type electronic component 1B, and the second direction E2 is the same as the first direction D1 used in the description of the chip-type electronic component 1B. In the example in Figure 12, the slit S1 extends in the second direction E2 along the sides 22c and 22d corresponding to the sides 2c (mounting surface P) and 2d of the chip-type electronic component 1B that are later formed in each of the multiple chip regions 22. By performing the laminate formation process S02 to the heat treatment process S04 using the base sheet 21B, multiple chip-type electronic components 1B described above can be obtained.

[0074] In this modified example, as in the above embodiment, in the multiple base sheets 21a to 21h used to form the laminate 31, the chip regions 22 aligned in the first direction E1 are separated by slits S1 formed by patterning, while the chip regions 22 aligned in the second direction E2 are left connected. Because the chip regions 22 aligned in the second direction E2 are connected, it becomes possible to treat multiple chip regions 22 as a sheet. Therefore, compared to the case where the chip regions 22 are separated in the first direction E1 and the second direction E2, the misalignment of the conductor pattern K in the chip regions 22 that overlap in the stacking direction when forming the laminate 31 can be reduced. In addition, since the laminate 31 can be made into individual pieces by cutting it only in the first direction E1, the misalignment of the cutting when cutting the laminate 31 can be reduced.

[0075] In this modified example, grooves M are formed on the sides 2c (mounting surface P) and 2d of the final chip-type electronic component 1B by stacking the inner wall surfaces Sa of the slit S1. In the chip-type electronic component 1B, the formation of grooves M ensures both the bonding strength during mounting and the reduction of stress concentration at the boundary between the base body and the electrode portion.

[0076] Figure 13 is a schematic cross-sectional view of a laminate formed in the laminate formation process according to a modified example. The laminate formation process S02 shown in Figure 13 differs from the above embodiment, in that it laminates multiple base sheets 21a to 21h while alternately offsetting each of them to one and the other in the first direction E1.

[0077] The laminate formation process S02 in the modified example corresponds to the manufacturing of the chip-type electronic component 1C described above. The offset amount F of the base sheets 21a to 21h is set within a range in which electrical connections are maintained between adjacent internal conductors 3 and between electrode portions of external electrodes 4 in the stacking direction. In the laminate formation process S02 in the modified example, the offset amount F of the base sheets 21a to 21h is set within a range smaller than the width of the slit S1. That is, in the laminate formation process S02 in the modified example, the offset amount F of the base sheets 21a to 21h is set within a range in which at least a portion of the slit S1 of the multiple base sheets 21a to 21h overlap when viewed from the stacking direction.

[0078] In the laminate formation process S02 according to this modified example, in addition to the grooves M formed by the side surface 11A of the base layer 11 that is inclined with respect to one surface 11B of the base layer 11, grooves M are further formed on the outer surface (here, end faces 2a, 2b) of the base layer 2 by the offset of the base layer 11. Therefore, it is possible to achieve a higher level of both ensuring bonding strength during mounting and mitigating stress concentration at the boundary between the base portion and the electrode portion.

[0079] In the example shown in Figure 13, the base sheets 21a to 21h are offset alternately by one layer each to the end face 2a and end face 2b sides. However, the base sheets 21a to 21h may be offset alternately by multiple layers each to the end face 2a and end face 2b sides. Furthermore, the offset amounts F of each base sheet 21a to 21h do not necessarily have to be the same; the offset amount F of at least one base sheet may differ from the offset amounts F of the other base sheets. In the example shown in Figure 13, the base sheets 21a to 21h constituting base sheet 21A are offset to the end face 2a and end face 2b sides. However, the base sheets 21a to 21h constituting base sheet 21B may have their base layers 11 offset to the side 2c (mounting surface P) and side 2d sides.

[0080] The method for manufacturing chip-type electronic components according to this disclosure is not limited to the above embodiment and can be further modified in various ways. For example, in the above embodiment, in each of the base sheets 21a to 21h, a plurality of chip regions 22 belonging to a row aligned in the first direction E1 are arranged offset in the first direction E1 relative to a plurality of chip regions 22 belonging to a row adjacent to that row. However, as shown in the base sheet 21D in Figure 14, the plurality of chip regions 22 in each row of each of the base sheets 21a to 21h may be aligned with respect to the first direction E1.

[0081] In the base sheet 21D, slits S1 that separate the chip regions 22 aligned in the first direction E1 extend linearly in the second direction E2 across each row. As a result, the chip regions 22 aligned in the first direction E1 are separated by the slits S1, while the chip regions 22 aligned in the second direction E2 remain connected linearly in the column direction (see dashed line J in Figure 14).

[0082] In this embodiment as well, similar to the above embodiment, the chip regions 22 aligned in the second direction E2 are connected to each other, making it possible to treat multiple chip regions 22 as a sheet. Therefore, compared to the case where the chip regions 22 are separated in the first direction E1 and the second direction E2 respectively, the misalignment of the conductor pattern K in the chip regions 22 that overlap in the stacking direction when forming the laminate 31 can be reduced. Furthermore, since the laminate 31 can be made into individual pieces by cutting it only in the first direction E1, the misalignment of the cutting when cutting the laminate 31 can be reduced.

[0083] Furthermore, in the above embodiment, each of the base sheets 21a to 21h is provided with only a slit S1 extending in the second direction E2. However, a slit S2 extending in the first direction E1 may also be provided, to the extent that it does not hinder the connection of the chip regions 22 aligned in the second direction E2. The slit S2 extending in the first direction E1 can be formed, like the slit S1 extending in the second direction E2, by patterning, for example, using photolithography. By providing such a slit S2, the portion that needs to be cut can be reduced when cutting the laminate 31 aligned in the second direction E2 only in the first direction E1. Therefore, cutting the laminate 31 becomes easier, and cutting deviations when cutting the laminate 31 can be reduced even more reliably. By reducing the portion that needs to be cut, the load on the blade during cutting can be reduced. This suppresses blade wear and reduces dimensional variations in the chip-type electronic components obtained by fragmenting the laminate 31.

[0084] The slit S2 in the first direction E1 may extend from both edges of the slit S1 extending in the second direction E2 to one and the other in the first direction E1, as shown in the example in Figure 15(a). The slit S2 in the first direction E1 may be provided to connect one end of one adjacent slit S1 in the row direction to the other end of the other slit S1, as shown in Figure 15(b).

[0085] The slit S2 in the first direction E1 is provided such that, in a plan view of the base sheets 21a to 21h, the shape defined by the slits S1 and S2 is not a closed shape. In this case, the slit S2 in the first direction E1 can be provided to the extent that it does not hinder the state in which the chip regions 22 aligned in the second direction E2 are connected to each other. In the example of Figure 15(a), for example, the length of the slit S2 in the first direction E1 can be made sufficiently shorter than the length of the side of the chip region 22 in the first direction E1, so that the slit S2 is arranged in a dashed line in the first direction E1. In the example of Figure 15(b), for example, the slit S2 in the first direction E1 can connect only a portion of adjacent slits S1 in the row direction. [Explanation of Symbols]

[0086] 1A~1C...Chip-type electronic component, 2...Base body, 2a,2b...End face, 3...Internal conductor, 4(4A,4B)...External electrode, P...Mounting surface, 21(21A,21B,21D)...Base sheet, 22...Chip area, 22a,22b...Edges corresponding to the end face, 22c...Edges corresponding to the mounting surface, E1...First direction, E2...Second direction, K...Conductor pattern, S1...Slit in the second direction, S2...Slit in the first direction.

Claims

1. A base sheet forming step, in which multiple base sheets are formed in which multiple chip regions before division are arranged in a first direction and a second direction perpendicular to the first direction, and a predetermined conductor pattern is provided in each of the multiple chip regions, A laminate formation step of stacking the plurality of base sheets so that the plurality of chip regions overlap in the stacking direction to form a laminate, The process includes a cutting step of cutting the laminate according to the chip region to obtain a plurality of chip-type electronic components, In the above-mentioned base sheet formation process, in each of the plurality of base sheets, the chip regions aligned in the first direction are separated by slits in the second direction formed by patterning, while the chip regions aligned in the second direction are left connected. A method for manufacturing a chip-type electronic component, wherein the cutting step involves cutting the laminate only in the first direction.

2. The chip-type electronic component has an internal conductor disposed inside the base body and external electrodes exposed on a part of the mounting surface of the base body and a part of the end face continuous with the mounting surface. The method for manufacturing a chip-type electronic component according to claim 1, wherein in the base sheet forming step, the slit is formed in each of the plurality of chip regions along the edge corresponding to the end face.

3. The chip-type electronic component has an internal conductor disposed inside the base body and external electrodes exposed on a part of the mounting surface of the base body and a part of the end face continuous with the mounting surface. The method for manufacturing a chip-type electronic component according to claim 1, wherein in the base sheet forming step, the slit is formed in each of the plurality of chip regions along the edge corresponding to the mounting surface.

4. A method for manufacturing a chip-type electronic component according to any one of claims 1 to 3, wherein in the base sheet forming step, the plurality of chip regions belonging to a row aligned in the first direction are arranged in each of the plurality of base sheets, offset in the first direction from the plurality of chip regions belonging to a row adjacent to the first row.

5. The method for manufacturing a chip-type electronic component according to claim 2 or 3, wherein in the laminate formation step, the plurality of base sheets are laminated while alternately offsetting each of the plurality of base sheets to one and the other in the first direction, in a range where at least a portion of the slits of the plurality of base sheets overlap when viewed from the lamination direction.

6. The method for manufacturing a chip-type electronic component according to claim 1, wherein in the base sheet forming step, slits in a first direction are further formed by patterning to the extent that the slits do not form a closed shape.

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