Semiconductor memory

Abstract

One embodiment aims to provide a semiconductor memory device that can appropriately configure a staircase structure. [Solution] According to one embodiment, a semiconductor memory device is provided having a laminate, a first insulating film, and one or more second insulating films. The laminate is formed by stacking a plurality of conductive layers with an insulating layer in between. The laminate includes a stepped structure near the center in the longitudinal direction in a plan view. The first insulating film extends in the stacking direction of the laminate at the terrace portion of the stepped structure. One or more second insulating films are arranged in a region that includes the stepped portion of the stepped structure inward in a plan view. One or more second insulating films extend in the stacking direction of the laminate. One or more second insulating films have a larger planar width than the first insulating film, or have a higher arrangement density than the first insulating film.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] In a semiconductor memory device having a stacked body in which a plurality of conductive layers are stacked via an insulating layer, in order to make the plurality of conductive layers electrically accessible, a stepped structure in which the plurality of conductive layers are drawn out in a stepped manner may be provided. In a semiconductor memory device, it is desirable that the stepped structure is appropriately configured.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device capable of appropriately configuring a stepped structure.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor memory device is provided having a laminate, a first insulating film, and one or more second insulating films. The laminate is formed by stacking a plurality of conductive layers with insulating layers in between. The laminate includes a stepped structure near the center in the longitudinal direction in a plan view. The first insulating film extends in the stacking direction of the laminate at the terrace portion of the stepped structure. One or more second insulating films are arranged in a region that includes the stepped portion of the stepped structure inward in a plan view. One or more second insulating films extend in the stacking direction of the laminate. One or more second insulating films have a larger planar width than the first insulating film, or have a higher arrangement density than the first insulating film. [Brief explanation of the drawing]

[0006] [Figure 1] A perspective view showing the configuration of a semiconductor memory device according to the embodiment. [Figure 2] A block diagram showing the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A circuit diagram showing the configuration of a memory cell array in an embodiment. [Figure 4] A cross-sectional view showing the configuration of the memory cell array in the embodiment. [Figure 5] A plan view showing the configuration of the memory cell in the embodiment. [Figure 6] A plan view showing the staircase structure in the embodiment. [Figure 7] A cross-sectional view showing the staircase structure in the embodiment. [Figure 8] A plan view showing a staircase structure in a first modified example of the embodiment. [Figure 9] A plan view showing a staircase structure in a second modified example of the embodiment. [Figure 10] A cross-sectional view showing a staircase structure in a second modified example of the embodiment. [Modes for carrying out the invention]

[0007] A semiconductor memory device according to an embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to this embodiment.

[0008] (Embodiment) The semiconductor memory device according to this embodiment has a laminate in which a plurality of conductive layers are stacked with an insulating layer in between, and a stepped structure is provided in which the plurality of conductive layers are brought out in a stepped manner in order to make the plurality of conductive layers electrically accessible, and measures are taken to ensure that the stepped structure is properly configured.

[0009] The semiconductor memory device 1 may be configured as shown in Figure 1. Figure 1 is a schematic perspective view showing the configuration of a memory cell array 2 included in the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 is a NAND-type non-volatile memory including three-dimensionally arranged memory cells. Hereinafter, the direction perpendicular to the surface of the substrate SUB will be defined as the Z direction, and the two mutually orthogonal directions in the plane perpendicular to the Z direction will be defined as the X direction and the Y direction.

[0010] As shown in Figure 1, the semiconductor memory device 1 includes a selection gate SGS, a word line WL, and a selection gate SGD. The selection gate SGS is stacked on the substrate SUB via an interlayer insulating film 7. In the example in Figure 1, there are three layers of selection gate SGS. The word line WL is stacked on top of the uppermost layer of selection gate SGS via the interlayer insulating film 7. The selection gate SGD refers to multiple selection gates that are contained within the same layer and divided. In the example in Figure 1, selection gates SGD0 and SGD1, divided in the Y direction, are shown. The selection gate SGD is stacked on top of the uppermost layer of word line WL via the interlayer insulating film 7. The selection gate SGS, word line WL, and selection gate SGD are plate-like structures extending in the X and Y directions, respectively.

[0011] In the example shown in Figure 1, the selection gate SGD, word line WL, and selection gate SGS are separated and insulated in the Y direction by a slit ST. The slit ST is provided in the substrate SUB and extends in the X and Z directions.

[0012] The selection gate SGD is, for example, divided in the Y direction by an insulating film 53. The insulating film 53 is provided above the word line WL (+Z side) and extends in the X and Z directions. Therefore, on the word line WL, the selection gates SGD0 and SGD1 are arranged side by side in the Y direction. In the example of FIG. 1, three layers of the selection gates SGD0 and SGD1 are provided respectively.

[0013] The substrate SUB can be formed of a material mainly composed of a semiconductor such as silicon. The selection gate SGS, the word line WL, and the selection gate SGD can be formed of materials mainly composed of metals such as tungsten (W), respectively. The interlayer insulating film 7 and the insulating film 53 can be formed of insulators such as silicon oxide, respectively.

[0014] The semiconductor memory device 1 further has a plurality of columnar bodies 4. The columnar bodies 4 penetrate the selection gate SGS, the word line WL, and the selection gate SGD and extend in the Z direction, which is their stacking direction. The semiconductor memory device 1 further includes a plurality of bit lines BL provided above the selection gate SGD and a source line SL.

[0015] The columnar bodies 4 are each electrically connected to the bit line BL via a contact plug 31. For example, one of the columnar bodies 4 sharing the selection gate SGD0 and one of the columnar bodies 4 sharing the selection gate SGD1 are electrically connected to one bit line BL.

[0016] In addition, in FIG. 1, for simplicity of illustration, the interlayer insulating film provided between the selection gate SGD and the bit line BL is omitted.

[0017] In the case of a semiconductor memory device (memory) having a three-dimensional structure such as the semiconductor memory device 1, a portion where the word line WL and the columnar body 4 intersect functions as a memory cell, and a memory cell array 2 in which a plurality of memory cells are three-dimensionally arranged is configured. Further, a portion where the selection gate SGS and the columnar body 4 intersect functions as a selection gate on the source side, and a portion where the selection gates SGD0 and SGD1 and the columnar body 4 intersect serves as a selection gate on the drain side. In the semiconductor memory device 1, by increasing the number of stacked word lines WL in the stacked body, it is possible to increase the memory capacity without using a finer patterning technique.

[0018] FIG. 2 is a block diagram showing the configuration of the semiconductor memory device 1.

[0019] As shown in FIG. 2, the semiconductor memory device 1 includes a memory cell array 2, a peripheral circuit 10, and an interface 20. The peripheral circuit 10 includes a WL drive circuit 11, an SGS drive circuit 12, an SGD drive circuit 13, an SL drive circuit 14, and a sense amplifier circuit 15.

[0020] The WL drive circuit 11 is a circuit that controls the voltage applied to the word line WL, and the SGS drive circuit 12 is a circuit that controls the voltage applied to the selection gate SGS. The SGD drive circuit 13 is a circuit that controls the voltage applied to the selection gate SGD, and the SL drive circuit 14 is a circuit that controls the voltage applied to the source line SL. The sense amplifier circuit 15 is a circuit that determines the data read out according to the signal from the selected memory cell.

[0021] The peripheral circuit 10 controls the operation of the semiconductor memory device 1 based on instructions input from an external source (for example, the memory controller of the memory system to which the semiconductor memory device 1 is applied) via the interface 20. For example, when the peripheral circuit 10 receives a write instruction, it selects the memory cell at the address to be written using the SGS drive circuit 12, the SGD drive circuit 13, and the WL drive circuit 11, and writes the data by applying a voltage corresponding to the data to the selected memory cell. Also, when the peripheral circuit 10 receives a read instruction, it selects the memory cell at the address to be written in the memory cell array 2 using the SGS drive circuit 12, the SGD drive circuit 13, and the WL drive circuit 11, determines the data read from the selected memory cell using the sense amplifier circuit 15, and outputs that data to an external source (memory controller) via the interface 20.

[0022] Next, the configuration of the memory cell array 2 will be explained using Figure 3. Figure 3 is a circuit diagram showing the configuration of the memory cell array 2 included in the semiconductor memory device 1.

[0023] The memory cell array 2 has multiple blocks BLK, each of which is a collection of multiple memory cells MT. Memory cells MT are also called memory cell transistors.

[0024] Each block BLK has multiple string units SU0, SU1, SU2, SU3, which are sets of memory cells MT associated with word lines WL and bit lines BL. Each string unit SU0 to SU3 has multiple memory strings MST, in which memory cells MT are connected in series. The number of memory strings MST within each string unit SU0 to SU3 is arbitrary.

[0025] Multiple string units SU0, SU1, SU2, and SU3 correspond to multiple selected gate lines SGD0, SGD1, SGD3, and SGD4, and share a selected gate line SGS, functioning as multiple drive units in block BLK. Each string unit SU can be driven by its corresponding selected gate line SGD and selected gate line SGS. Each string unit SU also contains multiple memory strings MST.

[0026] Each memory string MST includes, for example, eight memory cells MT (MT0 to MT11) and selection transistors SDT and SST. Each memory cell MT has a control gate and a charge storage layer, and retains data non-volatilely. The eight memory cells MT (MT0 to MT11) are connected in series between the source of the selection transistor SDT and the drain of the selection transistor SST. Note that the number of memory cells MT in a memory string MST is not limited to eight.

[0027] The gates of the selection transistor SDT in each string unit SU are connected to the selection gate line SGD. In contrast, the gates of the selection transistor SST in each string unit SU are connected to a common selection gate line, for example, SGS.

[0028] The drains of the selection transistor SDT of each memory string MST within each string unit SU are connected to different bit lines BL0 to BLk (where k is any integer greater than or equal to 2). Furthermore, the bit lines BL0 to BLk connect a single memory string MST within each string unit SU across multiple blocks BLK. Additionally, the sources of each selection transistor SST are commonly connected to the source line SL.

[0029] In other words, a string unit SU is a collection of memory strings MST connected to different bit lines BL0~BLk and the same selection gate line SGD. A block BLK is a collection of multiple string units SU0~SU3 that share a common word line WL. And memory cell array 2 is a collection of multiple block BLKs that share a common bit line BL0~BLk.

[0030] If we refer to a group of memory cells (MTs) that share a word line (WL) as a "memory cell group (MCG)," then a memory cell group (MCG) is the smallest unit of a collection of memory cells to which a predetermined voltage (e.g., write voltage, read voltage) can be applied collectively via the word line (WL).

[0031] Next, the specific configuration of the memory cell array 2 will be explained using Figures 4 and 5. Figure 4 is a ZY cross-sectional view showing the configuration of the memory cell array 2. Figure 5 is an XY plan view showing the configuration of the memory cell MT, and shows the XY plane when Figure 4 is cut along line AA.

[0032] As shown in Figures 1, 4, and 5, the memory cell array 2 is configured as a three-dimensional array of memory cells, with columnar bodies 4 arranged two-dimensionally in the XY direction on the +Z side of the substrate SUB, and multiple layers of word lines WL passing through the columnar bodies 4.

[0033] In the memory cell array 2, a laminated structure SST is formed by alternately stacking conductive layers 6 and insulating layers 7. In the laminated structure SST, each conductive layer 6 may be made of a material mainly composed of a conductor (e.g., a metal such as tungsten). Each insulating layer 7 may be made of a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide). Most of the conductive layers 6 function as word lines WL. The conductive layers 6 on the +Z side function as selected gate lines SGD. The conductive layers 6 on the -Z side function as selected gate lines SGS.

[0034] In the memory cell array 2, multiple memory cells MT are configured at multiple locations where multiple word lines WL intersect with multiple columnar bodies 4. Multiple selection transistors SDT are configured at multiple locations where selection gate lines SGD intersect with multiple columnar bodies 4. Multiple selection transistors SST are configured at multiple locations where selection gate lines SGS intersect with multiple columnar bodies 4. As shown in Figure 5, the columnar bodies 4 include a core insulating film 41, a semiconductor channel 42, and an insulating film 43. The core insulating film 41 may be formed from a material mainly composed of an insulator (e.g., silicon oxide). The semiconductor channel 42 is arranged to surround the core insulating film 41 from the outside and includes a substantially cylindrical shape extending along the central axis of the columnar body 4.

[0035] The semiconductor channel 42 includes the channel region (active region) in the memory string MST and can be formed from a material primarily composed of a substantially impurity-free semiconductor (e.g., polysilicon).

[0036] The insulating film 43 is disposed between the conductive layer 6 and the semiconductor channel 42, and surrounds the semiconductor channel 42 in a plan view. The insulating film 43 covers the sides of the semiconductor channel 42. The insulating film 43 is configured to have charge storage capability in the portion disposed between the conductive layer 6 and the semiconductor channel 42.

[0037] As shown in Figure 5, the insulating film 43 may consist of a three-layer structure: tunnel insulating film 431, charge storage film 432, and block insulating film 433, in that order from the semiconductor channel 42 side. The tunnel insulating film 431 may be formed from a material mainly composed of oxides (e.g., silicon oxide). The charge storage film 432 may be formed from a material mainly composed of nitrides (e.g., silicon nitride). The block insulating film 433 may be formed from a material mainly composed of oxides (e.g., silicon oxide, metal oxides, or stacks thereof).

[0038] In other words, the insulating film 43 may have an ONO-type three-layer structure in the portion (memory cell MT) located between the conductive layer 6 (word line WL) and the semiconductor channel 42, where the charge storage film is sandwiched between a pair of insulating films (tunnel insulating film, block insulating film). Alternatively, the insulating film 43 may consist of a single-layer structure of a gate insulating film in the portion (selection transistor SDT) located between the conductive layer 6 (selection gate line SGD) and the semiconductor channel 42. The gate insulating film can be formed from a material mainly composed of an oxide (e.g., silicon oxide).

[0039] Each laminated SST may include a stepped structure SBS near the center of the longitudinal direction in a plan view, as shown in Figures 6 and 7. Figure 6 is an XY plan view showing the stepped structure SBS. Figure 7 is an XZ cross-sectional view showing the stepped structure SBS, and shows the XZ cross-section obtained by cutting Figure 6 along line BB.

[0040] The semiconductor memory device 1 may include multiple stacked structures SST_1 and SST_2. The multiple stacked structures SST_1 and SST_2 are arranged in the Y direction. The multiple stacked structures SST_1 and SST_2 are separated in the Y direction by a slit ST.

[0041] The laminate SST_1 has a substantially rectangular shape in an XY planar view, with the X direction as its longitudinal direction. Laminate SST_1 is separated from laminate SST_2 on the -Y side via a slit ST_2. Laminate SST_1 may also be separated from other laminate SSTs (not shown) on the +Y side via a slit ST_1.

[0042] The laminate SST_2 has a substantially rectangular shape with the X direction as its longitudinal direction in an XY plan view. Laminate SST_2 is separated from laminate SST_1 on the +Y side via slit ST_2. Laminate SST_2 may also be separated from other laminate SSTs (not shown) on the -Y side via slit ST_3.

[0043] Each stacked SST has a stepped region STR in the center in the X direction, and memory cell array regions MAR1 and MAR2 on both sides of the stepped region STR in the X direction. In the stepped region STR, a stepped structure SBS is provided in which each conductive layer 6 is drawn out in a stepped manner. This makes each conductive layer 6 electrically accessible.

[0044] In the memory cell array region MAR1 on the +X side of each stacked SST, multiple columnar bodies 4 are arranged in the XY direction, and multiple memory cells MT are arranged in the XYZ direction at multiple positions where multiple conductive layers 6 (word lines WL) and multiple columnar bodies 4 intersect. Multiple selection transistors SDT are arranged in the XY direction at multiple positions where the conductive layer 6 (selection gate line SGD) on the +Z side intersects with multiple columnar bodies 4. Multiple selection transistors SST are arranged in the XY direction at multiple positions where the conductive layer 6 (selection gate line SGS) on the -Z side intersects with multiple columnar bodies 4.

[0045] In the memory cell array region MAR2 on the -X side of each stacked SST, multiple columnar bodies 4 are arranged in the XY direction, and multiple memory cells MT are arranged in the XYZ direction at multiple positions where multiple conductive layers 6 (multiple word lines WL) and multiple columnar bodies 4 intersect. Multiple selection transistors SDT are arranged in the XY direction at multiple positions where the conductive layer 6 (selection gate line SGD) on the +Z side intersects with multiple columnar bodies 4. Multiple selection transistors SST are arranged in the XY direction at multiple positions where the conductive layer 6 (selection gate line SGS) on the -Z side intersects with multiple columnar bodies 4.

[0046] In the stepped region STR at the center of each stacked structure SST in the X direction, a stepped structure SBS and a bridge structure BR are provided. The stepped structure SBS and the bridge structure BR are adjacent to each other in the Y direction. The stepped structure SBS is adjacent to the memory cell array region MAR1 on the +X side and adjacent to the memory cell array region MAR2 on the -X side. The bridge structure BR connects the conductive layer 6 of the memory cell array region MAR1 and the conductive layer 6 of the memory cell array region MAR2 in a bridge-like manner at the Z height of each conductive layer 6. As a result, the conductive layer 6 of the memory cell array region MAR1 and the conductive layer 6 of the memory cell array region MAR2 are electrically connected at the Z height of each conductive layer 6.

[0047] In laminate SST_1, the staircase structure SBS is provided on the -Y side, and the bridge structure BR is provided on the +Y side. In laminate SST_2, the staircase structure SBS is provided on the +Y side, and the bridge structure BR is provided on the -Y side. The staircase structure SBS of laminate SST_1 and the staircase structure SBS of laminate SST_2 are adjacent in the Y direction via the slit ST_2.

[0048] The staircase structure SBS has multiple terrace sections TER1 to TER5, multiple step sections STP1 to STP4, and multiple cliff sections CL1 to CL4. The multiple cliff sections CL1 to CL4 have a roughly rectangular shape in the XY plane view and define the boundary between the staircase structure SBS and the surrounding area. Inside the boundary, in the XY plane view, the terrace section TER1, step section STP1, terrace section TER2, step section STP2, terrace section TER3, step section STP3, terrace section TER4, step section STP4, and terrace section TER5 are arranged in order as you move away from the memory cell array area MAR1 in the -X direction.

[0049] In each laminated SST, the stepped structure SBS allows multiple conductive layers 6 to be drawn out in a stepped manner, as shown in Figure 7.

[0050] The terrace portion TER1 has a Z height on its +Z side that corresponds to the conductive layer 6 (word wire WL6). The conductive layer 6 (word wire WL6) is drawn out by the terrace portion TER1. A contact plug CC_6 extending in the Z direction from the +Z side is connected to the +Z side of the drawn-out conductive layer 6 (word wire WL6).

[0051] Terrace portion TER1 has a Z height on its +Z side that corresponds to the conductive layer 6 (word wire WL0). The conductive layer 6 (word wire WL0) is drawn out by terrace portion TER2. A contact plug CC_0 extending in the Z direction from the +Z side is connected to the +Z side of the drawn-out conductive layer 6 (word wire WL0).

[0052] Terrace portion TER1 has a Z height on its +Z side that corresponds to the conductive layer 6 (word wire WL1). The conductive layer 6 (word wire WL1) is drawn out by terrace portion TER3. A contact plug CC_1 extending in the Z direction from the +Z side is connected to the +Z side of the drawn-out conductive layer 6 (word wire WL1).

[0053] Terrace portion TER1 has a Z height on its +Z side that corresponds to the conductive layer 6 (word wire WL2). The conductive layer 6 (word wire WL2) is drawn out by terrace portion TER4. A contact plug CC_2 extending in the Z direction from the +Z side is connected to the +Z side of the drawn-out conductive layer 6 (word wire WL2).

[0054] Terrace portion TER1 has a Z height on its +Z side that corresponds to the conductive layer 6 (selected gate wire SGS). The conductive layer 6 (selected gate wire SGS) is drawn out by terrace portion TER5. A contact plug CC_S extending in the Z direction from the +Z side is connected to the +Z side of the drawn conductive layer 6 (selected gate wire SGS).

[0055] Of the multiple stepped sections STP1 to STP4, the stepped sections STP1 and STP4 shown by the dashed lines in Figure 6 have a Z height greater than the arrangement pitch of the conductive layer 6 in the Z direction, as shown in Figure 7. The Z height of the stepped sections STP1 and STP4 can correspond to N times the arrangement pitch of the conductive layer 6 in the Z direction, where N is an integer greater than or equal to 2. The stepped sections STP1 and STP4 will be referred to as multi-stage stepped sections.

[0056] The neighboring regions where the multi-stage stepped portions STP1 and STP4 are located will be called the multi-stage boundary region MBR. Multi-stage boundary region MBR1 contains the multi-stage stepped portion STP1 internally and extends in the X direction in its vicinity. Multi-stage boundary region MBR2 contains the multi-stage stepped portion STP4 internally and extends in the X direction in its vicinity.

[0057] Of the multiple stepped sections STP1 to STP4, the stepped sections STP2 and STP3, shown by dotted lines in Figure 6, have a Z height corresponding to 1 times the arrangement pitch of the conductive layer 6 in the Z direction. Stepped sections STP2 and STP3 will be referred to as single-stage stepped sections.

[0058] The stepped structure SBS further comprises multiple insulating films HR1 and multiple insulating films HR2.

[0059] Multiple insulating films HR1 are arranged in the XY direction in the terrace section TER of the stepped structure SBS. Each insulating film HR1 extends in the Z direction in the terrace section TER of the laminate SST. This allows the multiple insulating films HR1 to structurally reinforce the terrace section TER.

[0060] In the terrace portion TER1, multiple insulating films HR1_1 are arranged in the XY direction around the contact plug CC_6. Figure 6 illustrates a configuration in which multiple insulating films HR1_1 are arranged in a honeycomb pattern. Each insulating film HR1_1 has a minimum planar width equal to one another. Each insulating film HR1_1 has a maximum planar width equal to one another.

[0061] In the terrace portion TER2, multiple insulating films HR1_2 are arranged in the XY direction around the contact plug CC_0. Figure 6 illustrates a configuration in which multiple insulating films HR1_2 are arranged in a honeycomb pattern. Each insulating film HR1_2 has a minimum planar width equal to the others. Each insulating film HR1_2 has a maximum planar width equal to the others.

[0062] In the terrace portion TER3, multiple insulating films HR1_3 are arranged in the XY direction around the contact plug CC_1. Figure 6 illustrates a configuration in which multiple insulating films HR1_3 are arranged in a honeycomb pattern. Each insulating film HR1_3 has a minimum planar width equal to one another. Each insulating film HR1_3 has a maximum planar width equal to one another.

[0063] In the terrace portion TER4, multiple insulating films HR1_4 are arranged in the XY direction around the contact plug CC_2. Figure 6 illustrates a configuration in which multiple insulating films HR1_4 are arranged in a honeycomb pattern. Each insulating film HR1_4 has a minimum planar width equal to one another. Each insulating film HR1_4 has a maximum planar width equal to one another.

[0064] In the terrace portion TER5, multiple insulating films HR1_5 are arranged in the XY direction around the contact plug CC_S. Figure 6 illustrates a configuration in which multiple insulating films HR1_5 are arranged in a honeycomb pattern. Each insulating film HR1_5 has a minimum planar width equal to one another. Each insulating film HR1_5 has a maximum planar width equal to one another.

[0065] Multiple insulating film HR2s are each placed in the multi-stage boundary region MBR.

[0066] In the multi-stage boundary region MBR1, one insulating film HR2_1 is provided, which has a minimum planar width greater than that of insulating film HR1. If insulating film HR1 is approximately circular in the XY plane view, its diameter corresponds to the minimum planar width; if insulating film HR1 is approximately elliptical in the XY plane view, its minor axis corresponds to the minimum planar width. Insulating film HR2_1 extends in an approximately rectangular shape with the Y direction as its longitudinal direction, covering the multi-stage stepped portion STP1 in the XY plane view, and its X width corresponds to the minimum planar width. The X width of insulating film HR2_1 is greater than the diameter (or minor axis) of insulating film HR1. The X width of insulating film HR2_1 may be twice or more the diameter (or minor axis) of insulating film HR1.

[0067] A single insulating film HR2_1 with a maximum planar width greater than that of insulating film HR1 is placed in the multi-stage boundary region MBR1. If insulating film HR1 is approximately circular in XY plane view, its diameter corresponds to its maximum planar width; if insulating film HR1 is approximately elliptical in XY plane view, its major axis corresponds to its maximum planar width. Insulating film HR2_1 extends in an approximately rectangular shape with the Y direction as its longitudinal direction, covering the multi-stage stepped portion STP1 in XY plane view, and its Y width corresponds to its maximum planar width. The Y width of insulating film HR2_1 is greater than the diameter (or minor axis) of insulating film HR1. The Y width of insulating film HR2_1 may be more than twice the diameter (or minor axis) of insulating film HR1. The Y width of insulating film HR2_1 may be approximately equal to the Y width of the stepped structure SBS.

[0068] The insulating film HR2_1 shown in Figure 7 extends in the Z direction of the laminate SST in the multi-stage boundary region MBR1. This allows the insulating film HR2_1 to structurally reinforce the multi-stage boundary region MBR1. Furthermore, the insulating film HR2_1 can suppress electrical leakage between adjacent conductive layers 6 in the Z direction near the multi-stage boundary region MBR1.

[0069] The insulating film HR2_1 has a +Z-side surface on the +X side that forms part of terrace TER1, a +Z-side surface on the -X side that forms part of terrace TER2, and a multi-stage stepped portion STP1 on the -X-side surface of the portion in the center in the X direction. The multi-stage stepped portion STP1 extends in the YZ direction, but its -Z-side extension is located within the insulating film HR2_1.

[0070] In other words, the structure is such that the multi-stage stepped portion STP1 and the vicinity of its extended surface are filled with an insulating film HR2_1. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0071] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with fewer processing steps, thereby forming multi-step stepped sections STP1 in the staircase structure. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and holes for insulating film HR2_1 are formed in the multi-step stepped sections STP1.

[0072] In this case, the minimum planar width of the holes for insulating film HR2_1 is greater than the minimum planar width of the holes for insulating film HR1. The maximum planar width of the holes for insulating film HR2_1 is greater than the maximum planar width of the holes for insulating film HR1. Ions reflected by the multi-stage stepped portion STP1 remain within the holes for insulating film HR2_1, preventing erroneous etching of the sacrificial layer 6a.

[0073] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR2_1 is embedded in the holes for insulating film HR2_1. Sacrificial layer 6a is removed, and conductive layer 6 is embedded in the void formed by the removal of sacrificial layer 6a, with insulating films HR1 and HR2_1 functioning as structural reinforcements.

[0074] In this case, erroneous etching of the sacrificial layer 6a can be prevented, thus preventing pattern defects in the conductive layer 6 that is replaced by the sacrificial layer 6a.

[0075] For example, on the +X side of the insulating film HR2_1 shown in Figure 7, the conductive layer 6 (SGS), conductive layer 6 (WL0), and conductive layer 6 (WL6) are all in contact, and it is shown that there are no defects in the pattern of conductive layer 6. On the -X side of the insulating film HR2_1, the conductive layer 6 (SGS) and conductive layer 6 (WL0) are all in contact, and it is shown that there are no defects in the pattern of conductive layer 6.

[0076] In the multi-stage boundary region MBR2 shown in Figure 6, one insulating film HR2_2 is provided, which has a minimum planar width greater than that of insulating film HR1. In an XY plane view, insulating film HR2_2 covers the multi-stage stepped portion STP4 and extends in a substantially rectangular shape with the Y direction as its longitudinal direction, and its X width corresponds to the minimum planar width. The X width of insulating film HR2_1 is greater than the diameter (or minor axis) of insulating film HR1. The X width of insulating film HR2_2 may be more than twice the diameter (or minor axis) of insulating film HR1.

[0077] In the multi-stage boundary region MBR2, one insulating film HR2_2 is provided, which has a maximum planar width greater than that of insulating film HR1. In an XY plane view, insulating film HR2_2 covers the multi-stage stepped portion STP4 and extends in a substantially rectangular shape with the Y direction as its longitudinal direction, and its Y width corresponds to the maximum planar width. The Y width of insulating film HR2_2 is greater than the diameter (or minor axis) of insulating film HR1. The Y width of insulating film HR2_2 may be more than twice the diameter (or minor axis) of insulating film HR1. The Y width of insulating film HR2_2 may be approximately equal to the Y width of the stepped structure SBS.

[0078] The insulating film HR2_2 shown in Figure 7 extends in the Z direction of the laminate SST in the multi-stage boundary region MBR1. This allows the insulating film HR2_2 to structurally reinforce the multi-stage boundary region MBR1. Furthermore, the insulating film HR2_2 can suppress electrical leakage between adjacent conductive layers 6 in the Z direction near the multi-stage boundary region MBR1.

[0079] The insulating film HR2_2 has a +Z-side surface on the +X side that forms part of the terrace portion TER4, a +Z-side surface on the -X side that forms part of the terrace portion TER5, and a multi-stage stepped portion STP4 on the -X-side surface of the portion in the center in the X direction. The multi-stage stepped portion STP4 extends in the YZ direction, but its -Z-side extension surface is located within the insulating film HR2_2.

[0080] In other words, the structure is such that the multi-stage stepped portion STP4 and the vicinity of its extended surface are filled with an insulating film HR2_2. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0081] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with fewer processing steps, thereby forming multi-step stepped sections STP4 in the staircase structure SBS. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and holes for insulating film HR2_2 are formed in the multi-step stepped sections STP4.

[0082] In this case, the minimum planar width of the holes for insulating film HR2_2 is greater than the minimum planar width of the holes for insulating film HR1. The maximum planar width of the holes for insulating film HR2_2 is greater than the maximum planar width of the holes for insulating film HR1. Ions reflected by the multi-stage stepped portion STP4 remain within the holes for insulating film HR2_2, preventing accidental etching of the sacrificial layer 6a.

[0083] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR2_2 is embedded in the holes for insulating film HR2_2. Sacrificial layer 6a is removed, and conductive layer 6 is embedded in the void formed by the removal of sacrificial layer 6a, with insulating films HR1 and HR2_2 functioning as structural reinforcements.

[0084] In this case, erroneous etching of the sacrificial layer 6a can be prevented, thus preventing pattern defects in the conductive layer 6 that is replaced by the sacrificial layer 6a.

[0085] For example, on the +X side of the insulating film HR2_2 shown in Figure 7, the conductive layer 6 (SGS), conductive layer 6 (WL0), ... conductive layer 6 (WL2) are all in contact, and it is shown that there are no defects in the pattern of conductive layer 6. On the -X side of the insulating film HR2_2, the conductive layer 6 (SGS) is in contact, and it is shown that there are no defects in the pattern of conductive layer 6.

[0086] As described above, in the embodiment, in the semiconductor memory device 1, one insulating film HR2 with a minimum planar width larger than the insulating film HR1 is placed in each multi-stage boundary region MBR of the stepped structure SBS. The structure is such that the vicinity of the multi-stage stepped portion STP and its extended surface is filled with insulating film HR2. This structure is suitable for preventing pattern defects in the conductive layer 6. This makes it possible to provide a semiconductor memory device 1 in which the stepped structure SBS can be properly configured.

[0087] Furthermore, the placement of one insulating film HR2, which has a minimum planar width greater than insulating film HR1, may be limited to some of the multi-stage boundary regions MBR1 and MBR2 in the stepped SBS structure. For example, if, during manufacturing, erroneous etching of the sacrificial layer 6a is less likely to occur in the multi-stage boundary region MBR2 than in the multi-stage boundary region MBR1, insulating film HR2 may be placed in the multi-stage boundary region MBR1, and insulating film HR1 may be placed in the multi-stage boundary region MBR2 instead of insulating film HR2. Alternatively, insulating film HR2 may be placed in the multi-stage boundary region MBR1, and no insulating film may be placed in the multi-stage boundary region MBR2.

[0088] Alternatively, a single insulating film HR2 with a minimum planar width greater than insulating film HR1 may be placed not only near multi-stage stepped portions STP1 and STP4, but also near single-stage stepped portions STP2 and STP3.

[0089] Alternatively, as a first modification of the embodiment, in the memory cell array 102 of the semiconductor memory device 101, as shown in Figure 8, the insulating film HR102 near the multi-stage stepped portion STP may have a higher arrangement density than the insulating film HR1 of the terrace portion TER. Figure 8 is an XY plan view showing the stepped structure SBS in the first modification of the embodiment.

[0090] In the stepped structure SBS of the semiconductor memory device 101 shown in Figure 8, the arrangement density of multiple insulating films HR102_1 in the multi-stage boundary region MBR1 is higher than the arrangement density of insulating films HR1_1 to HR1_5 in the terrace sections TER1 to TER5.

[0091] For example, multiple insulating films HR102_1 are arranged in a planar manner within the multi-stage boundary region MBR1. The multiple insulating films HR102_1 may also be arranged in a grid pattern in the XY direction within the multi-stage boundary region MBR1. Each insulating film HR102_1 may be connected to other insulating films HR102_1 adjacent to it in the XY direction as a partially continuous film. As a result, the multiple insulating films HR102_1 are arranged in a connected manner to cover the multi-stage stepped portion STP1.

[0092] In Figure 8, of the multiple insulating films HR102_1, the +Z side surface of the +X side insulating film HR102_1 forms part of terrace portion TER1, the +Z side surface of the -X side insulating film HR102_1 forms part of terrace portion TER2, and the -X side surface of the insulating film HR102_1 in the center in the X direction forms a multi-stage stepped portion STP1. The multi-stage stepped portion STP1 extends in the YZ direction, but its -Z side extension surface is generally located within the insulating film HR102_1.

[0093] In other words, the structure is such that the multi-stage stepped portion STP1 and the vicinity of its extended surface are largely filled with the insulating film HR102_1. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0094] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with fewer processing steps, thereby forming multi-step stepped sections STP1 in the staircase structure. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and holes for insulating film HR102_1 are formed in the multi-step stepped sections STP1.

[0095] In this case, the arrangement density of holes for insulating film HR102_1 is higher than the arrangement density of holes for insulating film HR1. The holes for insulating film HR102_1 are arranged in a planar, connected manner. Ions reflected by the multi-stage stepped portion STP1 generally remain within the holes for insulating film HR102_1, preventing accidental etching of the sacrificial layer 6a.

[0096] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR102_1 is embedded in the holes for insulating film HR102_1. Sacrificial layer 6a is removed, and conductive layer 6 is embedded in the void formed by the removal of sacrificial layer 6a, with insulating films HR1 and HR102_1 functioning as structural reinforcements.

[0097] In this case, erroneous etching of the sacrificial layer 6a can be prevented, thus preventing pattern defects in the conductive layer 6 that is replaced by the sacrificial layer 6a.

[0098] Multiple insulating films HR102_2 are arranged in a planar manner within the multi-stage boundary region MBR2. The multiple insulating films HR102_2 may also be arranged in a grid pattern in the XY direction within the multi-stage boundary region MBR2. Each insulating film HR102_2 may be connected to other insulating films HR102_2 adjacent to it in the XY direction as a partially continuous film. As a result, the multiple insulating films HR102_2 are arranged in a connected manner to cover the multi-stage stepped portion STP4.

[0099] In Figure 8, of the multiple insulating films HR102_2, the +Z side of the insulating film HR102_2 on the +X side forms part of the terrace portion TER4, the +Z side of the insulating film HR102_2 on the -X side forms part of the terrace portion TER2, and the -X side of the insulating film HR102_2 in the center in the X direction forms a multi-stage stepped portion STP5. The multi-stage stepped portion STP4 extends in the YZ direction, but its -Z side extension is generally located within the insulating film HR102_2.

[0100] In other words, the structure is such that the multi-stage stepped portion STP4 and the vicinity of its extended surface are largely filled with the insulating film HR102_2. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0101] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with fewer processing steps, thereby forming multi-step stepped sections STP4 in the staircase structure. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and holes for insulating film HR102_2 are formed in the multi-step stepped sections STP4.

[0102] In this case, the arrangement density of holes for insulating film HR102_2 is higher than the arrangement density of holes for insulating film HR1. The holes for insulating film HR102_2 are arranged in a planar, connected manner. Ions reflected by the multi-stage stepped portion STP4 generally remain within the holes for insulating film HR102_2, preventing erroneous etching of the sacrificial layer 6a.

[0103] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR102_2 is embedded in the holes for insulating film HR102_2. Sacrificial layer 6a is removed, and conductive layer 6 is embedded in the void formed by the removal of sacrificial layer 6a, with insulating films HR1 and HR102_2 functioning as structural reinforcements.

[0104] In this case, erroneous etching of the sacrificial layer 6a can be prevented, thus preventing pattern defects in the conductive layer 6 that is replaced by the sacrificial layer 6a.

[0105] Thus, in the semiconductor memory device 101, the insulating film HR102 near the multi-stage stepped portion STP has a higher arrangement density than the insulating film HR1 of the terrace portion TER. The multi-stage stepped portion STP and the vicinity of its extended surface are filled with insulating film HR102. This structure is suitable for preventing pattern defects in the conductive layer 6. As a result, a semiconductor memory device 101 that can properly configure a stepped structure SBS can be provided.

[0106] Alternatively, as a second modification of the embodiment, in the memory cell array 202 of the semiconductor memory device 201, a plurality of insulating films 202 may be arranged in a ring-like manner in the multi-stage boundary region MBR, as shown in Figures 9 and 10. Figure 9 is an XY plan view showing the stepped structure SBS in the second modification of the embodiment. Figure 10 is an XZ cross-sectional view showing the stepped structure SBS in the second modification of the embodiment, showing the XZ cross-section when Figure 9 is cut along the CC line.

[0107] Multiple insulating films HR202_1 are arranged in a ring-like manner within the multi-stage boundary region MBR1. The multiple insulating films HR202_1 may be arranged along the boundary of the multi-stage boundary region MBR1. Each insulating film HR202_1 may be connected to other insulating films HR202_1 adjacent to it in the XY direction as a partially continuous film. As a result, the multiple insulating films HR202_1 are arranged in a way that surrounds the multi-stage stepped portion STP1. In an XY plan view, the multiple insulating films HR202_1 can be arranged in a substantially rectangular shape with the Y direction as the longitudinal direction, surrounding the multi-stage stepped portion STP1.

[0108] The multi-stage boundary region MBR1 shown in Figure 10 has insulating films HR202_1 extending in the Z direction at both the +X and -X ends, and a laminated structure in which sacrificial layers 6a and insulating layers 7 are alternately stacked between the insulating films HR202_1 on the +X side and the insulating films HR202_1 on the -X side. The +Z side surface of the insulating film HR202_1 on the +X side and the +Z side surface of the +X side portion of the laminated structure form part of terrace TER1. The +Z side surface of the -X side portion of the laminated structure and the +Z side surface of the insulating film HR202_1 on the -X side form part of terrace TER2. The -X side surface of the central portion in the X direction of the laminated structure forms a multi-stage stepped portion STP1. The multi-stage stepped portion STP1 extends in the YZ direction, but its -Z side extension is located within the laminated structure. This layered structure is surrounded by multiple insulating films HR202_1 in an XY planar view, and is separated from the conductive layer 6 on the outside in the XY direction via the insulating films HR202_1 (see Figure 9).

[0109] In other words, the structure is such that the multi-stage stepped portion STP1 and the vicinity of its extended surface are located within a laminated structure surrounded by multiple insulating films HR202_1. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0110] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with a small number of processing steps, thereby forming multi-step stepped sections STP1 in the staircase structure. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and multiple holes for insulating film HR202_1 are formed near the multi-step stepped sections STP1.

[0111] In this configuration, multiple holes for the insulating film HR202_1 are arranged in a connected manner, surrounding the multi-stage stepped section STP1 from the outside in the XY direction. Ions reflected by the multi-stage stepped section STP1 generally remain within the region surrounded by the multiple holes for the insulating film HR202_1, preventing erroneous etching of the sacrificial layer 6a on the XY direction outside of the multiple holes for the insulating film HR202_1.

[0112] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR202_1 is embedded in the holes for insulating film HR202_1. The sacrificial layers 6a on the outer sides in the XY direction of the multiple insulating films HR202_1 are removed. With insulating films HR1 and HR202_1 functioning as structural reinforcements, the conductive layer 6 is embedded in the voids formed by the removal of the sacrificial layers 6a on the outer sides in the XY direction of the multiple insulating films HR202_1.

[0113] In this case, erroneous etching of the sacrificial layer 6a on the outer side of the multiple insulating film HR202_1 in the XY direction can be prevented, and thus pattern defects in the conductive layer 6 that are replaced by the sacrificial layer 6a on the outer side of the multiple insulating film HR202_1 in the XY direction can be prevented.

[0114] Although the sacrificial layers 6a on the inner side of the multiple insulating films HR202_1 in the XY direction can be etched, these sacrificial layers 6a cannot be replaced by the conductive layer 6, and therefore do not affect the pattern defects of the conductive layer 6.

[0115] The multi-stage boundary region MBR2 has insulating films HR202_2 extending in the Z direction at both the +X and -X ends, and a laminated structure in which sacrificial layers 6a and insulating layers 7 are alternately stacked between the insulating films HR202_2 on the +X side and the insulating films HR202_2 on the -X side. The +Z side surface of the insulating film HR202_2 on the +X side and the +Z side surface of the +X side portion of the laminated structure form part of the terrace portion TER1. The +Z side surface of the -X side portion of the laminated structure and the +Z side surface of the insulating film HR202_2 on the -X side form part of the terrace portion TER2. The -X side surface of the X-center portion of the laminated structure forms a multi-stage stepped portion STP4. The multi-stage stepped portion STP4 extends in the YZ direction, but its -Z side extension is located within the laminated structure. This layered structure is surrounded by multiple insulating films HR202_2 in an XY plan view and separated from the conductive layer 6 on the outside in the XY direction via the insulating films HR202_2 (see Figure 9).

[0116] In other words, the multi-stage stepped portion STP4 and the vicinity of its extended surface are located within a laminated structure surrounded by multiple insulating films HR202_2. This structure is suitable for preventing pattern defects in the conductive layer 6.

[0117] For example, during manufacturing, a laminate SSTA is formed by alternately stacking sacrificial layers 6a and insulating layers 7 multiple times, and a staircase processing process is applied to create many steps with a small number of processing steps, thereby forming multi-step stepped sections STP4 in the staircase structure. Subsequently, a dry etching process forms holes for insulating film HR1 in the terrace portions, and multiple holes for insulating film HR202_2 are formed near the multi-step stepped sections STP4.

[0118] In this configuration, multiple holes for the insulating film HR202_2 are arranged in a connected manner, surrounding the multi-stage stepped section STP4 from the outside in the XY direction. Ions reflected by the multi-stage stepped section STP4 generally remain within the region surrounded by the multiple holes for the insulating film HR202_2, preventing erroneous etching of the sacrificial layer 6a on the XY side of the multiple holes for the insulating film HR202_2.

[0119] Subsequently, insulating film HR1 is embedded in the holes for insulating film HR1, and insulating film HR202_2 is embedded in the holes for insulating film HR202_2. The sacrificial layers 6a on the outer sides in the XY direction of the multiple insulating films HR202_2 are removed. With insulating films HR1 and HR202_2 functioning as structural reinforcements, the conductive layer 6 is embedded in the voids formed by the removal of the sacrificial layers 6a on the outer sides in the XY direction of the multiple insulating films HR202_2.

[0120] In this case, erroneous etching of the sacrificial layer 6a on the outer side of the multiple insulating film HR202_2 in the XY direction can be prevented, and thus pattern defects in the conductive layer 6 that are replaced by the sacrificial layer 6a on the outer side of the multiple insulating film HR202_2 can be prevented.

[0121] Although the sacrificial layers 6a on the inner side of the multiple insulating films HR202_2 in the XY direction can be etched, these sacrificial layers 6a cannot be replaced by the conductive layer 6, and therefore do not affect the pattern defects of the conductive layer 6.

[0122] Thus, in the semiconductor memory device 201, multiple insulating films HR202_1 are arranged connected to surround the multi-stage stepped portion STP1. The multi-stage stepped portion STP and the vicinity of its extended surface are located within the stacked structure of the multiple insulating films HR202_1 in the XY direction. This structure is suitable for preventing pattern defects in the conductive layer 6. As a result, a semiconductor memory device 201 can be provided that can properly configure the stepped structure SBS.

[0123] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0124] 1,101,201 Semiconductor memory device, 2,102,202 Memory cell array, SBR,SBR1,SBR2,SBS Stepped structure, SST,SST_1,SST_2 Stacked structure, HR1,HR1_1~HR1_5,HR2,HR2_1,HR2_2,HR102,HR102_1,HR102_2,HR202,HR202_1,HR202_2 Insulating film.

Claims

1. Multiple conductive layers are laminated with an insulating layer in between, and the laminate includes a stepped structure near the center in the longitudinal direction in a plan view. In the terrace portion of the aforementioned staircase structure, the laminate is provided with a first insulating film extending in the stacking direction, In a plan view, one or more second insulating films are arranged in a region that includes the stepped portion of the staircase structure on the inside, extending in the stacking direction of the laminate, and having a minimum planar width greater than the first insulating film, or having a higher arrangement density than the first insulating film. A semiconductor memory device equipped with [specific features / features].

2. In the region, one second insulating film is provided, which has a minimum planar width greater than that of the first insulating film. The semiconductor memory device according to claim 1.

3. In the region, one second insulating film is provided, which has a maximum planar width greater than that of the first insulating film. The semiconductor memory device according to claim 1.

4. In the aforementioned region, a plurality of the second insulating films are arranged in a planar manner, connected together. The semiconductor memory device according to claim 1.

5. In the region, a plurality of the second insulating films are arranged in a connected manner so as to cover the stepped portion. The semiconductor memory device according to claim 1.

6. In the region, a plurality of the second insulating films are arranged in a ring-like manner. The semiconductor memory device according to claim 1.

7. In the aforementioned region, a plurality of the second insulating films are arranged in a connected manner so as to surround the stepped portion. The semiconductor memory device according to claim 1.

8. The width of the stepped portion in the stacking direction, through which the second insulating film extends, is greater than the arrangement pitch of the conductive layers in the stacking direction in the laminate. The semiconductor memory device according to claim 1.

9. When N is an integer of 2 or more, the width of the stepped portion in the stacking direction to which the second insulating film extends corresponds to N times the arrangement pitch of the conductive layer in the stacking direction in the laminate. The semiconductor memory device according to claim 8.

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