Memory system and control method

Abstract

The present invention provides a memory system and control method capable of suppressing temperature rise and performance degradation. [Solution] The memory system comprises a non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, and a controller, the controller including a host interface circuit that receives external instruction information from a host device, which includes instructions to read and write data to the non-volatile memory, a memory interface circuit that communicates with the non-volatile memory, an instruction information processing unit that generates internal instruction information to cause the non-volatile memory to execute instructions based on the external instruction information and transmits the internal instruction information to the non-volatile memory through the memory interface circuit, and a delay circuit control unit that controls a delay circuit that delays the execution of instructions based on the relationship between the amount of data read and written by the non-volatile memory in a unit of time and a first threshold.

Description

Technical Field

[0001] This embodiment relates to a memory system and a control method.

Background Art

[0002] Storage devices equipped with non-volatile memories such as Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC), and Solid State Drive (SSD) are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to this embodiment, a memory system and a control method capable of suppressing temperature rise and performance degradation are provided.

Means for Solving the Problems

[0005] The memory system according to this disclosure includes a non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, and a controller, the controller including a host interface circuit that receives external instruction information from a host device, which includes an instruction to read and write the data to the non-volatile memory, a memory interface circuit that communicates with the non-volatile memory, an instruction information processing unit that generates internal instruction information to cause the non-volatile memory to execute the instruction based on the external instruction information and transmits the internal instruction information to the non-volatile memory through the memory interface circuit, and a delay circuit control unit that controls a delay circuit that delays the execution of the instruction based on the relationship between the amount of data read and written by the non-volatile memory in a unit time and a first threshold.

[0006] The control method relating to this disclosure is a control method for a memory system comprising a non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, and a controller that communicates with the non-volatile memory, the method comprising: receiving external instruction information from a host device including an instruction to cause the non-volatile memory to read and write the data; generating internal instruction information based on the external instruction information to cause the non-volatile memory to execute the instruction; transmitting the internal instruction information to the non-volatile memory; and controlling a delay circuit that delays the execution of the instruction based on the relationship between the amount of data read and written by the non-volatile memory in a unit time and a first threshold. [Brief explanation of the drawing]

[0007] [Figure 1] This is a functional block diagram of the memory system 101 according to this embodiment. [Figure 2] This shows a state transition diagram of the operating modes of the memory system 101. [Figure 3] This sequence diagram shows the internal processing operation of the memory system 101 when it receives an external read command from the host device 111 in normal mode M1. [Figure 4]This sequence diagram shows the internal processing operation of the memory system 101 when it receives multiple external read commands from the host device 111 in high-temperature mode M2. [Figure 5] This sequence diagram shows the internal processing operation of the memory system 101 when it receives multiple external read commands from the host device 111 while the operating mode is transitioning from high-temperature mode M2 ​​to performance suppression mode M3. [Figure 6] This figure shows an example of how the power consumption of the memory system 101 affects its performance. [Figure 7] This figure shows an example of how the temperature Tc of the memory system 101 changes with respect to power consumption. [Figure 8] This figure shows an example of the time change in temperature when performance throttling is implemented in a conventional memory system. [Figure 9] This figure shows an example of the time change of temperature Tc in the memory system 101 when the threshold Tth is set to 90°C and 100°C. [Figure 10] This figure shows an example of the temperature dependence of leakage current. [Figure 11] This figure shows examples of temperature changes for the memory system 101 when it is performing at 100% and 90% of its capacity. [Figure 12] This figure shows an example of the time variation of the operating current Icc when the memory system 101 performs a continuous sequential read operation. [Figure 13] This figure shows an example of the time variation of the operating current Icc when the comparative memory system performs a continuous sequential read operation. [Figure 14] This figure shows an example of the time variation of the operating current Icc when the comparative memory system performs continuous random read operations. [Figure 15] This figure shows an example of the time variation of the operating current Icc when the memory system 101 performs a continuous random read operation. [Modes for carrying out the invention]

[0008] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same reference numerals are given to the same components in each drawing as much as possible, and duplicate descriptions are omitted.

[0009] FIG. 1 is a functional block diagram of a memory system 101 according to this embodiment. The memory system 101 (an example of a "storage device") includes a non-volatile memory 10 (an example of a "memory") and a controller 20.

[0010] The controller 20 includes an internal logic unit 21 (an example of a "control unit"), a bus 22, a volatile memory 23, a host interface (I / F) circuit 24, a memory interface (I / F) circuit 25, a timer 26, and a delay circuit 27. Specifically, the controller 20 is a controller chip.

[0011] The memory system 101 may be, for example, a UFS (Universal Flash Storage) device compliant with the UFS standard (e.g., JESD220F). The UFS standard is a standard for NAND flash memories for digital cameras, smartphones, and home appliances, and is formulated by JEDEC (Joint Electron Device Engineering Councils).

[0012] The non-volatile memory 10 includes a non-volatile storage area 11 and a temperature sensor 12. Specifically, the non-volatile memory 10 is a memory chip. The storage area 11 in the non-volatile memory 10 is, for example, a memory cell array. The data stored in the storage area 11 is retained even when no power is supplied.

[0013] In this embodiment, the non-volatile memory 10 is a semiconductor memory. Specifically, the non-volatile memory 10 is a NAND-type flash memory.

[0014] Note that the non-volatile memory 10 may be MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[0015] The non-volatile memory 10 can read and write data to and from the storage area 11. Specifically, the non-volatile memory 10 includes, for example, a controller (an example of a "memory control unit").

[0016] The non-volatile memory 10 is configured to be able to execute data writing and data reading operations in a predetermined writing unit according to internal command information received from the controller 20.

[0017] Furthermore, the non-volatile memory 10 is configured to be able to erase data in an erasing unit including a plurality of writing units. For example, when the non-volatile memory 10 is a NAND-type flash memory, the non-volatile memory 10 performs writing and reading operations in page units and erases data in block units composed of a plurality of pages.

[0018] In detail, the non-volatile memory 10 includes, in addition to the storage area 11, an interface circuit (input / output circuit) for exchanging information with the controller 20, a sense amplifier for reading information stored in the memory cell array and sending information to be written to the memory cell array, a data register for storing data and other information received by the interface circuit from the controller 20, or data and other information read from the memory cell array using the sense amplifier, a status register for storing the status of the non-volatile memory 10, an address register for storing physical address information received by the interface circuit from the controller 20, a row decoder and a column decoder for accessing predetermined memory cells according to the physical address information stored in the address register, a command register for storing instruction information received by the interface circuit from the controller 20, and a sequencer for controlling, for example, the sense amplifier, data register, status register, row decoder, and column decoder according to the various instruction information stored in the command register, and for executing write operations, read operations, erase operations, etc.

[0019] The temperature sensor 12 acquires temperature information indicating the temperature of the memory system 101. In this embodiment, the temperature sensor 12 is a sensor circuit formed in the non-volatile memory 10. The sensor circuit is formed in the vicinity of the circuit of the storage area 11. The temperature sensor 12 acquires temperature information indicating the temperature of the non-volatile memory 10.

[0020] The temperature sensor 12 is not limited to being formed on the non-volatile memory 10; for example, it may be formed on the controller 20 or provided near the non-volatile memory 10 or the controller 20. Furthermore, the temperature sensor 12 may be provided at yet another location and configured to acquire temperature information indicating the temperature of the memory system 101 or the non-volatile memory 10 by correcting it based on a predetermined correction coefficient or the like. The temperature sensor 12 may be, for example, a thermocouple or a semiconductor temperature sensor that measures temperature using the electrical characteristic of a semiconductor whose band gap changes in response to temperature changes.

[0021] The host device 111 transmits external instruction information to the memory system 101, which includes instructions to read or write data to the non-volatile memory 10. Specifically, the instructions to read or write data to the non-volatile memory 10 are either external read instructions or external write instructions.

[0022] An external read instruction is an instruction used to read data from the non-volatile memory 10.

[0023] In detail, an external read instruction includes the logical address of the data to be read and the size of the data to be read.

[0024] When the memory system 101 receives an external read command, it retrieves the data to be read from the non-volatile memory 10 according to the external read command. The memory system 101 then sends the retrieved data to be read, along with response information indicating that the external read command has been completed, to the host device 111.

[0025] The external write instruction is an instruction for writing data (hereinafter sometimes referred to as "data to be written") to the non-volatile memory 10.

[0026] In detail, an external write instruction includes the logical address to which the data to be written should be written, and the size of the data to be written. An external write instruction may include the data to be written, or may be accompanied by the data to be written.

[0027] When the memory system 101 receives an external write command, it stores the data to be written in the non-volatile memory 10 according to the external write command. Then, the memory system 101 sends response information to the host device 111 indicating that the external write command has been completed.

[0028] The host device 111 is, for example, a UFS host compliant with the UFS standard (e.g., JESD220F). Specifically, the host device 111 is a personal computer, a portable information terminal, etc.

[0029] The controller 20 in the memory system 101 controls the operation of the non-volatile memory 10, including data writing and data reading operations.

[0030] In the controller 20, the internal logic unit 21, the volatile memory 23, the host interface circuit 24, the memory interface circuit 25, and the timer 26 are interconnected via the bus 22.

[0031] The host interface circuit 24 is the front end of the controller 20 and connects the host device 111 and the controller 20 in a communicative manner.

[0032] The host interface circuit 24 receives external read commands, external write commands, and data to be written from the host device 111.

[0033] The host interface circuit 24 communicates serially with, for example, the host device 111. The host interface circuit 24 converts the serial data received from the host device into parallel data and outputs it to the bus 22.

[0034] Furthermore, the host interface circuit 24 converts parallel data received from the bus 22 into serial data and transmits it to the host device 111.

[0035] For example, if the memory system 101 is a UFS device, the host interface circuit 24 includes a transport layer that uses MIPI UniPro (Mobile Industry Processor Interface Unified Protocol) compliant with the MIPI UniPro™ standard, and a MIPI M-PHY physical layer compliant with the MIPI M-PHY™ standard. The host interface circuit 24 has a physical configuration for sending and receiving differential signal pairs, DIN and DIN_c, which are information (data) received from the host device 111, and DOUT and DOUT_c, which are information (data) transmitted to the host device 111, as well as a reference clock signal, power supply voltage, etc.

[0036] The memory interface circuit 25 is the backend of the controller 20 and connects the non-volatile memory 10 and the controller 20 in a communicative manner. The memory interface circuit 25 has a configuration that conforms to, for example, the ONFI standard or the Toggle standard.

[0037] The volatile memory 23 is a volatile storage device. Specifically, the volatile memory 23 is SRAM (Static Random Access Memory). Alternatively, the volatile memory 23 may be DRAM (Dynamic Random Access Memory) located outside the controller 20. The volatile memory 23 is a buffer that temporarily stores various instructions and data.

[0038] The internal logic unit 21 is, for example, a CPU (Central Processing Unit). The internal logic unit 21 operates as a processing unit that processes instructions from the host device 111 by executing firmware (an example of a computer program).

[0039] The firmware is stored, for example, in non-volatile memory 10. The firmware is transferred from non-volatile memory 10 to volatile memory 23. The internal logic unit 21 executes the firmware stored in volatile memory 23.

[0040] The internal logic unit 21 stores the data necessary for firmware execution in the volatile memory 23 during firmware execution. The internal logic unit 21 reads the instructions and data necessary for firmware execution from the volatile memory 23 and executes arithmetic processing according to the contents of the processing instructions. At this time, the internal logic unit 21 may generate new data necessary for firmware execution and store it in the volatile memory 23.

[0041] The internal logic unit 21 includes, as functional blocks, an operation mode selection unit 28, a data amount acquisition unit 29, a temperature information acquisition unit 30, a transmission / reception information processing unit 31 (an example of an "instruction information processing unit"), and a delay circuit control unit 32.

[0042] The transmit / receive information processing unit 31 in the internal logic unit 21 generates internal instruction information corresponding to external instruction information. Specifically, the internal instruction information includes internal read instructions and internal write instructions corresponding to external read instructions and external write instructions, respectively. Internal read instructions and internal write instructions are internal commands that can be executed by the non-volatile memory 10.

[0043] The transmission / reception information processing unit 31 temporarily stores, for example, external read commands, external write commands, and data to be written that the host interface circuit 24 outputs to the bus 22 in the volatile memory 23.

[0044] The transmission / reception information processing unit 31 manages the logical and physical addresses of the non-volatile memory 10. More specifically, the transmission / reception information processing unit 31 manages a logic-to-physical conversion table that shows the correspondence between the logical address of the storage area 11 in the non-volatile memory 10 and the physical address of the storage area 11.

[0045] The logic-material conversion table is stored, for example, in memory area 11 and is transferred to volatile memory 23 when the firmware is executed.

[0046] The transmission / reception information processing unit 31 stores the external read command output to the bus 22 by the host interface circuit 24 in the volatile memory 23, and then generates an internal read command based on the external read command and the logic-to-physical conversion table.

[0047] In detail, the transmit / receive information processing unit 31 converts the logical address included in the external read instruction to a physical address based on, for example, a logic-to-physical conversion table. The transmit / receive information processing unit 31 generates an internal read instruction that includes the physical address and the size of the data to be read, and stores the internal read instruction in the volatile memory 23 as data to be sent to the non-volatile memory 10 (hereinafter sometimes referred to as data awaiting transmission).

[0048] Furthermore, when the transmission / reception information processing unit 31 stores the external write command and the data to be written, which have been output to the bus 22 by the host interface circuit 24, into the volatile memory 23, it performs the following processing.

[0049] In other words, the transmission / reception information processing unit 31 generates an internal write command based on the external write command and the data conversion table.

[0050] In detail, the transmit / receive information processing unit 31 converts the logical address included in the external write instruction to a physical address, for example, based on a logic-to-physical conversion table. The transmit / receive information processing unit 31 then generates an internal write instruction that includes the physical address and the size of the data to be written.

[0051] Furthermore, the transmission / reception information processing unit 31 converts the data to be written into a format suitable for storage in the non-volatile memory 10.

[0052] The transmission / reception information processing unit 31 stores the internal write command and the data to be written that is the target of the internal write command in the volatile memory 23 as data awaiting transmission.

[0053] The memory interface circuit 25 transmits internal instruction information to the non-volatile memory 10. Specifically, the memory interface circuit 25 transmits an internal read instruction, an internal write instruction, and the data to be written to the non-volatile memory 10.

[0054] In this embodiment, the memory interface circuit 25 communicates in parallel with, for example, the non-volatile memory 10. The memory interface circuit 25 receives the data waiting to be transmitted stored in the volatile memory 23 via the bus 22 and transmits the received data to the memory interface circuit 25.

[0055] Here, the data awaiting transmission is stored in the volatile memory 23 using a queue data structure. In other words, the internal read instructions, internal write instructions, and data to be written stored in the volatile memory 23 are transmitted to the non-volatile memory 10 via the memory interface circuit 25 in the order in which they were stored in the volatile memory 23.

[0056] The delay circuit 27 performs thermal throttling to delay the execution of internal read and write instructions by the non-volatile memory 10 (hereinafter sometimes referred to as instruction execution by the non-volatile memory 10). In this embodiment, the delay circuit 27 is provided in the memory interface circuit 25.

[0057] In this embodiment, the delay circuit 27 performs thermal throttling by preventing internal instruction information from being transmitted from the memory interface circuit 25 to the non-volatile memory 10 for a predetermined delay time.

[0058] In other words, the delay circuit 27 delays the timing at which the memory interface circuit 25 sends internal read instructions, internal write instructions, and data to be written to the non-volatile memory 10.

[0059] In detail, the delay circuit 27 includes, for example, a timer. The time measured by the timer, i.e., the delay time, is set by the internal logic unit 21. When the timer of the delay circuit 27 starts operating, the memory interface circuit 25 does not receive data waiting to be transmitted stored in the volatile memory 23 until the timer expires.

[0060] In other words, while the delay circuit 27 is operating, the data waiting to be transmitted stored in the volatile memory 23 is not transmitted from the memory interface circuit 25 to the non-volatile memory 10, and the data waiting to be transmitted generated by the transmit / receive information processing unit 31 is added to the transmit queue in the volatile memory 23. Then, a delay time is added to the transmission interval between two consecutively transmitted data waiting to be transmitted.

[0061] The delay circuit 27 may also be, for example, a circuit that stores data waiting to be transmitted until a predetermined time (a predetermined number of counts) has elapsed, or a configuration in which multiple flip-flop circuits having a predetermined delay amount are connected in series.

[0062] Timer 26 measures a unit of time according to control from the internal logic unit 21. The unit of time can be any length.

[0063] In detail, when the internal logic unit 21 sets the unit time, the timer 26 measures the time from the set timing. When the time being measured matches the unit time, the timer 26 notifies the internal logic unit 21 that the timer has expired.

[0064] When the non-volatile memory 10 receives an internal read command from the controller 20, it performs a data read operation. Specifically, the non-volatile memory 10 reads the data to be read from a portion of the storage area 11 indicated by the physical address included in the internal read command, and transmits the data to be read to the memory interface circuit 25.

[0065] Furthermore, when the non-volatile memory 10 receives an internal write instruction and the data to be written, it performs a data writing operation. Specifically, the non-volatile memory 10 writes the data to be written to a portion of the storage area 11 indicated by the physical address included in the internal write instruction, in accordance with the internal write instruction.

[0066] Figure 2 shows a state transition diagram of the operating modes of the memory system 101. Referring to Figures 1 and 2, the operating mode selection unit 28 in the internal logic unit 21 sets the operating mode of the memory system 101 to one of the following: normal mode M1, high temperature mode M2, or performance suppression mode M3.

[0067] The temperature information acquisition unit 30 repeatedly acquires temperature information from the temperature sensor 12 and outputs it to the operation mode selection unit 28. In this embodiment, the temperature information acquisition unit 30 repeatedly acquires temperature information at a period corresponding to the operation mode set by the operation mode selection unit 28, for example. The period for acquiring temperature information may be the same for each operation mode of the memory system 101, or it may be partially or entirely different.

[0068] Specifically, the temperature information acquisition unit 30 monitors the operation of the operation mode selection unit 28, and when the operation mode selection unit 28 sets normal mode M1, high-temperature mode M2, or performance suppression mode M3, it sets the periods to N milliseconds, M milliseconds, and M milliseconds, respectively. Here, N is greater than M.

[0069] The data acquisition unit 29 repeatedly performs a unit time I / O data acquisition process to acquire the amount of data read from and written to the non-volatile memory 10 during a unit time (hereinafter sometimes referred to as the unit time I / O data amount), and outputs the acquired unit time I / O data amount to the operation mode selection unit 28.

[0070] In this embodiment, the data acquisition unit 29 monitors the operation of the operation mode selection unit 28 and acquires the I / O data amount per unit time when the operation mode selection unit 28 sets either high-temperature mode M2 ​​or performance suppression mode M3. The unit time may be any time. The data acquisition unit 29 may use a statically fixed unit time or a dynamically changing unit time.

[0071] In detail, the data acquisition unit 29 sets a unit time in the timer 26 and performs the following accumulation process until it receives notification of completion from the timer 26.

[0072] In other words, the data acquisition unit 29 acquires the size of the data to be read included in the external read instruction or the internal read instruction each time an internal read instruction is generated based on an external read instruction. The data acquisition unit 29 acquires the amount of data read by the non-volatile memory 10 during a unit of time (hereinafter sometimes referred to as the amount of data read per unit of time) by accumulating the acquired sizes.

[0073] Furthermore, the data amount acquisition unit 29 acquires the size of the data to be written included in the external write instruction or the internal write instruction each time an internal write instruction is generated based on an external write instruction. The data amount acquisition unit 29 acquires the amount of data written by the non-volatile memory 10 during a unit of time (hereinafter sometimes referred to as the amount of data written per unit of time) by accumulating the acquired sizes.

[0074] The data acquisition unit 29 acquires the unit time I / O data amount by summing the acquired unit time read data amount and unit time write data amount, and outputs the unit time I / O data amount to the operation mode selection unit 28. When the operation mode is high temperature mode M2 ​​or performance suppression mode M3, the data acquisition unit 29 repeatedly performs the unit time I / O data amount acquisition process.

[0075] [Normal Mode M1] Normal mode M1 is an operating mode in which the memory system 101 operates in accordance with external read and write instructions from the host device 111.

[0076] The operating mode selection unit 28 sets, for example, the normal mode M1 as the initial value of the operating mode. In normal mode M1, the operating mode selection unit 28 performs a temperature comparison process each time it periodically receives temperature information from the temperature information acquisition unit 30, comparing the temperature Tc indicated by the temperature information with a threshold Tth (an example of a "second threshold").

[0077] The operating mode selection unit 28, when the operating mode is normal mode M1, transitions the operating mode from normal mode M1 to high-temperature mode M2 ​​when the temperature Tc becomes higher than the threshold Tth. The threshold Tth may be a predetermined value selected from, for example, a temperature range of 80 to 95 degrees.

[0078] On the other hand, when the operating mode is normal mode M1, the operating mode selection unit 28 maintains the operating mode in normal mode M1 when the temperature Tc is below the threshold Tth.

[0079] [High Temperature Mode M2] High-temperature mode M2 ​​is an operating mode that, compared to normal mode M1, further monitors the amount of I / O data per unit time.

[0080] In high-temperature mode M2, the operating mode selection unit 28 performs the temperature comparison processing described above, and each time it repeatedly receives the unit time I / O data amount from the data amount acquisition unit 29, it performs a data size comparison processing that compares the unit time I / O data amount with a threshold Dth (an example of a "first threshold").

[0081] The operating mode selection unit 28 maintains the operating mode in high-temperature mode M2 ​​when the operating mode is high-temperature mode M2, the temperature Tc is greater than or equal to the threshold Tth, and the amount of I / O data per unit time, i.e., Σ (Data size), is less than or equal to the threshold Dth. The threshold Dth may be a predetermined value selected from, for example, 2000 to 3500 MiB.

[0082] Furthermore, the operating mode selection unit 28, when the operating mode is high-temperature mode M2 ​​and the temperature Tc is greater than or equal to the threshold Tth, transitions the operating mode from high-temperature mode M2 ​​to performance suppression mode M3 if Σ(Data size) becomes greater than the threshold Dth.

[0083] On the other hand, when the operating mode is high-temperature mode M2, the operating mode selection unit 28 transitions the operating mode from high-temperature mode M2 ​​to normal mode M1 when the temperature Tc falls below the threshold Tth.

[0084] [Performance suppression mode M3] Performance suppression mode M3 is an operating mode in which thermal throttling is performed by the delay circuit 27, in addition to the high-temperature mode M2.

[0085] The operating mode selection unit 28 performs the temperature comparison process and data size comparison process described above in performance suppression mode M3.

[0086] The operating mode selection unit 28 maintains the operating mode in performance suppression mode M3 when the operating mode is performance suppression mode M3, the temperature Tc is greater than or equal to the threshold Tth, and Σ(Data size) is greater than or equal to the threshold Dth.

[0087] On the other hand, the operating mode selection unit 28, when the operating mode is performance suppression mode M3 and the temperature Tc is greater than or equal to the threshold Tth, transitions the operating mode from performance suppression mode M3 to high-temperature mode M2 ​​when Σ(Data size) falls below the threshold Dth.

[0088] Furthermore, when the operating mode is performance suppression mode M3, the operating mode selection unit 28 transitions the operating mode from performance suppression mode M3 to normal mode M1 when the temperature Tc falls below the threshold Tth.

[0089] The delay circuit control unit 32 controls the delay circuit 27 based on the relationship between the amount of I / O data per unit time and the threshold Dth.

[0090] Specifically, the delay circuit control unit 32 delays the execution of instructions by the non-volatile memory 10 for the delay circuit 27 when, for example, the temperature is above a threshold Tth and the amount of I / O data per unit time is above a threshold Dth.

[0091] More specifically, when the delay circuit control unit 32 controls the delay circuit 27 to prevent delays in instruction execution by the non-volatile memory 10, if the temperature Tc is greater than or equal to the threshold Tth and the amount of I / O data per unit time is greater than the threshold Dth, it initiates thermal throttling processing for the delay circuit 27.

[0092] In this embodiment, the delay circuit control unit 32 monitors the operation of the operation mode selection unit 28, and when the operation mode selection unit 28 sets the performance suppression mode M3, it operates the delay circuit 27 by setting a delay time in the timer included in the delay circuit 27.

[0093] On the other hand, the delay circuit control unit 32 stops the delay circuit 27 when the operating mode selection unit 28 sets either the normal mode M1 or the high-temperature mode M2.

[0094] In performance suppression mode M3, when the delay circuit 27 is activated, the data waiting to be transmitted stored in the volatile memory 23 is not sent to the non-volatile memory 10 until the delay time has elapsed since the circuit was activated.

[0095] In other words, the time from when the host interface circuit 24 receives external instruction information until the memory interface circuit 25 transmits the corresponding internal instruction information to the non-volatile memory 10 is longer when the delay circuit control unit 32 delays the execution of instructions by the non-volatile memory 10 to the delay circuit 27 than when the delay circuit control unit 32 does not delay the execution of instructions by the non-volatile memory 10 to the delay circuit 27.

[0096] [Operation] Figure 3 is a sequence diagram showing the internal processing operation of the memory system 101 when it receives an external read command from the host device 111 in normal mode M1.

[0097] Referring to Figures 1 and 3, the host device 111 sends an external read command to the memory system 101.

[0098] External read instructions are more specifically external sequential read instructions or external random read instructions. Internal read instructions are more specifically internal sequential read instructions or internal random read instructions. Internal sequential read instructions and internal random read instructions are based on external sequential read instructions and external random read instructions, respectively.

[0099] The external sequential read instruction and the internal sequential read instruction are instructions that cause the non-volatile memory 10 to read data stored in each of the multiple consecutive addresses in the memory area 11 in address order. Here, the addresses are logical addresses and physical addresses, respectively, in the external sequential read instruction and the internal sequential read instruction.

[0100] External random read instructions and internal random read instructions are instructions that cause the non-volatile memory 10 to read data stored in each of the multiple non-contiguous addresses in the memory area 11. Here, the addresses are logical addresses and physical addresses, respectively, in the external random read instructions and internal random read instructions.

[0101] Although not shown in the diagram, external write instructions are more specifically external sequential write instructions or external random write instructions. Internal write instructions are more specifically internal sequential write instructions or internal random write instructions. Internal sequential write instructions and internal random write instructions are based on external sequential write instructions and external random write instructions, respectively.

[0102] The external sequential write instruction and the internal sequential write instruction are instructions that cause the non-volatile memory 10 to write each target data to the memory area 11 to each area having multiple consecutive addresses in address order. Here, the addresses are the logical address and the physical address, respectively, in the external sequential write instruction and the internal sequential write instruction.

[0103] The external random write instruction and the internal random write instruction are instructions that cause the non-volatile memory 10 to write the data to be written to each of the multiple non-contiguous addresses in the memory area 11. Here, the addresses are the logical address and the physical address, respectively, in the external random write instruction and the internal random write instruction.

[0104] The operating mode of the internal logic unit 21 in the controller 20 is set to normal mode M1. When the internal logic unit 21 receives an external read command through the host interface circuit 24, it generates an internal read command corresponding to the external read command based on the external read command.

[0105] The internal logic unit 21 sends the generated internal read instruction to the non-volatile memory 10 through the memory interface circuit 25.

[0106] When the non-volatile memory 10 receives an internal read command, it retrieves the data to be read according to the internal read command and sends the data to be read to the controller 20.

[0107] When the memory interface circuit 25 receives data to be read from the non-volatile memory 10, it outputs the data to be read to the internal logic unit 21 via the bus 22. The data to be read may be temporarily buffered in the volatile memory 23.

[0108] When the internal logic unit 21 receives data to be read from the memory interface circuit 25, it converts the data units of the data to be read into data units managed by the host device 111. The internal logic unit 21 also generates response information indicating that the external read instruction has been completed.

[0109] The internal logic unit 21 outputs the data to be read and the response information to the host interface circuit 24 via the bus 22. The data to be read and the response information may be temporarily buffered in the volatile memory 23.

[0110] When the host interface circuit 24 receives the data to be read and the response information from the internal logic unit 21, it transmits the data to be read and the response information to the host device 111.

[0111] Figure 4 is a sequence diagram showing the internal processing operation of the memory system 101 when it receives multiple external read commands from the host device 111 in high-temperature mode M2.

[0112] Referring to Figures 1 and 4, the host device 111 repeatedly sends external read commands to the memory system 101.

[0113] Since the memory system 101 has, for example, two or more QDs (Que Depths), the host device 111 can send one or more external read commands to the memory system 101 between sending the first external read command and receiving the response information.

[0114] Specifically, for example, when the QD of the memory system 101 is 8, the host device 111 can send the second to eighth external read instructions to the memory system 101 before receiving the response information for the first external read instruction.

[0115] The operating mode of the internal logic unit 21 in the controller 20 is set to high-temperature mode M2. The internal logic unit 21 repeatedly receives external read commands through the host interface circuit 24.

[0116] Each time the internal logic unit 21 receives an external read instruction, it generates an internal read instruction corresponding to the external read instruction based on the external read instruction, and transmits the generated internal read instruction to the non-volatile memory 10 through the memory interface circuit 25.

[0117] Furthermore, the internal logic unit 21 sets a unit time for the timer 26 at time t1, and measures the amount of I / O data per unit time until it receives an expiration notification from the timer 26.

[0118] Each time the non-volatile memory 10 receives an internal read command, it retrieves the data to be read according to the internal read command and sends the data to be read to the controller 20. In the example shown in Figure 4, the size of the data to be read is 4KB (kilobytes).

[0119] The memory interface circuit 25 outputs the data to be read to the internal logic unit 21 via the bus 22 each time it receives data to be read from the non-volatile memory 10.

[0120] Each time the internal logic unit 21 receives data to be read from the memory interface circuit 25, it converts the data units of the data to be read into data units managed by the host device 111 and generates response information.

[0121] The internal logic unit 21 outputs the data to be read and the response information to the host interface circuit 24 via the bus 22.

[0122] Furthermore, when the internal logic unit 21 receives an expiration notification from the timer 26 at time t2, for example, it compares the measured amount of I / O data per unit time with the threshold Dth.

[0123] In the example shown in Figure 4, since the amount of I / O data per unit time (e.g., 12KB) is below the threshold Dth, the operating mode of the memory system 101 is maintained in high-temperature mode M2. Therefore, the memory system 101 keeps the delay circuit 27 stopped, and the timing of each internal read instruction transmission is not delayed.

[0124] The host interface circuit 24 transmits the data to be read and the response information to the host device 111 each time it receives the data to be read and the response information from the internal logic unit 21.

[0125] Figure 5 is a sequence diagram showing the internal processing operation of the memory system 101 when it receives multiple external read commands from the host device 111, in a transition from high-temperature mode M2 ​​to performance suppression mode M3.

[0126] Referring to Figures 1 and 5, the host device 111 sends an external sequential read (SeqR) instruction to the memory system 101.

[0127] The operating mode of the internal logic unit 21 in the controller 20 is set to high-temperature mode M2. The internal logic unit 21 receives external SeqR commands through the host interface circuit 24.

[0128] When the internal logic unit 21 receives an external SeqR instruction, it generates a series of internal read instructions based on the external SeqR instruction, causing the non-volatile memory 10 to read the data stored in each of the regions, each having a series of consecutive physical addresses, in address order. In the example shown in Figure 5, the internal logic unit 21 generates four internal read instructions.

[0129] The internal logic unit 21 repeatedly sends the four internal read instructions it has generated to the non-volatile memory 10 through the memory interface circuit 25.

[0130] Furthermore, the internal logic unit 21 sets a unit time for the timer 26 at time t1, and measures the amount of I / O data per unit time until it receives an expiration notification from the timer 26.

[0131] Each time the non-volatile memory 10 receives an internal read command, it retrieves the data to be read according to the internal read command and sends the data to be read to the controller 20. In the example shown in Figure 5, the size of the data to be read is 4KB (kilobytes).

[0132] The memory interface circuit 25 outputs the data to be read to the internal logic unit 21 via the bus 22 each time it receives data to be read from the non-volatile memory 10.

[0133] Each time the internal logic unit 21 receives data to be read from the memory interface circuit 25, it converts the data units of the data to be read into data units managed by the host device 111.

[0134] Furthermore, when the internal logic unit 21 confirms that it has received the four data to be read, acquired by the four internal read instructions, it generates response information.

[0135] The internal logic unit 21 repeatedly outputs four data to be read to the host interface circuit 24 via the bus 22. The internal logic unit 21 then outputs response information to the host interface circuit 24 via the bus 22.

[0136] Furthermore, when the internal logic unit 21 receives an expiration notification from the timer 26 at time t2, for example, it compares the measured amount of I / O data per unit time with the threshold Dth.

[0137] In the example shown in Figure 5, since the amount of I / O data per unit time (e.g., 2500-4000 MB / s) is greater than the threshold Dth, the internal logic unit 21 transitions the operating mode from high-temperature mode M2 ​​to performance suppression mode M3. The internal logic unit 21 then activates the delay circuit 27.

[0138] As a result, the delay circuit 27 does not transmit data waiting to be transmitted from the memory interface circuit 25 until the delay time DT1 has elapsed after the delay circuit 27 starts operating.

[0139] Specifically, the internal read instruction Read2, which corresponds to the external read instruction Read1 sent from the host device 111 following the external SeqR instruction, is pending data that was not sent to the non-volatile memory 10 before time t2. Therefore, it is sent from the memory interface circuit 25 to the non-volatile memory 10 after the delay time DT1 has elapsed.

[0140] The host interface circuit 24 transmits the data to be read from the internal logic unit 21 to the host device 111 each time it receives data to be read. Then, when the host interface circuit 24 receives response information from the internal logic unit 21, it transmits the response information to the host device 111.

[0141] [assignment] Figure 6 shows an example of the change in power consumption of the memory system 101 with respect to performance. The vertical axis represents power consumption in units of "W," and the horizontal axis represents performance in units of "MiB / s." Performance is, for example, the amount of I / O data per unit time.

[0142] Figure 7 shows an example of the change in power consumption with respect to the temperature Tc of the memory system 101. The vertical axis represents the temperature Tc in units of "°C," and the horizontal axis represents the power consumption in units of "W."

[0143] As shown in Figures 6 and 7, power consumption is approximately proportional to the amount of I / O data per unit time. Similarly, temperature Tc is approximately proportional to power consumption. Therefore, temperature Tc increases with increasing I / O data volume per unit time.

[0144] When external random read and write instructions are executed, time is required for the conversion from logical addresses to physical addresses based on the logic-to-physical address conversion table. For this reason, the amount of I / O data per unit time when external random read and write instructions are executed is smaller than the amount of I / O data per unit time when external sequential read and write instructions are executed.

[0145] In the comparative example, the memory system underwent performance throttling when the temperature Tc increased, regardless of the amount of I / O data per unit time. This performance throttling involved methods such as frequency division of the internal frequency or imposing a delay for each instruction.

[0146] As a result, delays were also imposed on external random read and external random write instructions, which have smaller I / O data volumes per unit time and contribute less to heat generation, thus increasing the processing time of these instructions.

[0147] Furthermore, in the comparative memory system, significant performance throttling is implemented only after the temperature Tc becomes high, in order to minimize the impact of performance throttling. As a result, the operation of the host device 111 sometimes became sluggish after the performance throttling was implemented.

[0148] Figure 8 shows an example of the time change in temperature when performance throttling is implemented in a conventional memory system. The vertical axis represents temperature Tc in degrees Celsius, and the horizontal axis represents time in seconds.

[0149] Table 1 shows the simulation results of the performance of the comparative memory system under normal conditions and with performance suppression implemented. [Table 1]

[0150] As shown in Figure 8 and Table 1, in conventional memory systems, performance throttling is implemented that reduces performance by 90% when the temperature Tc exceeds 110°C.

[0151] Despite significant performance throttling occurring after the temperature Tc exceeds 110°C, and a substantial decrease in the amount of I / O data per unit time, the temperature Tc remains at around 114°C without further reduction.

[0152] [Threshold Tth] Figure 9 shows an example of the time change of temperature Tc in the memory system 101 when the threshold Tth is set to 90°C and 100°C. The vertical axis represents temperature in degrees Celsius, and the horizontal axis represents time.

[0153] Figure 10 shows an example of the temperature dependence of leakage current. The vertical axis represents the leakage current in units of "mA," and the horizontal axis represents the temperature in units of "°C." Here, leakage current is the current that flows steadily. The leakage current is the current flowing through the circuits included in the memory system 101 minus the active current generated by data reading and writing operations in the memory system 101.

[0154] As shown in Figures 9 and 10, the curve Cr represents the time change of temperature Tc when the memory system 101 is operated continuously at 100% performance.

[0155] Curves C90 and C100 show the time change of temperature Tc when the memory system 101 is continuously operated at 100% performance with thresholds Tth set to 90°C and 100°C, respectively. In this example, when the temperature Tc exceeds the threshold Tth, the performance of the memory system 101 is reduced to 82% by thermal throttling by the delay circuit 27.

[0156] Here, 100% performance is, for example, the amount of I / O data per unit time in the memory system 101 when the host device 111 repeatedly sends an external sequential read command or an external sequential write command to the memory system 101 so that data waiting to be transmitted accumulates in the transmission queue of the volatile memory 23, without allowing the delay circuit 27 to perform thermal throttling.

[0157] The 82% performance is, for example, the performance when the delay circuit 27 is made to perform thermal throttling so that the amount of I / O data per unit time is 82% of the 100% performance.

[0158] When the threshold Tth is 90°C, the target temperature Tf1 can be reduced by approximately 12°C compared to the target temperature Tfr when the delay circuit 27 does not perform thermal throttling.

[0159] On the other hand, when the threshold Tth is 100°C, the achievable temperature Tf2 is only about 4°C lower than the achievable temperature Tfr.

[0160] The reason why the target temperature differs even when the same thermal throttling process is performed is as follows:

[0161] In other words, the leakage current in the memory system 101 increases exponentially with temperature (see Figure 10).

[0162] Therefore, the amount of heat generated by the leakage current at the target temperature Tf2 is significantly greater than the amount of heat generated by the leakage current at the target temperature Tf1. For this reason, even with the same thermal throttling process, the temperature drop from the target temperature Tfr when the threshold Tth is 100°C is smaller than the temperature drop from the target temperature Tfr when the threshold Tth is 90°C.

[0163] The inventor noticed that even with strong thermal throttling when the temperature approaches the target temperature Tfr, the effect of temperature reduction is diminished due to leakage current, and thus conceived a configuration that performs thermal throttling from an earlier timing.

[0164] Figure 11 shows examples of temperature changes of the memory system 101 when it is performing at 100% and 90% of its capacity. The vertical and horizontal axes represent temperature and time, respectively.

[0165] As shown in Figures 1, 10, and 11, the threshold Tth is below the temperature when the memory system 101 is continuously operated with the delay circuit 27 delaying the execution of instructions by the nonvolatile memory 10 when the nonvolatile memory 10 reads and writes data to each of the multiple consecutive physical addresses in the memory area 11.

[0166] In detail, curves C1 and C2 show the time change of temperature Tc when the memory system 101 is continuously operated at 100% and 90% performance, respectively, at room temperature (approximately 25°C).

[0167] 90% performance refers to the performance when the delay circuit 27 is made to perform thermal throttling so that the amount of I / O data per unit time is 90% of 100% performance.

[0168] If the memory system 101 is operated continuously at 100% performance, the temperature Tc will reach the target temperature Tf(100). If the memory system 101 is operated continuously at 90% performance, the temperature Tc will reach Tf(90). Here, the target temperature Tf(90) is lower than the target temperature Tf(100).

[0169] The inventors focused on the fact that, for example, when the target temperature Tf(90) is used as the reference temperature, performing thermal throttling processing before the temperature Tc becomes equal to or greater than the target temperature Tf(90) can reduce the adverse effects of heat generation due to leakage current.

[0170] The threshold Tth is, for example, less than or equal to the target temperature Tf(90). In this embodiment, the threshold Dth is the target temperature Tf(90).

[0171] Even if the delay circuit 27 is made to perform thermal throttling to achieve 90% performance when the temperature Tc is at the target temperature Tf(100), it is difficult to lower the temperature Tc to the target temperature Tf(90).

[0172] This is because the leakage current in the memory system 101 increases exponentially with temperature, and when the temperature Tc is at the target temperature Tf(100), the temperature Tc does not decrease easily due to the heat generated by the leakage current.

[0173] On the other hand, it is also conceivable to operate the memory system 101 at 90% of its performance from the start of operation, but this is undesirable because the amount of I / O data per unit time becomes low, thus increasing the time required for read and write operations.

[0174] By setting the threshold Tth to the target temperature Tf(90), the upper limit of the temperature Tc can be set to be near the target temperature Tf(90). Furthermore, when the temperature Tc is below the threshold Tth, i.e., below the target temperature Tf(90), the memory system 101 can operate at 100% performance, thus suppressing the time required for read and write operations.

[0175] [Threshold Dth] The threshold Dth is smaller than the amount of I / O data per unit time when the non-volatile memory 10 reads or writes data to each region in the storage area 11 that has multiple contiguous physical addresses, and larger than the amount of I / O data per unit time when the non-volatile memory 10 reads or writes data to each region in the storage area 11 that has multiple non-contiguous physical addresses.

[0176] Specifically, the threshold Dth is smaller than the amount of I / O data per unit time when, for example, the memory system 101 repeatedly receives external sequential read commands from the host device 111 so that data waiting to be transmitted accumulates in the transmission queue of the volatile memory 23 (hereinafter sometimes referred to as continuous sequential read operation).

[0177] The threshold Dth may be smaller than the amount of I / O data per unit time when, for example, the memory system 101 repeatedly receives external sequential write commands from the host device 111 so that data waiting to be transmitted accumulates in the transmission queue of the volatile memory 23 (hereinafter sometimes referred to as continuous sequential write operation).

[0178] Furthermore, the threshold Dth is greater than the amount of I / O data per unit time when, for example, the memory system 101 repeatedly receives external random read commands from the host device 111 so that data waiting to be transmitted accumulates in the transmission queue of the volatile memory 23 (hereinafter sometimes referred to as continuous random read operation).

[0179] The threshold Dth may be greater than the amount of I / O data per unit time when, for example, the memory system 101 repeatedly receives external random write commands from the host device 111 so that data waiting to be transmitted accumulates in the transmission queue of the volatile memory 23 (hereinafter sometimes referred to as continuous random write operation).

[0180] Hereinafter, continuous sequential read operation and continuous sequential write operation may be collectively referred to as continuous sequential R / W operation. Continuous random read operation and continuous random write operation may be collectively referred to as continuous random R / W operation.

[0181] Table 1 shows the simulation results of the memory system 101's performance when the operating mode is normal mode M1 and performance suppression mode M3. [Table 2]

[0182] As shown in Table 2, this simulation was performed under the following conditions: the performance corresponding to external sequential read and external sequential write instructions (hereinafter sometimes referred to as sequential performance), i.e., the amount of I / O data per unit time, was based on the assumption that the data size read and written by these instructions was 4 GiB, and the QD and chunk sizes were 8 and 512 KB, respectively.

[0183] The performance corresponding to external random read and external random write instructions (hereinafter sometimes referred to as random performance) is as follows: when the data size read or written by these instructions is 4 GiB, and the QD, chunk size, and number of consecutive commands are 32, 3 KB, and 24576, respectively.

[0184] The random performance of 400 KIOPs in normal mode M1 corresponds to approximately 1600 MiB / s. For example, by setting the threshold Dth to 3000 MiB / s, the operating mode can be kept in normal mode M1 or high-temperature mode M2 ​​even when receiving repeated external random read or write commands.

[0185] On the other hand, if an external sequential read command or external sequential write command is repeatedly received, the operating mode can be switched to performance suppression mode M3.

[0186] Since power consumption is roughly proportional to performance (see Figure 6), the power consumption when repeatedly receiving external random read or external random write instructions is approximately 38% of the power consumption when repeatedly receiving external sequential read or external sequential write instructions.

[0187] In other words, in the memory system 101, when repeatedly receiving external random read instructions or external random write instructions that generate relatively little heat, thermal throttling is not performed, thus suppressing the time required for read and write operations.

[0188] Figure 12 shows an example of the time change of the operating current Icc when the memory system 101 performs a continuous sequential read operation.

[0189] The vertical and horizontal axes in graphs S1 and S3 represent the operating current Icc and time, respectively. Graphs S1 and S3 show the time variation of the operating current Icc in normal mode M1 and performance suppression mode M3, respectively.

[0190] Here, the operating current Icc is the result of measuring the current consumption of the VCC power supply that provides power to the memory system 101.

[0191] As shown in Figure 12, in performance suppression mode M3, performance, i.e., the amount of I / O data per unit time, decreases, and power consumption decreases. Therefore, the operating current Icc in performance suppression mode M3 is lower than the operating current Icc in normal mode M1.

[0192] Figure 13 shows an example of the time variation of the operating current Icc when the comparative memory system performs a continuous sequential read operation.

[0193] Graphs Sr1 and Sr3 show the time variation of the operating current Icc under normal conditions and with performance suppression, respectively. The interpretation of graphs Sr1 and Sr3 is the same as for graphs S1 and S3.

[0194] As shown in Figure 13, the operating current Icc when performance suppression is implemented is lower than the operating current Icc under normal conditions, similar to the memory system 101 shown in Figure 12.

[0195] Figure 14 shows an example of the time variation of the operating current Icc when the comparative memory system performs continuous random read operations.

[0196] Graphs Rr1 and Rr3 show the time variation of the operating current Icc under normal conditions and with performance suppression, respectively. The interpretation of graphs Rr1 and Rr3 is the same as for graphs S1 and S3.

[0197] As shown in Figure 14, the operating current Icc when performance suppression is implemented is lower than the operating current Icc under normal conditions, similar to the comparative memory system shown in Figure 13.

[0198] In the comparative memory system, as mentioned above, performance suppression is implemented regardless of the amount of I / O data per unit time, resulting in a delay being imposed even on external random read instructions, which contribute little to heat generation.

[0199] Figure 15 shows an example of the time variation of the operating current Icc when the memory system 101 performs a continuous random read operation.

[0200] Graphs R1 and R3 show the time variation of the operating current Icc in normal mode M1 and performance suppression mode M3, respectively. The interpretation of graphs R1 and R3 is the same as for graphs S1 and S3.

[0201] As shown in Figure 15, when continuous random read operations are performed in the memory system 101, the amount of I / O data per unit time is smaller than the threshold Dth, so the operating mode does not transition to performance suppression mode M3. For this reason, the power consumption in normal mode M1 and high-temperature mode M2 ​​is almost the same, and the operating current Icc in high-temperature mode M2 ​​is almost the same as the operating current Icc in normal mode M1.

[0202] When the performance suppression mode M3 is set by the operation mode selection unit 28, the delay circuit control unit 32 may operate the delay circuit 27 once or multiple times. When the delay circuit 27 is operated multiple times, the delay circuit control unit 32 operates the delay circuit 27 for each internal read command and internal write command, for example. Alternatively, the delay circuit control unit 32 operates the delay circuit 27 for each time the data amount acquisition unit 29 acquires I / O data for a unit time. Or, the delay circuit control unit 32 operates the delay circuit 27 for each time the data amount acquisition unit 29 acquires I / O data for a predetermined number of times.

[0203] Furthermore, although a configuration in which the delay circuit 27 is provided in the memory interface circuit 25 has been described, the configuration is not limited to this. The delay circuit 27 may also be provided in the internal logic unit 21 or the non-volatile memory 10. When the delay circuit 27 is provided in the internal logic unit 21, the delay circuit 27 delays, for example, the generation of internal read instructions and internal write instructions by the internal logic unit 21 by a predetermined delay time. When the delay circuit 27 is provided in the non-volatile memory 10, the delay circuit 27 delays, for example, the generation of internal read instructions and internal write instructions by the internal logic unit 21 by a predetermined delay time.

[0204] Furthermore, while we have described a configuration in which a temperature Tc being higher than the threshold Tth is a condition for transitioning from normal mode M1 to high-temperature mode M2, the system is not limited to this configuration. A configuration in which a temperature Tc being greater than or equal to the threshold Tth is a condition for transitioning from normal mode M1 to high-temperature mode M2 ​​is also possible.

[0205] Furthermore, while we have described a configuration in which the transition from high-temperature mode M2 ​​to performance-reduced mode M3 is conditional on Σ(Data size) being greater than or equal to threshold Dth when temperature Tc is greater than or equal to threshold Tth, the system is not limited to this configuration. A configuration in which the transition from high-temperature mode M2 ​​to performance-reduced mode M3 is conditional on Σ(Data size) being greater than or equal to threshold Dth when temperature Tc is greater than or equal to threshold Tth is also possible.

[0206] Furthermore, while we have described a configuration in which the transition from performance suppression mode M3 to high-temperature mode M2 ​​is conditional on the temperature Tc being greater than or equal to the threshold Tth and Σ(Data size) being lower than the threshold Dth, the system is not limited to this configuration. A configuration in which the transition from performance suppression mode M3 to high-temperature mode M2 ​​is conditional on the temperature Tc being greater than or equal to the threshold Tth and Σ(Data size) being less than or equal to the threshold Dth is also possible.

[0207] Furthermore, while a configuration in which a temperature Tc lower than a threshold Tth is a condition for transitioning from performance suppression mode M3 or high-temperature mode M2 ​​to normal mode M1 has been described, the system is not limited to this configuration. A configuration in which a temperature Tc less than or equal to a threshold Tth is a condition for transitioning from performance suppression mode M3 or high-temperature mode M2 ​​to normal mode M1 is also possible.

[0208] Furthermore, while a configuration has been described in which the operation mode selection unit 28 compares the amount of I / O data per unit time with a threshold Dth and sets the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result, the system is not limited to this configuration. The operation mode selection unit 28 may also compare the amount of data read per unit time with a threshold Dth and set the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result. Since the power consumption of data read operations in the non-volatile memory 10 is greater than the power consumption of data write operations in the non-volatile memory 10, this configuration can still be sufficiently effective. Alternatively, the operation mode selection unit 28 may also compare the amount of data written per unit time with a threshold Dth and set the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result.

[0209] (a) A non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, A host interface circuit that receives external instruction information from a host device, including instructions to read and write the data to the non-volatile memory, A memory interface circuit that transmits internal instruction information corresponding to the external instruction information to the non-volatile memory, The system includes a delay circuit that delays the execution of the instruction by the non-volatile memory when the amount of data read from or written to the non-volatile memory during a unit of time is equal to or greater than a first threshold, storage device.

[0210] (b) A non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, A host interface circuit that receives external instruction information from a host device, including an instruction to read the data into the non-volatile memory, A memory interface circuit that transmits internal instruction information corresponding to the external instruction information to the non-volatile memory, The system includes a delay circuit that delays the execution of the instruction by the non-volatile memory when the amount of data read by the non-volatile memory during a unit of time is equal to or greater than a first threshold, storage device.

[0211] (c) A non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, A host interface circuit that receives external instruction information from a host device, including an instruction to write the data to the non-volatile memory, A memory interface circuit that transmits internal instruction information corresponding to the external instruction information to the non-volatile memory, The system includes a delay circuit that delays the execution of the instruction by the non-volatile memory when the amount of data written to the non-volatile memory during a unit of time exceeds a first threshold, storage device.

[0212] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of Symbols]

[0213] 10…Non-volatile memory 11…Storage area 12…Temperature sensor 20… Controller 21…Internal Logic Unit 22... Bus 23…Volatile memory 24…Host interface circuit 25…Memory interface circuit 26... Timer 27…Delay Circuit 28...Operation mode selection section 29...Data volume acquisition unit 30...Temperature information acquisition section 31…Transmission and Reception Information Processing Unit 32... Delay Circuit Control Unit 101…Memory System 111…Host device M1...Normal mode M2... High temperature mode M3... Performance suppression mode

Claims

1. A non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, Equipped with a controller, The aforementioned controller, A host interface circuit that receives external instruction information from a host device, including instructions to read and write the data to the non-volatile memory, A memory interface circuit that communicates with the aforementioned non-volatile memory, An instruction information processing unit generates internal instruction information for executing the instruction in the non-volatile memory based on the external instruction information, and transmits the internal instruction information to the non-volatile memory through the memory interface circuit. The system includes a delay circuit control unit that controls a delay circuit that delays the execution of an instruction based on the relationship between the amount of data read and written by the non-volatile memory during a unit of time and a first threshold, Memory system.

2. The memory system according to claim 1, wherein the delay circuit control unit delays the execution of the instruction to the delay circuit when the amount of data is equal to or greater than a first threshold.

3. The aforementioned memory system The system further includes a temperature sensor that acquires temperature information indicating the temperature of the memory system, The memory system according to claim 2, wherein the delay circuit control unit delays the execution of the instruction to the delay circuit when the temperature is equal to or greater than a second threshold and the amount of data is equal to or greater than a first threshold.

4. The delay circuit delays the execution of the instruction by preventing the internal instruction information from being transmitted to the non-volatile memory for a predetermined delay time. The memory system according to any one of claims 1 to 3.

5. The first threshold is smaller than the amount of data when the non-volatile memory reads or writes the data to each region having a plurality of contiguous addresses in the storage area, and larger than the amount of data when the non-volatile memory reads or writes the data to each region having a plurality of non-contiguous addresses in the storage area. The memory system according to claim 1.

6. The second threshold is less than or equal to the temperature when the memory system is continuously operated with the execution of the instruction delayed for the delay circuit, in which the non-volatile memory reads and writes the data to each of the multiple consecutive addresses in the memory area. The memory system according to claim 3.

7. The time from when the host interface circuit receives the external instruction information until the memory interface circuit transmits the internal instruction information is longer when the delay circuit control unit delays the execution of the instruction to the delay circuit than when the delay circuit control unit does not delay the execution of the instruction to the delay circuit. The memory system according to claim 2.

8. A control method for a memory system comprising a non-volatile memory having a non-volatile storage area and capable of reading and writing data to the storage area, and a controller that communicates with the non-volatile memory, The system receives external instruction information from the host device, which includes instructions to read or write the data to the non-volatile memory. Based on the external instruction information, internal instruction information is generated to cause the non-volatile memory to execute the instruction. The internal instruction information is transmitted to the non-volatile memory. Based on the relationship between the amount of data read and written by the non-volatile memory during a unit of time and a first threshold, a delay circuit that delays the execution of the instruction is controlled. A control method that includes the following.

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