Semiconductor equipment

Abstract

The objective is to provide a technology that can reduce the gate charge while suppressing the reduction in saturation current. [Solution] The semiconductor device comprises a semiconductor substrate having a drift layer, a carrier storage layer, and a base layer, and a two-stage active trench structure provided on the semiconductor substrate. The thickness of the lower insulating film in contact with the side of the lower electrode is greater than the thickness of the upper insulating film in contact with the side of the upper electrode, at least one of conditions (a), (b), and (c) is satisfied, and the lower end of the upper electrode is located above the position where the cumulative value of the impurity concentration in the carrier storage layer in the vertical direction is halved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device including an upper electrode and a lower electrode insulated from each other in a trench, a configuration has been proposed in which a lower insulating film contacting the side portion of the lower electrode is made thicker than an upper insulating film contacting the side portion of the upper electrode (for example, Patent Document 1). According to such a configuration, it is possible to suppress the influence of the channel on the threshold voltage characteristics and suppress the switching loss of the semiconductor device by reducing the gate charge.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a two-stage active trench structure, when the thickness of the lower insulating film is increased to reduce the gate charge amount (Qg), the carrier concentration in the accumulation layer on the side wall of the trench decreases, so the saturation current (Isat) decreases. Thus, in the two-stage active trench structure, there has been a problem that reduction of the gate charge amount (Qg) and maintenance of the saturation current (Isat) cannot be achieved simultaneously.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the gate charge amount while suppressing reduction of the saturation current.

Means for Solving the Problems

[0006] A semiconductor device according to this disclosure comprises a semiconductor substrate having a first main surface, wherein a drift layer of a first conductivity type, a carrier storage layer of the first conductivity type with a higher impurity concentration than the drift layer, and a base layer of a second conductivity type are provided in this order toward the first main surface, and a two-stage active trench structure provided on the first main surface side of the semiconductor substrate, wherein the two-stage active trench structure comprises a lower insulating film provided at the bottom of a trench that penetrates the base layer and the carrier storage layer from the first main surface to the drift layer, a lower electrode provided on the lower insulating film and electrically connected to the gate electrode, an upper insulating film provided at the top of the trench, and a layer provided on the upper insulating film that is electrically connected to the gate electrode and insulated from the lower electrode within the trench The lower electrode includes an upper electrode, wherein the thickness of the lower insulating film in contact with the side of the lower electrode is greater than the thickness of the upper insulating film in contact with the side of the upper electrode, and at least one of the following conditions is met: (a) the length of the portion of the upper electrode that protrudes below the base layer is less than the vertical length of the lower electrode; (b) the vertical length of the upper electrode is less than the vertical length of the lower electrode; and (c) the cross-sectional area of ​​the upper electrode in the cell region is less than the cross-sectional area of ​​the lower electrode in the cell region; the lower end of the upper electrode is located below the lower end of the base layer and above the position where the cumulative value of the impurity concentration in the carrier accumulation layer in the vertical direction is halved. [Effects of the Invention]

[0007] According to this disclosure, at least one of conditions (a), (b), and (c) is satisfied, and the lower end of the upper electrode is located above the position where the cumulative value of the impurity concentration in the carrier storage layer in the vertical direction is halved. With such a configuration, it is possible to reduce the gate charge while suppressing the reduction of the saturation current. [Brief explanation of the drawing]

[0008] [Figure 1] This is a top view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view showing the configuration of a semiconductor device according to Modification Example 1. [Figure 7] This is a cross-sectional view showing the configuration of a semiconductor device according to a modified example 2. [Figure 8] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 4. [Figure 9] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 4. [Figure 10] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 4. [Figure 11] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 12] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4. [Figure 13] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 5. [Figure 14] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 6. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each embodiment below are illustrative, and not all features are necessarily required. In addition, in the following description, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components will be described primarily. Also, in the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the positions and directions in actual implementation. Furthermore, a higher concentration in one part than in another part may mean, for example, that the average concentration of one part is higher than the average concentration of the other part. Conversely, a lower concentration in one part than in another part may mean, for example, that the average concentration of one part is lower than the average concentration of the other part. Furthermore, although the following description assumes that the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0010] <Embodiment 1> Figure 1 is a top view showing the configuration of a semiconductor substrate provided in the semiconductor device according to this embodiment 1. In the semiconductor substrate of Figure 1, a cell region 19 on which semiconductor elements are provided, a terminal region 20 surrounding the cell region 19, and an outer peripheral region 21 surrounding the terminal region 20 are defined.

[0011] The semiconductor substrate may be composed of a conventional semiconductor wafer or an epitaxial growth layer. Furthermore, the semiconductor substrate may be composed of conventional silicon (Si), or of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond. When the semiconductor substrate is composed of a wide-bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages, and faster switching speeds are possible.

[0012] Figs. 2 to 5 are cross-sectional views showing the configuration of the semiconductor device according to Embodiment 1, specifically, cross-sectional views showing the configuration of the cell region 19 provided with semiconductor elements. Hereinafter, a configuration in which the semiconductor element is an IGBT (Insulated Gate Bipolar Transistor) will be described as an example, but the present invention is not limited thereto. The semiconductor element may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an RC-IGBT (Reverse Conducting - IGBT) having an IGBT region provided with an IGBT and a diode region provided with an SBD (Schottky Barrier Diode) and a PND (PN junction diode), etc.

[0013] As shown in Fig. 2, the semiconductor substrate includes an n - -type drift layer 9, an n-type carrier accumulation layer 15, a p-type base layer 14, an n + -type source layer 2, an n-type buffer layer 10, and a p-type collector layer 11. The semiconductor substrate has a first main surface corresponding to the upper end of the source layer 2 and a second main surface corresponding to the lower end of the collector layer 11.

[0014] [[ID=II]] Next, each layer of the semiconductor substrate will be described. On the first main surface side of the drift layer 9, a carrier accumulation layer 15 having an n-type impurity concentration higher than that of the drift layer 9 is provided. On the first main surface side of the carrier accumulation layer 15, a base layer 14 is provided. On the first main surface side of the base layer 14, a source layer 2 having an n-type impurity concentration higher than that of the carrier accumulation layer 15 is provided.

[0015] Thus, in the semiconductor substrate according to Embodiment 1, the drift layer 9, the carrier accumulation layer 15, the base layer 14, and the source layer 2 are provided in this order toward the first main surface. On the other hand, in the semiconductor substrate, the drift layer 9, the buffer layer 10, and the collector layer 11 are provided in this order toward the second main surface. Each layer of the semiconductor substrate is selectively formed, for example, by mask formation and ion implantation.

[0016] The semiconductor device comprises not only a semiconductor substrate, but also a two-stage active trench structure 17, an interlayer insulating film 13, an emitter electrode 1, and a collector electrode 12.

[0017] The two-stage active trench structure 17 includes a lower insulating film 7, a lower electrode 6, a boundary insulating film 5, an upper insulating film 4, and an upper electrode 3, and is provided on the first main surface side of the semiconductor substrate.

[0018] The lower insulating film 7 is located below a trench 8 that penetrates the source layer 2, base layer 14, and carrier storage layer 15 from the first main surface of the semiconductor substrate to the drift layer 9. The lower electrode 6 is located on the lower insulating film 7 and is electrically connected to the gate electrode 16 as shown in Figure 3. Although not shown, the gate electrode 16 is located on the semiconductor substrate, similar to the emitter electrode 1, and corresponds to a gate pad to which an external gate potential is applied.

[0019] The boundary insulating film 5 in Figure 2 is provided above the lower electrode 6. The upper insulating film 4 is provided above the trench 8. The lower insulating film 7, boundary insulating film 5, and upper insulating film 4 are formed by, for example, thermal oxidation and CVD (Chemical Vapor Deposition). The upper electrode 3 is provided on the upper insulating film 4 and is insulated from the lower electrode 6 by the boundary insulating film 5 within the trench 8. The lower end of the upper electrode 3 is located below the lower end of the base layer 14. Also, as shown in Figure 3, the upper electrode 3 is electrically connected to the gate electrode 16.

[0020] The interlayer insulating film 13 in Figure 2 is provided on the upper electrode 3. The emitter electrode 1 is provided so as to cover the source layer 2 and the interlayer insulating film 13, is electrically connected to the source layer 2, and is insulated from the upper electrode 3 by the interlayer insulating film 13. The collector electrode 12 is provided so as to cover the collector layer 11 and is electrically connected to the collector layer 11.

[0021] As shown in Figure 4, the thickness (Lb) of the lower insulating film 7 in contact with the side of the lower electrode 6 is greater than the thickness (La) of the upper insulating film 4 in contact with the side of the upper electrode 3. Furthermore, condition (a) is satisfied, which states that the length (T2) of the portion of the upper electrode 3 that protrudes below the base layer 14 is smaller than the vertical length (T1) of the lower electrode 6.

[0022] Here, the gate charge (Qg) is proportional to the surface area of ​​the insulating film and inversely proportional to its thickness. Therefore, with the semiconductor device according to this embodiment 1 configured as described above, the sum of the lengths (T1) and (T2) is the same as in this embodiment 1, and the gate charge (Qg) can be reduced compared to a configuration where the length (T2) is greater than the length (T1). On the other hand, in a semiconductor device with a thicker lower insulating film 7 (Lb), the carrier concentration is reduced in the n-type storage layer such as the carrier storage layer 15 on the side wall of the trench 8, so the carriers at the interface of the trench 8 decrease, and the saturation current (Isat) decreases.

[0023] As shown in Figure 5, in this embodiment 1, the lower end of the upper electrode 3 is positioned above the position (CS1) where the cumulative value of the impurity concentration in the carrier storage layer 15 in the vertical direction is halved. Generally, in a two-stage active trench structure 17, the electric field becomes higher at the boundary between the thin upper insulating film 4 and the thick lower insulating film 7. In this embodiment 1, since the lower end of the upper electrode 3 is positioned above the position (CS1), the boundary where the electric field becomes higher is located near the base layer 14. Therefore, the electric field in the mesa region (i.e., the portion between adjacent trenches 8) near the channel (i.e., near the base layer 14) can be increased, and the field-plate effect of the trench 8 can be weakened.

[0024] The current I injected from the channel is expressed as I = qnμE and is roughly proportional to the electric field E near the channel. Therefore, as the electric field near the channel increases, the drift current increases, so the semiconductor device according to this embodiment 1 can suppress the reduction of the saturation current (Isat) caused by increasing the thickness (Lb) of the lower insulating film 7.

[0025] Furthermore, it is preferable that the thickness of the lower insulating film 7, which contacts the bottom of the lower electrode 6 rather than its side, is greater than the thickness (La) of the upper insulating film 4, which contacts the side of the upper electrode 3. With this configuration, the electric field is less likely to concentrate at the bottom of the two-stage active trench structure 17, and the electric field in the mesa region near the channel can be increased accordingly. As a result, the reduction in saturation current (Isat) caused by increasing the thickness (Lb) of the lower insulating film 7 can be further suppressed.

[0026] <Summary of Embodiment 1> In the semiconductor device according to this embodiment 1 described above, the thickness (Lb) of the lower insulating film 7 in contact with the side of the lower electrode 6 is greater than the thickness (La) of the upper insulating film 4 in contact with the side of the upper electrode 3, the length (T2) of the portion of the upper electrode 3 that protrudes below the base layer 14 is smaller than the vertical length (T1) of the lower electrode 6, and the lower end of the upper electrode 3 is located above the position (CS1) where the integrated value of the impurity concentration in the carrier storage layer 15 in the vertical direction is halved. With this configuration, it is possible to reduce the gate charge amount (Qg) while suppressing the reduction of the saturation current (Isat).

[0027] <Example 1> Figure 6 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1. In Embodiment 1, condition (a) was satisfied, where the length (T2) of the portion of the upper electrode 3 that protrudes below the base layer 14 is smaller than the vertical length (T1) of the lower electrode 6. In this Modification 1, instead of condition (a), condition (b) is satisfied, as shown in Figure 6, where the vertical length (T3) of the upper electrode 3 is smaller than the vertical length (T1) of the lower electrode 6.

[0028] As described above, the gate charge (Qg) is proportional to the surface area of ​​the insulating film and inversely proportional to its thickness. Therefore, with the semiconductor device according to this modified example 1, the sum of lengths (T1) and (T3) is the same as in this modified example 1, and the gate charge (Qg) can be reduced compared to a configuration where length (T3) is greater than length (T1). Since the other configurations of modified example 1 are the same as those of embodiment 1, the configuration of this modified example 1 makes it possible to reduce the gate charge (Qg) while suppressing the reduction of the saturation current (Isat).

[0029] <Modification 2> Figure 7 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 2. In this Modification 2, instead of conditions (a) and (b), condition (c) is met, as shown in Figure 7, where the cross-sectional area (S2) of the upper electrode 3 in the cell region 19 is smaller than the cross-sectional area (S1) of the lower electrode 6 in the cell region 19.

[0030] As described above, the gate charge (Qg) is proportional to the surface area of ​​the insulating film and inversely proportional to its thickness. Therefore, with the semiconductor device according to this modified example 2, the sum of the cross-sectional areas (S1) and (S2) is the same as in this modified example 2, and the gate charge (Qg) can be reduced compared to a configuration where the cross-sectional area (S2) is larger than the cross-sectional area (S1). Since the other configurations of modified example 2 are the same as those of embodiment 1, the configuration of this modified example 2 makes it possible to reduce the gate charge (Qg) while suppressing the reduction of the saturation current (Isat).

[0031] In summary, it is sufficient that at least one of the conditions (a) of Embodiment 1, (b) of Modification 1, and (c) of Modification 2 is satisfied. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations obtained by selecting one or more from the groups A, B, C, ..., and Z.

[0032] <Variation 3> In Figure 5, the peak position of the impurity concentration in the carrier storage layer 15 (CS2) is located above the position (CS1) where the cumulative value of the impurity concentration in the carrier storage layer 15 in the vertical direction is halved. In such a case, the lower end of the upper electrode 3 may be located above the peak position (CS2). With this configuration, the electric field of the mesa region near the channel can be further increased, and the drift current can be further increased, thereby further suppressing the reduction of the saturation current (Isat).

[0033] In Figure 5, the vertical center position (CS3) of the carrier storage layer 15 is located below the position (CS1) where the vertically integrated value of the impurity concentration in the carrier storage layer 15 is halved. However, depending on the distribution of impurity concentration, the center position (CS3) may be located above position (CS1). In such cases, the lower end of the upper electrode 3 may be located above the center position (CS3). With this configuration, the electric field of the mesa region near the channel can be further increased, and the drift current can be further increased, thereby further suppressing the reduction of the saturation current (Isat).

[0034] <Modification 4> Figures 8 to 10 are cross-sectional views showing the configuration of a semiconductor device according to Modification 4. As shown in Figure 8, the bottom of the upper electrode 3 may have a recessed portion in the center. Also, as shown in Figure 9, the upper part of the lower electrode 6 may have a protruding portion in the center. Furthermore, as shown in Figure 10, in the configuration of Figure 9, the upper end of the lower electrode 6 may be located above the lower end of the upper electrode 3.

[0035] In the following embodiments 2 and beyond, configurations are described that are appropriately modified versions of the configuration of embodiment 1, but modifications from embodiment 2 onwards may also be made in modified examples 1 to 4.

[0036] <Embodiment 2> Figure 11 is a cross-sectional view showing the configuration of a semiconductor device according to this second embodiment. As shown in Figure 11, in this second embodiment, not only a two-stage active trench structure 17 but also a dummy active trench structure 18 is provided on the first main surface side of the semiconductor substrate. The dummy active trench structure 18 is a structure corresponding to the two-stage active trench structure 17, that is, a structure similar to the two-stage active trench structure 17. However, in the dummy active trench structure 18, the upper electrode 3 is electrically connected to the emitter electrode 1 instead of the gate electrode 16.

[0037] In the upper part of the dummy active trench structure 18 configured in this way, virtually no capacitance is generated. Therefore, according to the semiconductor device of this second embodiment, the gate charge amount (Qg) can be further reduced.

[0038] <Embodiment 3> In this third embodiment, at least one of the above-mentioned conditions (a) to (c) and the following equation (1) are satisfied.

[0039] A × Cgc1 > (A + D) × Cgc2 ... (1) A is the number of two-stage active trench structures 17 in a cross-sectional view, and D is the number of dummy active trench structures 18 in a cross-sectional view. Cgc1 is the capacitance per unit length of the upper insulating film 4 that is in contact with the side of the portion of the upper electrode 3 that protrudes below the base layer 14, and Cgc2 is the capacitance per unit length of the lower insulating film 7 that is in contact with the side of the lower electrode 6. By rearranging equation (1), we obtain the following equation (2).

[0040] Y<100×(1-1 / (Lb / La)) ···(2) Y[%] is the ratio of the number of dummy active trench structures 18 to the number of two-stage active trench structures 17 and dummy active trench structures 18 in a cross-sectional view, i.e., the thinning rate, and is expressed as Y = 100 × D / (A + D). For example, if A = 1 and A + D = N, it is expressed as Y = 100 × (N - 1) / N. Similar to Embodiment 1, La is the thickness of the upper insulating film 4 in contact with the side of the upper electrode 3, and Lb is the thickness of the lower insulating film 7 in contact with the side of the lower electrode 6.

[0041] In this third embodiment, at least one of the above-mentioned conditions (a) to (c) and equation (2) (i.e., equation (1)) are satisfied, so the capacitance (Cgc) of the semiconductor device can be reduced, and as a result the gate charge amount (Qg) can be reduced.

[0042] <Embodiment 4> Figure 12 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 4. As shown in Figure 12, in this embodiment 4, the trench 8 has a tapered shape that narrows as it extends downward.

[0043] Furthermore, the taper angle of the side wall of the tapered portion of the trench 8 with respect to the horizontal direction is preferably 89 degrees or less, more preferably 87 degrees or less, and more preferably 85 degrees or less. Also, the depth of the trench 8 is preferably 3 μm or more, more preferably 4 μm or more, and more preferably 5 μm or more.

[0044] According to the semiconductor device of this embodiment 4, the cross-sectional area of ​​the lower insulating film 7 can be reduced, thereby further reducing the gate charge amount (Qg).

[0045] <Embodiment 5> Figure 13 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 5. As shown in Figure 13, in this embodiment 5, not only a two-stage active trench structure 17 but also a recessed active trench structure 23 is provided on the first main surface side of the semiconductor substrate. The recessed active trench structure 23 is a structure corresponding to the two-stage active trench structure 17, that is, a structure similar to the two-stage active trench structure 17. However, the recessed active trench structure 23 includes an insulating member 22, which is an insulating member, instead of the upper electrode 3.

[0046] The insulating member 22 may be made of the same material as the upper insulating film 4, or the same material as the interlayer insulating film 13. Using the same materials in the same configuration simplifies the manufacturing process and reduces manufacturing costs.

[0047] Furthermore, the insulating member 22 may be a thermal oxide film formed by thermal oxidation, or a CVD film formed by CVD. Since thermal oxide films have superior electrical properties compared to CVD films, gate characteristics can be improved when the insulating member 22 is a thermal oxide film. On the other hand, CVD films generally have a higher impurity concentration than thermal oxide films and can be manufactured at a lower cost. Alternatively, for example, the upper insulating film 4 or the lower insulating film 7 may be a thermal oxide film with superior electrical properties, and the insulating member 22 may be a CVD film. The impurity concentration of the insulating member 22 may be higher than the impurity concentration of the upper insulating film 4 or the lower insulating film 7.

[0048] In the dummy active trench structure 18 shown in Figure 11, described in Embodiment 2, capacitance (Cge) is generated between the lower electrode 6 connected to the gate electrode 16 and the upper electrode 3 connected to the emitter electrode 1, which causes an increase in the gate charge amount (Qg). In contrast, the recessed active trench structure 23 according to Embodiment 5 can reduce capacitance (Cge), thereby further reducing the gate charge amount (Qg).

[0049] <Embodiment 6> Figure 14 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 6. As shown in Figure 14, in this embodiment 6, the upper insulating film 4 in contact with the side of the upper electrode 3 includes a first portion in contact with the base layer 14 and a second portion not in contact with the base layer 14. The thickness (Lc) of the second portion is greater than the thickness (La) of the first portion. With this configuration, the capacitance of the second portion of the upper insulating film 4 can be reduced, and thus the gate charge amount (Qg) can be further reduced.

[0050] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0051] Furthermore, it is possible to freely combine each embodiment (and each modified example), and to modify or omit each embodiment and each modified example as appropriate.

[0052] The various aspects of this disclosure are summarized below as an appendix.

[0053] (Note 1) A semiconductor substrate having a first main surface, wherein a first conductivity type drift layer toward the first main surface, a first conductivity type carrier storage layer with a higher impurity concentration than the drift layer, and a second conductivity type base layer are provided in this order, A two-stage active trench structure provided on the first main surface side of the semiconductor substrate and Equipped with, The aforementioned two-stage active trench structure is A lower insulating film is provided at the bottom of a trench that penetrates the base layer and the carrier accumulation layer from the first main surface to reach the drift layer, A lower electrode is provided on the lower insulating film and is electrically connected to the gate electrode, An upper insulating film is provided at the top of the trench, The upper electrode is provided on the upper insulating film, electrically connected to the gate electrode, and insulated from the lower electrode within the trench. Includes, The thickness of the lower insulating film in contact with the side of the lower electrode is greater than the thickness of the upper insulating film in contact with the side of the upper electrode. The condition is met if at least one of the following conditions is satisfied: (a) the length of the portion of the upper electrode that protrudes below the base layer is smaller than the vertical length of the lower electrode; (b) the vertical length of the upper electrode is smaller than the vertical length of the lower electrode; and (c) the cross-sectional area of ​​the upper electrode in the cell region is smaller than the cross-sectional area of ​​the lower electrode in the cell region. A semiconductor device in which the lower end of the upper electrode is located below the lower end of the base layer and above the position where the cumulative value of the impurity concentration in the carrier storage layer in the vertical direction is halved.

[0054] (Note 2) The semiconductor device described in Appendix 1, A semiconductor device in which the lower end of the upper electrode is located above the position of the peak of the impurity concentration in the carrier accumulation layer.

[0055] (Note 3) The semiconductor device described in Appendix 1, A semiconductor device in which the lower end of the upper electrode is located above the vertical center position of the carrier storage layer.

[0056] (Note 4) A semiconductor device described in any one of the items 1 to 3 of the appendix, A semiconductor device comprising a structure corresponding to the two-stage active trench structure, wherein the upper electrode further comprises a dummy active trench structure in which the upper electrode is electrically connected to the emitter electrode instead of the gate electrode.

[0057] (Note 5) A semiconductor device described in any one of the items from Appendix 1 to Appendix 4, The trench has a tapered shape that narrows as it extends downwards, in a semiconductor device.

[0058] (Note 6) The semiconductor device described in Appendix 4, A semiconductor device in which, when the decimation rate is Y[%], which is the ratio of the number of dummy active trench structures to the number of the two-stage active trench structures and the dummy active trench structures in a cross-sectional view, and when the thickness of the upper insulating film is La and the thickness of the upper insulating film is Lb, the condition Y < 100 × (1 - 1 / (Lb / La)) is satisfied.

[0059] (Note 7) A semiconductor device described in any one of the items from Appendix 1 to Appendix 6, A semiconductor device comprising a structure corresponding to the aforementioned two-stage active trench structure, further comprising a recessed active trench structure that includes an insulating member instead of the upper electrode.

[0060] (Note 8) A semiconductor device described in any one of the items from Appendix 1 to Appendix 7, The upper insulating film that is in contact with the side portion of the upper electrode is The first portion in contact with the base layer, The second portion is not in contact with the base layer and is thicker than the first portion. Semiconductor equipment, including [Explanation of symbols]

[0061] 1 Emitter electrode, 3 Upper electrode, 4 Upper insulating film, 6 Lower electrode, 7 Lower insulating film, 8 Trench, 9 Drift layer, 14 Base layer, 15 Carrier storage layer, 16 Gate electrode, 17 Two-stage active trench structure, 18 Dummy active trench structure, 19 Cell region, 22 Insulating member, 23 Recessed active trench structure.

Claims

1. A semiconductor substrate having a first main surface, wherein a first conductivity type drift layer toward the first main surface, a first conductivity type carrier storage layer with a higher impurity concentration than the drift layer, and a second conductivity type base layer are provided in this order, A two-stage active trench structure provided on the first main surface side of the semiconductor substrate and Equipped with, The aforementioned two-stage active trench structure is A lower insulating film is provided at the bottom of a trench that penetrates the base layer and the carrier accumulation layer from the first main surface to reach the drift layer, A lower electrode is provided on the lower insulating film and is electrically connected to the gate electrode, An upper insulating film is provided at the top of the trench, The upper electrode is provided on the upper insulating film, electrically connected to the gate electrode, and insulated from the lower electrode within the trench. Includes, The thickness of the lower insulating film in contact with the side of the lower electrode is greater than the thickness of the upper insulating film in contact with the side of the upper electrode. The condition is met if at least one of the following conditions is satisfied: (a) the length of the portion of the upper electrode that protrudes below the base layer is smaller than the vertical length of the lower electrode; (b) the vertical length of the upper electrode is smaller than the vertical length of the lower electrode; and (c) the cross-sectional area of ​​the upper electrode in the cell region is smaller than the cross-sectional area of ​​the lower electrode in the cell region. A semiconductor device in which the lower end of the upper electrode is located below the lower end of the base layer and above the position where the cumulative value of the impurity concentration in the carrier storage layer in the vertical direction is halved.

2. A semiconductor device according to claim 1, A semiconductor device in which the lower end of the upper electrode is located above the position of the peak of the impurity concentration in the carrier accumulation layer.

3. A semiconductor device according to claim 1, A semiconductor device in which the lower end of the upper electrode is located above the vertical center position of the carrier storage layer.

4. A semiconductor device according to any one of claims 1 to 3, A semiconductor device comprising a structure corresponding to the two-stage active trench structure, wherein the upper electrode is electrically connected to the emitter electrode instead of the gate electrode, and further comprising a dummy active trench structure.

5. A semiconductor device according to any one of claims 1 to 3, The trench has a tapered shape that narrows as it extends downwards, in a semiconductor device.

6. A semiconductor device according to claim 4, A semiconductor device in which, when the decimation rate is Y [%], which is the ratio of the number of dummy active trench structures to the number of the two-stage active trench structures and the dummy active trench structures in a cross-sectional view, and when the thickness of the upper insulating film is La and the thickness of the upper insulating film is Lb, the condition Y < 100 × (1 - 1 / (Lb / La)) is satisfied.

7. A semiconductor device according to any one of claims 1 to 3, A semiconductor device comprising a structure corresponding to the two-stage active trench structure, further comprising a recessed active trench structure including an insulating member instead of the upper electrode.

8. A semiconductor device according to any one of claims 1 to 3, The upper insulating film that is in contact with the side portion of the upper electrode is The first portion in contact with the base layer, The second portion is not in contact with the base layer and is thicker than the first portion. Semiconductor equipment, including

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