Semiconductor equipment

Abstract

This disclosure aims to provide a semiconductor device that can reduce switching losses by suppressing an increase in gate voltage. [Solution] The semiconductor device according to the present disclosure comprises a semiconductor substrate and a two-stage dummy active trench provided on the surface side of the semiconductor substrate, having a first upper electrode connected to an emitter electrode and covered with a first upper insulating film in the upper stage, a first lower electrode connected to a gate electrode and covered with a first lower insulating film in the lower stage, and a first boundary insulating film located between the first upper electrode and the first lower electrode, wherein the thickness of the first boundary insulating film is greater than the thickness of the first upper insulating film and the thickness of the first lower insulating film, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal.

Background Art

[0002] In the turn-on operation of an IGBT (Insulated Gate Bipolar Transistor), the recovery voltage time change (dV / dt) of the diode at low current increases. High dV / dt causes noise in the product or breakdown of the motor insulation. To reduce dV / dt, a measure of increasing the gate resistance can be considered, but increasing the gate resistance causes a new problem of increased turn-on loss.

[0003] In order to solve the above problems, it is effective to increase the gate capacitance ratio (Cgc / Cge). Inside the trench, a semiconductor device having a two-stage dummy active trench having an upper electrode connected to the emitter electrode in the upper stage and a lower electrode connected to the gate electrode in the lower stage can increase the gate-collector capacitance (Cgc) while maintaining a low gate-emitter capacitance (Cge). Therefore, the gate capacitance ratio can be improved and the switching loss can be reduced (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, depending on the driving conditions or structure of the semiconductor device, displacement currents caused by potential fluctuations due to changes in hole density around the trench can flow into the lower electrode, which is at the gate potential. This increases the gate voltage and thus increases dV / dt, which may prevent sufficient reduction of switching losses.

[0006] This disclosure is made to solve such problems and aims to provide a semiconductor device that can suppress the increase in gate voltage and reduce switching losses. [Means for solving the problem]

[0007] To solve the above problems, the semiconductor device according to this disclosure comprises a semiconductor substrate and a two-stage dummy active trench provided on the surface side of the semiconductor substrate, having a first upper electrode connected to an emitter electrode and covered with a first upper insulating film in the upper stage, a first lower electrode connected to a gate electrode and covered with a first lower insulating film in the lower stage, and a first boundary insulating film located between the first upper electrode and the first lower electrode, wherein the thickness of the first boundary insulating film is greater than the thickness of the first upper insulating film and the thickness of the first lower insulating film, respectively. [Effects of the Invention]

[0008] According to this disclosure, it is possible to suppress the increase in gate voltage and reduce switching losses. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of a semiconductor device according to a modified example 1 of Embodiment 1. [Figure 3] This is a cross-sectional view of a semiconductor device according to a modified example 2 of Embodiment 1. [Figure 4] This is a cross-sectional view of a semiconductor device according to a modified example 3 of Embodiment 1. [Figure 5] This is a cross-sectional view of a semiconductor device according to a modified example 4 of Embodiment 1. [Figure 6] Cross-sectional view of a semiconductor device according to Modification Example 4 of Embodiment 1. [Figure 7] Cross-sectional view of a semiconductor device according to Modification Example 5 of Embodiment 1. [Figure 8] Cross-sectional view of a semiconductor device according to Modification Example 6 of Embodiment 1. [Figure 9] Cross-sectional view of a semiconductor device according to Modification Example 7 of Embodiment 1. [Figure 10] Cross-sectional view of a semiconductor device according to Modification Example 8 of Embodiment 1. [Figure 11] Cross-sectional view of a semiconductor device according to Modification Example 9 of Embodiment 1. [Figure 12] Cross-sectional view of a semiconductor device according to Modification Example 10 of Embodiment 1. [Figure 13] Cross-sectional view of a semiconductor device according to Modification Example 10 of Embodiment 1. [Figure 14] Cross-sectional view of a semiconductor device according to Modification Example 11 of Embodiment 1. [Figure 15] Cross-sectional view of a semiconductor device according to Modification Example 12 of Embodiment 1. [Figure 16] Cross-sectional view of a semiconductor device according to Modification Example 12 of Embodiment 1. [Figure 17] Cross-sectional view of a semiconductor device according to Modification Example 13 of Embodiment 1. [Figure 18] Cross-sectional view of a semiconductor device according to Modification Example 14 of Embodiment 1.

Mode for Carrying Out the Invention

[0010] <Embodiment 1> Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. The semiconductor device is an IGBT. Note that the same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted. In the following description, N and P indicate the conductivity types of semiconductors. These conductivity types may be reversed.

[0011] FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1. In FIG. 1, the semiconductor substrate ranges from the base layer 3 to the collector layer 6. In FIG. 1, the upper end of the base layer 3 is referred to as the surface of the semiconductor substrate, and the lower end of the collector layer 6 is referred to as the back surface of the semiconductor substrate. The front and back surfaces face each other.

[0012] As shown in FIG. 1, a P-type base layer 3 is provided on the surface side of the N-type drift layer 4.

[0013] The semiconductor substrate is provided with a two-stage dummy active trench 8 that penetrates the base layer 3 and reaches the drift layer 4. The two-stage dummy active trench 8 has a first upper electrode 9 connected to the emitter electrode 1 in the upper stage and a first lower electrode 10 connected to a gate electrode (not shown) in the lower stage inside a trench provided on the surface side of the semiconductor substrate.

[0014] Further, the two-stage dummy active trench 8 has a first upper insulating film 11 provided to cover the side wall of the first upper electrode 9, a first lower insulating film 12 provided to cover the side wall of the first lower electrode 10, and a first boundary insulating film 13 provided between the first upper electrode 9 and the first lower electrode 10. The first upper electrode 9 and the first lower electrode 10 are electrically separated via the first boundary insulating film 13. The film thickness T1 of the first boundary insulating film 13 is thicker than the film thicknesses T3 of the first upper insulating film 11 and T2 of the first lower insulating film 12, respectively. Note that since the film thickness T1 varies in the lateral direction (the width direction of the two-stage dummy active trench 8), the film thickness T1 in the present disclosure is the film thickness at the center in the lateral direction of the first boundary insulating film 13.

[0015] An interlayer insulating film 2 is provided on the two-stage dummy active trench 8. An emitter electrode 1 is provided on the base layer 3 and the interlayer insulating film 2.

[0016] On the back side of the drift layer 4, there is an N-type buffer layer 5 with a higher N-type impurity concentration than the drift layer 4. On the back side of the buffer layer 5, there is a P-type collector layer 6. On the back side of the collector layer 6, there is a collector electrode 7.

[0017] The effect of displacement current is proportional to the length (depth) of the first lower electrode 10, which is the path through which the displacement current enters. Specifically, the longer the length of the first lower electrode 10, the easier it is for the displacement current to flow into the first lower electrode 10. On the other hand, the gate capacitance is inversely proportional to the thickness of the insulating film. Specifically, the thicker the insulating film, the smaller the gate capacitance. The gate-emitter capacitance (Cge) depends on the thickness of the first boundary insulating film 13, and the gate-collector capacitance (Cgc), which affects dV / dt, depends on the thickness of the first lower insulating film 12.

[0018] According to Embodiment 1, since the thickness of the first boundary insulating film 13 is greater than the thickness of the first lower insulating film 12, the gate capacitance ratio (Cgc / Cge) can be increased, and the first lower electrode 10, which is the gate potential into which the displacement current flows, can be reduced. Therefore, it is possible to suppress the increase in gate voltage and reduce switching losses.

[0019] The influence of displacement current generated by potential fluctuations caused by holes is particularly large in IGBTs, which are bipolar devices that use holes as carriers. According to Embodiment 1, a synergistic effect can be obtained between the IGBT and the above configuration, resulting in a greater reduction in displacement current.

[0020] <Example 1> Figure 2 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. As shown in Figure 2, in the semiconductor device according to Modification 1, the film thickness T2 of the first lower insulating film 12 is thicker than the film thickness T3 of the first upper insulating film 11.

[0021] The displacement current is inversely proportional to the thickness of the first lower insulating film 12, which is the entry path for the displacement current. Specifically, the thicker the first lower insulating film 12, the smaller the displacement current. According to Modification 1, the thickness T2 of the first lower insulating film 12 is thicker than the thickness T3 of the first upper insulating film 11, so the displacement current can be reduced and the increase in gate voltage can be suppressed.

[0022] Furthermore, the gate-emitter capacitance (Cge) is proportional to the area where the first upper electrode 9 and the first lower electrode 10 face each other. Specifically, the larger the facing area, the larger the gate-emitter capacitance (Cge). Here, the facing area refers to the area where the lower end (back surface) of the first upper electrode 9 and the upper end (front surface) of the first lower electrode 10 face each other. According to Modification 1, since the film thickness T2 of the first lower insulating film 12 is thicker than the film thickness T3 of the first upper insulating film 11, the area where the first upper electrode 9 and the first lower electrode 10 face each other becomes smaller, and the gate-emitter capacitance (Cge) can be reduced. Therefore, switching losses can be reduced while maintaining a high gate capacitance ratio (Cgc / Cge).

[0023] <Modification 2> In the semiconductor device according to Modification 2, the film thickness T1 of the first boundary insulating film 13 is 1.5 times or more the film thickness T3 of the first upper insulating film 11 and the film thickness T2 of the first lower insulating film 12. The semiconductor device according to Modification 2 is the same as the semiconductor device according to Embodiment 1 (see Figure 1).

[0024] The thickness of the insulating film varies due to the influence of the insulating film formation process. In particular, the thickness T1 of the first boundary insulating film 13 is affected by the shape of the underlying first lower electrode 10 and the shape of the upper first electrode 9, resulting in significant variation, and may be locally thinner than the thickness T2 of the first lower insulating film 12 and the thickness T3 of the first upper insulating film 11. In order to satisfy the relationship "T1 > T2 and T1 > T3" even with such variations, the thickness T1 of the first boundary insulating film 13 must be at least 1.5 times the thickness T3 of the first upper insulating film 11 and the thickness T2 of the first lower insulating film 12. By adopting such a configuration, it is possible to suppress the increase in gate voltage and reduce switching losses while maintaining a high gate capacitance ratio (Cgc / Cge).

[0025] Based on the inventors' findings, the thickness T1 of the first boundary insulating film 13 may be reduced by 30% due to the influence of the shape of the underlying first lower electrode 10 and the shape of the upper first upper electrode 9. If the thickness T1 of the first boundary insulating film 13 is 1.5 times or more the thickness T3 of the first upper insulating film 11 and the thickness T2 of the first lower insulating film 12, then even if the thickness T1 is reduced by 30% due to variation, the thickness T1 will be 1.05 times that of the thicknesses T2 and T3, satisfying the relationship "T1 > T2 and T1 > T3". Therefore, it is possible to suppress the increase in gate voltage and reduce switching losses while maintaining a high gate capacitance ratio (Cgc / Cge).

[0026] Furthermore, preferably, the film thickness T1 of the first boundary insulating film 13 may be at least twice the film thickness T3 of the first upper insulating film 11 and the film thickness T2 of the first lower insulating film 12. By using such film thicknesses, even if the film thickness T1 is reduced by 30% due to variations, the film thickness T1 will be 1.4 times that of the film thicknesses T2 and T3. Therefore, compared to the case where the film thicknesses are equivalent, the gate capacitance ratio (Cgc / Cge) can be increased, thereby suppressing the increase in gate voltage and further reducing switching losses.

[0027] Furthermore, as shown in Figure 3, even if the first upper electrode 9 has a configuration in which pointed portions 14 protrude to the back side on the left and right sides of its lower end, the thickness T1 of the first boundary insulating film 13 can be maintained, thereby suppressing the increase in gate voltage and reducing switching losses while maintaining a high gate capacitance ratio (Cgc / Cge).

[0028] <Variation 3> Figure 4 is a cross-sectional view of a semiconductor device according to a modification 3 of Embodiment 1. As shown in Figure 4, the semiconductor device according to modification 3 further comprises an N-type source layer 15 provided on the surface side of the base layer 3, and a two-stage active trench 16 that penetrates the source layer 15 and the base layer 3 and reaches the drift layer 4.

[0029] The two-stage active trench 16 has a second upper electrode 17 connected to the gate electrode in the upper stage, and a second lower electrode 18 connected to the gate electrode in the lower stage, inside the trench provided on the surface side of the semiconductor substrate.

[0030] Furthermore, the two-stage active trench 16 includes a second upper insulating film 19 provided to cover the side wall of the second upper electrode 17, a second lower insulating film 20 provided to cover the side wall of the second lower electrode 18, and a second boundary insulating film 21 provided between the second upper electrode 17 and the second lower electrode 18. The second upper electrode 17 and the second lower electrode 18 are electrically isolated via the second boundary insulating film 21.

[0031] According to Modification 3, by providing a two-stage active trench 16 having a second upper electrode 17 which is the gate potential, and a source layer 15, a channel can be formed in the base layer 3, making it possible to turn on the semiconductor device.

[0032] In particular, the second upper electrode 17 and the second lower electrode 18 are affected by the displacement current because they are at the gate potential. Therefore, the displacement current can be effectively reduced by increasing the thickness of the second boundary insulating film 21.

[0033] <Modification 4> Figure 5 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 1. As shown in Figure 5, the semiconductor device according to Modification 4 further comprises a carrier storage layer 22. The carrier storage layer 22 is provided on the back side of the base layer 3 (the front side of the drift layer 4).

[0034] According to Modification 4, the inclusion of a carrier storage layer 22 increases the amount of holes stored, thus increasing the displacement current. In this configuration, a synergistic effect can be obtained from the effect of the carrier storage layer 22 and the effect of Embodiment 1, and in particular, the effect of reducing the displacement current is greatly increased.

[0035] Preferably, the first boundary insulating film 13 and the carrier storage layer 22 may be positioned adjacent to each other in the lateral direction. This allows the first boundary insulating film 13 to reduce the effect of displacement current due to the high density of holes in the carrier storage layer 22.

[0036] More preferably, the entire region of the first boundary insulating film 13 and the carrier storage layer 22 may be positioned adjacent to each other in the lateral direction. This can further reduce the displacement current.

[0037] More preferably, as shown in Figure 6, the first boundary insulating film 13 and the concentration peak of the carrier storage layer 22 may be positioned adjacent to each other in the lateral direction. This makes it possible to reduce the influence of displacement current on the concentration peak portion that is susceptible to the influence of displacement current due to the high density of holes in the carrier storage layer 22 by increasing the thickness of the first boundary insulating film 13.

[0038] As shown in Figure 6, the concentration peak of the carrier storage layer 22 may be located on the surface side of the center (center in the depth direction) of the carrier storage layer 22. By adopting this positional relationship, the high-concentration portion of the carrier storage layer 22, where the electric field tends to increase, can be separated from the bottom of the two-stage dummy active trench 8, where the electric field tends to concentrate, thereby improving the breakdown voltage.

[0039] Furthermore, the concentration peak of the carrier storage layer 22 may be located on the back side of the carrier storage layer 22 rather than at its center (center in the depth direction). By adopting this positional relationship, holes can be mainly accumulated on the back side of the carrier storage layer 22 rather than at its center, thereby reducing the amount of holes accumulated on the front side. Consequently, the region in which displacement current is generated can be reduced, and thus the influence of displacement current can be minimized.

[0040] The carrier storage layer 22 in modified example 4 is also applicable to embodiment 1 and other modified examples.

[0041] <Modification 5> Figure 7 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 1. As shown in Figure 7, in the semiconductor device according to Modification 5, the width W1 of the first lower electrode 10 is shorter than the width W2 of the first upper electrode 9. Here, widths W1 and W2 are lengths in the lateral direction (width direction of the two-stage dummy active trench 8).

[0042] The displacement current is inversely proportional to the thickness of the first lower insulating film 12, which is the entry path for the displacement current. According to Modification 5, since the width W1 of the first lower electrode 10 is shorter than the width W2 of the first upper electrode 9, the thickness of the first lower insulating film 12 can be increased. Therefore, the displacement current can be reduced, which suppresses the increase in gate voltage and reduces switching losses.

[0043] <Variation 6> Figure 8 is a cross-sectional view of a semiconductor device according to a modification 6 of Embodiment 1. As shown in Figure 8, in the semiconductor device according to modification 6, the film thickness T1 of the first boundary insulating film 13 is longer than the width W1 of the first lower electrode 10.

[0044] According to Modification 6, since the film thickness T1 of the first boundary insulating film 13 is longer than the width W1 of the first lower electrode 10, the first lower electrode 10 into which the displacement current flows can be made smaller, and the increase in gate voltage can be suppressed.

[0045] Furthermore, the gate-emitter capacitance (Cge) in the first boundary insulating film 13 is proportional to the area where the first upper electrode 9 and the first lower electrode 10 face each other, and inversely proportional to the film thickness T1 of the first boundary insulating film 13. Also, the gate-collector capacitance (Cgc) is inversely proportional to the film thickness of the first lower insulating film 12. Therefore, by making the width W1 of the first lower electrode 10, which is the gate potential, shorter than the film thickness T1 of the first boundary insulating film 13, the gate-emitter capacitance (Cge) can be further reduced while minimizing the reduction in the gate-collector capacitance (Cgc), thereby maintaining a high gate capacitance ratio (Cgc / Cge) and reducing switching losses.

[0046] <Example 7> Figure 9 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 1. As shown in Figure 9, in the semiconductor device according to Modification 7, the length L1 of the first lower electrode 10 is shorter than the film thickness T1 of the first boundary insulating film 13.

[0047] If the thickness of the first boundary insulating film 13 is increased without changing the length of the first lower electrode 10, the depth of the two-stage dummy active trench 8 increases, which shortens the effective thickness of the drift layer 4 and reduces the breakdown voltage. According to modification 7, since the length L1 of the first lower electrode 10 is shorter than the thickness T1 of the first boundary insulating film 13, the breakdown voltage can be maintained without changing the depth of the two-stage dummy active trench 8, while reducing the displacement current and suppressing the increase in gate voltage.

[0048] <Differentiation Example 8> Figure 10 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. As shown in Figure 10, in the semiconductor device according to Modification 8, the width W1 of the first lower electrode 10 is longer than the length L1 of the first lower electrode 10.

[0049] According to Modification 8, since the width W1 of the first lower electrode 10 is longer than the length L1 of the first lower electrode 10, the displacement current can be reduced, and the increase in gate voltage can be reduced.

[0050] Furthermore, by reducing the thickness of the first lower insulating film 12 to increase the gate-collector capacitance (Cgc) while increasing the thickness of the first boundary insulating film 13, the gate-emitter capacitance (Cge) can be reduced. Consequently, a high gate capacitance ratio (Cgc / Cge) can be maintained, and switching losses can be reduced.

[0051] <Modification 9> Figure 11 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 1. As shown in Figure 11, in the semiconductor device according to Modification 9, the impurity concentration of the first boundary insulating film 13 is higher than that of the first upper insulating film 11 and the first lower insulating film 12. Specifically, the impurity concentration of the CVD (Chemical Vapor Deposition) film 23, which is the first boundary insulating film 13, is higher than that of the thermal oxide films 24, which are the first upper insulating film 11 and the first lower insulating film 12, respectively. Note that the impurity concentration of the first boundary insulating film 13 may be higher than that of either the first upper insulating film 11 or the first lower insulating film 12.

[0052] Generally, the CVD method can produce thicker insulating films more productively than thermal oxidation. Thermally oxidized films 24 are superior to those produced by the CVD method in terms of electrical properties. Also, CVD films 23 have a higher impurity concentration compared to thermally oxidized films. Examples of CVD films include HTO (High Temperature Oxide), TEOS (Tetra Eth Oxy Silane), and BPTEOS (BoroPhospho Tetra Ethyl Ortho Silicate).

[0053] According to Modification 9, the impurity concentration of the first boundary insulating film 13 is higher than that of the first upper insulating film 11 and the first lower insulating film 12. Specifically, the first boundary insulating film 13 is a CVD film 23, and the first upper insulating film 11 and the first lower insulating film 12 are thermal oxide films 24. This makes it possible to form a first boundary insulating film 13 with a thick film thickness with good productivity. In addition, by making the first upper insulating film 11 and the first lower insulating film 12, which are related to the electrical properties of the trench interface, thermal oxide films 24 can be used to improve the electrical properties of the gate.

[0054] <Variation 10> Figure 12 is a cross-sectional view of a semiconductor device according to a modified example 10 of Embodiment 1. As shown in Figure 12, in the semiconductor device according to modified example 10, the first boundary insulating film 13 is composed of two layers, including a layer with a high impurity concentration (first layer) and a layer with a low impurity concentration (second layer). Specifically, the layer with a high impurity concentration is a CVD film 23, and the layer with a low impurity concentration is a thermal oxide film 24.

[0055] According to Modification 10, after forming a CVD film 23, which is part of the first boundary insulating film 13, by the CVD method, a thermal oxide film 24 is formed in a step to form a thermal oxide film, which constitutes part of the first boundary insulating film and the first upper insulating film 11. As a result, the first boundary insulating film 13 is composed of two layers: the CVD film 23 and the thermal oxide film 24. This makes it possible to increase the thickness of the first boundary insulating film 13 and reduce the gate-emitter capacitance (Cge).

[0056] As shown in Figure 13, the first boundary insulating film 13 may be composed of three layers in which a CVD film 23 is sandwiched between two thermal oxide films 24. The thermal oxide films 24 on the back side of the CVD film 23 are formed by thermal oxidation in a process prior to forming the CVD film 23. This makes it possible to increase the thickness of the first boundary insulating film 13 and reduce the gate-emitter capacitance (Cge).

[0057] <Variation 11> Figure 14 is a cross-sectional view of a semiconductor device according to a modified example 11 of Embodiment 1. As shown in Figure 14, the impurity concentration in the first portion of the first boundary insulating film 13 in contact with the drift layer 4 (semiconductor layer) contained in the semiconductor substrate is lower than the impurity concentration in the second portion of the first boundary insulating film 13 other than the first portion. Specifically, the first portion of the first boundary insulating film 13 is a thermal oxide film 24, and the second portion of the first boundary insulating film 13 is a CVD film 23.

[0058] According to modification 11, the electrical properties can be improved by making the portion of the first boundary insulating film 13 that is in contact with the semiconductor layer a thermal oxide film 24.

[0059] <Variation 12> Figure 15 is a cross-sectional view of a semiconductor device according to a modified example 12 of Embodiment 1. As shown in Figure 15, in the semiconductor device according to modified example 12, the impurity concentration of the first boundary insulating film 13 and the impurity concentration of the first lower insulating film 12 are higher than the impurity concentration of the first upper insulating film 11. Specifically, the first boundary insulating film 13 and the first lower insulating film 12 are CVD films 23, and the first upper insulating film 11 is a thermal oxide film 24.

[0060] According to modification 12, the first boundary insulating film 13 and the first lower insulating film 12, which have thicker film thicknesses, can be formed productively by the CVD method, thereby reducing manufacturing costs.

[0061] As shown in Figure 16, the first lower insulating film 12 may be composed of two layers: a thermal oxide film 24 and a CVD film 23. Although not shown, the first upper insulating film 11 may also be composed of two layers: a thermal oxide film 24 and a CVD film 23.

[0062] <Example 13> Figure 17 is a cross-sectional view of a semiconductor device according to a modified example 13 of Embodiment 1. As shown in Figure 17, in the semiconductor device according to modified example 13, the first upper insulating film 11, the first lower insulating film 12, and the first boundary insulating film 13 are CVD films 23.

[0063] According to modification 13, the first upper insulating film 11, the first lower insulating film 12, and the first boundary insulating film 13 can be formed productively by the CVD method, thereby reducing manufacturing costs.

[0064] <Example 14> Figure 18 is a cross-sectional view of a semiconductor device according to a modified example 14 of Embodiment 1. As shown in Figure 18, the semiconductor device according to Modified Example 14 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) comprising a drain layer 25 provided on the back side of a semiconductor substrate and a drain electrode 26 provided on the back side of the drain layer 25. The other configurations are the same as those of Embodiment 1 (see Figure 1).

[0065] Since MOSFETs are unipolar devices in which holes do not contribute to the ON operation, the effect of displacement current caused by holes is small. On the other hand, because MOSFETs do not have holes, switching can be done at high speed, resulting in a large dV / dt. Since the displacement current is determined by the product of dV / dt and the gate-drain capacitance (Cgd), the displacement current becomes large in MOSFETs during high-frequency operation.

[0066] According to Modification 14, since it is equipped with a two-stage dummy active trench 8 having a thick first boundary insulating film 13, it is possible to reduce switching losses while suppressing an increase in gate voltage.

[0067] <Example 15> In the semiconductor device according to Modification 15, the semiconductor substrate includes a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide).

[0068] Even when the semiconductor substrate includes a wide-bandgap semiconductor, as in Modification 15, the same effects as in Embodiment 1 can be obtained. In particular, because wide-bandgap semiconductors enable high-speed switching compared to Si, the displacement current increases due to the large dV / dt. The semiconductor device according to this disclosure is equipped with a two-stage dummy active trench 8 having a thick first boundary insulating film 13, so that even with a wide-bandgap semiconductor where the displacement current is large, the increase in gate voltage can be suppressed while reducing switching losses.

[0069] It should be noted that the embodiments may be modified or omitted as appropriate within the scope of this disclosure.

[0070] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0071] (Note 1) Semiconductor substrate and A two-stage dummy active trench is provided inside a trench on the surface side of the semiconductor substrate, having a first upper electrode connected to the emitter electrode and covered with a first upper insulating film in the upper stage, a first lower electrode connected to the gate electrode and covered with a first lower insulating film in the lower stage, and a first boundary insulating film located between the first upper electrode and the first lower electrode. Equipped with, A semiconductor device wherein the thickness of the first boundary insulating film is greater than the thickness of the first upper insulating film and the thickness of the first lower insulating film, respectively.

[0072] (Note 2) The semiconductor device according to Appendix 1, wherein the thickness of the first lower insulating film is greater than the thickness of the first upper insulating film.

[0073] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein the thickness of the first boundary insulating film is 1.5 times or more the thickness of the first upper insulating film and the first lower insulating film, respectively.

[0074] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, further comprising a two-stage active trench inside a trench provided on the surface side of the semiconductor substrate, the trench having a second upper electrode connected to a gate electrode on the upper stage and a second lower electrode connected to a gate electrode on the lower stage.

[0075] (Note 5) A semiconductor device according to any one of the appendices 1 to 4, which is an IGBT (Insulated Gate Bipolar Transistor) having a collector layer provided on the back side of the semiconductor substrate.

[0076] (Note 6) The semiconductor device according to any one of appendices 1 to 5, further comprising a carrier storage layer provided on the semiconductor substrate.

[0077] (Note 7) The semiconductor device according to any one of the appendices 1 to 6, wherein the width of the first lower electrode is shorter than the width of the first upper electrode.

[0078] (Note 8) The semiconductor device according to any one of appendices 1 to 7, wherein the thickness of the first boundary insulating film is longer than the width of the first lower electrode.

[0079] (Note 9) The semiconductor device according to any one of the appendices 1 to 8, wherein the length of the first lower electrode is shorter than the thickness of the first boundary insulating film.

[0080] (Note 10) The semiconductor device according to any one of the appendices 1 to 9, wherein the width of the first lower electrode is longer than the length of the first lower electrode.

[0081] (Note 11) The semiconductor device according to any one of appendices 1 to 10, wherein the impurity concentration of the first boundary insulating film is higher than at least one of the impurity concentration of the first upper insulating film and the impurity concentration of the first lower insulating film.

[0082] (Note 12) The semiconductor device according to any one of appendices 1 to 11, wherein the first boundary insulating film is composed of two or more layers, including a first layer and a second layer having a lower impurity concentration than the first layer.

[0083] (Note 13) The semiconductor device according to any one of the appendices 1 to 12, wherein the impurity concentration of the first portion of the first boundary insulating film in contact with the semiconductor layer contained in the semiconductor substrate is lower than the impurity concentration of the second portion of the first boundary insulating film other than the first portion.

[0084] (Note 14) The semiconductor device according to any one of appendices 1 to 13, wherein the impurity concentration of the first boundary insulating film and the impurity concentration of the first lower insulating film are higher than the impurity concentration of the first upper insulating film.

[0085] (Note 15) The semiconductor device according to any one of the appendices 1 to 10, wherein the first upper insulating film, the first lower insulating film, and the first boundary insulating film are CVD (Chemical Vapor Deposition) films.

[0086] (Note 16) A semiconductor device according to any one of the appendices 1 to 15, which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain layer provided on the back side of the semiconductor substrate.

[0087] (Note 17) The semiconductor substrate is a semiconductor device according to any one of the appendices 1 to 16, including a wide-bandgap semiconductor. [Explanation of Symbols]

[0088] 1 Emitter electrode, 2 Interlayer insulating film, 3 Base layer, 4 Drift layer, 5 Buffer layer, 6 Collector layer, 7 Collector electrode, 8 Two-stage dummy active trench, 9 First upper electrode, 10 First lower electrode, 11 First upper insulating film, 12 First lower insulating film, 13 First boundary insulating film, 14 Pointed section, 15 Source layer, 16 Two-stage active trench, 17 Second upper electrode, 18 Second lower electrode, 19 Second upper insulating film, 20 Second lower insulating film, 21 Second boundary insulating film, 22 Carrier storage layer, 23 CVD film, 24 Thermal oxide film, 25 Drain layer, 26 Drain electrode.

Claims

1. Semiconductor substrate and A two-stage dummy active trench is provided inside a trench on the surface side of the semiconductor substrate, having a first upper electrode connected to the emitter electrode and covered with a first upper insulating film in the upper stage, a first lower electrode connected to the gate electrode and covered with a first lower insulating film in the lower stage, and a first boundary insulating film located between the first upper electrode and the first lower electrode. Equipped with, A semiconductor device wherein the thickness of the first boundary insulating film is greater than the thickness of the first upper insulating film and the thickness of the first lower insulating film, respectively.

2. The semiconductor device according to claim 1, wherein the thickness of the first lower insulating film is greater than the thickness of the first upper insulating film.

3. The semiconductor device according to claim 1 or 2, wherein the thickness of the first boundary insulating film is 1.5 times or more the thickness of the first upper insulating film and the first lower insulating film, respectively.

4. The semiconductor device according to claim 1 or 2, further comprising a two-stage active trench inside a trench provided on the surface side of the semiconductor substrate, the trench having a second upper electrode connected to a gate electrode on the upper side and a second lower electrode connected to a gate electrode on the lower side.

5. The semiconductor device according to claim 1 or 2, wherein the IGBT (Insulated Gate Bipolar Transistor) comprises a collector layer provided on the back side of the semiconductor substrate.

6. The semiconductor device according to claim 1 or 2, further comprising a carrier storage layer provided on the semiconductor substrate.

7. The semiconductor device according to claim 1 or 2, wherein the width of the first lower electrode is shorter than the width of the first upper electrode.

8. The semiconductor device according to claim 1 or 2, wherein the thickness of the first boundary insulating film is longer than the width of the first lower electrode.

9. The semiconductor device according to claim 1 or 2, wherein the length of the first lower electrode is shorter than the thickness of the first boundary insulating film.

10. The semiconductor device according to claim 1 or 2, wherein the width of the first lower electrode is longer than the length of the first lower electrode.

11. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first boundary insulating film is higher than at least one of the impurity concentration of the first upper insulating film and the impurity concentration of the first lower insulating film.

12. The semiconductor device according to claim 1 or 2, wherein the first boundary insulating film is composed of two or more layers, including a first layer and a second layer having a lower impurity concentration than the first layer.

13. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first portion of the first boundary insulating film in contact with the semiconductor layer contained in the semiconductor substrate is lower than the impurity concentration of the second portion of the first boundary insulating film other than the first portion.

14. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first boundary insulating film and the impurity concentration of the first lower insulating film are higher than the impurity concentration of the first upper insulating film.

15. The semiconductor device according to claim 1 or 2, wherein the first upper insulating film, the first lower insulating film, and the first boundary insulating film are CVD (Chemical Vapor Deposition) films.

16. The semiconductor device according to claim 1 or 2, wherein the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has a drain layer provided on the back side of the semiconductor substrate.

17. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate includes a wide-bandgap semiconductor.

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