Semiconductor equipment

Abstract

The present disclosure aims to provide a semiconductor device that can reduce dV / dt by suppressing an increase in gate voltage. [Solution] The semiconductor device according to the present disclosure comprises a semiconductor substrate, a base layer provided on the surface side of the semiconductor substrate, and a two-stage dummy active trench provided on the surface side of the semiconductor substrate, penetrating the base layer, with a first upper electrode connected to an emitter electrode in the upper stage and a first lower electrode connected to a gate electrode in the lower stage. The first upper electrode includes a pointed portion protruding to the back side from at least one of the left and right ends of the back side, and the tip of the pointed portion is located on the back side of the base layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal.

Background Art

[0002] A semiconductor device including a two-stage dummy active trench having an upper electrode connected to an emitter electrode in the upper stage and a lower electrode connected to a gate electrode in the lower stage inside the trench can reduce voltage time change (dV / dt), which is a factor of noise and motor breakdown, by increasing the gate-collector capacitance (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, under very fast switching conditions such as high-speed turn-on switching, holes fluctuate the potential around the trench, and a displacement current flows into the lower electrode, which is the gate potential. As a result, there is a problem that the gate voltage increases and dV / dt increases.

[0005] The present disclosure has been made to solve such problems, and an object thereof is to provide a semiconductor device capable of suppressing an increase in gate voltage and reducing dV / dt.

Means for Solving the Problems

[0006] To solve the above problems, the semiconductor device according to this disclosure comprises a semiconductor substrate, a base layer provided on the surface side of the semiconductor substrate, and a two-stage dummy active trench provided on the surface side of the semiconductor substrate, penetrating the base layer, with a first upper electrode connected to an emitter electrode on the upper stage and a first lower electrode connected to a gate electrode on the lower stage. The first upper electrode includes a pointed portion protruding to the back side from at least one of the left and right ends of the back side, and the tip of the pointed portion is located on the back side of the base layer. [Effects of the Invention]

[0007] According to this disclosure, it is possible to suppress the increase in gate voltage and reduce dV / dt. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of a semiconductor device according to a modified example 1 of Embodiment 1. [Figure 3] This is a cross-sectional view of a semiconductor device according to a modified example 2 of Embodiment 1. [Figure 4] This is a cross-sectional view of a semiconductor device according to a modified example 3 of Embodiment 1. [Figure 5] This is a cross-sectional view of a semiconductor device according to a modified example 4 of Embodiment 1. [Figure 6] This is a cross-sectional view of a semiconductor device according to a modified example 5 of Embodiment 1. [Figure 7] This is a cross-sectional view of a semiconductor device according to a modified example 6 of Embodiment 1. [Figure 8] This is a cross-sectional view of a semiconductor device according to a modified example 7 of Embodiment 1. [Figure 9] This is a cross-sectional view of a semiconductor device according to a modified example 8 of Embodiment 1. [Figure 10] This is a cross-sectional view of a semiconductor device according to a modified example 9 of Embodiment 1. [Figure 11] This is a cross-sectional view of a semiconductor device according to a modified example 10 of Embodiment 1. [Figure 12] Cross-sectional view of a semiconductor device according to Modified Example 11 of Embodiment 1. [Figure 13] Cross-sectional view of a semiconductor device according to Modified Example 11 of Embodiment 1. [Figure 14] Cross-sectional view of a semiconductor device according to Modified Example 11 of Embodiment 1. [Figure 15] Cross-sectional view of a semiconductor device according to Modified Example 12 of Embodiment 1. [Figure 16] Cross-sectional view of a semiconductor device according to Modified Example 14 of Embodiment 1.

Embodiments for Carrying Out the Invention

[0009] <Embodiment 1> Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. The semiconductor device is an IGBT (Insulated Gate Bipolar Transistor). Note that the same or corresponding components may be denoted by the same reference numerals, and repeated descriptions may be omitted. In the following description, N and P indicate the conductivity types of semiconductors. These conductivity types may be reversed.

[0010] FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1. In FIG. 1, the semiconductor substrate is in the range from the base layer 3 to the collector layer 6. In FIG. 1, the upper end of the base layer 3 is referred to as the surface of the semiconductor substrate, and the lower end of the collector layer 6 is referred to as the back surface of the semiconductor substrate. The surface and the back surface face each other.

[0011] As shown in FIG. 1, a P-type base layer 3 is provided on the surface side of the N-type drift layer 4.

[0012] The semiconductor substrate is provided with a two-stage dummy active trench 8 that penetrates the base layer 3 and reaches the drift layer 4. The two-stage dummy active trench 8 has a first upper electrode 9 connected to the emitter electrode 1 in the upper stage and a first lower electrode 11 connected to a gate electrode (not shown) in the lower stage inside a trench provided on the surface side of the semiconductor substrate. The first upper electrode 9 includes pointed portions 10 that protrude toward the back surface on the left and right at the end face on the back surface side. The tip portions 15 of the pointed portions 10 are located on the back surface side of the base layer 3. In the example of FIG. 1, the pointed portions 10 are provided on both the left and right at the end face on the back surface side of the first upper electrode 9, but the pointed portions 10 may be provided on either the left or the right.

[0013] Further, the two-stage dummy active trench 8 has a first upper insulating film 12 provided on the side wall of the first upper electrode 9, a first lower insulating film 13 provided on the side wall of the first lower electrode 11, and a first boundary insulating film 14 provided between the first upper electrode 9 and the first lower electrode 11. The first upper electrode 9 and the first lower electrode 11 are electrically separated via the first boundary insulating film 14.

[0014] An interlayer insulating film 2 is provided on the two-stage dummy active trench 8. An emitter electrode 1 is provided on the base layer 3 and the interlayer insulating film 2.

[0015] On the back surface side of the drift layer 4, an N-type buffer layer 5 having an N-type impurity concentration higher than that of the drift layer 4 is provided. On the back surface side of the buffer layer 5, a P-type collector layer 6 is provided. On the back surface side of the collector layer 6, a collector electrode 7 is provided.

[0016] Displacement current is generated when holes cause fluctuations in the potential around the trench. The region where this displacement current is generated is on the back side of the base layer 3 where holes accumulate. According to Embodiment 1, the first upper electrode 9 includes a pointed portion 10 that protrudes to the back side, and the tip 15 of the pointed portion 10 is located on the back side of the base layer 3. Therefore, the displacement current flows to the pointed portion 10, which is at the lower emitter potential. As the displacement current flows to the pointed portion 10, the number of holes flowing into the first lower electrode 11, which is at the gate potential, decreases, thus reducing the increase in gate voltage. In other words, according to Embodiment 1, it is possible to suppress the increase in gate voltage and reduce dV / dt.

[0017] Furthermore, the influence of displacement current generated by potential fluctuations caused by holes is particularly large in IGBTs, which are bipolar devices that use holes as carriers. According to Embodiment 1, a synergistic effect can be obtained between the IGBT and the above configuration, resulting in a greater reduction in displacement current.

[0018] <Example 1> Figure 2 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. As shown in Figure 2, in the semiconductor device according to Modification 1, the pointed portion 10 of the first upper electrode 9 and the first lower electrode 11 face each other in the width direction (lateral direction) of the two-stage dummy active trench 8.

[0019] According to Modification 1, the pointed portion 10 of the first upper electrode 9 and the first lower electrode 11 are positioned to face each other in the width direction of the two-stage dummy active trench 8. As a result, the pointed portion 10 shields the first lower electrode 11, reducing the inflow of displacement current to the first lower electrode 11. Therefore, the increase in gate voltage is suppressed, and dV / dt can be reduced.

[0020] <Modification 2> Figure 3 is a cross-sectional view of a semiconductor device according to a modified example 2 of Embodiment 1. As shown in Figure 3, the first lower electrode 11 includes a portion having a first width G1 on the front surface side and a portion having a second width G2 that is larger than the first width G1 on the back surface side. The portion having the first width G1 faces the pointed portion 10 and the two-stage dummy active trench 8 in the width direction. The portion having the second width G2 does not face the pointed portion 10 and the two-stage dummy active trench 8 in the width direction.

[0021] According to Modification 2, by reducing the width (first width G1) of the portion of the first lower electrode 11 that faces the pointed portion 10 of the first upper electrode 9 (the portion having the first width G1), a space is formed that allows the pointed portion 10 to protrude toward the first lower electrode 11, and the pointed portion 10 can be made longer. Therefore, the displacement current flowing into the pointed portion 10 can be increased and the displacement current flowing into the first lower electrode 11 can be reduced, thereby suppressing the increase in gate voltage.

[0022] In Figure 3, an example is shown where the thickness of the first lower insulating film 13 is thicker than the thickness of the first upper insulating film 12. Such a configuration may be applied to Embodiment 1 and Modification 1.

[0023] <Variation 3> Figure 4 is a cross-sectional view of a semiconductor device according to a modification 3 of Embodiment 1. As shown in Figure 4, the semiconductor device according to modification 3 further comprises an N-type source layer 16 provided on the surface side of the base layer 3, and a two-stage active trench 17 that penetrates the source layer 16 and the base layer 3 and reaches the drift layer 4.

[0024] The two-stage active trench 17 has a second upper electrode 18 connected to the gate electrode in the upper stage and a second lower electrode 19 connected to the gate electrode in the lower stage, located inside the trench on the surface side of the semiconductor substrate.

[0025] Furthermore, the two-stage active trench 17 includes a second upper insulating film 20 provided on the side wall of the second upper electrode 18, a second lower insulating film 21 provided on the side wall of the second lower electrode 19, and a second boundary insulating film 22 provided between the second upper electrode 18 and the second lower electrode 19. The second upper electrode 18 and the second lower electrode 19 are electrically isolated via the second boundary insulating film 22.

[0026] According to Modification 3, by providing a two-stage active trench 17 having a second upper electrode 18 which is the gate potential, and a source layer 16, a channel can be formed in the base layer 3, making it possible to turn on the semiconductor device.

[0027] Since the second upper electrode 18 is connected to the gate electrode, displacement current flows into the second upper electrode 18 of the two-stage active trench 17. However, by arranging the two-stage active trench 17 and the two-stage dummy active trench 8 adjacent to each other, a synergistic effect can be obtained in which the two-stage dummy active trench 8 can be turned on while a displacement current flows through its first upper electrode 9.

[0028] In the example shown in Figure 4, the shapes of the first lower electrode 11 and the second lower electrode 19 are the same as those in modified examples 1 and 2 (see Figures 2 and 3), but the invention is not limited to these shapes. The shapes of the first lower electrode 11 and the second lower electrode 19 may also be the same as those in Embodiment 1 (see Figure 1).

[0029] <Modification 4> Figure 5 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 1. As shown in Figure 5, the semiconductor device according to Modification 4 further comprises a carrier storage layer 23. The carrier storage layer 23 is provided on the back side of the base layer 3 (the front side of the drift layer 4).

[0030] According to Modification 4, the inclusion of the carrier storage layer 23 increases the amount of holes stored, thus increasing the displacement current. In this configuration, a synergistic effect can be obtained from the effect of the carrier storage layer 23 and the effect of Embodiment 1, and in particular, the effect of reducing the displacement current is greatly increased.

[0031] Furthermore, the pointed portion 10 of the first upper electrode 9 and the carrier storage layer 23 may be positioned opposite each other in the width direction of the two-stage dummy active trench 8. By adopting this configuration, the effect of displacement current due to the high density of holes in the carrier storage layer 23 can be reduced by the pointed portion 10.

[0032] The entire area of ​​the pointed portion 10 of the first upper electrode 9 and the carrier storage layer 23 may be positioned opposite each other in the width direction of the two-stage dummy active trench 8. By adopting such a configuration, the displacement current can be further reduced.

[0033] The pointed portion 10 of the first upper electrode 9 and the concentration peak in the carrier storage layer 23 may be positioned opposite each other in the width direction of the two-stage dummy active trench 8. By positioning the pointed portion 10 opposite the part of the carrier storage layer 23 that is susceptible to displacement current due to the high density of holes in the carrier storage layer 23, the influence of displacement current can be reduced.

[0034] The carrier storage layer 23 in modified example 4 is also applicable to embodiment 1 and other modified examples.

[0035] <Modification 5> Figure 6 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 1. As shown in Figure 6, in the semiconductor device according to Modification 5, the film thickness T2 of the first lower insulating film 13 is thicker than the film thickness T1 of the first upper insulating film 12.

[0036] According to Modification 5, by making the film thickness T2 of the first lower insulating film 13 thicker than the film thickness T1 of the first upper insulating film 12, a space is formed in which the pointed portion 10 of the first upper electrode 9 can protrude toward the first lower electrode 11, and the pointed portion 10 can be made longer. Therefore, the displacement current flowing into the pointed portion 10 can be increased and the displacement current flowing into the first lower electrode 11 can be reduced, thereby suppressing the increase in gate voltage.

[0037] In the example shown in Figure 6, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8.

[0038] <Variation 6> Figure 7 is a cross-sectional view of a semiconductor device according to Modification 6 of Embodiment 1. As shown in Figure 7, in the semiconductor device according to Modification 6, the length U2 of the pointed portion 10 is longer than the length U1 from the end face on the surface side of the first upper electrode 9 to the base portion 24 of the pointed portion 10.

[0039] According to Modification 6, the length U2 of the pointed portion 10 can be made longer than the length U1 from the end face on the surface side of the first upper electrode 9 to the base portion 24 of the pointed portion 10. Therefore, the displacement current flowing into the pointed portion 10 can be increased and the displacement current flowing into the first lower electrode 11 can be reduced, thereby suppressing the increase in gate voltage.

[0040] Furthermore, since the first lower electrode 11 can be made longer on the surface side, the wiring resistance of the first lower electrode 11 can be reduced, and the increase in the gate potential, which is determined by the product of the wiring resistance and the displacement current, can be suppressed.

[0041] In the example shown in Figure 7, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8.

[0042] <Example 7> Figure 8 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 1. As shown in Figure 8, in the semiconductor device according to Modification 7, the base portion 24 of the pointed portion 10 of the first upper electrode 9 is located on the back side of the base layer 3 (position B1 from the surface of the semiconductor substrate).

[0043] In the layers on the back side of the base layer 3, holes tend to accumulate, making it easier for displacement currents to be generated. According to Modification 7, by positioning the entire base portion 24 of the pointed portion 10 on the back side of the base layer 3, the displacement current flowing into the pointed portion 10 can be increased, and the displacement current flowing into the first lower electrode 11 can be reduced, thereby suppressing the increase in gate voltage.

[0044] In the example shown in Figure 8, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8.

[0045] Furthermore, in the example shown in Figure 8, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1).

[0046] <Differentiation Example 8> Figure 9 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. As shown in Figure 9, in the semiconductor device according to Modification 8, the base portion 24 of the pointed portion 10 of the first upper electrode 9 is located on the front side of the back side of the base layer 3 (position B1 from the surface of the semiconductor substrate). The tip portion 15 of the pointed portion 10 is located on the back side of the base layer 3, similar to Embodiment 1.

[0047] According to Modification 8, by positioning the base portion 24 of the pointed portion 10 on the surface side of the back side end face of the base layer 3, the displacement current flowing into the pointed portion 10 is increased, the displacement current flowing into the first lower electrode 11 is reduced, and the area of ​​the first lower electrode 11 is expanded on the surface side, thereby reducing the wiring resistance of the first lower electrode 11 and suppressing the increase in gate voltage.

[0048] In the example shown in Figure 9, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8.

[0049] In the example shown in Figure 9, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1).

[0050] <Modification 9> Figure 10 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 1. As shown in Figure 10, in the semiconductor device according to Modification 9, the two-stage dummy active trenches 8 are arranged on both sides of the two-stage active trench 17. In the example in Figure 10, two two-stage dummy active trenches 8 are arranged on both sides of the two-stage active trench 17, but the number of two-stage dummy active trenches 8 is not limited to this.

[0051] According to Modification 9, by placing the two-stage dummy active trench 8 on both sides of the two-stage active trench 17, the displacement current flowing into the second upper electrode 18 of the two-stage active trench 17 can be directed to the first upper electrode 9 of the two-stage dummy active trench 8, thereby suppressing the increase in gate voltage due to the displacement current.

[0052] Furthermore, the number of two-stage dummy active trenches 8 may be greater than the number of two-stage active trenches 17. By adopting this configuration, the effect of reducing displacement current can be further enhanced.

[0053] In the example shown in Figure 10, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8. The same applies to the two-stage active trench 17.

[0054] In the example shown in Figure 10, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1). The same applies to the two-stage active trench 17.

[0055] <Variation 10> Figure 11 is a cross-sectional view of a semiconductor device according to a modified example 10 of Embodiment 1. As shown in Figure 11, in the semiconductor device according to modified example 10, in the two-stage dummy active trench 8, the cross-sectional area of ​​the first upper electrode 9 is smaller than the cross-sectional area of ​​the first lower electrode 11. Also, in the two-stage active trench 17, the cross-sectional area of ​​the second upper electrode 18 is smaller than the cross-sectional area of ​​the second lower electrode 19.

[0056] By increasing the cross-sectional area of ​​the first lower electrode 11 and the second lower electrode 19, the wiring resistance in each of the first lower electrode 11 and the second lower electrode 19 can be reduced, thereby suppressing the increase in gate voltage.

[0057] In the example shown in Figure 11, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only configuration. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8. The same applies to the two-stage active trench 17.

[0058] In the example shown in Figure 11, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1). The same applies to the two-stage active trench 17.

[0059] <Variation 11> Figure 12 is a cross-sectional view of a semiconductor device according to a modified example 11 of Embodiment 1. As shown in Figure 12, the semiconductor device according to modified example 11 is an RC-IGBT (Reverse Conducting IGBT) comprising an IGBT region 26 including a collector layer 6 and a diode region 27 including a cathode layer 25 provided on the back side of the semiconductor substrate. A two-stage active trench 17 and a two-stage dummy active trench 8 are arranged in the IGBT region 26, and a two-stage dummy active trench 8 is arranged in the diode region 27.

[0060] Even with an RC-IGBT like the modified example 11, the same effects as in Embodiment 1 can be obtained. In particular, by placing a two-stage dummy active trench 8 in the diode region 27 where a gate is not required, the displacement current generated in the IGBT region 26 can be diverted to the two-stage dummy active trench 8, thereby suppressing the increase in gate voltage.

[0061] The semiconductor device relating to the modified example 11 is not limited to the configuration shown in Figure 12, but may also have the configuration shown in Figure 13 or Figure 14.

[0062] The semiconductor device shown in Figure 13 has a two-stage dummy trench 28 placed in the diode region 27. The two-stage dummy trench 28 has a third upper electrode 29 connected to the emitter electrode 1 in the upper stage and a third lower electrode 30 connected to the emitter electrode 1 in the lower stage, inside a trench provided on the surface side of the semiconductor substrate. The two-stage dummy trench 28 also has a third upper insulating film 31 provided on the side wall of the third upper electrode 29, a third lower insulating film 32 provided on the side wall of the third lower electrode 30, and a third boundary insulating film 33 provided between the third upper electrode 29 and the third lower electrode 30. The third upper electrode 29 and the third lower electrode 30 are electrically isolated via the third boundary insulating film 33.

[0063] The semiconductor device shown in Figure 14 has a single-stage dummy trench 34 placed in the diode region 27. The single-stage dummy trench 34 has a dummy electrode 35 and a dummy insulating film 36 provided on the side wall of the dummy electrode 35 inside the trench provided on the surface side of the semiconductor substrate.

[0064] By configuring the semiconductor device as shown in Figure 13 or Figure 14, the displacement current flowing into the first lower electrode 11 of the two-stage dummy active trench 8 and the second lower electrode 19 of the two-stage active trench 17, which are located in the IGBT region 26, can be reduced.

[0065] In the diode region 27, the two-stage dummy active trench 8 shown in Figure 12, the two-stage dummy trench 28 shown in Figure 13, and the single-stage dummy trench 34 shown in Figure 14 may be arranged in an appropriate combination.

[0066] In the examples shown in Figures 12-14, the pointed portion 10 and the first lower electrode 11 face each other in the width direction of the two-stage dummy active trench 8, but this is not the only arrangement. The pointed portion 10 and the first lower electrode 11 do not need to face each other in the width direction of the two-stage dummy active trench 8. The same applies to the two-stage active trench 17 and the two-stage dummy trench 28.

[0067] In the examples shown in Figures 12-14, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1). The same applies to the two-stage active trench 17 and the two-stage dummy trench 28.

[0068] <Variation 12> Figure 15 is a cross-sectional view of a semiconductor device according to a modified example 12 of Embodiment 1. As shown in Figure 15, in the semiconductor device according to modified example 12, the film thickness of the portion of the first upper insulating film 12 facing the pointed portion 10 is thinner than the film thickness of the other portions of the first upper insulating film 12 and the film thickness of the first lower insulating film 13.

[0069] According to modification 12, by making the film thickness of the portion of the first upper insulating film 12 facing the pointed portion 10 thinner than the film thickness of the other portions of the first upper insulating film 12 and the film thickness of the first lower insulating film 13, the displacement current can be preferentially directed to the pointed portion 10, thereby reducing the influence of the displacement current on the gate voltage.

[0070] Furthermore, the film thickness of the portion of the first upper insulating film 12 facing the pointed portion 10 may be made thicker than the film thickness of the other portions of the first upper insulating film 12. By adopting this configuration, the total amount of displacement current can be reduced while maintaining the ease with which displacement current flows into the pointed portion 10. If a large amount of displacement current flows into the first upper electrode 9, a voltage drop will occur, affecting the gate potential of the first lower electrode 11. According to modification 12, the fluctuation of the gate potential can be reduced by reducing the total amount of displacement current.

[0071] In the example shown in Figure 15, the shape of the first lower electrode 11 is the same as in the modified examples 1 and 2 (see Figures 2 and 3), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Embodiment 1 (see Figure 1).

[0072] <Example 13> In the semiconductor device according to Modification 13, the semiconductor substrate includes a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide).

[0073] Even if the semiconductor substrate is configured to include a wide-bandgap semiconductor, as in Modification 13, the same effects as in Embodiment 1 can be obtained. In particular, because wide-bandgap semiconductors can be switched at higher speeds than Si, the displacement current increases due to the large dV / dt ratio. The semiconductor device according to this disclosure is equipped with a two-stage dummy active trench 8 having a first upper electrode 9 including a pointed portion 10, so that the displacement current can flow to the first upper electrode 9 side. Therefore, in particular, the increase in gate voltage can be suppressed in wide-bandgap semiconductors where the displacement current is large.

[0074] <Example 14> Figure 16 is a cross-sectional view of a semiconductor device according to a modified example 14 of Embodiment 1. As shown in Figure 16, the semiconductor device according to Modified Example 14 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) comprising a drain layer 37 provided on the back side of a semiconductor substrate and a drain electrode 38 provided on the back side of the drain layer 37. The other configurations are the same as those of Embodiment 1 (see Figure 1).

[0075] Since MOSFETs are unipolar devices in which holes do not contribute to the ON operation, the effect of displacement current caused by holes is small. On the other hand, because MOSFETs do not have holes, switching can be done at high speed, resulting in a large dV / dt. Since the displacement current is determined by the product of dV / dt and Cgd (gate-drain capacitance), the displacement current becomes large in MOSFETs during high-frequency operation. According to Modification 14, a two-stage dummy active trench 8 having a first upper electrode 9 including a pointed portion 10 is provided, so the displacement current can be directed to the first upper electrode 9 side, and the increase in gate voltage can be suppressed.

[0076] In the example shown in Figure 16, the shape of the first lower electrode 11 is the same as in Embodiment 1 (see Figure 1), but it is not limited to this. The shape of the first lower electrode 11 may also be the same as in Modifications 1 and 2 (see Figures 2 and 3).

[0077] It should be noted that the embodiments may be modified or omitted as appropriate within the scope of this disclosure.

[0078] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0079] (Note 1) Semiconductor substrate and A base layer provided on the surface side of the semiconductor substrate, A two-stage dummy active trench is provided inside a trench that penetrates the base layer on the surface side of the semiconductor substrate, having a first upper electrode connected to the emitter electrode in the upper stage and a first lower electrode connected to the gate electrode in the lower stage. Equipped with, The first upper electrode includes a pointed portion that protrudes toward the rear side from at least one of the left and right ends of the rear side, The tip of the pointed portion is located on the back side of the base layer, in a semiconductor device.

[0080] (Note 2) The semiconductor device described in Appendix 1, wherein the pointed portion and the first lower electrode face each other in the width direction of the trench.

[0081] (Note 3) The first lower electrode includes a portion having a first width on the surface side and a portion having a second width greater than the first width on the back side. The portion having the first width faces the pointed portion and the trench in the width direction, The semiconductor device according to Appendix 1 or 2, wherein the portion having the second width is not opposite the pointed portion and the trench in the width direction.

[0082] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, further comprising a two-stage active trench having a second upper electrode connected to a gate electrode on the upper stage and a second lower electrode connected to a gate electrode on the lower stage, inside a trench provided on the surface side of the semiconductor substrate that penetrates the base layer.

[0083] (Note 5) A semiconductor device according to any one of the appendices 1 to 4, which is an IGBT (Insulated Gate Bipolar Transistor) having a collector layer provided on the back side of the semiconductor substrate.

[0084] (Note 6) The semiconductor device according to any one of appendices 1 to 5, further comprising a carrier storage layer provided on the back surface side of the base layer.

[0085] (Note 7) The two-stage dummy active trench has a first upper insulating film provided on the side wall of the first upper electrode and a first lower insulating film provided on the side wall of the first lower electrode. The semiconductor device according to any one of the appendices 1 to 6, wherein the thickness of the first lower insulating film is greater than the thickness of the first upper insulating film.

[0086] (Note 8) The semiconductor device according to any one of the appendices 1 to 7, wherein the length of the pointed portion is longer than the length from the end face on the surface side of the first upper electrode to the base of the pointed portion.

[0087] (Note 9) The semiconductor device according to any one of appendices 1 to 8, wherein the base of the pointed portion is located on the back side of the base layer.

[0088] (Note 10) The semiconductor device according to any one of appendices 1 to 8, wherein the base of the pointed portion is located on the front side of the back side end face of the base layer.

[0089] (Note 11) The aforementioned two-stage dummy active trench is a semiconductor device as described in Appendix 4, located on both sides of the aforementioned two-stage active trench.

[0090] (Note 12) The semiconductor device according to any one of the appendices 1 to 11, wherein the cross-sectional area of ​​the first upper electrode is smaller than the cross-sectional area of ​​the first lower electrode.

[0091] (Note 13) A semiconductor device according to any one of the appendices 1 to 12, comprising an IGBT region including a collector layer provided on the back side of the semiconductor substrate and a diode region including a cathode layer provided on the back side of the semiconductor substrate, which is an RC-IGBT (Reverse Conducting IGBT).

[0092] (Note 14) The two-stage dummy active trench has a first upper insulating film provided on the side wall of the first upper electrode and a first lower insulating film provided on the side wall of the first lower electrode. The semiconductor device according to any one of the appendices 1 to 13, wherein the film thickness of the portion of the first upper insulating film facing the pointed portion is thinner than the film thickness of the other portion of the first upper insulating film and the film thickness of the first lower insulating film.

[0093] (Note 15) The semiconductor substrate is a semiconductor device according to any one of the appendices 1 to 14, including a wide-bandgap semiconductor.

[0094] (Note 16) A semiconductor device according to any one of the appendices 1 to 3, which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain layer provided on the back side of the semiconductor substrate. [Explanation of symbols]

[0095] 1 Emitter electrode, 2 Interlayer insulating film, 3 Base layer, 4 Drift layer, 5 Buffer layer, 6 Collector layer, 7 Collector electrode, 8 Two-stage dummy active trench, 9 First upper electrode, 10 Pointed part, 11 First lower electrode, 12 First upper insulating film, 13 First lower insulating film, 14 First boundary insulating film, 15 Tip, 16 Source layer, 17 Two-stage active trench, 18 Second upper electrode, 19 Second lower electrode, 20 Second upper insulating film, 21 Second lower insulating film, 22 Second boundary insulating film, 23 Carrier storage layer, 24 Base, 25 Cathode layer, 26 IGBT region, 27 Diode region, 28 Two-stage dummy trench, 29 Third upper electrode, 30 Third lower electrode, 31 Third upper insulating film, 32 Third lower insulating film, 33 Third boundary insulating film, 34 1-stage dummy trench, 35 dummy electrode, 36 dummy insulating film, 37 drain layer, 38 drain electrode.

Claims

1. Semiconductor substrate and A base layer provided on the surface side of the semiconductor substrate, A two-stage dummy active trench is provided inside a trench that penetrates the base layer on the surface side of the semiconductor substrate, having a first upper electrode connected to the emitter electrode in the upper stage and a first lower electrode connected to the gate electrode in the lower stage. Equipped with, The first upper electrode includes a pointed portion that protrudes toward the rear side from at least one of the left and right ends of the rear side, The tip of the pointed portion is located on the back side of the base layer, in a semiconductor device.

2. The semiconductor device according to claim 1, wherein the pointed portion and the first lower electrode face each other in the width direction of the trench.

3. The first lower electrode includes a portion having a first width on the surface side and a portion having a second width greater than the first width on the back side. The portion having the first width faces the pointed portion and the trench in the width direction, The semiconductor device according to claim 2, wherein the portion having the second width is not opposite the pointed portion and the trench in the width direction.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a two-stage active trench having a second upper electrode connected to a gate electrode on the upper stage and a second lower electrode connected to a gate electrode on the lower stage, inside a trench provided on the surface side of the semiconductor substrate that penetrates the base layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein the IGBT (Insulated Gate Bipolar Transistor) comprises a collector layer provided on the back side of the semiconductor substrate.

6. The semiconductor device according to any one of claims 1 to 3, further comprising a carrier storage layer provided on the back surface side of the base layer.

7. The two-stage dummy active trench has a first upper insulating film provided on the side wall of the first upper electrode and a first lower insulating film provided on the side wall of the first lower electrode. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first lower insulating film is greater than the thickness of the first upper insulating film.

8. The semiconductor device according to any one of claims 1 to 3, wherein the length of the pointed portion is longer than the length from the end face on the surface side of the first upper electrode to the base of the pointed portion.

9. The semiconductor device according to any one of claims 1 to 3, wherein the base of the pointed portion is located on the back side of the base layer.

10. The semiconductor device according to any one of claims 1 to 3, wherein the base of the pointed portion is located on the front side of the back side end face of the base layer.

11. The semiconductor device according to claim 4, wherein the two-stage dummy active trench is located on both sides of the two-stage active trench.

12. The semiconductor device according to any one of claims 1 to 3, wherein the cross-sectional area of ​​the first upper electrode is smaller than the cross-sectional area of ​​the first lower electrode.

13. A semiconductor device according to any one of claims 1 to 3, comprising an IGBT region including a collector layer provided on the back side of the semiconductor substrate and a diode region including a cathode layer provided on the back side of the semiconductor substrate.

14. The two-stage dummy active trench has a first upper insulating film provided on the side wall of the first upper electrode and a first lower insulating film provided on the side wall of the first lower electrode. The semiconductor device according to any one of claims 1 to 3, wherein the film thickness of the portion of the first upper insulating film facing the pointed portion is thinner than the film thickness of the other portion of the first upper insulating film and the film thickness of the first lower insulating film.

15. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate includes a wide-bandgap semiconductor.

16. The semiconductor device according to any one of claims 1 to 3, wherein the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) comprises a drain layer provided on the back side of the semiconductor substrate.

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