Semiconductor equipment

Abstract

To provide semiconductor devices with improved reliability. [Solution] The semiconductor device according to the present invention includes a base insulating layer, a channel structure located on a first surface of the base insulating layer, a gate structure surrounding the channel structure, and source / drain patterns arranged on both sides of the channel structure, spaced apart from each other along a first direction, each of the source / drain patterns includes a liner layer and a filling layer located on the inner surface of the liner layer, the lower surface and a portion of the sides of the source / drain pattern are covered by the base insulating layer, and the liner layer contains carbon-doped silicon germanium.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Semiconductor devices are used in various electronic devices such as storage devices for storing data and processors for performing arithmetic processing of data. With the development of the electronics industry, various solutions have been studied to improve various characteristics such as the integration degree, reliability, speed, and functions of semiconductor devices. For example, in order to overcome the limitations due to the reduction in the size of semiconductor devices, semiconductor devices having a three-dimensional structure have been proposed.

[0003] Recently, research has been conducted to improve the congestion of routing by arranging a power delivery network for routing signals provided to a semiconductor device on the back surface of a substrate and scaling the size of the semiconductor device.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor device with improved reliability and a method for manufacturing the same.

[0005] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] A semiconductor device according to one aspect of the present invention, made to achieve the above objective, includes a base insulating layer, a channel structure located on a first surface of the base insulating layer, a gate structure surrounding the channel structure, and source / drain patterns arranged on both sides of the channel structure, spaced apart from each other along a first direction, wherein each of the source / drain patterns includes a liner layer and a filling layer located on the inner surface of the liner layer, the lower surface and a portion of the sides of the source / drain pattern are covered by the base insulating layer, and the liner layer contains carbon-doped silicon germanium.

[0007] Another embodiment of the present invention made to achieve the above objectives includes a base insulating layer including a first surface and a second surface facing the first surface; a channel structure located on the first surface of the base insulating layer; a gate structure surrounding the channel structure; source / drain patterns located on both sides of the channel structure and extending into the base insulating layer; a lower wiring structure located on the second surface of the base insulating layer; and a lower contact electrode connecting at least one of the source / drain patterns to the lower wiring structure, wherein the lower contact electrode includes a first contact region extending into the base insulating layer and a second contact region extending from the upper surface of the first contact region into at least one of the source / drain patterns, and the upper surface of the first contact region is located between the lower surface of the gate structure and the lower surface of the source / drain pattern.

[0008] A semiconductor device according to yet another aspect of the present invention made to achieve the above objectives includes a base insulating layer, a channel structure located on the base insulating layer, a gate structure surrounding the channel structure, a source / drain pattern including a first source / drain pattern and a second source / drain pattern located on both sides of the channel structure, a lower wiring structure located on the lower surface of the base insulating layer, a lower contact electrode connecting the first source / drain pattern and the lower wiring structure, an upper wiring structure located on the source / drain pattern, and an upper contact electrode connecting the second source / drain pattern and the upper wiring structure, wherein the lower contact electrode includes a first contact region extending into the base insulating layer and a second contact region extending from the upper surface of the first contact region into the first source / drain pattern, and the upper surface of the first contact region is located between the lower surface of the gate structure and the lower surface of the source / drain pattern. [Effects of the Invention]

[0009] The semiconductor device according to the present invention has a source / drain pattern formed deeply in the downward direction of the substrate, and may include regions adjacent to the inner sides and bottom surfaces of the source / drain pattern that are doped with carbon (C) or boron (B).

[0010] According to the present invention, in the process of etching the back surface of a substrate to form a back-side power delivery network, the source / drain patterns can be protected from etching material, thereby improving the reliability of the semiconductor device. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view showing a semiconductor device according to one embodiment. [Figure 2] This is a cross-sectional view of the semiconductor device along the line I1-I1' in Figure 1. [Figure 3]It is a cross-sectional view of a semiconductor device along the line I2-I2' in FIG. 1. [Figure 4] It is a cross-sectional view of a semiconductor device along the line I3-I3' in FIG. 1. [Figure 5] It is a cross-sectional view of a semiconductor device along the line I4-I4' in FIG. 1. [Figure 6] It is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 7] It is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 8] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 9] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 10] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 11] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 12] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 13] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 14] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 15] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 16] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 17] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 18] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 19] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 20]It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 21] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 22] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 23] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 24] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 25] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 26] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 27] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 28] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 29] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 30] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 31] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment. [Figure 32] It is a process cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. The present invention can be implemented in various different forms and is not limited to the embodiments described in this specification.

[0013] To clearly illustrate the present invention, irrelevant parts have been omitted, and the same or similar reference numerals are used throughout the specification for identical or similar components.

[0014] Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrarily indicated for the sake of explanation, and therefore the present invention is not necessarily limited to those shown. In the drawings, the thicknesses are shown enlarged to clearly represent various layers and regions. Also, in the drawings, the thicknesses of some layers and regions are shown exaggerated for the sake of explanation.

[0015] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on top of" another part, this includes not only the case where it is "directly above" the other part, but also the case where the other part is in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on top of" a reference part means being located above or below the reference part, and does not necessarily mean being located "up" in the opposite direction of gravity.

[0016] Furthermore, when a part of the specification "includes" a certain component, unless otherwise stated, this does not mean that other components are excluded, but rather that other components may be included.

[0017] Furthermore, throughout the specification, "on a plane" means when the subject is viewed from above, and "on a cross-section" means when the subject is viewed from the side of a cross-section obtained by cutting the subject perpendicularly.

[0018] In the drawings relating to a semiconductor device according to one embodiment, a GAA (Gate All Around) and an MBCFET (Multi-Bridge Channel Field Effect Transistor) including nanowires or nanosheets are shown exemplarily, but are not limited thereto. Of course, the semiconductor device may include a fin-type transistor (FinFET) including a channel structure with a fin-shaped pattern, a tunneling transistor (tunneling FET), a 3D-SFET (3D Stack Field Effect Transistor) structure, and a CFET (Complementary Field Effect Transistor) structure, depending on the embodiment.

[0019] A semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings.

[0020] Figure 1 is a plan view showing a semiconductor device according to one embodiment. Figures 2 to 4 are cross-sectional views showing a semiconductor device according to one embodiment. Specifically, Figure 2 is a cross-sectional view of the semiconductor device along the line I1-I1' in Figure 1, and Figure 3 is a cross-sectional view of the semiconductor device along the line I2-I2' in Figure 1. Figure 4 is a cross-sectional view of the semiconductor device along the line I3-I3' in Figure 1. Figure 5 is a cross-sectional view of the semiconductor device along the line I4-I4' in Figure 1.

[0021] Referring to Figures 1 to 5, a semiconductor device according to one embodiment includes a base insulating layer 101, a channel structure CH located on the base insulating layer 101, a gate structure GS surrounding the channel structure CH, and source / drain patterns 150 located on both sides of each channel structure CH.

[0022] The base insulating layer 101 is an insulating substrate. The base insulating layer 101 includes oxides, nitrides, oxynitrides, or combinations thereof. For example, the base insulating layer 101 includes silicon oxide (SiO2). The base insulating layer 101 is shown as a single film, but this is for illustrative purposes only and is not limited thereto. The base insulating layer 101 is formed by filling the etched portion with an insulating material after the substrate 10 (see Figure 5), which will be described later, has been etched. In one embodiment, the base insulating layer 101 includes an insulating material having an etching selectivity ratio with the source / drain pattern 150, which will be described later.

[0023] In Figures 2 to 5, the base insulating layer 101 is shown as a single layer, but the base insulating layer 101 may consist of two or more layers. In this case, the two or more layers may contain different insulating materials or the same insulating material.

[0024] The base insulating layer 101 includes a first surface and a second surface that are opposite to each other. The first and second surfaces of the base insulating layer 101 consist of planes parallel to a first direction D1 and a second direction D2 that intersects the first direction D1. For example, the first surface of the base insulating layer 101 is the top surface and the second surface is the bottom surface. The top surface of the base insulating layer 101 is the surface opposite the bottom surface of the base insulating layer 101 in a third direction D3. The third direction D3 is perpendicular to the first direction D1 and the second direction D2. The bottom surface of the base insulating layer 101 is referred to as the back side of the base insulating layer 101. In some embodiments, the logic circuits of the cell region are realized on the top surface of the base insulating layer 101.

[0025] The base insulating layer 101 includes a protruding region 103 that protrudes from the first surface. The protruding region 103 is a portion that protrudes from the upper surface of the base insulating layer 101 in a third direction D3. The protruding region 103 is formed when the lower pattern BP (see Figure 8), which will be described later, is etched, and the etched portion is filled with an insulating material.

[0026] In one embodiment, the protruding region 103 includes a recess region RC formed in the direction toward the upper surface of the base insulating layer 101. The recess region RC is formed in the source / drain recess 150R (see Figure 10) formation process described later, by recessing the lower pattern BP (see Figure 10) deeply to the portion adjacent to the upper surface of the base insulating layer 101. The remaining lower pattern BP region that is not recessed is then replaced with insulating material to form the protruding region 103.

[0027] The recess region RC gradually narrows in width as it approaches the upper surface of the base insulating layer 101. The bottom surface of the recess region RC is located at a higher level than the upper surface of the base insulating layer 101.

[0028] Inside the recess region RC is the source / drain pattern 150, which will be described later. At least a portion of the source / drain pattern 150 is surrounded by the protruding region 103. A portion of the source / drain pattern 150 that is located at a level lower than the upper surface of the protruding region 103 is surrounded by the protruding region 103.

[0029] Referring to Figures 3 and 4, the protruding regions 103 are arranged on the upper surface of the base insulating layer 101, spaced apart from each other in the second direction D2. Referring to Figure 2, each protruding region 103 extends in the first direction D1. The source / drain patterns 150 are arranged on each protruding region 103, spaced apart from each other in the first direction D1.

[0030] The protruding region 103 contains an insulating material. The protruding region 103 contains silicon oxide (SiO2), silicon nitride (SiN X This includes silicon oxynitride (SiON), or a combination thereof. In the embodiment, the protruding region 103 and the remaining region of the base insulating layer 101 are integrated. In this case, the boundary between the protruding region 103 and the remaining region of the base insulating layer 101 is not visible.

[0031] The channel structures CH are located on the upper surface of the base insulating layer 101. As shown in Figures 2 and 3, the channel structures CH are located on the protruding region 103. The channel structures CH are arranged spaced apart in a first direction D1 on the protruding region 103. Each channel structure CH includes a first channel pattern 110a, a second channel pattern 110b, a third channel pattern 110c, and a fourth channel pattern 110d. The multiple channel patterns 110a, 110b, 110c, and 110d are arranged spaced apart from each other in a third direction D3. As an example, each of the multiple channel patterns 110a, 110b, 110c, and 110d has a sheet-like structure. Each channel pattern 110a, 110b, 110c, and 110d is a nanosheet with a thickness of several nanometers along the third direction D3.

[0032] The channel structure CH provides a path for current to flow between the source / drain patterns 150, which will be described later. Referring to Figure 2, the channel structure CH is positioned between the source / drain patterns 150 and connects them. The channel structure CH penetrates a portion of the gate structure GS in a direction that intersects the direction in which the gate structure GS extends (for example, the first direction D1), which will be described later. In Figure 2, the channel structure CH shows four channel patterns 110a, 110b, 110c, and 110d arranged spaced apart in the third direction D3, but is not limited to this, and the number of stacked channel patterns 110a, 110b, 110c, and 110d included in one channel structure CH can be varied in various ways.

[0033] The channel structure CH contains a semiconductor material. For example, the channel structure CH includes group IV semiconductors such as Si and Ge, group III-V compound semiconductors, group II-VI compound semiconductors, etc. In the embodiment, a protruding region 103 is located at the bottom of the channel structure CH. The protruding region 103 is located between the lowest subgate structure S_GS among the multiple subgate structures S_GS described later and the upper surface of the base insulating layer 101. In the embodiment, the channel structure CH overlaps with the protruding region 103 in the third direction D3. At least a portion of the upper surface of the protruding region 103 is in contact with the lower surface of the lowest subgate structure S_GS among the multiple subgate structures S_GS. In the embodiment, the recess RC formed in the protruding region 103 does not overlap with the channel structure CH in the third direction D3.

[0034] Referring to Figures 2 and 3, a semiconductor device according to one embodiment further includes a field insulating layer 105 located on the base insulating layer 101. The field insulating layer 105 is located between two protruding regions 103 adjacent to each other in the second direction D2. The field insulating layer 105 is not located on the upper surface of the protruding regions 103.

[0035] The field insulating layer 105 is located on the upper surface of the base insulating layer 101 and on the side surface of the protruding region 103. The field insulating layer 105 is located on both sides of the protruding region 103. The field insulating layer 105 completely covers the side surface of the protruding region 103. Contrary to what is shown, the field insulating layer 105 may also cover a portion of the side surface of the protruding region 103. In such a case, a portion of the protruding region 103 protrudes further in the third direction D3 than the upper surface of the field insulating layer 105. In the embodiment, the field insulating layer 105 includes a portion of the source / drain pattern 150 described later and a portion of it overlapping in the second direction D2. Specifically, in the embodiment, the source / drain pattern 150 is also located inside the recess region RC inside the protruding region 103, and a portion of the source / drain pattern 150 located inside the recess region RC overlaps with the field insulating layer 105 in the second direction D2. In the region located at a level lower than the lower surface of the gate structure GS, which will be described later, filling layers 151b and 152b are located between the field insulating layer 105 and the liner layers 151a and 152a.

[0036] The field insulating layer 105 includes, for example, an oxide, nitride, oxynitride, or a combination thereof. While the field insulating layer 105 is shown as a single film, this is for illustrative purposes only and is not limited thereto.

[0037] The gate structure GS is located on the base insulating layer 101. A protruding region 103 or a field insulating layer 105 is located between the gate structure GS and the upper surface of the base insulating layer 101. The gate structure GS extends in a direction different from the direction in which the protruding region 103 extends on the base insulating layer 101. For example, the gate structure GS extends in a direction intersecting the direction in which the protruding region 103 extends on the base insulating layer 101 (e.g., a second direction D2). The gate structure GS is located on the base insulating layer 101. The gate structures GS are arranged spaced apart from each other in a first direction D1. The gate structure GS includes a sub-gate structure S_GS and a main gate structure M_GS. The sub-gate structure S_GS is located on the base insulating layer 101, and the main gate structure M_GS is located on the sub-gate structure S_GS.

[0038] Each subgate structure S_GS consists of several layers. For example, each subgate structure S_GS includes a subgate electrode 120S and a subgate insulating film 130S. The subgate structures S_GS and channel patterns 110a, 110b, 110c, and 110d are stacked alternately in the third direction D3. Figure 2 shows four subgate structures S_GS arranged spaced apart in the third direction D3, but the number of spaced subgate structures S_GS is not limited to this. For example, a gate structure GS may also contain three subgate structures S_GS.

[0039] The sub-gate electrodes 120S are located on the protruding region 103. Multiple sub-gate electrodes 120S are located on the protruding region 103, spaced apart from each other. Multiple sub-gate electrodes 120S and multiple channel patterns 110a, 110b, 110c, and 110d are stacked alternately in a repeating manner. At least one of the upper and lower surfaces of the multiple channel patterns 110a, 110b, 110c, and 110d is covered by the sub-gate electrodes 120S. For example, the lower surface of the first channel pattern 110a is covered by the sub-gate electrodes 120S, and the upper surface of the fourth channel pattern 110d is covered by the sub-gate electrodes 120S. The upper and lower surfaces of the second channel pattern 110b and the third channel pattern 110c are covered by the sub-gate electrodes 120S.

[0040] The sub-gate electrode 120S includes at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxynitride. Examples of sub-gate electrode 120S include: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride (TaC The following are included, but are not limited to, conductive metal oxides and conductive metal oxynitrides, including, but are not limited to, oxidized forms of the above-mentioned substances.

[0041] The subgate insulating film 130S is positioned along the periphery of the multiple channel patterns 110a, 110b, 110c, and 110d. The subgate insulating film 130S is interposed between the multiple channel patterns 110a, 110b, 110c, and 110d and the subgate electrode 120S. The subgate insulating film 130S contains various insulating materials. Although not clearly shown in Figure 2, a semiconductor device according to one embodiment may further include an inner gate spacer located between the subgate insulating film 130S and the source / drain pattern 150, which will be described later.

[0042] In one embodiment, the subgate insulating film 130S is shown as a single film, but is not limited to this. For example, the subgate insulating film 130S consists of a multilayer film containing silicon oxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material includes a material with a dielectric constant greater than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0043] The main gate structure M_GS is located on the sub-gate structure S_GS and on multiple channel patterns 110a, 110b, 110c, and 110d. The main gate structure M_GS is located on the upper surface of channel pattern 110a, which is the uppermost of the multiple channel patterns 110a, 110b, 110c, and 110d. Referring to Figure 5, the main gate structure M_GS is also located on the field insulating layer 105. The main gate structure M_GS covers both sides of the sub-gate structure S_GS.

[0044] The main gate structure M_GS includes a main gate electrode 120M and a main gate insulating film 130M.

[0045] The main gate electrode 120M is located on the subgate structure S_GS and the multiple channel patterns 110a, 110b, 110c, and 110d. The main gate electrode 120M extends in a direction intersecting the protruding region 103. At least a portion of the main gate electrode 120M is located on a structure in which the subgate electrode 120S and the multiple channel patterns 110a, 110b, 110c, and 110d are alternately stacked. The remaining portion of the main gate electrode 120M covers the sides of the structure in which the subgate electrode 120S and the multiple channel patterns 110a, 110b, 110c, and 110d are alternately stacked. Each of the four faces of the multiple channel patterns 110a, 110b, 110c, and 110d are surrounded by the subgate electrode 120S and / or the main gate electrode 120M.

[0046] The main gate electrode 120M contains the same material as the sub-gate electrode 120S. For example, the main gate electrode 120M contains at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxynitride.

[0047] The main gate insulating film 130M extends along the side surface of the main gate electrode 120M. The main gate insulating film 130M also extends along the side surface of the gate spacer 142, which will be described later. The main gate insulating film 130M contains various insulating materials. The main gate insulating film 130M contains the same material as the subgate insulating film 130S.

[0048] In one embodiment, the main gate insulating film 130M is shown as a single film, but the embodiment is not limited to this. For example, the main gate insulating film 130M consists of a multilayer film containing silicon oxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material includes a material with a dielectric constant greater than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0049] A semiconductor device according to one embodiment may further include a capping layer 141 and a gate spacer 142.

[0050] The gate spacer 142 is located on the side surface of the main gate electrode 120M. The gate spacer 142 is located on the channel structure CH. The gate spacer 142 is not located on the side surface of the sub-gate electrode 120S. The gate spacer 142 is not located on the side surfaces of the channel patterns 110a, 110b, 110c, and 110d. The gate spacer 142 is not located between the protruding region 103 and the multiple channel patterns 110a, 110b, 110c, and 110d. The gate spacer 142 is not located between the multiple channel patterns 110a, 110b, 110c, and 110d adjacent to the third direction D3. The gate spacer 142 is shown as a single film, but this is for illustrative purposes only and is not limited thereto.

[0051] The gate spacer 142 is, for example, silicon nitride (SiN X This includes at least one of the following: silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbide (SiOC), and combinations thereof. The gate spacer 142 is shown as a single film, but this is for illustrative purposes only and is not limited thereto.

[0052] The capping layer 141 is located on the main gate structure M_GS and the gate spacer 142. The top and sides of the capping layer 141 are covered by the first interlayer insulating layer 171, which will be described later. Contrary to what is shown in the diagram, the capping layer 141 may be located between the gate spacers 142.

[0053] The capping layer 141 includes, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The capping layer 141 includes a material having an etching selectivity ratio with respect to the first interlayer insulating layer 171, which will be described later.

[0054] The source / drain pattern 150 is located on the upper surface of the base insulating layer 101. A protruding region 103 is located between the source / drain pattern 150 and the upper surface of the base insulating layer 101. Channel structures CH and gate structures GS are located between the source / drain patterns 150. Multiple source / drain patterns 150 and multiple channel structures CH are arranged alternately along the first direction D1 from which the protruding region 103 extends.

[0055] In the embodiment, the source / drain pattern 150 extends into the interior of the protruding region 103 along the third direction D3. The protruding region 103 is located between the multiple source / drain patterns 150. Referring to Figure 2, the source / drain pattern 150 extends further below the lower surface of the gate structure GS. The lower surface of the source / drain pattern 150 is lower than the level lower than the lower surface of the gate structure GS. Specifically, the lower surface of the source / drain pattern 150 is located at a level lower than the lower surface of the lowest sub-gate electrode 120S among the multiple sub-gate electrodes 120S located spaced apart from each other in the third direction D3 on the protruding region 103. In the embodiment, the distance d1 (referred to as the first distance) between the lower surface of the gate structure GS and the lower surface of the source / drain pattern 150 is greater than or equal to about 20 nm and less than or equal to about 100 nm.

[0056] Referring to Figures 2 to 4, the lower surface of the source / drain pattern 150 is located at a higher level than the upper surface of the base insulating layer 101. In other words, the source / drain pattern 150 extends to a level higher than the upper surface of the base insulating layer 101.

[0057] However, the source / drain pattern 150 may extend through the protruding region 103 into the interior of the base insulating layer 101. In this case, the lower surface of the field insulating layer 105 is located at a lower level than the upper surface of the base insulating layer 101.

[0058] The lower surface of the source / drain pattern 150 is located at a lower level than the upper surface of the field insulation layer 105. Referring to Figures 3 and 4, the source / drain pattern 150 includes a region that overlaps with the field insulation layer 105 in the second direction D2. The region of the source / drain pattern 150 located inside the recess region RC overlaps with the field insulation layer 105 in the second direction D2. A protruding region 103 is located between the source / drain pattern 150 and the field insulation layer 105 in the region where the source / drain pattern 150 and the field insulation layer 105 overlap. In one embodiment, the lower surface of the source / drain pattern 150 is located even more adjacent to the lower wiring structure 420 compared to the upper surface of the first contact region 195a, which will be described later.

[0059] In one embodiment, the ratio d1 / d2 of the first distance d1 to the second distance d2 between the upper surface of the channel pattern 110a, which is the uppermost of the channel patterns 110a, 110b, 110c, and 110d, and the upper surface of the protruding region 103, is, for example, greater than or equal to about 0.5 and less than or equal to about 1.0. The ratio d1 / d2 of the first distance d1 to the second distance d2 is, for example, greater than or equal to about 0.6 and less than or equal to about 0.9.

[0060] In one embodiment, the ratio d1 / (d1+d2) of the first distance d1 to the distance d1+d2 between the upper and lower surfaces of the source / drain pattern 152 is, for example, greater than or equal to about 0.2 and less than or equal to about 0.6. The ratio d1 / (d1+d2) of the first distance d1 to the distance d1+d2 between the upper and lower surfaces of the source / drain pattern 152 is, for example, greater than or equal to about 0.3 and less than or equal to about 0.5.

[0061] At least a portion of each of the source / drain patterns 150 is surrounded by the protruding region 103. Specifically, referring to Figures 2 to 4, the entire area of ​​the side and bottom surfaces of the source / drain pattern 150 located within the recess region RC is surrounded by the protruding region 103. In this embodiment, the side and bottom surfaces of the source / drain pattern 150 located within the recess region RC are in contact with the inner surface and bottom surface of the protruding region 103, respectively.

[0062] The source / drain pattern 150 is arranged in the second direction D2. Referring to Figures 1, 3, and 4, the multiple protruding regions 103 are spaced apart on the base insulating layer 101 along the second direction D2, and the source / drain pattern 150 is located on each of the protruding regions 103. The source / drain pattern 150 is positioned to overlap each of the protruding regions 103 in the third direction D3.

[0063] The source / drain patterns 150 are located on both sides of the channel structure CH or the subgate structure S_GS. Specifically, the two source / drain patterns 150 located on one protruding region 103 are spaced apart in a direction (e.g., a first direction D1) that intersects the direction in which the gate structure GS extends across the channel structure CH and / or subgate structure S_GS. The source / drain patterns 150 are in direct contact with the channel structure CH or the subgate structure S_GS. The source / drain patterns 150 are in direct contact with the subgate insulating film 130S of the subgate structure S_GS. The sides and bottom surfaces of the source / drain patterns 150, which are located at a level lower than the bottom surface of the lowest subgate gate 120S among the multiple subgate gates 120S located spaced apart in a third direction D3, are in direct contact with the protruding region 103.

[0064] Although not shown in the diagram, an inner spacer is further positioned between the source / drain pattern 150 and the subgate insulating film 130S. The inner spacer is made of silicon nitride (SiN X), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbide (SiOC), and at least one combination thereof.

[0065] The source / drain pattern 150 is composed of an epitaxial layer formed by selective epitaxial growth (SEG). The source / drain pattern 150 is formed by selective epitaxial growth after removing at least a portion of the semiconductor pattern stacked on the base insulating layer 101. When the semiconductor pattern stacked on the base insulating layer 101 is removed, a portion of the lower pattern BP (see Figure 10) located beneath the semiconductor pattern is also removed, forming the recess region RC shown in Figures 2 to 4. As a result, the source / drain pattern 150 is also formed inside the recess region RC by selective epitaxial growth.

[0066] The source / drain pattern 150 includes liner layers 151a and 152a and filling layers 151b and 152b, respectively. The liner layers 151a and 152a are located outside the filling layers 151b and 152b. The sides and bottom surfaces of the filling layers 151b and 152b are surrounded by the liner layers 151a and 152a. The liner layers 151a and 152a are in direct contact with the subgate structure S_GS and the channel structure CH. The filling layers 151b and 152b are located on top of the liner layers 151a and 152a. The filling layers 151b and 152b and the liner layers 151a and 152a have top surfaces of substantially the same height. However, it is not limited to this, and unlike the one shown in Figure 2, the filling layers 151b, 152b and the liner layers 151a, 152a have upper surfaces of different heights in some areas.

[0067] In one embodiment, the liner layers 151a and 152a are conformally positioned along the interfaces with the gate structure GS and the channel structure CH, and with the protruding region 103. Filling layers 151b and 152b are located on the inner surfaces of the liner layers 151a and 152a.

[0068] Specifically, referring to Figures 2 to 4, the liner layers 151a and 152a in the region where the source / drain pattern 150 overlaps with the channel structure CH and gate structure GS in the first direction D1 are located between the channel structure CH and gate structure GS and the filling layers 151b and 152b. The liner layers 151a and 152a in the region where the source / drain pattern 150 overlaps with the channel structure CH and gate structure GS in the first direction D1 extend along the sides of the filling layers 151b and 152b.

[0069] In the region where the source / drain pattern 150 overlaps the protruding region 103 in the first direction D1 or the second direction D2, the liner layers 151a and 152a are located between the protruding region 103 and the filling layers 151b and 152b. In the region where the source / drain pattern 150 overlaps the protruding region 103 in the first direction D1 or the second direction D2, the liner layers 151a and 152a extend along the sides and bottom surfaces of the filling layers 151b and 152b. Referring to Figures 2 to 4, the liner layers 151a and 152a are conformally located along the entire area of ​​the sides and bottom surfaces of the recess region RC. In the region where the filling layers 151b and 152b are located at a level lower than the bottom surface of the gate structure GS, the entire side area is surrounded by the liner layers 151a and 152a. In the region located at a level lower than the lower surface of the gate structure GS, the liner layers 151a and 152a are located between the field insulating layer 105 and the filling layers 151b and 152b.

[0070] The liner layers 151a and 152a are located on the sides of the filling layers 151b and 152b. In one embodiment, the liner layers 151a and 152a are located on only a portion of the entire surface area of ​​the filling layers 151b and 152b. Referring to Figure 2, the liner layers 151a and 152a are located on the entire surface area of ​​two opposing sides 150b_S1 and 150b_S2 of the filling layers 151b and 152b along the first direction D1. Referring to Figures 3 and 4, the liner layers 151a and 152a are located on only a portion of two opposing sides 150b_S3 and 150b_S4 of the filling layers 151b and 152b along the second direction D2. Specifically, referring to Figures 3 and 4, the liner layers 151a and 152a in the cross-sectional view consisting of the second direction D2 and the third direction D3 are located on the sides of the filling layers 151b and 152b that overlap with the protruding region 103 and the first direction D1, but not on the sides of the filling layers 151b and 152b that do not overlap with the protruding region 103 and the first direction D1. This is due to the process characteristics in which the liner layers 151a and 152a are formed through a selective epitaxial growth process that uses multiple channel patterns 110a, 110b, 110c, 110d and the lower pattern BP (see Figures 10 and 11) as seeds.

[0071] Referring to Figures 2 to 4, the sides of the liner layers 151a and 152a are in contact with the protruding region 103, the channel patterns 110a, 110b, 110c, and 110d, and the sub-gate electrode 120S, but are not in contact with the first interlayer insulating layer 171, which will be described later.

[0072] Referring to Figure 3, the lowest level region of the entire lower surface area of ​​the filling layer 152b (the region closest to the upper surface of the lower wiring structure 420) is at a lower level than the lowest level region of the entire upper surface area of ​​the field insulation layer 105 (the region closest to the upper surface of the lower wiring structure 420). Alternatively, the lowest level region of the entire lower surface area of ​​the liner layer 152a (the region closest to the upper surface of the lower wiring structure 420) is at a lower level than the lowest level region of the entire upper surface area of ​​the field insulation layer 105 (the region closest to the upper surface of the lower wiring structure 420).

[0073] The source / drain pattern 150 includes a semiconductor material. For example, the source / drain pattern 150 includes silicon (Si) or germanium (Ge). Furthermore, the source / drain pattern 150 includes, for example, a binary compound or ternary compound containing at least two of the following: carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the source / drain pattern 150 includes, but is not limited to, silicon (Si), silicon-germanium (SiGe), germanium (Ge), and silicon carbide (SiC).

[0074] The liner layers 151a and 152a and the filling layers 151b and 152b contain different semiconductor materials. For example, liner layers 151a and 152a contain silicon (Si), while filling layers 151b and 152b contain silicon germanium (SiGe). In other examples, liner layers 151a and 152a and filling layers 151b and 152b may contain the same material. In this case, the concentrations of the material contained in liner layers 151a and 152a and filling layers 151b and 152b will differ. For example, if liner layers 151a and 152a and filling layers 151b and 152b both contain silicon germanium (SiGe), the germanium (Ge) concentration in filling layers 151b and 152b will be greater than, but not limited to, the germanium (Ge) concentration in liner layers 151a and 152a. As another example, the filling layers 151b and 152b may contain the same material as the liner layers 151a and 152a, and the filling layers 151b and 152b and the liner layers 151a and 152a may have the same concentration of constituent material.

[0075] In one embodiment, the liner layers 151a and 152a contain a material having an etching selectivity ratio with respect to the substrate 10 (see Figures 20 and 21). In this case, damage to the source / drain pattern 150 by the etching material is prevented during the etching process of the first substrate 10, which will be described later. As an example, if the semiconductor device according to one embodiment is NMOS (i.e., doped with N-type impurities) and the first substrate 10 contains silicon (Si), then the liner layers 151a and 152a contain silicon germanium (SiGe) doped with carbon (C). In this case, the liner layers 151a and 152a have an etching selectivity ratio with respect to the first substrate 10, thereby protecting the source / drain pattern 150 from damage by the etching material during processes excluding the first substrate 10.

[0076] For example, if the semiconductor device according to one embodiment is PMOS (i.e., doped with P-type impurities) and the first substrate 10 contains silicon (Si), then the liner layers 151a and 152a contain silicon germanium (SiGe) doped with boron (B). In this case, the liner layers 151a and 152a have an etching selectivity ratio with respect to the first substrate 10, thereby protecting the source / drain pattern 150 from damage by etching material in processes excluding the first substrate 10.

[0077] In one embodiment, the liner layers 151a and 152a contain silicon germanium (SiGe) doped with carbon (C) or boron (B) at a certain concentration or less. The silicon germanium (SiGe) contained in the liner layers 151a and 152a has a carbon (C) or boron (B) doping concentration of, for example, 0.1 at% or less and greater than 0 at%.

[0078] In one embodiment of a semiconductor device, during the etching process of the first substrate 10, the first substrate 10 is completely removed without damaging the source / drain pattern 150 by the etching material. Subsequently, the area where the first substrate 10 was located is filled with a base insulating layer 101. By completely replacing the first substrate 10 with the base insulating layer 101, the leakage current flowing between adjacent source / drain patterns 150 is reduced, thereby improving the reliability of the semiconductor device.

[0079] A semiconductor device according to one embodiment further includes a lower wiring structure 420 located on the lower surface of the base insulating layer 101. The upper surface of the lower wiring structure 420 is in contact with the lower surface of the lower contact electrode 195 in a portion of the area. The lower wiring structure 420 includes a lower conductive pattern 421 and a lower wiring insulating layer 422. The lower conductive pattern 421 includes lower wirings arranged spaced apart in a third direction D3 and lower wiring vias connecting two lower wirings. The lower conductive pattern 421 is located between the lower wiring insulating layers 422. The lower wiring insulating layers 422 surround the lower conductive pattern 421. That is, the lower wiring insulating layer 422 covers the lower conductive pattern 421, and the lower conductive pattern 421 is located within the lower wiring insulating layers 422.

[0080] The lower conductive pattern 421 contains a metal (for example, copper). The lower wiring insulating layer 422 contains, for example, silicon oxide (SiO2), silicon nitride (SiN X ), comprising at least one of silicon oxynitride (SiON), or a low dielectric constant film.

[0081] A semiconductor device according to one embodiment includes a lower contact electrode 195 that connects a lower wiring structure 420 and a source / drain pattern 150. The lower contact electrode 195 connects at least one source / drain pattern 151 of the source / drain pattern 150 to the lower wiring structure 420. Referring to Figures 2 and 4, the lower contact electrode 195 penetrates the base insulating layer 101 in a third direction D3 and connects to the first source / drain pattern 151. Referring to Figure 1, the lower contact electrode 195 in the plan view is shown to have a rectangular shape, but is not limited to this, and the lower contact electrode 195 may also have a circular or other polygonal shape other than a rectangle.

[0082] In one embodiment, the lower contact electrode 195 includes a first contact region 195a located on the upper surface of the lower wiring structure 420 and a second contact region 195b located on the upper surface of the first contact region 195a. The first contact region 195a extends from the upper surface of the lower wiring structure 420 along a third direction D3 into the interior of the base insulating layer 101. The first contact region 195a penetrates the upper surface of the base insulating layer 101.

[0083] The first contact region 195a has an inclined side surface in which the width of the upper region is narrower than the width of the lower region due to the aspect ratio. The width of the first contact region 195a along the first direction D1 is even wider than the width of the source / drain pattern 150 along the first direction D1. Referring to Figure 2, the width of the upper surface of the first contact region 195a along the first direction D1 is even wider than the width of the source / drain pattern 150 along the first direction D1.

[0084] Referring to Figure 4, the width of the first contact region 195a along the second direction D2 on the same plane as the interface between the upper surface of the base insulating layer 101 and the lower surface of the field insulating layer 105 is even wider than the width of the protruding region 103 along the second direction D2. In one embodiment, the first contact region 195a penetrates the base insulating layer 101 and extends further into the interior of the protruding region 103 along the third direction D3. The side surface of the first contact region 195a in the region where it overlaps with the field insulating layer 105 in the second direction D2 is located along the side surface of the field insulating layer 105.

[0085] In one embodiment, the upper surface of the first contact region 195a is located at a higher level than the lower surface of the source / drain pattern 150. For example, referring to Figure 2, the upper surface of the first contact region 195a is located between the upper and lower surfaces of the first source / drain pattern 151 and the second source / drain pattern 152, which is spaced apart in the first direction D1. Specifically, the upper surface of the first contact region 195a is located at a higher level than the lower contact electrode 195 of the source / drain pattern 150, the first source / drain pattern 151 which overlaps in the third direction D3, and the lower surface of the second source / drain pattern 152 which is adjacent in the first direction D1.

[0086] The second contact region 195b extends from the upper surface of the first contact region 195a along the third direction D3 into the interior of the first source / drain pattern 151. Referring to Figures 2 and 4, the second contact region 195b has an inclined side surface in which the upper region is even narrower than the lower region in terms of aspect ratio. In one embodiment, the width of the second contact region 195b along the first direction D1 is the same as or narrower than the width of the source / drain pattern 150 along the first direction D1. In one embodiment, the width of the second contact region 195b along the second direction D2 is the same as or narrower than the width of the source / drain pattern 150 along the second direction D2.

[0087] Referring to Figure 2, the second contact region 195b at the boundary between the first contact region 195a and the second contact region 195b is even narrower in width along the first direction D1 compared to the first contact region 195a. As a result, the gate contact portion 190 includes a bent portion located at the boundary between the first contact region 195a and the second contact region 195b. In one embodiment, the lower surface of the source / drain pattern 150 is located at a lower level than the bent portion located at the boundary between the first contact region 195a and the second contact region 195b.

[0088] Specifically, the lowest level region of the entire lower surface area of ​​the liner layer 152a (the region closest to the upper surface of the lower wiring structure 420) is located at a lower level than the bent portion located at the boundary between the first contact area 195a and the second contact area 195b. Specifically, the lowest level region of the entire lower surface area of ​​the filling layer 152b (the region closest to the upper surface of the lower wiring structure 420) is located at a lower level than the bent portion located at the boundary between the first contact area 195a and the second contact area 195b.

[0089] In one embodiment, the upper surface of the second contact region 195b is located between the lower surface of the gate structure GS and the upper surface of the source / drain pattern 150. The upper surface of the second contact region 195b is located at a higher level than the upper surface of the protruding region 103. The second contact region 195b overlaps with at least one of the channel patterns 110a, 110b, 110c, and 110d in the first direction D1. Referring to Figure 2, the second contact region 195b is shown to overlap in the first direction D1 only with the lowest channel pattern 110d among a plurality of channel patterns 110a, 110b, 110c, and 110d located spaced apart in the third direction D3, but is not limited to this. For example, the second contact region 195b overlaps in the first direction D1 with both the lowest channel pattern 110d and the channel pattern 110c located above it.

[0090] The lower contact electrode 195 includes at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional (2D) material. The metal includes at least one of the following: titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride includes at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0091] A semiconductor device according to one embodiment further includes a barrier pattern 197 located along the side and top surfaces of the lower contact electrode 195. The barrier pattern 197 covers the side and top surfaces of the lower contact electrode 195. The barrier pattern 197 includes a metal, a metal alloy, and a conductive metal nitride. The metal includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride includes at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN). Unlike those shown in Figures 1 to 5, a semiconductor device according to one embodiment may not include the barrier pattern 197.

[0092] A semiconductor device according to one embodiment further includes a silicide layer 199 located between the second contact region 195b and the first source / drain pattern 151. The silicide layer 199 extends along at least a portion of the side and top surfaces of the second contact region 195b between the first source / drain pattern 151 and the second contact region 195b.

[0093] A semiconductor device according to one embodiment further includes a first interlayer insulating layer 171. The first interlayer insulating layer 171 is located on the side surface of the gate spacer 142, the side surface of the capping layer 141, and the upper surface of the source / drain pattern 150. Referring to Figures 3 and 4, the first interlayer insulating layer 171 covers at least a portion of the side surface of the source / drain pattern 150. The first interlayer insulating layer 171 covers the field insulating layer 105. The first interlayer insulating layer 171 does not cover the upper surface of the capping layer 141.

[0094] Referring to Figure 3, the lowest level region of the entire lower surface area of ​​the filling layer 152b (the region closest to the upper surface of the lower wiring structure 420) is at a lower level than the lowest level region of the entire lower surface area of ​​the first interlayer insulating layer 171 (the region closest to the upper surface of the lower wiring structure 420). Alternatively, the lowest level region of the entire lower surface area of ​​the liner layer 152a (the region closest to the upper surface of the lower wiring structure 420) is at a lower level than the lowest level region of the entire lower surface area of ​​the first interlayer insulating layer 171 (the region closest to the upper surface of the lower wiring structure 420).

[0095] The first interlayer insulating layer 171 includes, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material. Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane(HSQ), Bis-benzoCycloButene(BCB), TetraMethylOrthoSilicate(TMOS), OctaMethyleyCloTetraSiloxane(OMCTS), HexaMethylDiSiloxane(HMDS), TriMethylSilyl Borate(TMSB), DiAcetoxyDitertiaryButoSiloxane(DADBS), TriMethylSilil Polyimide nanofoams like Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated This includes, but is not limited to, carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof.

[0096] A semiconductor device according to one embodiment includes an upper contact electrode 191. The upper contact electrode 191 is located on a source / drain pattern 150. The upper contact electrode 191 is connected to at least one second source / drain pattern 152, which is not connected to a lower contact electrode 195 of the multiple source / drain patterns 150, and provides an externally supplied electrical signal or power supply voltage, etc., to the second source / drain pattern 152.

[0097] A semiconductor device according to one embodiment includes a plurality of upper contact electrodes 191. The plurality of upper contact electrodes 191 are arranged along a second direction D2. In this case, separation patterns 173 are located between the upper contact electrodes 191 that are spaced apart along the second direction D2. For example, referring to Figures 1 and 3, the plurality of upper contact electrodes 191 are spaced apart from each other along the second direction D2, and separation patterns 173 are located between each of the upper contact electrodes 191.

[0098] Referring to Figures 1 to 3, the upper surface of the upper contact electrode 191 lies on the same plane as the plane that includes the upper surface of the first interlayer insulating layer 171 and the upper surface of the capping layer 141.

[0099] Referring to Figures 1 and 2, the upper contact electrode 191 penetrates a portion of the first interlayer insulating layer 171 in the third direction D3 in the region where the first interlayer insulating layer 171 overlaps with the second source / drain pattern 152 in the third direction D3. At this time, the lower surface of the upper contact electrode 191 is in contact with the second source / drain pattern 152. Referring to Figure 2, the upper contact electrode 191 is recessed by a predetermined depth from the upper surface of the second source / drain pattern 152 toward the upper surface of the first substrate 10. However, it is not limited to this, and the upper contact electrode 191 may have a lower surface that is in contact with the upper surface of the second source / drain pattern 152. Referring to Figure 3, the upper contact electrode 191 covers at least a portion of the upper and side surfaces of the second source / drain pattern 152.

[0100] The upper contact electrode 191 contains a conductive material. For example, the upper contact electrode 191 contains at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional (2D) material. The metal contains at least one of the following: titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride contains at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0101] A semiconductor device according to one embodiment further includes isolation patterns 173 located between a plurality of upper contact electrodes 191. The isolation patterns 173 are also located between source / drain patterns 150. The isolation patterns 173 electrically isolate adjacent upper contact electrodes 191 from each other. For example, referring to Figures 1 and 3, the isolation patterns 173 are located between a plurality of upper contact electrodes 191 arranged spaced apart from each other in a second direction D2. The isolation patterns 173 include an insulating material, in which case the two upper contact electrodes 191 located on either side of the isolation patterns 173 are electrically isolated from each other. In one embodiment, the isolation patterns 173 have sides that are in contact with the upper contact electrodes 191 located on either side.

[0102] Separation pattern 173 includes an insulating material. For example, separation pattern 173 is silicon nitride (SiN X ), silicon oxide (SiOx), and / or silicon carbonitride (SiCxNy). However, the separation pattern 173 may include, but is not limited to, various insulating materials for electrically separating the upper contact electrodes 191 from each other.

[0103] In one embodiment, the semiconductor device further includes a second interlayer insulating layer 175 located on a first interlayer insulating layer 171, an upper wiring structure 410, and an upper contact via 193.

[0104] The second interlayer insulating layer 175 covers the first interlayer insulating layer 171, a portion of the upper surface of the upper contact electrode 191, the upper surface of the capping layer 141, and the upper surface of the separation pattern 173. The second interlayer insulating layer 175 contains an insulating material. The second interlayer insulating layer 175 contains the same or a different insulating material as the first interlayer insulating layer 171. In one embodiment, if the second interlayer insulating layer 175 contains a different insulating material than the first interlayer insulating layer 171, the boundary between the first interlayer insulating layer 171 and the second interlayer insulating layer 175 may not be visible.

[0105] The upper wiring structure 410 is located on the second interlayer insulating layer 175. The lower surface of the upper wiring structure 410 is in contact with the upper surface of the upper contact via 193, which will be described later, in a portion of the area. The upper wiring structure 410 includes an upper conductive pattern 411 and an upper wiring insulating layer 412. The upper conductive pattern 411 includes upper wiring vias that connect upper wirings arranged spaced apart in the third direction D3 to two upper wirings. The upper conductive pattern 411 is located between the upper wiring insulating layers 412. The upper wiring insulating layers 412 surround the upper conductive pattern 411. That is, the upper wiring insulating layer 412 covers the upper conductive pattern 411, and the upper conductive pattern 411 is located within the upper wiring insulating layer 412.

[0106] The upper conductive pattern 411 contains a metal (for example, copper). The upper wiring insulating layer 412 contains, for example, silicon oxide (SiO2), silicon nitride (SiN X ), comprising at least one of silicon oxynitride (SiON), or a low dielectric constant film.

[0107] The upper contact via 193 is located between the upper wiring structure 410 and the upper contact electrode 191. The upper contact via 193 penetrates a portion of the second interlayer insulating layer 175. The lower surface of the upper contact via 193 is in contact with the upper surface of the upper contact electrode 191, and the upper surface is in contact with a portion of the upper conductive pattern 411 of the upper wiring structure 410. The upper contact via 193 is connected to the second source / drain pattern 152 via the upper contact electrode 191.

[0108] The upper contact via 193 contains a conductive material. For example, the upper contact via 193 contains at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0109] Figure 6 is a cross-sectional view showing a semiconductor device according to one embodiment. The semiconductor device shown in Figure 6 is substantially the same as that of the previous embodiment, so the following explanation will focus on the differences from the previous embodiment. Specifically, the semiconductor device shown in Figure 6 has a width along the second direction D2 of the lower contact electrode 195 that is partially different from that of the previous embodiment.

[0110] Referring to Figure 6, in one embodiment, the width of the lower contact electrode 195 along the second direction D2 is even narrower than the width of the source / drain pattern 150 along the second direction D2.

[0111] Specifically, referring to Figure 6, the width of the first contact region 195a along the second direction D2 on the same plane as the interface between the upper surface of the base insulating layer 101 and the lower surface of the field insulating layer 105 is even narrower than the width of the protruding region 103 along the second direction D2. In one embodiment, the first contact region 195a penetrates the base insulating layer 101 and extends further along the third direction D3 into the protruding region 103 and the first source / drain pattern 151. In one embodiment, a silicide layer 199 is located on the side surface of the region of the first contact region 195a that overlaps with the first source / drain pattern 151 in the second direction D2.

[0112] The second contact region 195b extends from the upper surface of the first contact region 195a along the third direction D3 into the interior of the first source / drain pattern 151. The second contact region 195b has inclined sides, with the upper region being even narrower than the lower region in terms of aspect ratio. In one embodiment, the width of the second contact region 195b along the second direction D2 is narrower than the width of the source / drain pattern 150 along the second direction D2.

[0113] Figure 7 is a cross-sectional view showing a semiconductor device according to one embodiment. As shown in Figure 7, the semiconductor device is substantially the same as that of the previous embodiment, so the following explanation will focus on the differences from the previous embodiment. Specifically, the semiconductor device shown in Figure 7 differs from the previous embodiment in that it further includes a semiconductor pattern SP.

[0114] Referring to Figure 7, in one embodiment, a semiconductor pattern SP is located between the gate structure GS and the protruding region 103. The semiconductor pattern SP shown in Figure 7 is the portion of the lower pattern BP that remained after the process excluding the first substrate 10 and the lower pattern BP (see Figures 20 and 21), which will be described later, and was not completely etched by the etching material.

[0115] The semiconductor pattern SP is located between the sub-gate electrode 120S and the protruding region 103 in the region where the protruding region 103 overlaps with the gate structure GS. Referring to Figure 7, the semiconductor pattern SP has its side surface in contact with the source / drain pattern 150, and its top and bottom surfaces in contact with the bottom surface of the sub-gate electrode 120S and the top surface of the protruding region 103, respectively. The semiconductor pattern SP is not located in the region where the protruding region 103 overlaps with the source / drain pattern 150 in the third direction D3.

[0116] The semiconductor pattern SP includes semiconductor materials such as group IV semiconductors like Si and Ge, group III-V compound semiconductors, and group II-VI compound semiconductors. In one embodiment, the semiconductor pattern SP includes the same material as the channel structure CH.

[0117] Figures 8 to 32 are cross-sectional process views illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0118] Figures 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, and 30 are cross-sectional views corresponding to the region cut along I1-I1' in Figure 1, illustrating a method for manufacturing a semiconductor device according to one embodiment. Figures 9, 11, 13, 15, 17, 19, 21, 23, and 31 are cross-sectional views corresponding to the region cut along I2-I2' in Figure 1, illustrating a method for manufacturing a semiconductor device according to one embodiment. Figures 25, 27, 29, and 32 are cross-sectional views corresponding to the region cut along I3-I3' in Figure 1, illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0119] As shown in Figures 8 and 9, a lower pattern BP and an upper pattern structure U_AP are formed on the first substrate 10.

[0120] Specifically, sacrificial patterns SC_L and active patterns ACT_L are alternately stacked on the first substrate 10 using the epitaxial growth method, and then a portion of the area is etched to form the upper pattern structure U_AP. At this time, a portion of the first substrate 10 is etched to form the lower pattern BP. Alternatively, the lower pattern BP may be formed by etching both the sacrificial patterns SC_L and ACT_L after they have been grown on the first substrate 10 using the epitaxial growth method.

[0121] The first substrate 10 is SOI (silicon-on-insulator) or bulk silicon. In contrast, the first substrate 10 may be a silicon substrate or may contain, but is not limited to, other materials such as silicon germanium (SiGe), SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0122] The lower pattern BP contains semiconductor materials such as silicon (Si) or germanium (Ge). In contrast, the lower pattern BP may contain compound semiconductors. For example, the lower pattern BP may contain a group IV-IV compound semiconductor or a group III-V compound semiconductor. Group IV-IV compound semiconductors are binary or ternary compounds containing, for example, carbon (C), silicon (Si), germanium (Ge), tin (Sn), or combinations thereof. Group III-V compound semiconductors are binary, ternary, or quaternary compounds formed by bonding group III elements such as aluminum (Al), gallium (Ga), indium (In), or combinations thereof, with group V elements such as phosphorus (P), arsenic (As), antimonium (Sb), or combinations thereof. The sacrificial pattern SC_L contains silicon germanium (SiGe). The active pattern ACT_L contains silicon (Si).

[0123] Next, a field insulating layer 105 is formed that covers the upper surface of the first substrate 10 and at least a portion of the side surface of the lower pattern BP. The field insulating layer 105 is formed by first depositing an insulating layer onto the first substrate 10, the lower pattern BP, and the upper pattern structure U_AP, and then etching a portion of the area. Unlike the illustration, the field insulating layer 105 may also be formed to cover a portion of the side surface of the upper pattern structure U_AP.

[0124] Next, a preliminary gate insulating film 132P, a preliminary main gate electrode 131MP, and a preliminary capping layer 141P are formed on the upper pattern structure U_AP. The preliminary gate insulating film 132P includes, for example, silicon oxide (SiO2), but is not limited thereto. The preliminary main gate electrode 131MP includes, for example, polysilicon, but is not limited thereto. The preliminary capping layer 141P is, for example, silicon nitride (SiN X This includes, but is not limited to, the above. A spare gate spacer 142P is formed on both sides of the spare main gate electrode 131MP.

[0125] As shown in Figures 10 and 11, the preliminary capping layer 141P and the preliminary gate spacer 142P are used as masks to etch at least a portion of the upper pattern structure U_AP to form the source / drain recess 150R. Specifically, a portion of the upper pattern structure U_AP located between the two preliminary main gate electrodes 131MP arranged along the first direction D1 is etched.

[0126] The channel structure CH is formed while the active pattern ACT_L is separated by the formation of the source / drain recess 150R. The channel structure CH is located on both sides of the source / drain recess 150R. Multiple channel patterns 110a, 110b, 110c, 110d and the sacrificial pattern SC_L contained within the channel structure CH are alternately stacked in the third direction D3. In this case, the lengths of each of the multiple channel patterns 110a, 110b, 110c, 110d are either different or the same.

[0127] In one embodiment, during the process of forming the source / drain recess 150R, a portion of the lower pattern BP is etched. For example, as shown in Figures 10 and 11, the lower pattern BP is etched up to the portion adjacent to the interface between the first substrate 10 and the lower pattern BP. Referring to Figures 10 and 11, the bottom surface of the source / drain recess 150R is located at a higher level than the interface between the first substrate 10 and the lower pattern BP. In another embodiment, the source / drain recess 150R penetrates the lower pattern BP and is formed up to a portion of the first substrate 10. In this case, the bottom surface of the source / drain recess 150R is located at a lower level than the interface between the first substrate 10 and the lower pattern BP.

[0128] In one embodiment, when a portion of the lower pattern BP is etched, the field insulating layer 105 located on both sides of the lower pattern BP is used as a mask. In the region where the field insulating layer 105 overlaps with the second direction D2, the width of the source / drain recess 150R along the second direction D2 gradually narrows as it approaches the upper surface of the first substrate 10. As a result, a portion of the lower pattern BP in the region where the field insulating layer 105 overlaps with the second direction D2 remains unetched. Specifically, referring to Figure 11, the lower pattern BP remains unetched between the side surface of the field insulating layer 105 and the source / drain recess 150R. In one embodiment, the portion of the lower pattern BP that remains unetched is then used as a seed for forming the source / drain pattern 150.

[0129] As shown in Figures 12 and 13, a source / drain pattern 150 is formed within the source / drain recess 150R (see Figure 10). The source / drain pattern 150 is formed on the first substrate 10. The source / drain pattern 150 is formed using an epitaxial growth method.

[0130] The source / drain pattern 150 is in direct contact with the channel patterns 110a, 110b, 110c, 110d and the sacrificial pattern SC_L. The source / drain pattern 150 contains silicon (Si), germanium (Ge), or silicon germanium (SiGe). The source / drain pattern 150 consists of several regions having different concentrations from each other. For example, referring to Figures 12 and 13, the source / drain pattern 150 includes liner layers 151a, 152a and filling layers 151b, 152b. The liner layers 151a, 152a and the filling layers 151b, 152b are formed sequentially. The liner layers 151a, 152a and the filling layers 151b, 152b are each formed using an epitaxial growth method.

[0131] First, liner layers 151a and 152a are conformally formed along the inner wall of the source / drain recess 150R. In this process, channel patterns 110a, 110b, 110c, and 110d and the lower pattern BP located on the inner wall of the source / drain recess 150R are used as seeds. Specifically, referring to Figure 12, in a cross-sectional view consisting of a first direction D1 and a third direction D3, liner layers 151a and 152a are formed using channel patterns 110a, 110b, 110c, and 110d and the lower pattern BP as seeds.

[0132] Referring to Figure 13, in the cross-sectional view consisting of the second direction D2 and the third direction D3, liner layers 151a and 152a are formed using the lower pattern BP as a seed. Specifically, as explained with reference to Figures 11 and 12, after a portion of the lower pattern BP is recessed, liner layers 151a and 152a are formed along the remaining inner wall of the lower pattern BP. In the process of forming the source / drain recess 150R, as explained with reference to Figures 10 and 11, a portion of the upper pattern structure U_AP located between the two preliminary main gate electrodes 131MP arranged along the first direction D1 is removed. Therefore, in the cross-sectional view consisting of the second direction D2 and the third direction D3, channel patterns 110a, 110b, 110c, and 110d as shown in Figure 12 are not located on the lower pattern BP. As a result, as shown in Figure 13, in the cross-sectional view consisting of the second direction D2 and the third direction D3, liner layers 151a and 152a are formed only on the inner wall of the lower pattern BP.

[0133] In one embodiment, the liner layers 151a and 152a contain silicon germanium (SiGe) doped with carbon (C) or boron (B). For example, if the semiconductor device according to one embodiment is NMOS, the liner layers 151a and 152a contain silicon germanium (SiGe) doped with carbon (C). For example, if the semiconductor device according to one embodiment is PMOS, the liner layers 151a and 152a contain silicon germanium (SiGe) doped with boron (B).

[0134] Next, filling layers 151b and 152b are formed using liner layers 151a and 152a as seeds. Filling layers 151b and 152b fill the remaining region of the source / drain recess 150R, excluding the region where liner layers 151a and 152a are formed. Referring to Figures 12 and 13, the upper surfaces of liner layers 151a and 152a and filling layers 151b and 152b have upper surfaces that are substantially at the same level as the uppermost channel pattern 110a among the channel patterns 110a, 110b, 110c, and 110d. In one embodiment, liner layers 151a and 152a and filling layers 151b and 152b contain silicon germanium (SiGe). In one embodiment, liner layers 151a and 152a and filling layers 151b and 152b have different germanium (Ge) concentrations. For example, the concentration of germanium (Ge) in the liner layers 151a and 152a is lower than the concentration of germanium (Ge) in the filling layers 151b and 152b.

[0135] As shown in Figures 14 and 15, a first interlayer insulating layer 171 is formed on the source / drain pattern 150. Subsequently, a portion of the first interlayer insulating layer 171 and the preliminary capping layer 141P are removed to expose the upper surface of the preliminary main gate electrode 131MP. At the same time, a portion of the preliminary gate spacer 142P is also removed to form the gate spacer 142. After that, the remaining preliminary gate insulating film 132P and the preliminary main gate electrode 131MP are removed to expose the upper pattern structure U_AP between the gate spacers 142. Subsequently, the sacrificial pattern SC_L between the channel structure CH and the lower pattern BP is removed to form the gate trench 130t.

[0136] As shown in Figures 16 and 17, a subgate insulating film 130S and a subgate electrode 120S are sequentially formed in the gate trench 130t. The main gate insulating film 130M, the main gate electrode 120M, and the capping layer 141 are also sequentially formed. The subgate insulating film 130S and the main gate insulating film 130M are formed simultaneously in the same process. The subgate electrode 120S and the main gate electrode 120M are formed simultaneously in the same process.

[0137] Next, a photo-etching process is used to etch a portion of the first interlayer insulating layer 171 between two source / drain patterns 150 that are spaced apart along the second direction D2, thereby forming a separation pattern 173. Subsequently, a portion of the first interlayer insulating layer 171 located between two opposing gate structures GS along the first direction D1 is etched, and then an upper contact electrode 191 is formed in the area where the first interlayer insulating layer 171 was removed.

[0138] As shown in Figures 18 and 19, a second interlayer insulating layer 175, an upper contact via 193, and an upper wiring structure 410 are formed on the first interlayer insulating layer 171. First, the second interlayer insulating layer 175 is formed on the first interlayer insulating layer 171, and a portion of the second interlayer insulating layer 175 that overlaps with the upper contact electrode 191 in the third direction D3 is etched to form a contact hole. Then, a conductive material is deposited into the contact hole formed in the second interlayer insulating layer 175 to form an upper contact via 193, and the upper wiring structure 410 is formed on the second interlayer insulating layer 175.

[0139] As shown in Figures 20 and 21, the first substrate 10 and the lower pattern BP are etched. To etch the first substrate 10 and the lower pattern BP, the semiconductor device according to one embodiment is attached to the second substrate 500. Specifically, the upper surface of the upper wiring structure 410 is positioned to face one surface of the second substrate 500, and then one surface of the second substrate 500 and the upper surface of the upper wiring structure 410 are attached to each other. At that time, the semiconductor device according to the embodiment is rotated so that the upper surface of the upper wiring structure 410 and the upper surface of the second substrate 500 face each other. Although not shown in Figures 20 and 21, an adhesive member is positioned between one surface of the second substrate 500 and the upper surface of the upper wiring structure 410.

[0140] Subsequently, an etching process is performed to remove the entire area of ​​the first substrate 10 and the lower pattern BP. To remove the first substrate 10 and the lower pattern BP, at least one of the following processes is performed: wet etching, dry etching, and CMP (chemical mechanical polishing). As an example, first, the first substrate 10 is etched to a sufficiently thin state by the CMP (chemical mechanical polishing) process, and then a wet etching process is performed to etch the remaining first substrate 10 and lower pattern BP. In this case, the wet etching process is performed for a sufficient amount of time so that no part of the first substrate 10 and lower pattern BP remains. In one embodiment, while the first substrate 10 and lower pattern BP are etched, the source / drain pattern 150 is protected from damage by the etching material by liner layers 151a and 152a doped with carbon (C) or boron (B).

[0141] As shown in Figures 22 and 23, a base insulating layer 101 is formed in the area where the first substrate 10 and the lower pattern BP have been removed. In one embodiment, the base insulating layer 101 includes a protruding region 103 that protrudes from the upper surface. In this embodiment, the protruding region 103 is located in the area where the lower pattern BP has been removed. The protruding region 103 surrounds at least a portion of the side and bottom surfaces of the source / drain pattern 150.

[0142] As shown in Figures 24 and 25, a portion of the base insulating layer 101 is etched to form a first lower recess BRC1. Specifically, a portion of the base insulating layer 101 that overlaps with one of the multiple source / drain patterns 150 in the third direction D3 is etched by a photoetching process. The first lower recess BRC1 exposes a portion of the source / drain pattern 150. In one embodiment, a portion of the source / drain pattern 150 is etched together with the base insulating layer 101. In one embodiment, the process of forming the first lower recess BRC1 is carried out by a dry etching process, but is not limited to this.

[0143] Referring to Figures 24 and 25, the width of the first lower recess BRC1 along the first direction D1 and the second direction D2 is even wider than the width of the lower surface of the source / drain pattern 150 along the first direction D1 and the second direction D2. In one embodiment, the etching of the base insulating layer 101 is performed using an etching material that has a higher etching selectivity ratio for the base insulating layer 101 compared to the field insulating layer 105.

[0144] As shown in Figures 26 and 27, a portion of the source / drain pattern 150 exposed by the first lower recess BRC1 is etched to form a second lower recess BRC2. In one embodiment, the process of forming the second lower recess BRC2 is performed by a Self-Aligned Contact (SAC) process. In one embodiment, the base insulating layer 101 and the field insulating layer 105 contain insulating materials having an etching selectivity ratio with respect to the source / drain pattern 150. For example, the process of etching a portion of the source / drain pattern 150 exposed by the first lower recess BRC1 is performed using an etching material having a higher etching selectivity ratio with respect to the source / drain pattern 150 compared to the base insulating layer 101 and the field insulating layer 105.

[0145] In one embodiment, the process of forming the second lower recess BRC2 is carried out by a dry etching or wet etching process.

[0146] As shown in Figures 28 and 29, a conductive material is deposited inside the first lower recess BRC1 and the second lower recess BRC2 to form the lower contact electrode 195. First, a barrier pattern 197 is conformally formed on the inner walls of the first lower recess BRC1 and the second lower recess BRC2. Then, the lower contact electrode 195 is formed in the remaining area of ​​the first lower recess BRC1 and the second lower recess BRC2, excluding the area where the barrier pattern 197 is formed. In one embodiment, a silicide layer 199 is further formed at the interface between the lower contact electrode 195 and the source / drain pattern 150.

[0147] As shown in Figures 30 to 32, a lower wiring structure 420 is formed on the lower surface of the base insulating layer 101. The lower wiring structure 420 includes a lower conductive pattern 421 and a lower wiring insulating layer 422. The lower conductive pattern 421 is located on the lower surface of the base insulating layer 101. The lower conductive pattern 421 contains a metal (copper, for example). The lower conductive pattern 421 is electrically connected to the lower contact electrode 195. The lower wiring insulating layer 412 includes at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low dielectric constant film, for example.

[0148] Although embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the present invention also fall within the scope of the rights of the present invention. [Explanation of Symbols]

[0149] 10. First board 101 Base insulating layer 103 Prominent area 105 Field Insulation Layer 141 Capping layer 142 Gate Spacer 150 Source / Drain Patterns 151a, 152a Liner layer 151b, 152b Filling layer 150R Source / Drain Recess 171 First interlayer insulating layer 173 Separation Patterns 175 Second interlayer insulating layer 191 Upper contact electrode 193 Upper contact via 195 Lower contact electrode 197 Barrier Pattern 199 Silicide layer CH channel structure M_GS Main Gate Structure S_GS Subgate Structure SC_L Sacrifice Layer GS Gate Structure BP lower pattern RC recess area 410 Upper wiring structure 411 Upper conductive pattern 412 Upper wiring insulation layer 420 Lower wiring structure 421 Lower conductive pattern 422 Lower wiring insulation layer

Claims

1. Base insulating layer, A channel structure located on the first surface of the base insulating layer, A gate structure surrounding the channel structure, The channel structure includes source / drain patterns arranged on both sides of the channel structure, spaced apart from each other along a first direction, Each of the source / drain patterns includes a liner layer and a filling layer located on the inner surface of the liner layer. The lower surface and a portion of the side surface of the source / drain pattern are covered by the base insulating layer. The semiconductor device is characterized in that the liner layer contains carbon-doped silicon germanium.

2. The aforementioned base insulating layer is Including the protruding region that protrudes from the first surface, The semiconductor device according to claim 1, characterized in that a portion of the lower surface and side surface of the source / drain pattern is covered by the protruding region.

3. The lower wiring structure is located on a second surface of the base insulating layer that is opposite to the first surface, The source / drain pattern includes a first source / drain pattern connected to the lower wiring structure, The system further includes a lower contact electrode that connects the first source / drain pattern and the lower wiring structure, The semiconductor device according to claim 2, characterized in that the lower contact electrode includes a first contact region penetrating the base insulating layer and a second contact region extending from the upper surface of the first contact region into the interior of the first source / drain pattern.

4. The semiconductor device according to claim 3, characterized in that the lower surface of the source / drain pattern is located more adjacent to the lower wiring structure than the upper surface of the first contact area.

5. The semiconductor device according to claim 3, characterized in that the upper surface of the second contact region is located at a level between the lower surface of the gate structure and the upper surface of the source / drain pattern.

6. The source / drain pattern further includes a second source / drain pattern located at a distance from the first source / drain pattern in the first direction, The semiconductor device according to claim 3, characterized in that the second source / drain pattern includes a region that overlaps with the first contact region in the first direction.

7. The semiconductor device according to claim 3, characterized in that the width of the first contact area along the first direction is wider than the width of the first source / drain pattern along the first direction.

8. The invention further includes field insulating layers located on both sides of the protruding region, The semiconductor device according to claim 1, characterized in that the liner layer in a region of the source / drain pattern located at a level lower than the lower surface of the gate structure is located between the field insulating layer and the filling layer.

9. A base insulating layer including a first surface and a second surface facing the first surface, A channel structure located on the first surface of the base insulating layer, A gate structure surrounding the channel structure, Source / drain patterns are located on both sides of the channel structure and extend into the base insulating layer, A lower wiring structure located on the second surface of the base insulating layer, Includes a lower contact electrode that connects at least one of the source / drain patterns to the lower wiring structure, The lower contact electrode includes a first contact region extending into the base insulating layer and a second contact region extending from the upper surface of the first contact region into at least one of the source / drain patterns. The semiconductor device is characterized in that the upper surface of the first contact region is located between the lower surface of the gate structure and the lower surface of the source / drain pattern.

10. Base insulating layer, A channel structure located on the base insulating layer, A gate structure surrounding the channel structure, A source / drain pattern including a first source / drain pattern and a second source / drain pattern located on both sides of the channel structure, A lower wiring structure located on the lower surface of the base insulating layer, A lower contact electrode connecting the first source / drain pattern and the lower wiring structure, An upper wiring structure located on the aforementioned source / drain pattern, The upper contact electrode connects the second source / drain pattern to the upper wiring structure, The lower contact electrode includes a first contact region extending into the base insulating layer and a second contact region extending from the upper surface of the first contact region into the first source / drain pattern. The semiconductor device is characterized in that the upper surface of the first contact region is located between the lower surface of the gate structure and the lower surface of the source / drain pattern.

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