Master-slave type D flip-flop

Abstract

This invention provides a low-power D flip-flop (DFF) that offers operating speed and cell area comparable to a transmission gate flip-flop, while reducing power consumption related to the clock signal to less than one-third. [Solution] The DFF consists of N-channel FETs 1, 3, 5, 7, P-channel FETs 2, 6, 8, 14, 16, 18 and an inverter 40. In this master latch with a two-stage semi-latch configuration where the latch state is limited to a low level, the gates of the P-channel ground-source FETs 16 and 18, which together with the clocked FET 14 form a power supply circuit to both semi-latch nodes, are connected to the memory nodes 62 and 63 of the slave latch, respectively. Additionally, a P-channel ground-source FET 8, whose gate is connected to the output terminal of the inverter 40, is connected in parallel to the P-channel ground-source FET 18. Furthermore, the source of the feedback FET 7, which, in connection with the clocked FET 3, perpetuates the low-level hold of the first-stage semi-latch node, is connected to the memory node 63.

Description

Technical Field

[0005]

[0001] The present invention relates to a D flip-flop (hereinafter referred to as DFF) with a low clock signal load that contributes to reducing the power consumption of CMOS LSIs.

Background Art

[0002] A DFF is a basic logic circuit that captures a logical value from the level of an input signal D at the time of either the rising or falling edge of a clock signal (hereinafter referred to as a trigger edge), and outputs the level of the captured logical value as a non-inverted output (generally denoted as Q), or outputs the inversion of that logical level as an inverted output (generally denoted as QN) until the next trigger edge arrives. However, since the power consumption of the circuit alone is significantly larger than that of other basic logic circuits, it is one of the factors contributing to the increased power consumption of CMOS LSIs. For this reason, master-slave type DFFs (hereinafter referred to as MS-DFFs) with a low clock signal load that do not rely on precharge, such as ACFF, LLFF [see Non-Patent Document 1], LRFF [see Non-Patent Document 2], and TCFF [see Non-Patent Document 3], which suppress the power consumption related to the clock signal, which is the main cause of power consumption inside the DFF, have been proposed so far.

[0003] Among these MS-DFFs, LRFF and TCFF, which have a transparent master latch that can also be regarded as a two-stage configuration of an incomplete latch (hereinafter referred to as a semi-latch) that only holds a low level in the latch state, are MS-DFFs with significantly small power consumption related to the clock signal, with only 4 and 3 gate terminals for clock signal input, respectively.

[0004] Here, a transparent latch is a circuit in which a latch state that holds and continues to output the input at the time of switching to that state and a transparent state that continues to output the input to itself as it is are switched according to the logical level of the clock signal, and is also called a D latch.

[0005] The LRFF, with its small number of gate terminals (only 4) that act as the clock signal load, does not use a precharge that is activated every cycle by the clock signal, as is clear from the circuit diagram shown in Figure 1, and also has a small number of constituent transistors (19). This configuration, which can be considered ideal for a low-power MS-DFF, is realized by a slave latch consisting of a master latch, which can be seen as a two-stage semi-latching configuration, and pass transistors 13 and 15, which are N-channel clocked FETs (FETs whose gate terminal input is the clock signal) connected via a cross-coupled CMOS inverter pair and its input to memory nodes 62 and 63. Here, since memory nodes 62 and 63 are nodes that hold the logic value taken from the input signal D and its inverted form, they will be referred to as non-inverting memory node 62 and inverting memory node 63, respectively.

[0006] This master latch, which can be understood as a two-stage semi-latch configuration, consists of a power supply circuit consisting of P-channel common-source FETs 4 and 8 and a clocked FET 14; the first stage of a CMOS logic gate that functions as a semi-latch due to this power supply (in this diagram, the simplest CMOS logic gate consisting of an N-channel FET 1 and a P-channel FET 2, with a CMOS inverter whose input to the gate terminal is signal D); the second stage of a CMOS inverter consisting of an N-channel FET 5 and a P-channel FET 6; a CMOS inverter 40 that inverts the semi-latch output of this second stage; a feedback FET 7 to maintain the low level of the semi-latch node 60; and an N-channel common-source clocked FET 3 that limits this feedback to when the master latch is in a latched state (hereinafter referred to as "latched"). The operation of the master latch under this understanding will be explained below.

[0007] When the clock signal is low level, the first and second stage half-latches enter a transparent state, outputting the inverted input. The CMOS inverters that make up the first and second stage half-latches are powered directly from the open drain terminal of the P-channel common-source FETs 4 and 8, if their power receiving terminals (source terminals of P-channel FETs 2 and 6) are connected to the open drain terminal of the P-channel common-source FETs 4 and 8, one of which is always open. If the power receiving terminals are connected to the closed drain terminal, the power is supplied via a detour through the pass transistor 14, which opens with a low-level clock signal. Here, one of the P-channel common-source FETs 4 and 8 is always open because, as shown in Figure 1, the gate terminals of the P-channel common-source FETs 4 and 8 are configured to receive the inverted signals of each other.

[0008] In contrast, when the clock signal is high level, it enters a latch state. In this latch state, if the first-stage half-latch node 60 is low level at the rising edge of the clock signal on the trigger edge, that low level is held there, and its inverted high level is output from the second-stage half-latch node 61. On the other hand, if the first-stage half-latch node 60 is high level at the rising edge of the clock signal, that high level is not held there, but its inverted low level is held by the second-stage half-latch node 61 that outputs it. In short, a transparent latch that can hold both high and low levels is realized by a two-stage half-latch configuration that holds a low level in the latch state.

[0009] Here, the low level of the first and second stage half-latches is maintained in the latched state because the inversion of that low level is input to their gate terminals, causing the P-channel common-source FETs 4 and 8 to close respectively. In addition, the high-level clock signal closes the pass transistor 14, eliminating bypass power supply and preventing the half-latches 60 and 61, which are at a low level, from being pulled up.

[0010] In this state where pulling up is impossible, when the N-channel FETs 1 and 5 turn off due to the switching of signal D, the semi-latch nodes 60 and 61 can enter a high-impedance state where they are not connected to either the power supply or ground, causing dynamic retention. To avoid this dynamic retention, feedback from FET 7 to semi-latch node 60 is applied only in the latched state via the N-channel common-source clocked FET 3. As a result, when semi-latch node 60 goes low, the pull to the low level is sustained thereafter, and it does not return to the high level when latched. Similarly, when semi-latch node 61's low level is captured by the slave ratchet after the rising edge of the clock signal, the pull to the low level is sustained by the N-channel FET 11 via the pass transistor 13 of the N-channel clocked FET, preventing it from returning to the high level.

[0011] Another MS-DFF with a remarkably low clock signal load, the TCFF, has 21 transistors, two more than the LRFF, but it further reduces the number of gate terminals that act as clock signal loads to just three. This low clock signal load is achieved by a master latch, which is configured by adding an N-channel feedback FET 17 to the master latch of the LRFF, as shown in the circuit diagram in Figure 2, and a slave latch whose output is received by FETs 21 and 23, which share a common-source N-channel clocked FET 19. Here, the N-channel feedback FET 17 operates in a latched state, similar to the other N-channel feedback FET 7, to maintain the low level of the semi-latch node 61.

[0012] However, LRFFs and TCFFs suffer from a critical weakness: their low-clock signal load master latch configuration results in significantly inferior speed performance compared to the previously dominant transmission gate flip-flops (hereinafter abbreviated as TGFFs), which consist of a CMOS inverter and pass transistor. This weakness stems from the fact that the bypass power supply via either of the P-channel common-source FETs 4 or 8 and the pass transistor 14, used in the transparent state of the master latch, weakens the ability to raise the level of the half-latch node 60 or 61 to the power supply side. The following will explain this bypass power supply problem in more detail.

[0013] When the half-latch node 61 is pulled up, the source-grounded FET 4, which is involved in the bypass power supply to the drain terminal of the P-channel FET 6 responsible for pulling up, switches off simultaneously with the pull-up. The other source-grounded FET 8 switches on with a delay equal to the propagation time of the inverter 40 to which its gate terminal is connected, after the pull-up. In the end, the source-grounded FET 4 starts to switch off earlier than the source-grounded FET 8 starts to switch on by the propagation time of one gate stage.

[0014] On the other hand, when the half-latch node 60 is pulled up, the source-grounded FET 4 switches on with a delay equal to the propagation time of the second-stage half-latch to which its gate terminal is connected, after the half-latch node 60 is pulled up. The source-grounded FET 8, which is involved in the bypass power supply until it switches on, switches off with an even greater delay than the pulling up of the half-latch node 60, equal to the propagation time of the inverter 40 to which its gate terminal is connected. In the end, the source-grounded FET 4 starts to switch on earlier than the source-grounded FET 8 starts to switch off by the propagation time of one gate stage.

[0015] Thus, when the signal D passes through the two stages of half-latches in a transparent state, neither of the P-channel FETs 4 and 8 that form the power supply circuit to the P-channel FETs 2 and 6 responsible for pulling up the half-latch nodes 60 and 61 maintains a sufficiently open state due to the switching between their open and closed states, and the power supply to the P-channel FETs 2 and 6 responsible for pulling up the half-latch nodes tends to be interrupted. In particular, when the half-latch node 61 is pulled up just before the trigger edge, the source-grounded FET 4 on the bypass circuit starts to switch off by the propagation time of one gate stage earlier than the source-grounded FET 8 on the bypass circuit starts to switch on, so the power supply interruption becomes more serious. When the half-latch node 60 is pulled up, the source-grounded FET 4 starts to switch on by the propagation time of one gate stage earlier than the source-grounded FET 8 on the bypass circuit starts to switch off, so although the interruption is less severe, an interruption due to reduced conductivity still occurs. [Prior art documents] [Non-patent literature]

[0016] [Non-Patent Document 1] A. Khorami, M. Sachdev, and M. Sharifkhani, “A contention-free, static, single-phase flip-flop for low data activity applications,” in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp.11-16, 2019. [Non-Patent Document 2] J. Lin, M. Sheu, Y. Hwang, C. Wong and M. Tsai, “Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp.3033-3044, 2017. [Non-Patent Document 3] Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, “A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75 percent Power Saving,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, 2526-2533, 2014. [Overview of the project] [Problems that the invention aims to solve]

[0017] Therefore, the problem that the present invention aims to solve is to ensure that power supply to the CMOS logic gates (basic gates or composite gates in a CMOS configuration) and the CMOS inverter that constitute the first and second stage semi-latches is not interrupted, and to improve the driving capability of the master latch for the slave latch, thereby shortening the response time as a DFF (setup time or output delay time from the trigger edge). [Means for solving the problem]

[0018] Instead of inputting the output of the second-stage half-latch and its output inverting circuit, the CMOS inverter, into the gate terminals of the first and second source-grounded FETs that constitute the power supply circuit responsible for supplying power to the two-stage half-latch, the logic value and its inverted level, which are captured from signal D to the slave ratchet via the master latch, are instead input to the gate terminals of the first and second source-grounded FETs that constitute the power supply circuit responsible for supplying power to the two-stage half-latch.

[0019] If higher speed performance is required, a third common-source FET with the same channel polarity is connected in parallel to the second common-source FET, and the inverted output of the second-stage half-latch is input to the gate terminal.

[0020] Furthermore, do one of the following as needed: (1) Instead of passing the series connection of the feedback FET (the FET whose gate terminal is connected to the second stage half-latch node) and the clocked FET between the first stage half-latch node and ground, it is passed between the first stage half-latch node and the slave rack inverted memory node. In other words, the first stage half-latch node and the slave rack inverted memory node are connected via two FETs (the clocked FET and the feedback FET whose gate terminal is connected to the second stage half-latch node, hereafter referred to as connected pass transistors) which have opposite channel polarity to the first and second common-source FETs and act as pass transistors. (2) A lead drive FET is added to the first stage half-latch node, non-inverting memory node, and the drain terminal of the source-grounded clocked FET, with its own gate terminal, drain terminal, and source terminal connected to the drain terminal of the source-grounded FET, respectively. The channel polarity of the lead drive FET is the opposite of that of the first and second source-grounded FETs. [Effects of the Invention]

[0021] Closing of the first or second source-grounded FET responsible for bypass power supply together with the pass transistor is delayed after the trigger edge. This is because the logical value captured by the slave latch and the level of its inversion after the trigger edge are input to the gate terminals of the first and second source-grounded FETs. As a result, power supply does not get stuck before the trigger edge, and the capture of the input signal D in the transparent state of the master latch speeds up, significantly improving the response speed as a DFF. Also, by connecting a third source-grounded FET that opens from before the trigger edge in parallel to the second source-grounded FET by inputting the inversion of the second-stage half-latch output to the gate terminal, the bypass power supply that disappears during latching is complemented, and the power supply delay immediately after the trigger edge is alleviated. Furthermore, passing the connection pass transistor not to ground but between the inverted memory node is due to its bidirectional operation, and when the high-level duration of the input signal D satisfies the setup and hold times, it energizes the pulling of the inverted memory node to the ground side during the hold period through the low-level output of the first-stage half-latch that persists during the hold period. This speeds up the capture of the high level of the input signal D to the slave latch. Also, when this capture is completed and the level of the inverted memory node of the slave latch switches to the low level, thereafter, the cross-coupled inverter driving the inverted memory node pulls the first-stage half-latch node to the low level side in reverse through the connection pass transistor. As a result, level floating that may occur at the first-stage half-latch node is suppressed. In addition, although the pre-driving FET is limited to the case of pulling the non-inverted memory node to the ground side, the start of pulling is advanced by one or two gate stages compared to the conventional case. By this advance, the capture of the logical value that makes the level of the non-inverted memory node become the low level speeds up.

Brief Description of Drawings

[0022] [Figure 1] Figure 1 is a circuit diagram of a LRFF. [Figure 2] Figure 2 is a circuit diagram of a TCFF. [Figure 3] Figure 3 is a circuit diagram of a MS-DFF configuration example according to the first embodiment. (Example 1) [Figure 4] Figure 4 is a circuit diagram of an MS-DFF configuration example related to the second embodiment. (Example 2) [Figure 5] Figure 5 is a circuit diagram of an MS-DFF configuration example related to the third embodiment. (Example 3) [Figure 6] Figure 6 is a circuit diagram of an MS-DFF configuration example related to the fourth embodiment. (Example 4) [Figure 7] Figure 7 is a circuit diagram of an MS-DFF configuration example related to the fifth embodiment. (Example 5) [Figure 8] Figure 8 is a circuit diagram of an MS-DFF configuration example related to the sixth embodiment. (Example 6) [Figure 9] Figure 9 is a circuit diagram of an MS-DFF configuration example related to the seventh embodiment. (Example 7) [Figure 10] Figure 10 is a circuit diagram of an MS-DFF configuration example related to the eighth embodiment. (Example 8) [Figure 11] Figure 11 is a circuit diagram of a scan flip-flop configuration example related to the ninth embodiment. (Example 9) [Figure 12] Figure 12 is a circuit diagram of block 70 in FIG. 11.

Embodiments for Carrying Out the Invention

[0023] An MS-DFF that operates at the same speed as TGFF while adopting a two-stage semi-latch configuration in which the master latch can minimize the clock signal load has been realized.

[0024] Figure 3 is a circuit diagram of an MS-DFF configuration example (Example 1) related to the first embodiment of the present invention. 1, 3, 5, 7, 9, 11, 13, 15 are N-channel FETs, 2, 6, 10, 12, 14, 16, 18 are P-channel FETs, 40, 41 are CMOS inverters, 50 is a CLK terminal for clock signal input, 51 is a D terminal for signal D input, and 52 is a Q terminal for non-inverting output that outputs the level of the logical value captured from its input signal D without inversion.

[0025] The LRFF in Figure 1 is the same as the LRFF in Figure 1, consisting of a master latch with a two-stage semi-latching configuration and a slave latch of a cross-coupled CMOS inverter pair, whose output and inverted output are input to its own memory nodes 62 and 63 via N-channel clocked FETs 13 and 15 that operate as pass transistors. The differences are that the P-channel source-grounded FETs 4 and 8 in the power supply circuit are replaced with a first source-grounded FET P-channel FET 16 whose gate terminal is connected to a non-inverting memory node 62 that holds the logic value taken from signal D and outputs its level, and a second source-grounded FET P-channel FET 18 whose gate terminal is connected to an inverting memory node 63 that holds the inverted logic value taken from signal D and outputs its level, and the source terminals of the P-channel FETs 10 and 12 that constitute the cross-coupled CMOS inverter pair are directly connected to the power supply.

[0026] By replacing the P-channel common-source FETs in the power supply circuit with P-channel common-source FETs 16 and 18 whose gate terminals are connected to the non-inverting and inverting memory nodes of the slave ratchet, power supply to the half-latch is no longer delayed before the trigger edge, and the operating speed of the master latch in the transparent state is significantly faster compared to conventional LRFF and TCFF. This is because the level of the memory node rises after the trigger edge due to input to the slave ratchet, so the P-channel common-source FETs 16 or 18 involved in bypass power supply no longer begin to close before the trigger edge.

[0027] However, because the inputs to the gate terminals of the P-channel source-grounded FETs 16 and 18, which are responsible for supplying power to the CMOS inverters that constitute the first and second stage half-latches, are the outputs from the non-inverting memory node 62 and the inverting memory node 63, there is a delay between the trigger edge and the acquisition of the slave ratchet before a low level can be reliably held in each half-latch. For this reason, the hold time of the input signal D is slightly longer than that of a conventional LRFF.

[0028] In this embodiment, the source terminals of the P-channel FETs 10 and 12 constituting the cross-coupled CMOS inverter pair are directly connected to the power supply because even if the signal were routed through the P-channel FETs 16 and 18 in the power supply circuit, they would not turn off before the P-channel FETs 10 and 12, thus preventing the input signal D from being brought into the cross-coupled CMOS inverter pair more quickly.

[0029] Furthermore, in this embodiment, the output from the non-inverting memory node 62 is directly input to the gate terminal of the P-channel common-source FET 16 as the logic value taken into the slave rack. However, this can be replaced with a configuration in which the output of the inverter 41 is input to the gate terminal of the P-channel common-source FET 16. This is because the output from the inverting memory node 63 is inverted, so that the output of the inverter 41 matches the level of the logic value taken from signal D, just like the output from the non-inverting memory node 62. Similarly, instead of inputting the output from the inverting memory node 63 to the gate terminal of the P-channel common-source FET 18, it is also possible to add an inverter that inverts the output from the non-inverting memory node 62 and input its output to the gate terminal of the P-channel common-source FET 18. By reducing the load on the memory nodes 62 and 63 through the inverter in this way, the speed performance of the DFF can be improved.

[0030] Figure 4 is a circuit diagram of an MS-DFF configuration example (Example 2) relating to a second embodiment of the present invention, where 1, 3, 5, 7, 9, 11, 17, 19, 21, and 23 are N-channel FETs, 2, 6, 10, 12, 14, 16, and 18 are P-channel FETs, 40 and 41 are CMOS inverters, 50 is a CLK terminal for clock signal input, 51 is a D terminal for signal D input, and 52 is a Q terminal for non-inverting output that outputs the level of the logic value taken from the input signal D in a non-inverting manner.

[0031] The difference from Embodiment 1 in Figure 3 is that instead of the LRFF in Figure 1, the P-channel ground-source FETs 4 and 8 in the master latch power supply circuit of the TCFF shown in Figure 2 are replaced with P-channel ground-source FETs 16 and 18. By replacing them with P-channel ground-source FETs 16 and 18, as in Embodiment 1, power supply to the CMOS inverter that forms a semi-latch before the trigger edge is no longer interrupted, and the operating speed of the master latch in the transparent state is significantly faster compared to the conventional TCFF.

[0032] Figure 5 is a circuit diagram of an MS-DFF configuration example (Example 3) relating to a third embodiment of the present invention. The differences from Example 1 are two: firstly, a third P-channel FET 8, which is a common-source FET, is connected in parallel to the P-channel common-source FET 18 in the power supply circuit, and secondly, the source terminal of the P-channel FET 12 is connected to the drain terminals of the P-channel FETs 8 and 18 instead of the power supply.

[0033] The parallel-connected P-channel common-source FET 8 begins to open before the trigger edge when the input signal D rises, thus providing higher conductivity immediately after the trigger edge than the P-channel common-source FET 18, which begins to open from that point. This compensates for the bypass power supply that closes at the trigger edge, preventing delays in power supply to the CMOS inverter that constitutes the second-stage half-latch immediately after the trigger edge. As a result, the slave ratchet capture is accelerated, and the response speed as a DFF is significantly improved. Furthermore, by connecting the source terminal of P-channel FET 12 to the drain terminals of P-channel FETs 8 and 18, power is also supplied to P-channel FET 12 via P-channel FET 8, which opens and closes before the trigger edge. This causes the power supply capability to begin to decrease before the trigger edge when a low level is captured in the non-inverting memory node, thus accelerating the capture. However, the degree of acceleration is slight, so the source terminal of P-channel FET 12 can also be directly connected to the power supply.

[0034] Figure 6 is a circuit diagram of an MS-DFF configuration example (Example 4) according to the fourth embodiment of the present invention. The difference from Example 2 is that, similar to Example 3, a third P-channel FET 8, which is a common-source FET to which the inverted output from the half-latch node 61 (output of the CMOS inverter 40) is input to the gate terminal, is connected in parallel to the P-channel common-source FET 18 in the power supply circuit. This compensates for the bypass power supply that closes simultaneously with the trigger edge, and prevents delays in power supply to the CMOS inverter that constitutes the second-stage half-latch immediately after the trigger edge. As a result, the capture of the slave ratchet is accelerated, and the response speed as a DFF is greatly improved.

[0035] Figure 7 is a circuit diagram of an MS-DFF configuration example (Example 5) related to the fifth embodiment of the present invention. The difference from Example 3 is that the order of the clocked FET 3 and feedback FET 7, which are connected in series, is reversed, the source common configuration is discontinued, and they are connected to the inverting memory node 63. As a result, both the clocked FET 3 and feedback FET 7 operate as pass transistors. When a high-level signal D that satisfies the setup time and hold time conditions is input, the turn on of the source common FET 1, which persists at least during the hold period, pulls the inverting memory node 63 to the low level side via the feedback FET 7 and clocked FET 3, which are both open. This assists the pull via the pass transistor 15 by the CMOS inverter 40 at the same time, speeding up the capture of the slave latch and improving the response speed as a DFF. After the inverting memory node 63 goes to a low level, the N-channel FET 9, which is in the ON state, pulls the half-latch node 60 to the low level side via the clocked FET 3 and feedback FET 7. This prevents the level of the half-latch node 60 from floating even when the N-channel FET 1 is turned off during latching, similar to the original latch-time feedback circuit. In this embodiment, the order of the series-connected clocked FET 3 and feedback FET 7 is swapped, but this swap is not necessary, as it only slightly reduces the rate of improvement in response speed.

[0036] Figure 8 is a circuit diagram of an MS-DFF configuration example (Example 6) according to the sixth embodiment of the present invention. The difference from Example 5 is that the CMOS logic gate constituting the first stage half-latch is a CMOS NAND gate instead of a CMOS inverter. While it still functions as a first stage half-latch by achieving low-level holding of the half-latch node 60 through power supply circuit switching, it has the advantage of adding the function of setting a logic value of 1 to the DFF by low-level input to the SETN terminal 53 with only two additional FETs.

[0037] Figure 9 is a circuit diagram of an MS-DFF configuration example (Example 7) relating to the seventh embodiment of the present invention. The difference from Example 4 is that the gate terminal of the FET 21, which pulls the non-inverting memory node 62 to ground during latching, is connected to a semi-latch node 60 two gate stages before the output node of the inverter 40, rather than to the output node. This change in connection advances the start of the pull drive by two gate stages. As a result, the acquisition of the logic value of the slave latch, which sets the non-inverting memory node 62 to a low level, is accelerated. The advance drive of the non-inverting memory node 62 pull by the FET 21 is not guaranteed to continue after the hold period ends, as the high-level persistence of the semi-latch node 60 is only guaranteed during the hold period. However, this is not a problem. As long as a sufficient hold time is set to ensure that the logic value can be acquired during the hold period, the cross-coupled inverter pair will complete the acquisition on its own even after the pull stops.

[0038] Figure 10 is a circuit diagram of an MS-DFF configuration example (Example 8) relating to the eighth embodiment of the present invention. The difference from Example 3 is the addition of an FET 21a for pre-drive, which connects its gate terminal, drain terminal, and source terminal to the drain terminal of the half-latch node 60, the non-inverting memory node 62, and the common-source clocked FET 3, respectively. This FET 21a pulls the non-inverting memory node 62 to ground by being connected in series with the common-source clocked FET 3 after the trigger edge when a low-level input signal D is acquired. However, this pull does not necessarily continue after the hold period ends, as the high-level persistence of the half-latch node 60 is only guaranteed during the hold period. Nevertheless, since the start of the pull is advanced by two gate stages, the acquisition of the logic value of the slave ratchet, which sets the non-inverting memory node 62 to a low level, can be accelerated.

[0039] Figure 11 is a circuit diagram of a scan flip-flop configuration example (Example 9) related to the ninth embodiment of the present invention. In this example, an LSSD type scan flip-flop is configured by adding a TCFF master latch as the pre-stage of the scan-side flip-flop to block 70 of the configuration shown in Figure 12, which has QI and QNI terminals added to Example 5. The transfer of cross-coupled CMOS inverter pairs within block 70 to the memory nodes 62 and 63 can also be performed via N-channel FETs 113 and 115 of the pass transistors controlled by the clock signal SCLKB, thereby allowing the slave latch to function as a post-stage latch of the LSSD type scan flip-flop. By configuring the DQ path with the MS-DFF of Example 5 and configuring the scan-side pre-stage latch with a TCFF master latch consisting of only 12 FETs, both capture mode operation and high-speed, low-power normal mode operation are achieved. Here, normal mode is realized by setting SCLKB to a low level, and capture mode is realized by setting CLK to a low level and applying appropriate pulses to SCLKAN and SCLKB.

[0040] In Examples 1-9, it is also possible to configure the MOS FETs with all channel polarities reversed. However, in this case, the power supply and ground are swapped, and the logic of the CLK and SETN terminals is also inverted, becoming the CLKN and SET terminals. [Industrial applicability]

[0041] This invention is expected to be widely used as a low-power DFF to replace TGFFs. This is because, despite being implementable with a cell area equivalent to or smaller than that of TGFFs, it can reduce the power delay product to about one-third of that of TGFFs under the average operating conditions of a DFF with a data activation rate of about 10% or less. [Explanation of Symbols]

[0042] 1,5,7,17,21,21a,101,105,107,117 N Channel FETs 2,6,102,106 P-ChannelFETs 4,8,16,18,104,108 P-channel common-source FETs that constitute the power supply circuit 3 N-channel clocked FETs 19,103 Source-common N-channel clocked FET 13, 15, 113, 115 N-channel clocked FETs with pass transistors 14,114 Pass-through transistor P-channel clocked FET 9,11 N-channel FETs constituting a cross-coupled CMOS inverter pair 10,12 P-channel FETs constituting a cross-coupled CMOS inverter pair 40, 41, 140 CMOS inverters 50 CLK (clock signal input) terminal 51 D terminal 52 Q terminals 53 SETN terminal 55 SI terminal 56 SCLKAN (inverted signal of SCLKA) terminal 57 SCLKB terminal 60, 61, 160, 161 Half-latch node 62 Non-inverting memory node (also functions as a QI terminal in Figure 12) 63. Inverted memory node (also known as the QNI terminal in Figure 12) 70 Circuit block with QI and QNI terminals added to Example 5

Claims

1. A master-slave type D flip-flop with a two-stage latch configuration to which a signal D is input, comprising: a master latch in the preceding stage comprising first and second common-source FETs with the same channel polarity, each inputting a logic value and its inverted level, which are taken in from the signal D to the slave latch in the subsequent stage via itself, to their respective gate terminals; a pass transistor having the same channel polarity as the common-source FET and whose gate terminal input is a clock signal FET; a first node to which one of the two input / output terminals of the pass transistor is connected to the drain terminal of the first common-source FET; a second node to which the other of the two input / output terminals of the pass transistor is connected to the drain terminal of the second common-source FET; a CMOS logic gate that is powered via the first node and to which the signal D is input; and a CMOS inverter that is powered via the second node and to which the output of the CMOS logic gate is input.

2. The master-slave type D flip-flop according to claim 1, characterized in that the master latch comprises a circuit for inverting the output of the CMOS inverter, and a third common-source FET whose channel polarity is the same as that of the pass transistor, with the output of the inverting circuit input to the gate terminal and its drain terminal connected to the second node.

3. The master-slave type D flip-flop according to claim 1 or 2, characterized in that the slave latch comprises a non-inverting storage node that holds a logic value acquired from the signal D via the master latch, and the master latch comprises a fourth common-source FET whose input to its gate terminal is a clock signal and whose channel polarity is opposite to that of the pass transistor, and an FET whose channel polarity is the same as that of the fourth common-source FET, connecting its gate terminal, drain terminal, and source terminal to the output node of the CMOS logic gate, the non-inverting storage node, and the drain terminal of the fourth common-source FET, respectively.

4. The master-slave type D flip-flop according to claim 1 or 2, characterized in that the slave latch includes an inverting memory node that holds the inverted logic value acquired from the signal D via the master latch, and the master latch includes a connected pass transistor in which a pass transistor whose input to the gate terminal is a clock signal and whose channel polarity is opposite to that of the pass transistor is connected in series with a pass transistor which has the same channel polarity as the pass transistor and whose own gate terminal is connected to the output node of the CMOS inverter, and the output node of the CMOS logic gate and the inverting memory node are connected via the connected pass transistor.

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