How to create an isolation structure thyristor

Abstract

We provide semiconductor-based thyristors. [Solution] The thyristor semiconductor 200 includes a first layer 222 located on a first surface of a substrate 212, where the first layer is a first P layer. A second layer 214 located on a second surface of the substrate is a second P layer. The second surface is opposite the first surface. A third layer 210 is located between the first layer and the substrate. An isolation region 218 is located along the edge of the substrate. The isolation region is adjacent to the second P layer. An emitter 202 adjacent to the third layer is connected to the cathode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to thyristors, more specifically, semiconductor-based thyristors.

Background Art

[0002] A thyristor is a semiconductor switch used to control the flow of current. Thyristors are used in applications such as household appliances (lighting, heating, temperature control, alarm activation, fan speed), power tools (for motor speed control, stapling events, battery charging), and outdoor equipment (water sprinklers, gas engine ignition, electronic displays, area lighting, sports equipment, physical fitness). In many applications, thyristors perform a primary function and help meet environmental, speed, and reliability specifications that cannot be achieved by their electromechanical equivalents.

[0003] Similar to a diode, a thyristor is a three-terminal device with a PNPN configuration, composed of an anode terminal connected to a first P section, a cathode terminal connected to a second N section, and a gate terminal connected to the P section closest to the cathode. A thyristor is known to have three P-N junctions. When a positive voltage is applied to the gate terminal of the device, the thyristor turns on and remains on even when the gate terminal signal is removed. When the current flowing through the thyristor falls below the latching current level, the thyristor turns off.

[0004] The non-repeating peak-off state voltage (VDSM), also known as VDSM, is an important characteristic of thyristors. VDSM is applicable when there is no signal between the gate and cathode and within the rated junction temperature range. VDSM is applicable for time widths less than half the length of a sine wave at commercial frequency. The repetitive peak reverse current (IRRM), also known as silicon-controlled rectifier (SCR), is another important characteristic of thyristors. IRRM is the maximum instantaneous value of the reverse current resulting from the application of a repetitive peak reverse voltage. Both VDSM and IRRM are affected by the arrangement of the materials forming these three PN junctions.

[0005] This improvement may be useful with respect to these and other considerations. [Overview of the project]

[0006] This summary is provided to introduce various concepts that will be further described in more detail later. This summary is not intended to identify the main or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0007] An exemplary embodiment of the thyristor semiconductor according to this disclosure may include a first layer located on a first surface of a substrate, wherein the first layer is a first P layer. A second layer located on a second surface of the substrate is a second P layer. The second surface is opposite the first surface. A third layer is located between the first layer and the substrate. An isolation region is located along the edge of the substrate. The isolation region is connected to the second P layer. An emitter adjacent to the third layer is connected to the cathode.

[0008] Exemplary embodiments of a method for forming a thyristor semiconductor according to the present disclosure may include the steps of: providing an N-substrate; performing a P-type isolation photoresist and diffusion in a first region above the N-substrate and simultaneously in a second region below the N-substrate; and forming a first layer by performing a P-based gallium diffusion in the first and second regions simultaneously. The method further includes the step of performing a grinding operation on the second region to remove P- from the second region.

[0009] Another exemplary embodiment of a method for forming a thyristor semiconductor according to the present disclosure may include the steps of: providing an N-substrate; forming a first layer by performing a P-type isolation photoresist and diffusion in a first region above the N-substrate and simultaneously in a second region below the N-substrate; performing a P-based boron diffusion in the first region; and performing a P-based diffusion in the first and second regions. [Brief explanation of the drawing]

[0010] [Figure 1A] This diagram illustrates a conventional thyristor semiconductor. [Figure 1B] This diagram illustrates a conventional thyristor semiconductor.

[0011] [Figure 2A] This figure illustrates a thyristor semiconductor according to an exemplary embodiment. [Figure 2B] This figure illustrates a thyristor semiconductor according to an exemplary embodiment.

[0012] [Figure 3] These are flowcharts illustrating a conventional method for manufacturing the thyristor semiconductors shown in Figures 1A and 1B.

[0013] [Figure 4]This flowchart illustrates a first method for manufacturing the thyristor semiconductor shown in Figures 2A and 2B, according to an exemplary embodiment.

[0014] [Figure 5] This flowchart illustrates a second method for manufacturing the thyristor semiconductor shown in Figures 2A and 2B, according to an exemplary embodiment. [Modes for carrying out the invention]

[0015] A thyristor semiconductor and a method for manufacturing the thyristor semiconductor are disclosed. The semiconductor thyristor has a double base on the cathode side to improve VDSM and a single base on the anode side to ensure sufficient substrate width, thereby reducing IRRM.

[0016] For convenience and clarity, terms such as “top,” “bottom,” “up,” “down,” “vertical,” “horizontal,” “lateral,” “lateral,” “radial,” “internal,” “external,” “left,” and “right” may be used herein to describe the relative arrangement and orientation of features and components with respect to the geometry and orientation of other features and components appearing in the perspective views, exploded perspective views, and section views provided herein, respectively. The above terminology is not intended to be limiting and includes the words specifically mentioned, their derivatives, and words with similar meanings.

[0017] Figures 1A and 1B are typical diagrams of a prior art thyristor semiconductor 100. Figure 1A is a cross-sectional view of the thyristor semiconductor 100, while Figure 1B is a top view of the thyristor semiconductor 100. The thyristor semiconductor 100 is known as a single-sided mesa type thyristor. The thyristor semiconductor 100 includes a gate 104, a cathode 120, and an anode 116, as shown. The moat 106, shown as two parts 106a and 106b in Figure 1A, is arranged to surround the emitter 102 of the thyristor semiconductor 100, as shown in Figure 1B, with moat part 106a adjacent to the gate 104 and moat part 106b adjacent to the emitter 102. In addition to the emitter 102, the semiconductor region has a P-base 110, an N-substrate 112, and a P-base 114, with an isolation region 118 arranged along the outer edge, surrounding the moat 106 of the thyristor semiconductor 100. The emitter 102 is an N+ doped area (heavy doping). Therefore, in the thyristor semiconductor 100, there is a PN junction between the emitter 102 and the P-base 110, a second PN junction between the P-base 110 and the N-substrate 112, and a third PN junction between the N-substrate 112 and the P-base 114, resulting in a total of three PN junctions, as is characteristic of thyristors.

[0018] Semiconductor silicon is etched to form a moat 106, and then glass is used as a passivation region. Glass 108 covers the entire moat 106 and is visible as glass portions 108a, 108b, and 108c, with glass portion 108c positioned between the gate 104 and the emitter 102, and glass portion 108c also positioned above both the emitter 102 and the P-base 110. The P-bases 110 and 114 are formed simultaneously and have the same doping properties. This is known as a symmetric P-base diffusion structure on the anode 116 side and the cathode 120 side (in other words, on both sides of the N-substrate 112). By simultaneously depositing and diffusing the P-bases 110 and 114, the thyristor semiconductor 100 has the same junction depth at both the anode 116 and the cathode 120.

[0019] To increase the breakdown voltage of the thyristor semiconductor compared to the breakdown voltage of the thyristor semiconductor 100, the P-base junction depth may be increased. For example, a low-concentration (light) P-base diffusion area may be introduced to increase the breakdown voltage. The process is symmetric, and the low-concentration P-base diffusion is performed at the cathode and the anode. If the P-base is added only to the cathode 120, the P-base 110 is deeper than the P-base 114. However, if the P-base is added to both the cathode 120 side and the anode 116 side, both the P-base 110 and the P-base 114 become deeper than before. As a result, since both the P-base 110 and the P-base 114 become deeper than before, the thickness of the N-substrate is reduced.

[0020] When the N-substrate becomes thinner, the drift region area of the N-substrate is reduced. As a result, since the N-substrate becomes thinner, a limit is imposed on the reverse breakdown capability of the thyristor semiconductor. To achieve a high breakdown voltage, a thicker wafer may be used. However, when the wafer becomes thicker, as a result, the VT (on-state voltage) becomes higher. VT is the main voltage when the thyristor is in the on state.

[0021] Furthermore, by increasing the P-base junction depth of the thyristor semiconductor 100, the VDSM capability can be improved. However, as a result, the N-substrate becomes thinner, thereby increasing the IRRM. It is difficult to design a thyristor semiconductor that optimizes both VDSM and IRRM.

[0022] Figures 2A and 2B are representative drawings of a thyristor semiconductor 200 according to an exemplary embodiment. FIG. 2A is a cross-sectional view of the thyristor semiconductor 200, while FIG. 2B is a top view of the thyristor semiconductor 200. The structure of the thyristor semiconductor 200 solves the above-described problems. The thyristor semiconductor 200 includes a gate 204, a cathode 220, and an anode 216 as shown. A moat 206 shown as two parts 206a and 206b in FIG. 2A is arranged to surround an emitter 202 of the thyristor semiconductor 200 as shown in FIG. 2B, with moat part 206a adjacent to the gate 204 and moat 206b adjacent to the emitter 202.

[0023] In addition to the emitter 202, the semiconductor region also has a P base 222 (at the gate 204), a P base 210, an N-substrate 212, and a P base 214, and an isolation region 218 is arranged on the opposite side of the thyristor semiconductor 200, with the isolation region 218 arranged along the outer edge and surrounding the moat 206 of the thyristor semiconductor 200. The emitter 202 is an N+-doped area (high-concentration doping). Thus, in the thyristor semiconductor 200, there is a PN junction between the emitter 202 and the P base 222, a second PN junction between the P base 210 and the N-substrate 212, and a third PN junction between the N-substrate 212 and the P base 214, and there are a total of three PN junctions, which is characteristic of a thyristor.

[0024] The semiconductor silicon is etched to form the moat 206, and then glass is used as the passivation region. Glass 208 covers the entire moat 206 and is visible as glass parts 208a, 208b, and 208c, with glass part 208c arranged between the gate 204 and the emitter 202, and glass 208c also arranged over both the emitter and the P base 222.

[0025] P-bases 222 and 214 are diffused simultaneously and have the same doping properties. However, while thyristor semiconductor 100 is symmetrical, the structure of thyristor semiconductor 200 is asymmetrical due to the addition of P-base 210 in the cathode region. Thyristor semiconductor 200 has both P-base 210 and P-base 222 in the cathode 220 region. In some embodiments, this increases the blocking capacity of thyristor semiconductor 200, resulting in improved VDSM characteristics. On the back (anode 216) side, a single P-base diffusion is used (P-base 214). This makes it possible to maintain the thickness of the N-substrate 212, preventing it from becoming too thin and avoiding the use of thicker wafers. In some embodiments, the voltage capability of thyristor semiconductor 200 exceeds that of thyristor semiconductor 100 due to the structural change. In some embodiments, the N-substrate 212 of the thyristor semiconductor 200 is slightly thicker than the N-substrate 112 of the thyristor semiconductor 100 (note that the P-base 114 (Figure 1A) is slightly thicker than the P-base 214 (Figure 2B)). Also, in some embodiments, the P-base 210 is doped differently from the P-base 110. In exemplary embodiments, the doping of the P-base 210 is lighter than the doping of the P-base 222 (lightly doped). In some embodiments, the doping concentration of the P-base 210 is 2.5E16 / cm³. 3 On the other hand, the doping concentration of P-Base 222 is 1.5E18 / cm³. 3 That is the case.

[0026] In some embodiments, the thyristor semiconductor 200 is characterized by having a double base, i.e., both a P-base 222 and a P-base 210 at the cathode 220. Furthermore, in some embodiments, the thyristor semiconductor 200 is characterized by having a single base (P-base 214) at the anode 216. The single base at the anode 216 ensures a sufficient N-substrate width 212 to reduce IRRM. Thus, in some embodiments, the structure of the thyristor semiconductor 200 improves both VDSM and IRRM.

[0027] Figure 3 is a typical flow chart showing a method 300 performed when producing the thyristor semiconductor 100 shown in Figures 1A and 1B, according to the prior art. An N-substrate is obtained (block 302). P-type isolation photoresist and diffusion are performed, and this operation is carried out simultaneously on both sides of the N-substrate (block 304). Next, P-base diffusion is performed on both sides of the N-substrate (block 306). The P-base may be boron doping or gallium doping. Next, N+ photoresist and diffusion are performed at the emitter (block 308). Then, subsequent moat, passivation, contact, and metal steps are performed (block 310).

[0028] Figure 4 is a typical flow chart showing a method 400 performed to produce the thyristor semiconductor 200 of Figures 2A and 2B according to several embodiments. Similar to method 300, the process begins with obtaining an N-substrate (block 402). A P-type isolation photoresist and diffusion operation is performed, which is carried out simultaneously on both sides of the N-substrate (e.g., cathode side and anode side) (block 404). P-base gallium diffusion is then performed on both sides of the N-substrate (cathode side and anode side) to form a P-base layer 210 (block 406).

[0029] Next, a grinding operation is performed on the back surface (e.g., the anode side) to remove the anode P- (block 408). P-base diffusion is performed on both sides of the N-substrate (cathode side and anode side) (block 410), resulting in the formation of P-base 222 and P-base 214. In some embodiments, the P-base is doped with boron. In other embodiments, the P-base is doped with gallium. Therefore, using method 400, P-base 210 is formed using gallium diffusion (block 406), but since gallium diffusion is performed on both the anode side and the cathode side, grinding is performed on the anode side to remove P- (block 408), and then P-base 214 and P-base 222 are formed by using P-base diffusion (block 410).

[0030] To form the emitter 202 layer, N+ emitter photoresist and diffusion are performed at the emitter (e.g., emitter 202) (block 412). In some embodiments, N+ emitter doping is heavily doped compared to N- substrate doping. Subsequently, moating, passivation, contact, and metallization steps are performed (block 414), resulting in the formation of the thyristor semiconductor 200.

[0031] Figure 5 is a representative flow chart showing alternative methods 500 performed in producing the thyristor semiconductor 200 of Figures 2A and 2B according to several embodiments. Similar to methods 300 and 400, the process begins with doping the semiconductor wafer to become an N-substrate (block 502). A P-type isolation photoresist and diffusion operation is performed, which is carried out simultaneously on both sides of the N-substrate (cathode side and anode side) (block 504). To form the P-base layer 210, P-base boron diffusion is then performed on the cathode side of the N-substrate (block 506), resulting in the P-base 210 (Figure 2A).

[0032] P-base diffusion is performed on both sides of the N-substrate (simultaneously on the cathode-side P-base 222 and the anode-side P-base 214) (block 508). In some embodiments, the P-base is doped with boron. In other embodiments, the P-base is doped with gallium. Thus, using method 500, the P-base 210 is formed using boron diffusion (block 506), and since boron diffusion is performed only on the cathode side, the grinding step (as shown in block 408) is unnecessary, after which the P-bases 214 and 222 are formed (block 508).

[0033] To form the emitter 202 layer, N+ emitter photoresist and diffusion are performed at the emitter (e.g., emitter 202) (block 510). In some embodiments, N+ emitter doping is performed at a higher concentration compared to N- substrate doping. Subsequently, moating, passivation, contact, and metallization steps are performed (block 512), resulting in the formation of the thyristor semiconductor 200.

[0034] When used herein, elements or steps described in the singular and preceded by the word "a" or "an" should be understood not to exclude multiple elements or steps unless explicitly stated otherwise. Furthermore, references to “one embodiment” in this disclosure are not intended to be construed as excluding the existence of additional embodiments that also incorporate the described features.

[0035] While this disclosure refers to specific embodiments, numerous modifications, alterations, and changes can be made to the embodiments described without departing from the scope and scope of this disclosure as defined in the appended claims. Accordingly, this disclosure is not limited to the embodiments described and is intended to have the entire scope as defined by the following claims language and equivalents.

Claims

1. A first layer having a first P layer, disposed on a first surface of a substrate; A second layer having a second P layer, disposed on a second surface of the substrate, facing the first surface; A third layer disposed between the first layer and the substrate; An isolation region is provided along the edge of the substrate, wherein the isolation region is bonded to the second P layer; and An emitter is positioned adjacent to the first P layer, wherein the emitter is coupled to the cathode. A thyristor semiconductor equipped with this feature.

2. The thyristor semiconductor according to claim 1, wherein the first P layer includes a P base.

3. The thyristor semiconductor according to claim 2, wherein the second P layer includes the P base.

4. The thyristor semiconductor according to claim 1 or 2, wherein the third layer has a P-base.

5. The emitter is doped with N+, according to claim 1 or 2, the thyristor semiconductor.

6. The substrate is doped with N-, as described in claim 1 or 2, the thyristor semiconductor.

7. The thyristor semiconductor according to claim 6, wherein the emitter and the first P layer form a first PN junction, the third layer having a P base and the substrate form a second PN junction, and the substrate and the second P layer form a third PN junction.

8. The thyristor semiconductor according to claim 1 or 2, further comprising a moat disposed adjacent to the isolation region.

9. The thyristor semiconductor according to claim 8, wherein the moat is adjacent to the substrate, the first P layer, and the third layer having a P-base.

10. The thyristor semiconductor according to claim 8, wherein the moat is covered with glass, and the glass is used as a passivation region.

11. The step of providing an N-substrate; In the first region above the N-substrate, and simultaneously in the second region below the N-substrate, Performing P-type isolation photoresist and diffusion; and Performing P-based gallium diffusion simultaneously in the first and second regions. The step of forming a first layer; and A step in which a grinding operation is performed on the second region to remove P- from the second region. A method for forming a thyristor semiconductor comprising the features described above.

12. The method according to claim 11, further comprising the step of performing P-based diffusion on the first region and the second region.

13. The method according to claim 12, wherein the P-based diffusion is boron doping.

14. The method according to claim 12, wherein the P-based diffusion is gallium doping.

15. The method according to any one of claims 12 to 14, wherein the P-based diffusion is performed simultaneously on the first region and the second region.

16. The method according to any one of claims 12 to 14, further comprising the step of performing N+ emitter photoresist and diffusion.

17. The step of providing an N-substrate; A step of forming a first layer by performing diffusion of a P-type isolation photoresist in a first region above the N-substrate and simultaneously in a second region below the N-substrate; A step of performing P-based boron diffusion in the first region; and Steps to perform P-based diffusion in the first and second regions. A method for forming a thyristor semiconductor comprising the features described above.

18. The method according to claim 17, wherein the P-based diffusion is boron doping.

19. The method according to claim 17, wherein the P-based diffusion is gallium doping.

20. The method according to any one of claims 17 to 19, further comprising the step of performing N+ emitter photoresist and diffusion.

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