Polycrystalline ceramic substrate and method for manufacturing the same

Abstract

This provides a substrate structure suitable for epitaxial growth. [Solution] A designed substrate structure is provided, comprising: a polycrystalline ceramic substrate having a front surface characterized by a plurality of voids; a barrier layer bonded to the polycrystalline ceramic substrate and defining a plurality of valleys corresponding to the plurality of voids; a first bonding layer comprising a bonding layer material and bonded to the barrier layer on the front surface of the polycrystalline ceramic substrate, the first bonding layer defining a plurality of filled regions in which the bonding layer material is filled in the plurality of valleys corresponding to the plurality of voids; and a designed layer bonded to the barrier layer and the first bonding layer.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 354,623, filed on 24 June 2016, entitled “POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE,” the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002]

[0002] The following U.S. patent applications were filed concurrently with this application, and the disclosures of this application are incorporated herein by reference in their entirety for all purposes.

[0003]

[0003] Patent application No. 15 / 621,235, titled "POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE", filed on June 13, 2017 (agent reference number 098825-1049531 (003210US)). [Background technology]

[0004]

[0004] Light-emitting diode (LED) structures are typically grown epitaxially on a sapphire substrate. Currently, many products use LED devices, including lighting, computer monitors, and other display devices.

[0005]

[0005] The growth of gallium nitride-based LED structures on a sapphire substrate is a heteroepitaxial growth process because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown material may exhibit various adverse effects, including reduced uniformity and decreased metrics related to the electronic / optical properties of the epitaxial layer. Therefore, improved methods and systems related to the epitaxial growth process and substrate structure are needed in this field. [Overview of the Initiative]

[0006]

[0006] The present invention relates to generally designed substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. As just one example, the present invention applies to methods and systems that provide substrate structures suitable for epitaxial growth, the structures characterized by a coefficient of thermal expansion (CTE) substantially compatible with the epitaxial layer grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0007]

[0007] According to one embodiment, a method for manufacturing a ceramic substrate structure includes preparing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer bonded to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define a filling region, and depositing a second bonding layer on the exposed barrier layer and at least a portion of the filling region. In other embodiments, the barrier layer is not exposed during the removal process.

[0008]

[0008] According to another embodiment, a method for manufacturing a ceramic substrate structure includes preparing a ceramic substrate, forming a bonding layer to bond to the front surface of the ceramic substrate, performing a chemical mechanical polishing (CMP) process to remove part of the bonding layer and expose at least part of the front surface of the ceramic substrate, and encapsulating the ceramic substrate in a barrier layer. In some embodiments, the barrier layer may contain silicon nitride. The front surface of the ceramic substrate may be characterized by an RMS roughness in the range of 50 to 600 nm, and the barrier layer may be characterized by an RMS roughness in the range of 0.5 to 2 nm. The front surface of the ceramic substrate may be characterized by a plurality of voids, and the bonding layer may fill a plurality of voids.

[0009]

[0009] Many advantages are achieved by the present invention compared to the prior art. For example, embodiments of the present invention provide a substrate structure suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) substantially matching that of the epitaxial layer grown thereon. Matching the thermal expansion characteristics of the growth substrate to those of the epitaxial layer reduces stress in the epitaxial layer and / or the designed substrate. Stress can cause several types of defects. For example, stress can increase the dislocation density in the epitaxial layer, which impairs the electrical and optical properties of the epitaxial layer. Stress can also result in residual strain in the epitaxial layer or substrate, which can lead to further processing concerns in later processes, such as stress cracks, dislocation slippage, bending, and warping. Bending and warping of the substrate due to thermal expansion can make handling the material difficult in automated equipment and limit the ability to perform additional lithography steps required for equipment manufacturing, substrate cracking, and material creep. In addition, stressed materials shorten the performance life of the equipment. Stress relaxation and stress-induced crack propagation resulting from thermal mismatch, dislocation sliding, and other lattice movements can lead to early failures ranging from degraded instrument performance to fracture or delamination of the instrument and instrument layers. The instrument is manufactured in an epitaxial layer.

[0010]

[0010] These and other embodiments of the present invention, along with many of their advantages and features, This will be explained in more detail in relation to the text and attached diagrams below. [Brief explanation of the drawing]

[0011] [Figure 1A] This is a simplified schematic diagram showing a substrate structure designed according to one embodiment of the present invention. [Figure 1B] This is a simplified flowchart illustrating a method for manufacturing a circuit board designed according to one embodiment of the present invention. [Figure 1C] This is a simplified schematic diagram showing a designed substrate structure including an epitaxial layer according to one embodiment of the present invention. [Figure 2] A simplified schematic diagram showing a designed substrate structure after deposition of a bonding layer according to an embodiment of the present invention. [Figure 3A] A simplified schematic diagram showing a designed substrate structure after thinning a bonding layer according to an embodiment of the present invention. [Figure 3B] A simplified schematic diagram showing a designed substrate structure after polishing to an etching stop layer according to an embodiment of the present invention. [Figure 3C] A simplified schematic diagram showing a designed substrate structure after redeposition of a bonding layer according to an embodiment of the present invention. [Figure 4] A simplified schematic diagram showing a designed substrate structure after forming one or more designed layers according to an embodiment of the present invention. [Figure 5] A simplified schematic diagram showing a designed substrate structure including a release layer according to an embodiment of the present invention. [Figure 6A] A simplified schematic diagram showing a polycrystalline ceramic core and a planarizing material according to an embodiment of the present invention. [Figure 6B] A simplified schematic diagram showing a polycrystalline ceramic core and a planarizing material after a CMP process according to an embodiment of the present invention. [Figure 6C] A simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell according to an embodiment of the present invention. [Figure 6D] A simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell having a peeled single-crystalline Si layer according to an embodiment of the present invention. [Figure 6E] A simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell covered with a deposited oxide and a peeled single-crystalline Si layer according to an embodiment of the present invention. [Figure 6F] A simplified schematic diagram showing formation of a designed layer on an encapsulated and planarized polycrystalline ceramic core according to an embodiment of the present invention. [Figure 6G]Simplified schematic view showing a detached Si layer above a designed layer on an encapsulated and planarized polycrystalline ceramic core according to an embodiment of the present invention. [Figure 6H] Simplified schematic view showing the formation of a bonding layer on a designed layer on an encapsulated and planarized polycrystalline ceramic core according to an embodiment of the present invention. [Figure 6I] Simplified schematic view showing the formation of a bonding layer on a designed layer on an encapsulated and planarized polycrystalline ceramic core having a detached Si layer according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]

[0029] Embodiments of the present invention relate to a designed substrate structure. More specifically, the present invention relates to methods and systems suitable for use in an epitaxial growth process. By way of example only, the present invention is applicable to methods and systems for providing a substrate structure suitable for epitaxial growth, the structure of which is characterized by a coefficient of thermal expansion (CTE) that substantially matches that of an epitaxial layer grown thereon. The methods and techniques can be applied to various semiconductor processing operations.

[0013]

[0030] FIG. 1A is a simplified schematic view showing a designed substrate structure according to an embodiment of the present invention. As shown in FIG. 1A, the designed substrate structure shown in FIG. 1A is suitable for various electronic and optical applications. The designed substrate structure can include a core 110 (e.g., an AlN substrate) having a coefficient of thermal expansion (CTE) that substantially matches that of an epitaxial material grown on the designed substrate structure, e.g., on a detached silicon (111) layer. As discussed more fully herein, the epitaxial material can include other elemental semiconductor materials including silicon layers having different crystal orientations other than (111) silicon, and / or compound semiconductor materials including gallium nitride (GaN)-based materials. These variations include, for example, crystal growth surfaces. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0014]

[0031] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 110 can be polycrystalline aluminum nitride (AlN) which can contain a polycrystalline ceramic material, such as a binder material such as yttrium oxide. Other materials, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), and polycrystalline gallium trioxide (Ga2O3), can be used for the core.

[0015]

[0032] The core thickness is approximately 100–1500 μm, for example, 725 μm. The core is encapsulated in an adhesive layer 112 (labeled TEOS), which can be called a shell or encapsulation shell. Figure 1A, which shows only the central portion of the designed substrate structure and not the edges, illustrates this encapsulation by showing the presence of the adhesive layer 112 above and below the core 110, and it will be understood that the adhesive layer 112 is also present at the edges of the core 110, which are not shown for clarity. Similarly, the conductive layer 114, the second adhesive layer 116, and the barrier layer 118, which will be discussed in detail below, are shown above and below the core layer, but it will be understood that these layers are also present at the edges. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0016]

[0033] In one embodiment, the adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) oxide layer with a thickness of approximately 1,000 Å. In other embodiments, the thickness of the adhesive layer varies, for example, from 100 Å to 2,000 Å. While TEOS oxide is used for the adhesive layer in some embodiments, other materials (e.g., ceramics, particularly polycrystalline ceramics) that provide adhesion between the later deposited layer and the layer or material beneath it can also be used according to embodiments of the present invention. For example, SiO2 or other silicon oxide (Si) x O yThe adhesive layer adheres well to ceramic materials and provides a surface suitable for subsequent deposition of conductive materials, for example. In some embodiments, the adhesive layer 112 completely surrounds the core 110, forming a fully enclosed core, which can be formed using an LPCVD process or other suitable deposition process, which may be compatible with semiconductor processing, particularly polycrystalline or composite substrates and layers. The adhesive layer provides a surface upon which subsequent layers are bonded to form elements of the designed substrate structure.

[0017]

[0034] In addition to the use of LPCVD processes, spin-on-glass / dielectric, and furnace processes for forming the encapsulation adhesive layer, other semiconductor processes, including CVD processes or similar deposition processes, can be utilized according to embodiments of the present invention. For example, a deposition process can be used to coat a portion of the core, the core can be flipped over, and the deposition process can be repeated to coat additional portions of the core. Thus, in some embodiments, LPCVD technology is used to provide a fully encapsulated structure, but other film deposition technologies can be used depending on the specific application.

[0018]

[0035] A conductive layer 114 is formed so as to surround the adhesive layer 112. In one embodiment, since polysilicon has poor adhesion to ceramic materials, the conductive layer is a polysilicon (i.e., polycrystalline silicon) shell formed so as to surround the adhesive layer. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer is about 500 to 5,000 Å. For example, it may be 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell so as to completely surround the adhesive layer (e.g., a TEOS oxide layer), thereby forming a fully encapsulated adhesive layer, and can also be formed using an LPCVD process. In other embodiments, as will be described later, the conductive material can be formed in part of the adhesive layer, for example, in the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a fully encapsulated layer and subsequently removed on one side of the substrate structure.

[0019]

[0036] In one embodiment, the conductive layer 114 can be a polysilicon layer doped to provide a highly conductive material, such as a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, to provide high conductivity, the doping with boron is from 1×10 19 cm -3 to 1×10 20 cm -3 level. Other dopants at different dopant concentrations (e.g., phosphorus, arsenic, bismuth, etc. with dopant concentrations in the range of 1×10 16 cm -3 to 5×10 18 cm -3 can be utilized to provide either an n-type or p-type semiconductor material suitable for use in the conductive layer. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0020]

[0037] The presence of the conductive layer 114 is useful when electrostatically chucking a designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC or e-chuck). The conductive layer enables rapid de-chucking after processing in a semiconductor processing tool. In embodiments of the present invention, the conductive layer enables electrical contact with the chuck or capacitive coupling to an electrostatic chuck (ESC or e-chuck) during future processing including bonding. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives. Further, having a substrate structure with high thermal conductivity in combination with an ESD chuck can provide better deposition conditions for subsequent formation of designed layers and epitaxial layers, as well as for subsequent device manufacturing processes. For example, it can provide a desirable thermal profile that can result in lower stress, more uniform deposition thickness, and better stoichiometric control through subsequent layer formation.

[0021]

[0038] A second adhesive layer 116 (for example, a TEOS oxide layer with a thickness of about 1000 Å) is formed to surround the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer to form a complete encapsulation structure, which can be formed using an LPCVD process, a CVD process, or any other suitable deposition process including spin-on dielectric deposition.

[0022]

[0039] A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer with a thickness of approximately 2,000 Å to 5,000 Å. In some embodiments, the barrier layer completely surrounds the second adhesive layer 116 to form a complete encapsulation structure, and can also be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc., can be used as barrier layers. In some embodiments, the barrier layer consists of several sublayers constructed to form the barrier layer. Therefore, the term barrier layer is intended to encompass one or more materials laminated in a composite manner, rather than meaning a single layer or single material. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0023]

[0040] In some embodiments, the barrier layer 118, for example, a silicon nitride layer, allows the designed substrate to be exposed to the environment of a semiconductor processing chamber, for example, during a high-temperature (e.g., 1,000°C) epitaxial growth process, while protecting it from elements present within the core 110, such as yttrium (of the element), yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements. However, it prevents diffusion and / or gas release. By utilizing the encapsulation layer described herein, ceramic materials containing polycrystalline AlN designed for non-cleanroom environments can be used in semiconductor process flows and cleanroom environments.

[0024]

[0041] Typically, the ceramic material used to form the core is fired at temperatures in the range of 1,800°C. This process is expected to remove a considerable amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, during the epitaxial growth process, which takes place at much lower temperatures in the range of 800°C to 1,100°C, it would be expected that the subsequent diffusion of these impurities would be minimal. However, contrary to conventional expectations, the inventors have found that significant diffusion of elements can occur through the layers of the designed substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Therefore, embodiments of the present invention integrate a barrier layer into the designed substrate structure to prevent this undesirable diffusion.

[0025]

[0042] Referring again to Figure 1A, the bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, for example, on the upper surface of the barrier layer, and is then used during bonding of the substantial single-crystal layer 125 (e.g., a single-crystal silicon layer such as the exfoliated silicon (111) layer). In some embodiments, the bonding layer 120 may have a thickness of about 1.5 μm. In some embodiments, the thickness of the bonding layer is 20 nm or more for bonding-induced void relaxation. In some embodiments, the thickness of the bonding layer is in the range of 0.75 to 1.5 μm.

[0026]

[0043] The substantially single-crystal layer 125 (e.g., exfoliated Si(111)) is suitable for use as a growth layer during the epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material may include a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of several layers utilized in optoelectronic devices, RF devices, and power devices. In one embodiment, the substantially single-crystal layer includes a single-crystal silicon layer attached to a junction layer using a layer transfer process.

[0027]

[0044] Figure 1B is a simplified flowchart illustrating a method for manufacturing a designed substrate according to one embodiment of the present invention. This method can be used to manufacture a substrate with CTE matching to one or more epitaxial layers grown on the substrate. Method 150 includes forming a support structure by providing a polycrystalline ceramic core (160), which can be a cleaned and inspected aluminum nitride (AlN) substrate. Other polycrystalline ceramic cores can be used as described above.

[0028]

[0045] The method also includes encapsulating a polycrystalline ceramic core in a first adhesive layer (e.g., a tetraethyl orthosilicate (TEOS) oxide shell with a thickness of approximately 80 nm) that forms a shell (162), and encapsulating the first adhesive layer in a conductive shell (164) (e.g., a polysilicon shell with a thickness of approximately 300 nm). The first adhesive layer can be formed as a single layer of TEOS oxide. The conductive shell can be formed as a single layer of polysilicon.

[0029]

[0046] The method also includes encapsulating a conductive shell in a second adhesive layer (166) (e.g., a second TEOS oxide shell with a thickness of approximately 80 nm) and encapsulating the second adhesive layer in a barrier layer shell (168). The second adhesive layer can be formed as a single layer of TEOS oxide. The barrier layer shell can be formed as a single layer of silicon nitride with a thickness of approximately 400 nm. Further descriptions of the designed substrate structure are provided in U.S. Provisional Patent Application No. 62 / 350084, filed on 14 June 2016 (Agent Reference Number 098825-1011030-001100US), and the disclosures thereof are fully disclosed. For the purpose of this invention, the whole is incorporated herein by reference. Embodiments of the present invention, as described herein, are Si x O y Si x N y Si x O y N zVarious materials, including various dielectrics such as diamond-like carbon (DLC) and combinations thereof, can be used for the adhesive layer and diffusion barrier. Other materials such as Ti, TiW, Ta, and TiN encapsulated in dielectrics can also be used. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0030]

[0047] Once a support structure including a core, adhesive layer, conductive layer, and diffusion barrier is formed by processes 160-168, the method further includes depositing a bonding layer (e.g., a PECVD silicon oxide layer) on the support structure (170) and bonding a substantial single-crystal layer, e.g., a single-crystal silicon layer, to the bonding layer (172). According to embodiments of the present invention, other substantial single-crystal layers including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc., can be used. The deposition of the bonding layer may include the deposition of a bonding material and the subsequent planarization process described herein. In embodiments described later, bonding a substantial single-crystal layer (e.g., a single-crystal silicon layer) to the bonding layer utilizes a layer transfer process in which the layer is a single-crystal silicon layer transferred from a silicon wafer.

[0031]

[0048] Referring to Figure 1A, the bonding layer 120 can be formed by depositing a thick (e.g., 4 μm thick) oxide layer (e.g., PECVD), followed by a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of approximately 1.5 μm (as further described below in relation to Figure 3A). The thick initial oxide may be present after the fabrication of the polycrystalline core and helps fill voids and surface features present on the support structure that may remain present when the encapsulation layer shown in Figure 1A is formed. The CMP process provides a substantially flat surface free from voids, particles, or other features, which can then be used during the wafer transport process to bond a substantially single-crystal layer, represented by the exfoliated single-crystal silicon (111) layer shown in Figure 1A, to the bonding layer. The bonding layer does not need to be characterized by an atomically flat surface, but should provide a substantially flat surface that facilitates bonding of a substantially single-crystal layer (e.g., a single-crystal silicon layer) with the desired reliability.

[0032]

[0049] One example of a layer transfer process that can be used to bond a substantial single-crystal layer to a bonding layer is the bonding of a hydrogen-implanted donor wafer (e.g., a silicon wafer containing a substantial single-crystal layer (e.g., a single-crystal silicon layer) implanted to form a cleavage plane) to a bonding layer. The bonding pair is then annealed at an annealing temperature (e.g., 200°C) for an annealing period (e.g., 4 hours) to cluster the implanted species (e.g., hydrogen) into blisters. After annealing, the donor wafer cracks along the cleavage plane, exfoliating the layer of substantial single-crystal material onto the bonding layer. As shown in Figure 1A, the Si layer (111) is exfoliated onto the PECVD bonding layer. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0033]

[0050] The method shown in Figure 1B may also include smoothing the substantial single-crystal layer (174). Referring to Figure 1A, the substantial single-crystal layer 125 may be a single-crystal silicon (e.g., a Si(111) layer) transferred onto the junction layer 120. The thickness of the substantial single-crystal layer 125 can be varied to suit the specifications of various applications. Furthermore, the crystal orientation of the substantial single-crystal layer 125 can be varied to suit the specifications of the application. In addition, the doping level and profile in the substantial single-crystal layer 125 can be varied to suit the specifications of a particular application. The smoothing shown in relation to reference no. 174 may also include thinning the substantial single-crystal layer as a component of the smoothing process.

[0034]

[0051] In some embodiments, the thickness and surface roughness of the substantial single-crystal layer 125 can be further modified for high-quality epitaxial growth. Different apparatus applications may have slightly different specifications regarding the thickness and surface smoothness of the substantial single-crystal layer 125. The cleavage process exfoliates a substantial single-crystal layer 125 from the bulk single-crystal silicon wafer at the peak of the implanted ion profile. After cleavage, the substantial single-crystal layer 125 can be prepared or modified in several ways before being used as a growth surface for the epitaxial growth of other materials such as gallium nitride.

[0035]

[0052] Firstly, the transferred substantial single-crystal layer 125 may contain a small amount of residual hydrogen and may have some crystal damage due to the implantation. Therefore, it may be beneficial to remove the thin portion of the transferred substantial single-crystal layer 125 in which the crystal lattice is damaged. In some embodiments, the implantation depth can be adjusted to be greater than the desired final thickness of the substantial single-crystal layer 125. The additional thickness allows for the removal of the damaged thin portion of the transferred substantial single-crystal layer, leaving an undamaged portion of the desired final thickness.

[0036]

[0053] Secondly, it may be desirable to adjust the overall thickness of the substantial single-crystal layer 125. Generally, the substantial single-crystal layer 125 is desirable to be thick enough to provide a high-quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough for a high degree of fit. The substantial single-crystal layer 125 can be said to be "well-fitted" when it is relatively thin, such that its physical properties (e.g., CTE) closely resemble those of the surrounding material. The fit of the substantial single-crystal layer 125 may be inversely proportional to its thickness. A higher fit results in a lower defect density in the epitaxial layer grown on the template, allowing for the growth of thicker epitaxial layers. In some embodiments, the thickness of the substantial single-crystal layer 125 can be increased by epitaxially growing silicon on a delaminate silicon layer.

[0037]

[0054] Thirdly, improving the smoothness of the substantial single-crystal layer 125 may be beneficial. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-injected species, and the annealing conditions used to form the hydrogen-based cleavage plane. As will be discussed later, the initial roughness resulting from the layer transfer (i.e., the cleavage process) can be mitigated by thermal oxidation and oxide exfoliation.

[0038]

[0055] In some embodiments, the removal of the damaged layer and adjustment of the final thickness of the substantially single-crystal layer 125 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by exfoliation of the oxide layer with hydrofluoric acid (HF). For example, a exfoliated silicon layer having an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of approximately 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer may be approximately 53 nm. During thermal oxidation, the injected hydrogen can move toward the surface. Therefore, the subsequent exfoliation of the oxide layer can remove some damage. Also, thermal oxidation is typically carried out at temperatures of 1000°C or higher. High temperatures can also repair lattice damage.

[0039]

[0056] The silicon oxide layer formed on top of the substantial single-crystal layer during thermal oxidation can be exfoliated using HF acid etching. The etching selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by adjusting the temperature and concentration of the HF solution, as well as the stoichiometry and density of the silicon oxide. Etching selectivity refers to the etching rate of one material compared to another. The selectivity of the HF solution can range from about 10:1 to about 100:1 for (SiO2:Si). High etching selectivity can reduce surface roughness from the initial surface roughness by similar factors. However, the resulting surface roughness of the substantial single-crystal layer 125 may still be greater than desired. For example, a bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm, as determined by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness for epitaxially growing gallium nitride material on Si(111) is, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm on a 30 μm × 30 μm AFM scan area. could be.

[0040]

[0057] If the surface roughness of the substantial single-crystal layer 125 after thermal oxidation and oxide layer delamination exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods for smoothing a silicon surface. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing, i.e., CMP). These methods may involve preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, resulting in a smoother surface.

[0041]

[0058] Figure 1C is a simplified schematic diagram showing a designed substrate structure including an epitaxial layer according to one embodiment of the present invention. As shown in Figure 1C, a planarization layer 705, which may be a planarized version of a substantially single-crystal layer 125, is utilized in the growth process for the formation of the epitaxial layer 710. The planarization layer 705 can be manufactured using one or more planarization techniques described herein. In some embodiments, the epitaxial layer 710 includes a GaN-based layer with a thickness of 2 μm to 10 μm or more, which can be used as one of several layers utilized in an optoelectronic device.

[0042]

[0059] It should be understood that the specific steps shown in Figure 1B provide a specific method for manufacturing a substrate designed according to one embodiment of the present invention. Other embodiments may also perform other sets of steps. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, the individual steps shown in Figure 1B may include several sub-steps that can be performed in various orders as appropriate for the individual steps. Additionally, additional steps may be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0043]

[0060] Figure 2 is a simplified schematic diagram showing a designed substrate structure after deposition of a bonding layer according to one embodiment of the present invention. As shown in Figure 2, the upper surface 121 of the bonding layer 120 (e.g., PECVD oxide) is originally rough, and the surface profile is determined to some extent by the surface roughness of the underlying layers and materials. As discussed with respect to Figure 1B, the initial thickness of the bonding layer may be several microns (e.g., 4 μm) in order for the bonding layer to fill the pores present in the polycrystalline ceramic core 110. The bonding layer can be formed in a single-step process or a multi-step process, such as repeated deposition / removal cycles. As an example, the bonding layer can be polished after deposition of the bonding layer material to reduce its thickness and improve its planarity. Then, this deposition / polishing cycle can be repeated several times to obtain a bonding layer having a surface roughness smaller than the surface roughness characterizing the original polycrystalline ceramic core surface. Furthermore, different materials can be used in different cycles, providing a layered structure with multiple materials. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0044]

[0061] Figure 3A is a simplified schematic diagram showing a designed substrate structure after thinning the junction layer according to one embodiment of the present invention. The inventors have found that heat transfer and capacitive effects affecting switching speed are improved for apparatus applications, or that the junction layer (e.g., PECVD oxide layer) can be customized for apparatus applications by thinning it from an initial value of a few microns to a value in the range of 100 Å to 1.5 μm.

[0045]

[0062] As shown in Figure 3A, the thickness of the bonding layer 120 can be reduced using the CMP process. However, if the initial thickness of the bonding layer is around a few microns (e.g., 4 μm), which is suitable for the bonding layer to fill the pores present in the polycrystalline ceramic core, the CMP process cannot smooth out all defects present in the bonding layer. Furthermore, CMP pad fitting, slurry control, and pressing in various areas on the apparatus are also challenges. Controlling the downward force presents a challenge in achieving flatness across the entire substrate, thereby providing a smooth and flat bond layer. For example, roll-off at the substrate edges may result in edge film thicknesses that are smaller (i.e., thinner) or larger (i.e., thicker) than the average layer thickness.

[0046]

[0063] Figure 3A shows a flat top surface 310, but in a realistic process flow, the thickness variation of the bonding layer 120 is within a range of 4,000 Å, and as a result, a significant thickness variation occurs when the layer thickness decreases to 1.5 μm or less.

[0047]

[0064] Figure 3B is a simplified schematic diagram showing the designed substrate structure after polishing to the etching stop layer according to one embodiment of the present invention. As shown in Figure 3B, the CMP process ends when the barrier layer 118 (e.g., silicon nitride) is exposed. Since the hardness of the barrier layer material can be much greater than that of the relatively softer bonding layer, the barrier layer material can provide a natural CMP stop layer.

[0048]

[0065] Referring to Figure 3B, the bonding layer 120 (e.g., PECVD oxide) is thinned by a CMP process using the barrier layer 118 (e.g., LPCVD nitride) as the CMP stop layer. Differences in removal rates are induced on the CMP tool, and in combination with a thickness feedback system, the CMP process stops on the barrier (e.g., nitride) layer. Note that in Figure 3B, the amount of pores present in the polycrystalline core is exaggerated for illustrative purposes. In reality, the relative surface area of ​​the exposed barrier layer (i.e., the coplanar nitride region) is much larger than the surface area of ​​the bonding layer represented by the PECVD oxide.

[0049]

[0066] As shown in Figure 3B, the top surface 320 of the substrate structure includes regions of bonding layer material 120 (e.g., PECVD oxide) and regions of barrier layer material 118 (e.g., LPCVD nitride). This electrically insulating top surface 320 can provide a bonding surface suitable for bonding donor wafers as described above. In this example, a single-crystal silicon layer can be bonded to the collection of oxide and nitride regions. The valleys or voids between adjacent peaks of the polycrystalline ceramic core can be called filled regions 305, since they are filled with bonding layer material. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0050]

[0067] In some embodiments, instead of using the barrier layer 118 as a CMP stop, an additional CMP stop layer is deposited before the deposition of the bonding layer. Referring to Figure 2, the additional CMP stop layer is formed between the barrier layer 118 (e.g., a nitride layer) and the PECVD bonding layer 120. Thus, the CMP process ends with the additional CMP stop layer, thereby protecting the barrier layer from removal or excessive thinning that could impair its barrier properties. The ability of the barrier layer to prevent the diffusion of impurities depends on the thickness and diffusion rate of the barrier layer. If the barrier layer is too thin, it may not provide sufficient barrier function.

[0051]

[0068] Figure 3C is a simplified schematic diagram showing a designed substrate structure after redeposition of the bonding layer 320 according to one embodiment of the present invention. As an alternative to the bonding surface shown in Figure 3B, a thin layer of bonding material can be deposited after the CMP process. Referring to Figure 3B, after stopping at the barrier layer 118 and removing the bonding layer material using the CMP process, a thin layer (e.g., 200 Å) of a very uniform bonding material (e.g., PECVD oxide) can be redeposited on the polished structure. The bonding layer 320 can be called the redeposited layer. Using a stopping layer (either a barrier layer or an additional CMP stopping layer) allows for better control of surface flatness compared to thinning without a stopping layer, so the surface of the bonding layer after the CMP process shown in Figure 3B can be relatively flat. The bonding layer 320 is conformal to the planarized surface of the bonding layer, and Since the surface uniformity of the bonding layer 320 is proportional to the total thickness of the bonding layer 320, the surface of a thin bonding layer 320 can be perfectly uniform. Therefore, the bonding layer 320 provides a continuous bonding surface with superior surface flatness compared to that which can be achieved by applying CMP to a thick bonding layer without using a stop layer. In Figure 3C, PECVD oxide is shown as the bonding material, but this is not required in the present invention, and other materials, such as silicon nitride, can be redeposited. Thus, embodiments of the present invention provide a thin and controllable bonding layer with properties independent of the bonding material used to enhance the planarity of a polycrystalline ceramic core. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0052]

[0069] In some embodiments, the CMP stop layer may be a polycrystalline ceramic core 110 (e.g., AlN material within the core). In these embodiments, the barrier layer and the underlying adhesive and conductive layers are removed to expose the upper surface of the core material.

[0053]

[0070] Using the processes described herein, a significant increase in the planarity from the polycrystalline ceramic core to the redeposited layer 320 can be achieved. For example, in one embodiment, the grown surface of the ceramic substrate can be characterized by an RMS roughness in the range of 50–600 nm RMS for an AFM scan of a 50 μm × 50 μm area, which is achievable with conventional wafer polishing techniques. Using the processes described herein, the redeposited layer can be characterized by an RMS roughness in the range of 0.5–2 nm RMS for an AFM scan of a 30 μm × 30 μm area, which represents an improvement of two to three orders of magnitude in surface roughness. The planarity of the layer before CMP can be as high as 30% of the total thickness of the layer. For a 4 μm layer, this could be 1.2 μm. The planarity of the surface after CMP on the stop layer is typically less than 2%, meaning the planarity improves by approximately 10 times.

[0054]

[0071] Figure 4 is a simplified schematic diagram showing a designed substrate structure after forming one or more designed layers according to one embodiment of the present invention. Starting from a designed substrate structure after thinning the bonding layer as shown in Figure 3A or Figure 3B, one or more designed layers, which may include one or more dielectric layers, are formed or deposited on the thin designed substrate structure. As shown in Figure 4, the designed layer 410, which provides good adhesion to the barrier layer 118 and the bonding layer 120 material (e.g., PECVD oxide), can be deposited to cover the exposed barrier layer portion and the filler region.

[0055]

[0072] The designed layers can be formed using a variety of materials. Examples of dielectric materials include silicon nitride, oxynitride, silicon oxynitride, spin-on-glass / dielectric, DLC, and combinations thereof. The thickness of the designed layer can range from very thin layers of about 100-200 Å to thick layers of several microns (e.g., 2 μm), depending on the specific device specifications, including heat transfer, capacitance, and breakdown voltage characteristics. In some embodiments, a conductive layer containing a high-melting-point metal, rather than a dielectric, is deposited as the designed layer. In other embodiments, a multilayer structure containing both one or more dielectric layers and one or more conductive layers is fabricated to provide desired thermal, mechanical, and electrical properties.

[0056]

[0073] The designed layer 410 shown in Figure 4 enables extended processing capacity compared to the use of a bonding layer 320 formed using the same material as bonding layer 120. Therefore, the embodiment shown in Figure 4 provides an alternative bonding capacity with extended capabilities compared to the embodiment shown in Figure 3C.

[0057]

[0074] Figure 5 is a simplified schematic diagram showing a designed substrate structure including a delamination layer 510 according to one embodiment of the present invention. The structure shown in Figure 5 utilizes one or more designed layers shown in Figure 4 to provide a bonding interface between the designed layer and the substantially single-crystal layer 510, which is delamination. It could be a single-crystal silicon (111) layer.

[0058]

[0075] The thickness of the release layer 510 can be varied to suit the specifications of various applications. Furthermore, the crystal orientation of the release layer can be varied to suit the specifications of the application. For example, the crystal orientation can be controlled to strain the next epitaxial layer grown after the fabrication of the structure shown in Figure 5. In addition, the doping level and profile in the release layer can be varied to suit the specifications of a particular application. Note that the release layer can be integrated with other designed substrate structures described herein, including the designed substrate structures shown in Figures 1A, 3A, 3B, 3C, and 4.

[0059]

[0076] As an alternative to the process flow and structure described above, some embodiments of the present invention enhance the flatness of the polycrystalline ceramic core before the deposition of the conductive layer and barrier layer. Accordingly, some embodiments provide a surface treatment process for the polycrystalline ceramic core before forming the designed laminate described herein, thereby enhancing the flatness of the polycrystalline ceramic core surface before forming the conductive layer, barrier layer, and other layers.

[0060]

[0077] Figure 6A is a simplified schematic diagram showing a polycrystalline ceramic core and planarizing material according to one embodiment of the present invention. The polycrystalline ceramic core 110 is shown as an AlN substrate. An adhesion-promoting layer 610 is formed on one or more faces of the polycrystalline ceramic core, and a planarizing material 620 (e.g., a PECVD oxide packing layer) is deposited on the adhesion-promoting layer 610. The adhesion-promoting layer can be TEOS oxide, e.g., TEOS oxide of 100 Å to 1,000 Å, or other suitable material, as discussed herein. The planarizing material 620 can be an oxide, nitride, spin-on-glass (SOG), or other suitable material. In some embodiments where the planarizing material adheres well to the polycrystalline ceramic core, the adhesion-promoting layer is removed. The thickness of the planarizing material is selected to fill voids and surface features present in the polycrystalline ceramic core, and the thickness may be on the order of a few microns. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0061]

[0078] Figure 6B is a simplified schematic diagram showing a polycrystalline ceramic core and planarization material after the CMP process according to one embodiment of the present invention. After the deposition of the planarization material 620, a CMP process is used in which the polycrystalline ceramic core 110 (AlN substrate) becomes the CMP stop, thereby polishing away the excess portion of the planarization material. As shown in Figure 6B, the presence of polycrystalline ceramic core material as the CMP stop is in a very small amount (e.g., only 50 Å to 100 Å of planarization material outside the void). This reduction in the amount of oxide or other insulating material increases the thermal conductivity of the finished substrate structure and ultimately the equipment fabricated thereon. Since polycrystalline ceramic cores have high thermal conductivity, reducing the thickness of the oxide or other insulating layer can have a significant impact on the overall thermal performance. In some embodiments, a thin dielectric layer (e.g., oxide or nitride) is deposited after the completion of the CMP process.

[0062]

[0079] Figure 6C is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell according to one embodiment of the present invention. A barrier layer 630 (e.g., silicon nitride) is deposited, and as shown in Figure 6C, the barrier layer 630 encapsulates the polycrystalline ceramic core 110 and can be made from one or more materials including Si3N4, oxynitrides, diamond-like carbon (DLC), other suitable materials, or combinations thereof. In one embodiment, the polycrystalline ceramic core is completely encapsulated using an LPCVD process or a suitable furnace process.

[0063]

[0080] A barrier layer 630, for example, a silicon nitride layer, is formed to surround the polycrystalline ceramic core. In one embodiment, the barrier layer is made of silicon nitride with a thickness of about 2,000 Å to 5,000 Å. This is a silicon nitride layer. In some embodiments, the barrier layer completely surrounds the polycrystalline ceramic core, forming a fully enclosed structure. In addition to the silicon nitride layer, amorphous materials including SiCN, SiON, AlN, SiC, etc., can be used as barrier layers. In some embodiments, the barrier layer 630 consists of several sublayers constructed to form the barrier layer. Thus, the term barrier layer is intended to encompass one or more materials laminated in a composite manner, rather than meaning a single layer or single material. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0064]

[0081] In some embodiments, the barrier layer 630, for example, a silicon nitride layer, prevents elements present within the polycrystalline ceramic core, such as yttrium (elemental), yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements, from diffusing and / or releasing gases into the semiconductor processing chamber environment in which the designed substrate can be present, for example, during high-temperature (e.g., 1,000°C) epitaxial growth processes. By utilizing the encapsulation layer described herein, ceramic materials containing polycrystalline AlN designed for non-cleanroom environments can be used in semiconductor process flows and cleanroom environments.

[0065]

[0082] Figure 6D is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated in a barrier shell having a delaminated single-crystal silicon layer according to an embodiment of the present invention. A delamination layer 640, for example, a single-crystal silicon layer, is formed on a barrier layer 630, for example, a silicon nitride layer. The thickness of the delamination layer 640 can be varied to meet the specifications of various applications. Furthermore, the crystal orientation of the delamination layer 640 can be varied to suit the application specifications. Furthermore, the doping level and profile in the delamination layer can be varied to suit the specifications of a particular application. The delaminated single-crystal silicon layer (e.g., delaminated Si(111)) is suitable for use as a growth layer in an epitaxial growth process for forming an epitaxial material. In some embodiments, the epitaxial material may include a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of several layers utilized in optoelectronic devices, RF devices, and power devices. While a single-crystal silicon layer is shown in Figure 6D, other substantial single-crystal layers may be utilized according to embodiments of the present invention.

[0066]

[0083] Figure 6E is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell covered with a deposited oxide and a delaminated single-crystal silicon layer, according to one embodiment of the present invention. In this embodiment, an oxide layer 642 (e.g., a silicon oxide layer) is deposited on the barrier layer 630. The oxide layer 642 can function as a bonding interface between the barrier layer 630 and the delamination layer 640, which can be a single-crystal silicon layer. According to some embodiments, the oxide layer can have a thickness of several hundred angstroms. Although a single-crystal silicon layer is shown in Figure 6E, other substantially single-crystal layers may be utilized according to embodiments of the present invention.

[0067]

[0084] Figure 6F is a simplified schematic diagram showing the formation of a designed layer on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. Figure 6F shows the deposition of a conductive layer 650 for the chuck, including a metal layer (e.g., W, Ti, etc.), a polysilicon layer, or a combination thereof. In addition to the conductive layer, a thermal management layer 652 (e.g., DLC, SiON, silicon nitride, etc.) can be deposited to provide high thermal conductivity across the substrate.

[0068]

[0085] In Figure 6F, only the barrier layer 630 is shown to enclose the polycrystalline ceramic core, but this is not essential to the present invention. Other layers, including a conductive layer and a thermal management layer, can be formed as a shell. In some embodiments, the conductive layer 650 is formed on the bottom or back surface 651 of the substrate structure to suit the chuck, and the thermal management layer is formed on the top or front surface of the substrate structure to conduct heat generated in the device laterally. Thus, the layers seal Whether or not they are formed as an infill shell, the position of the layers relative to the polycrystalline ceramic core can be varied according to embodiments of the present invention. Furthermore, adhesion-promoting layers and other suitable layers can be inserted as appropriate for specific applications.

[0069]

[0086] Figure 6G is a simplified schematic diagram showing a delamination Si layer 654 on a designed layer on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. The thickness of the delamination layer 654 can be varied to meet the specifications of various applications. Furthermore, the crystal orientation of the delamination layer can be varied to suit the application specifications. Furthermore, the doping level and profile in the delamination layer can be varied to suit the specifications of a particular application. As an example, a delamination single-crystal silicon layer (e.g., delamination Si(111)) is suitable for use as a growth layer in an epitaxial growth process for forming an epitaxial material. In some embodiments, the epitaxial material (not shown) may include a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of several layers utilized in optoelectronic devices, RF devices, and power devices. Although a single-crystal silicon layer is shown in Figure 6G, other substantially single-crystal layers may be utilized according to embodiments of the present invention.

[0070]

[0087] Figure 6H is a simplified schematic diagram showing the formation of a bonding layer 660 on a designed layer on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. To provide a suitable bonding surface when the designed layer shown in Figure 6F (e.g., conductive layer 650 and thermal management layer 652) is not suitable for bonding, a layer of silicon oxide (e.g., 10 nm to 20 nm PECVD oxide), another dielectric, or another suitable bonding material can be deposited as the bonding layer 660 to facilitate bonding. Alternatively, the oxide may be present on the donor wafer.

[0071]

[0088] The layers shown in Figure 6H can be modified in several ways, including the deposition order (e.g., conductive / thermal / bonding or thermal / conductive / bonding), and the barrier shell can be formed after the deposition of one or more conductive and thermal layers. In some embodiments, one or more layers are removed from the substrate structure. Furthermore, each layer may include sublayers. Although the conductive and thermal layers are shown on only one side of the substrate, they can be formed on other sides depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0072]

[0089] Figure 6I is a simplified schematic diagram illustrating the formation of a bonding layer 660 on a designed layer on an encapsulated and planarized polycrystalline ceramic core, having a delamination layer 670 (e.g., Si) on top, according to one embodiment of the present invention. The thickness of the delamination layer can be varied to suit the specifications of various applications. Furthermore, the crystal orientation of the delamination layer 670 can be varied to suit the specifications of the application. Furthermore, the doping level and profile in the delamination layer can be varied to suit the specifications of a particular application. The delaminated single-crystal silicon layer (e.g., delaminated Si(111)) is suitable for use as a growth layer in the epitaxial growth process for forming an epitaxial material. In some embodiments, the epitaxial material (not shown) may include a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of several layers utilized in optoelectronic devices, RF devices, and power devices. Although a single-crystal silicon layer is shown in Figure 6I, other substantially single-crystal layers may be utilized according to embodiments of the present invention.

[0073]

[0090] Furthermore, the examples and embodiments described herein are for illustrative purposes only, and it will be understood that various modifications or changes in light thereof will be suggested to those skilled in the art and will be included in the spirit and scope of this application and the appended claims.

Claims

1. A method for manufacturing a substrate structure, wherein the method is A ceramic substrate is prepared having a front surface characterized by multiple voids and containing a polycrystalline material. The ceramic substrate is sealed in a barrier layer that defines valleys corresponding to the plurality of voids, A bonding layer comprising a bonding layer material is formed to bond to the barrier layer on the front surface of the ceramic substrate, By removing a portion of the bonding layer, at least a portion of the barrier layer is exposed, and a filling region is defined in the valleys corresponding to the plurality of voids, in which the bonding layer material is filled. A second bonding layer is deposited on the exposed barrier layer and at least a portion of the filling area. Methods that include...

2. The method according to claim 1, wherein the ceramic substrate contains polycrystalline aluminum nitride.

3. The method according to claim 1, wherein removing the portion of the bonding layer includes a chemical mechanical polishing (CMP) process.

4. The method according to claim 1, wherein the barrier layer includes silicon nitride.

5. The front surface of the ceramic substrate is characterized by an RMS roughness in the range of 50 to 600 nm. The method according to claim 1, wherein the second bonding layer is characterized by an RMS roughness in the range of 0.5 to 5 nm.

6. The method according to claim 1, wherein the bonding layer contains silicon oxide, and the second bonding layer contains a silicon oxide layer with a thickness of 100 nm to 1000 nm.

7. The method according to claim 1, further comprising removing a portion of the bonding layer and then forming a second barrier shell that encloses the exposed barrier layer and the filling region.

8. The method involves bonding a substantial single crystal layer to the second bonding layer, wherein the substantial single crystal layer is characterized by a first surface roughness. The substantially single-crystal layer is treated to form a grown surface characterized by a second surface roughness smaller than the first surface roughness, To form an epitaxial layer bonded to the growth surface. The method according to claim 1, further comprising:

9. A method for manufacturing a substrate structure, wherein the method is A ceramic substrate is prepared that has a front surface characterized by multiple peaks and contains a polycrystalline material, The bonding layer includes a bonding layer material and forms a bonding layer that is bonded to the front surface of the ceramic substrate, Performing a chemical mechanical polishing (CMP) process to remove a portion of the bonding layer in order to expose at least a portion of the front surface of the ceramic substrate, and defining a filled region in which the spaces between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate are filled with the bonding layer material, The ceramic substrate is sealed in the barrier layer. Methods that include...

10. The method according to claim 9, further comprising depositing an adhesion promoting layer between the front surface of the ceramic substrate and the bonding layer.

11. The method according to claim 9, wherein the ceramic substrate contains polycrystalline aluminum nitride.

12. The method according to claim 9, further comprising depositing a conductive layer bonded to at least a portion of the barrier layer.

13. The method according to claim 9, further comprising depositing a thermal conductive layer bonded to at least a portion of the barrier layer.

14. A method for manufacturing a substrate structure, wherein the method is A ceramic substrate is prepared having a front surface characterized by multiple voids and containing a polycrystalline material. The bonding layer includes a bonding layer material and forms a bonding layer that is bonded to the front surface of the ceramic substrate, By removing a portion of the bonding layer, at least a portion of the front surface of the ceramic substrate is exposed, and a filling region is defined in which the bonding layer material is filled into the plurality of voids. The ceramic substrate and the bonding layer are sealed in a barrier layer, Forming a substantially single-crystal gallium oxide layer bonded to the barrier layer Methods that include...

15. The method further includes forming an adhesive layer to be bonded to the front surface of the ceramic substrate before forming the bonding layer, The method according to claim 14, wherein the bonding layer is bonded to the front surface of the ceramic substrate via the adhesive layer.

16. The method according to claim 14, wherein the ceramic substrate contains aluminum nitride.

17. The method according to claim 14, wherein the barrier layer includes silicon nitride.

18. The method according to claim 14, wherein the substantially single-crystal gallium oxide layer includes a peeled single-crystal gallium oxide layer.

19. The method according to claim 14, further comprising an epitaxial layer bonded to the substantially single-crystal gallium oxide layer.

20. The method according to claim 19, wherein the epitaxial layer includes an epitaxial III-V layer.

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