Multilayer electronic components

Abstract

The present invention provides a multilayer electronic component that suppresses the decrease in capacitance caused by the addition of In to the dielectric layer. [Solution] The stacked electronic component includes a main body including a capacitance forming portion Ac, an upper cover portion 112, and a lower cover portion 113, and an external electrode 131. The capacitance forming portion includes an upper region adjacent to the upper cover portion (corresponding to a thickness T1 portion), a lower region adjacent to the lower cover portion (corresponding to a thickness T2 portion), and a central region Cp disposed between the upper and lower regions. At least one of the dielectric layers disposed in the upper and lower regions is a first dielectric layer 111a containing In, and at least one of the dielectric layers disposed in the central region is a second dielectric layer 111b that does not contain In or has a lower atomic percentage of average In content than the first dielectric layer.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Such multilayer ceramic capacitors can be used as components in various electronic devices due to their advantages of being small, yet guaranteeing high capacitance, and being easy to implement.

[0004] Recently, with the miniaturization and increased performance of electronic devices, multilayer ceramic capacitors (MLCs) have also tended to become smaller and have higher capacitance. This trend has increased the importance of ensuring high reliability in MLCs. Furthermore, high reliability characteristics are required for use in automotive electronic components.

[0005] Therefore, there were attempts to improve the reliability of MLCCs by incorporating in (In) into the dielectric layer. However, when a large amount of in was included in the dielectric layer, a decrease in capacitance sometimes occurred.

[0006] Therefore, there is a need to develop a method that can improve reliability while suppressing the negative effects of adding In. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Korean Published Patent Gazette No. 10-2024-0094947 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] One of the problems that this invention aims to solve is to provide a highly reliable stacked electronic component.

[0009] One of the problems that this invention aims to solve is to suppress the decrease in capacitance caused by the addition of In.

[0010] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0011] A stacked electronic component according to one embodiment of the present invention includes a main body including a capacitance forming section in which dielectric layers and internal electrodes are alternately arranged in a first direction, an upper cover section located above the capacitance forming section in the first direction, and a lower cover section located below the capacitance forming section in the first direction, and an external electrode located on the main body, wherein the capacitance forming section includes an upper region adjacent to the upper cover section, a lower region adjacent to the lower cover section, and a central region located between the upper and lower regions, and at least one of the dielectric layers located in the upper and lower regions is a first dielectric layer containing In, and at least one of the dielectric layers located in the central region may not contain In, or may be a second dielectric layer having a lower atomic percentage of average In content than the first dielectric layer. [Effects of the Invention]

[0012] One of the various effects of the present invention is that the reliability of multilayer electronic components is improved by adjusting the In content of the dielectric layer according to the position in which the dielectric layer is arranged.

[0013] One of the various effects of the present invention is that the decrease in capacitance due to the addition of In is suppressed.

[0014] However, the diverse and beneficial advantages and effects of the present invention are not limited to the above-described content, and can be more easily understood in the process of explaining the specific embodiments of the present invention.

Brief Description of the Drawings

[0015] [Figure 1] Schematically shows a perspective view of a multilayer electronic component according to an embodiment of the present invention. [Figure 2] Schematically shows a cross-sectional view taken along the line I-I' of FIG. 1. [Figure 3] Schematically shows a cross-sectional view taken along the line II-II' of FIG. 1. [Figure 4] It is a figure corresponding to FIG. 3 for explaining the upper region, central region, and lower region of the capacitance forming portion. [Figure 5] It is an enlarged view of the P1 region of FIG. 2. [Figure 6] It is an enlarged view of the P1 region of FIG. 2. [Figure 7] It is a figure schematically showing the first dielectric crystallites contained in the first dielectric layer. [Figure 8] It is a figure schematically showing the second dielectric crystallites contained in the second dielectric layer. [Figure 9] It is an image obtained by photographing the upper region and the upper cover portion of Test No. 2 with SEM. [Figure 10] It is an image obtained by photographing the central region of Test No. 2 with SEM. [Figure 11] It is a figure for explaining the manufacturing method of the multilayer electronic component of FIG. 1.

Embodiments for Carrying Out the Invention

[0016] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0017] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation; therefore, the present invention is not necessarily limited to what is shown. Components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, this does not exclude other components unless otherwise stated, but rather means that it may further include other components.

[0018] In drawings, the X direction can be defined as the first direction, the lamination direction, or the thickness T direction; the Y direction as the second direction or the length L direction; and the Z direction as the third direction or the width W direction.

[0019] Multilayer electronic components Figure 1 schematically shows a perspective view of a stacked electronic component according to one embodiment of the present invention, Figure 2 schematically shows a cross-sectional view along the line I-I' in Figure 1, Figure 3 schematically shows a cross-sectional view along the line II-II' in Figure 1, Figure 4 is a diagram corresponding to Figure 3 for explaining the upper region, central region, and lower region of the capacitance forming portion, Figure 5 is an enlarged view of region P1 in Figure 2, Figure 6 is an enlarged view of region P1 in Figure 2, Figure 7 schematically shows the first dielectric crystal grains contained in the first dielectric layer, and Figure 8 schematically shows the second dielectric crystal grains contained in the second dielectric layer.

[0020] The stacked electronic component 100 according to one embodiment of the present invention will be described in detail below with reference to Figures 1 to 8.

[0021] A stacked electronic component 100 according to one embodiment of the present invention includes a main body 110 including a capacitance forming section Ac in which dielectric layers 111 and internal electrodes 121 and 122 are alternately arranged in a first direction, an upper cover section 112 arranged above the capacitance forming section in the first direction, and a lower cover section arranged below the capacitance forming section in the first direction, and external electrodes 131 and 132 arranged on the main body, wherein the capacitance forming section Ac includes an upper region Up adjacent to the upper cover section, a lower region Lp adjacent to the lower cover section, and a central region Cp arranged between the upper region and the lower region, and at least one of the dielectric layers arranged in the upper region and the lower region is a first dielectric layer 111a containing In, and at least one of the dielectric layers arranged in the central region may not contain In, or may be a second dielectric layer 111b having a lower atomic percentage of average In content than the first dielectric layer.

[0022] There have been attempts to improve reliability, such as mean time to failure (MTTF) and insulation resistance (IR), by incorporating indium (In) into the dielectric layer. However, while the reliability of multilayer electronic components can be improved when indium is included in the dielectric layer, a decrease in capacitance can occur.

[0023] The inventors have found that reliability defects mainly occur in the upper and lower regions of the capacitance forming area, and hardly occur in the central region of the capacitance forming area. Therefore, they have attempted to improve the reliability of the stacked electronic component 100 by making at least one of the dielectric layers 111 located in the upper region Up and lower region Lp of the capacitance forming area a first dielectric layer 111a containing In, and by making at least one of the dielectric layers 111 located in the central region Cp of the capacitance forming area a second dielectric layer 111b that does not contain In or has a lower average In content atomic percentage than the first dielectric layer, thereby suppressing the decrease in capacitance.

[0024] The following describes in detail each component of the stacked electronic component 100 according to one embodiment of the present invention.

[0025] The main body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0026] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be a hexahedron or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedron-shaped.

[0027] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0028] Due to the overlap of margin regions on the dielectric layer 111 where internal electrodes 121 and 122 are not placed, a step difference is generated due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface, fifth surface 5, and sixth surface 6 may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0029] On the other hand, in order to suppress the step formed by the internal electrodes 121 and 122, after cutting such that the internal electrodes after lamination are exposed on the fifth surface 5 and the sixth surface 6 of the main body, when a single dielectric layer or two or more dielectric layers are laminated in the third direction (width direction) on both side surfaces of the capacitance forming portion Ac to form the margin portions 114 and 115, the portions connecting the first surface and the fifth and sixth surfaces, and the portions connecting the second surface and the fifth and sixth surfaces do not have to have a shrunk form.

[0030] The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between the adjacent dielectric layers 111 can be integrated so as to be difficult to confirm without using a scanning electron microscope (SEM).

[0031] According to an embodiment of the present invention, the raw material for forming the dielectric layer 111 is not particularly limited as long as a sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, or the like can be used. The barium titanate-based material can contain BaTiO3-based ceramic powder. Examples of the ceramic powder include BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc.

[0032] In addition, various ceramic additives, organic solvents, binders, dispersants, etc. can be added to the powder such as barium titanate (BaTiO3) as the raw material for forming the dielectric layer 111 according to the object of the present invention.

[0033] On the other hand, the ceramic green sheet for forming the first dielectric layer 111a may further contain In as an additive, and the ceramic green sheet for forming the second dielectric layer 111b may not contain In. However, it is not limited to this, and the first dielectric layer 111a can also be made to contain In by not including In as an additive in the ceramic green sheet for forming the first dielectric layer 111a, adding In to the paste for forming the internal electrodes, and diffusing In into the dielectric layer during the sintering process.

[0034] Furthermore, the average thickness td of the dielectric layer 111 does not need to be particularly limited and can be set arbitrarily according to the desired characteristics and application. For example, the average thickness td of the dielectric layer 111 may be 300 nm or more and 10 μm or less. Also, at least one of the multiple dielectric layers 111 may have an average thickness td of 300 nm or more and 10 μm or less.

[0035] Here, the average thickness td of the dielectric layer 111 can mean the average thickness of the dielectric layer 111 that is placed between the first internal electrode 121 and the second internal electrode 122.

[0036] The average thickness of the dielectric layer 111 can be measured by scanning an image of the cross-section of the main body 110 in the length and thickness direction (LT) with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, in the scanned image, the thickness of a single dielectric layer can be measured at 30 equally spaced points in the length direction, and the average value can be calculated. These 30 equally spaced points can be specified by the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 dielectric layers and measuring the average values, the average thickness of the dielectric layer can be further generalized.

[0037] The main body 110 may include a capacitance forming section Ac in which dielectric layers and internal electrodes are alternately arranged in a first direction, and cover sections 112 and 113 positioned above and below the capacitance forming section in the first direction.

[0038] The cover portions 112 and 113 may include an upper cover portion 112 positioned above the volume-forming portion Ac in the first direction, and a lower cover portion 113 positioned below the volume-forming portion Ac in the first direction.

[0039] The capacitance-forming portion Ac is the part that contributes to the capacitance formation of the capacitor, and can be formed by repeatedly stacking a plurality of first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between.

[0040] The cover portions 112 and 113 can be formed by stacking a single dielectric layer 111 or two or more dielectric layers 111 in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0041] The capacitance forming portion Ac includes an upper region Up adjacent to the upper cover portion, a lower region Lp adjacent to the lower cover portion, and a central region Cp located between the upper and lower regions. At least one of the dielectric layers located in the upper and lower regions is a first dielectric layer 111a containing In, and at least one of the dielectric layers located in the central region may be a second dielectric layer 111b that does not contain In or has a lower average In content atomic percentage than the first dielectric layer.

[0042] The dielectric layer 111 may include a first dielectric layer 111a containing In, and a second dielectric layer 111b that does not contain In, or has a lower average In content atomic percentage than the first dielectric layer. The first dielectric layer 111a may be arranged in one or more of the upper region Up and lower region Lp of the capacitance forming portion, and the second dielectric layer 111b may be arranged in the central region Cp of the capacitance forming portion.

[0043] By making at least one of the dielectric layers 111 located in the upper region Up and lower region Lp of the capacitance-forming section a first dielectric layer 111a containing In, the reliability of the stacked electronic component 100 can be improved. Furthermore, by making at least one of the dielectric layers 111 located in the central region Cp of the capacitance-forming section a second dielectric layer 111b that does not contain In or has a lower average In content atomic percentage than the first dielectric layer, the decrease in capacitance can be suppressed.

[0044] In one embodiment, the first dielectric layer 111a may have an average In content of 0.08 at% or more measured at the center in the first direction, and the second dielectric layer 111b may have an average In content of 0.04 at% or less measured at the center in the first direction. This makes it possible to further improve the effect of suppressing the decrease in capacitance while improving the reliability of the present invention.

[0045] By having an average In content of 0.04 at% or less measured at the center of the second dielectric layer 111b in the first direction, the effect of suppressing the decrease in capacitance of the multilayer electronic component can be further improved.

[0046] Furthermore, if the average In content measured at the center of the second dielectric layer 111b in the first direction is 0.01 at% or less, the effect of suppressing the decrease in capacitance of the multilayer electronic component can be further improved. In this case, it can be determined that the second dielectric layer 111b is substantially In-free.

[0047] In one embodiment, the average In content measured at the center of the first dielectric layer 111a in a first direction may be 0.08 at% or less and 0.12 at% or less. The reliability of the multilayer electronic component can be further improved by having an average In content of 0.08 at% or more measured at the center of the first dielectric layer 111a in a first direction. On the other hand, there is no particular need to limit the upper limit, but for example, the average In content of the first dielectric layer 111a measured at the center of the first direction may be 0.08 at% or more and 0.12 at% or less.

[0048] Furthermore, the atomic percentage of the average In content measured at the center of the first dielectric layer 111a in the first direction may be twice or more the atomic percentage of the average In content measured at the center of the second dielectric layer 111b in the first direction.

[0049] There is no particular limitation on the method for measuring the In content of the first dielectric layer 111a and the second dielectric layer 111b.

[0050] For example, after polishing a multilayer electronic component to the center in the width direction to expose the cross-section in the length and thickness direction (LT cross-section), the first dielectric layer 111a and the second dielectric layer 111b in the LT cross-section can be analyzed by SEM-EDS to measure the In content of the first dielectric layer 111a and the second dielectric layer 111b. As shown in Figure 5, by analyzing Ar1, which is the central region in the thickness direction of the first dielectric layer, with SEM-EDS, the average In content at% measured at the center of the first dielectric layer 111a in the first direction can be determined. Similarly, as shown in Figure 6, by analyzing Ar2, which is the central region in the thickness direction of the second dielectric layer, with SEM-EDS, the average In content at% measured at the center of the second dielectric layer 111b in the first direction can be determined.

[0051] The at% of the In content can be expressed as the percentage of In atoms out of the total number of atoms located in the measurement regions Ar1 and Ar2.

[0052] The first dielectric layer 111a may contain a plurality of first dielectric crystal grains Ga, and the second dielectric layer 111b may contain a plurality of second dielectric crystal grains Gb.

[0053] The average size of multiple first dielectric crystal grains Ga may be smaller than the average size of multiple second dielectric crystal grains Gb. This can further enhance the reliability improvement effect of the first dielectric layer 111a.

[0054] The size of a dielectric crystal grain can be defined as the arithmetic mean of the maximum ferret diameter and minimum ferret diameter of that dielectric crystal grain. The average size of a dielectric crystal grain can be the average of the sizes of 100 or more dielectric crystal grains.

[0055] The ferret diameter refers to the distance between two parallel lines that completely enclose a dielectric crystal grain when its outline is projected from a specific direction. Of the ferret diameters measured in all possible directions of the dielectric crystal grain, the largest value is the maximum ferret diameter, and the smallest value is the minimum ferret diameter.

[0056] Furthermore, the maximum ferret diameter, minimum ferret diameter, and size of dielectric crystal grains can be determined by polishing the multilayer electronic component to the center in the width direction to expose the cross-section in the length and thickness direction (LT cross-section), and then measuring the LT cross-section. By scanning the LT cross-section with an SEM (scanning electron microscope) and analyzing the resulting image using image analysis software such as ImageJ, the maximum and minimum ferret diameters of each dielectric crystal grain can be determined, and the size of each dielectric crystal grain can be calculated. The average size of the dielectric crystal grains can then be obtained by averaging the sizes of 100 or more dielectric crystal grains.

[0057] Referring to Figures 7 and 8, the first dielectric crystal grain Ga and the second dielectric crystal grain Gb can have a core-shell structure. However, it is not limited to this, and the first dielectric crystal grain Ga and the second dielectric crystal grain Gb can consist only of cores or have a core-double shell structure.

[0058] The first dielectric crystal grain Ga includes a first core Ga1 and a first shell Ga2 surrounding at least a portion of the first core Ga1, and the second dielectric crystal grain Gb includes a second core Gb1 and a second shell Gb2 surrounding at least a portion of the second core Gb1.

[0059] The size of the first core Ga1 may be larger than the size of the second core Gb1. The core size can be the arithmetic mean of the maximum and minimum ferret diameters of the core. The maximum ferret diameter La1 of the first core Ga1 may be larger than the maximum ferret diameter Lb1 of the second core Gb1. Also, the maximum ferret diameter La2 of the first dielectric crystal grain Ga may be smaller than the maximum ferret diameter Lb2 of the second dielectric crystal grain Gb. As a result, the area fraction occupied by the first core Ga1 in the first dielectric crystal grain Ga may be larger than the area fraction occupied by the second core Gb1 in the second dielectric crystal grain Gb. This may be due to the difference in In content contained in the dielectric layers.

[0060] In one embodiment, the average size of dielectric crystal grains Ga contained in the first dielectric layer 111a may be smaller than the average size of dielectric crystal grains Gb contained in the second dielectric layer 111b, and the average size of the cores of the core-shell dielectric crystal grains contained in the first dielectric layer 111a may be larger than the average size of the cores of the core-shell dielectric crystal grains contained in the second dielectric layer 111b.

[0061] The maximum ferret diameter, minimum ferret diameter, and size of the core can also be measured in the same way as the measurement methods for the maximum ferret diameter, minimum ferret diameter, and size of the dielectric crystal grains described above. On the other hand, core Ga1, Gb1 and shell Ga2, Gb2 can be classified by analyzing the dielectric crystal grains with TEM-EDS, with the region where the additive content per 100 moles of Ti is less than 0.2 moles designated as core Ga1, Gb1, and the region where the additive content per 100 moles of Ti is greater than 0.2 moles designated as shell Ga2, Gb2.

[0062] In one embodiment, the dielectric layers arranged in the upper region Up and the lower region Lp may have an average In content of 0.08 at% or more measured at the center in the first direction, while the dielectric layer arranged in the central region Cp may have an average In content of 0.04 at% or less measured at the center in the first direction. That is, the dielectric layers arranged in the upper region Up and the lower region Lp may be the first dielectric layer 111a, and the dielectric layer arranged in the central region Cp may be the second dielectric layer 111b. This makes it possible to further improve the effect of suppressing the decrease in capacitance while improving the reliability of the present invention.

[0063] On the other hand, Figure 2 shows that two internal electrodes and two dielectric layers are arranged in the upper region Up and the lower region Lp, respectively. However, this is a simplified representation, and two or more internal electrodes and two or more dielectric layers may be arranged in the upper region Up and the lower region Lp, respectively.

[0064] In one embodiment, the dielectric layers located in the upper region Up and the lower region Lp may have an average In content of 0.08 at% or more and 0.12 at% or less measured at the center in the first direction, and the dielectric layer located in the central region Cp may have an average In content of 0.01 at% or less measured at the center in the first direction.

[0065] In one embodiment, when the average thickness of the capacitance forming portion Ac in the first direction is Ta, the average thickness of the upper region Up in the first direction is T1, and the average thickness of the lower region Lp in the first direction is T2, then (T1+T2) / Ta may be 0.3 or more and 0.7 or less. This further improves the effect of suppressing the decrease in capacitance while improving the reliability according to the present invention.

[0066] If (T1+T2) / Ta is less than 0.3, it is difficult to further improve reliability, and if it exceeds 0.7, it may be difficult to further improve the effect of suppressing capacitance reduction.

[0067] Furthermore, the above Ta, T1, and T2 can satisfy 0.15 ≤ T1 / Ta ≤ 0.35 and 0.15 ≤ T2 / Ta ≤ 0.35.

[0068] The above values ​​of Ta, T1, and T2 can be obtained by polishing the multilayer electronic component up to the center in the width direction to expose the cross-section in the length and thickness direction (LT cross-section), and then measuring the LT cross-section.

[0069] The average thickness Ta in the first direction of the volume-forming portion Ac can be the average of the thicknesses in the first direction measured at five points that are evenly spaced in the longitudinal direction of the LT cross section, from the interface between the volume-forming portion and the upper cover portion to the interface between the volume-forming portion and the lower cover portion.

[0070] In the case where the average thickness T1 of the upper region Up in the first direction and the average thickness T2 of the lower region Lp in the first direction are used, after dividing the capacitance forming region Ac into the upper region Up, the central region Cp, and the lower region Lp using the In content measurement method of the dielectric layer described above, the average value of the thickness in the first direction of the upper region Up measured at five points equally spaced in the longitudinal direction can be taken as T1, and the average value of the thickness in the first direction of the lower region Lp measured at five points equally spaced in the longitudinal direction can be taken as T2.

[0071] However, Ta, T1, and T2 do not necessarily need to be measured in the LT section; they can also be measured in the WT section as shown in Figure 4.

[0072] In one embodiment, the atomic percentage of the average In content measured at the center of the dielectric layer in the first direction, located in the upper region Up and the lower region Lp, may be twice or more the atomic percentage of the average In content measured at the center of the dielectric layer in the first direction, located in the central region Cp. This further improves the effect of suppressing the decrease in capacitance while improving the reliability according to the present invention.

[0073] In one embodiment, the average grain size of the dielectric crystal grains contained in the upper region and the lower region Up, Lp may be smaller than the average grain size of the dielectric crystal grains contained in the central region Cp. This makes it possible to further improve the effect of suppressing the decrease in capacitance while improving the reliability according to the present invention.

[0074] In one embodiment, the dielectric layer 111 contains dielectric crystal grains with a core-shell structure, and the average value of the maximum ferret diameter of the cores of the dielectric crystal grains with a core-shell structure contained in the upper region and the lower region Up, Lp may be greater than the average value of the maximum ferret diameter of the cores of the dielectric crystal grains with a core-shell structure contained in the central region Cp. The area fraction occupied by the cores in the dielectric crystal grains with a core-shell structure contained in the upper region and the lower region Up, Lp may be greater than the area fraction occupied by the cores in the dielectric crystal grains with a core-shell structure contained in the central region Cp. This may be due to the difference in In content contained in the dielectric layer.

[0075] The dielectric layers located in the upper region Up and the lower region Lp contain a higher content of In than the dielectric layer located in the central region Cp, thereby suppressing the formation of a secondary phase. Here, the secondary phase can be defined as a reaction between the main component of the dielectric layer and the additive, or the formation of another phase with a different crystal structure or chemical composition from the main component during the sintering process.

[0076] As a result, the dielectric layer 111 includes a secondary phase, and at least one of the dielectric layers located in the upper region and the lower region Up, Lp may have a smaller average number of secondary phases than at least one of the dielectric layers located in the central region Cp.

[0077] Furthermore, the dielectric layer 111 includes a secondary phase, and the average area of ​​the secondary phase included in at least one of the dielectric layers arranged in the upper and lower regions may be smaller than the average area of ​​the secondary phase included in at least one of the dielectric layers arranged in the central region.

[0078] In one embodiment, the average porosity of at least one of the dielectric layers disposed in the upper region and the lower region may be lower than the average porosity of at least one of the dielectric layers disposed in the central region.

[0079] The average number of secondary phases, the average area of the secondary phases, and the average porosity of the dielectric layer are measured by SEM-EDS on the L-T cross section after polishing the multilayer electronic component to the center in the width direction to expose the cross section in the length and thickness directions (L-T cross section), and can be the average value of the values measured in three unit areas (100 μm 2 , 10 μm × 10 μm).

[0080] The cover portions 112 and 113 may not include internal electrodes. The cover portions 112 and 113 may be made of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1) in which Ca (calcium), Zr (zirconium), etc. are partially solid-solved in BaTiO3, Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc. <00​​​​​On the other hand, there is no particular limit to the method for controlling the In content of the positional dielectric layers. For example, the In content contained in the ceramic green sheet can be adjusted to differ at different positions, or the In content contained in the internal electrode paste applied on the ceramic green sheet can be adjusted to differ at different positions, and both methods can be applied simultaneously.

[0083] Figure 11 is a diagram illustrating the manufacturing method of the stacked electronic component shown in Figure 1. Referring specifically to Figure 11, one or more ceramic green sheets GS without internal electrode paste are stacked on the upper and lower parts in the first direction to form cover parts 112 and 113. A ceramic green sheet 11 coated with internal electrode paste P1 with a high In content is placed on the lower part of the upper cover part 112 in the first direction and on the upper part of the lower cover part 113 in the first direction. Between these, a ceramic green sheet 12 coated with internal electrode paste P2 with a low In content or no In content is placed to form a capacitance forming part Ac, thereby stacking the components. After that, the stacked components are cut to the size of the stacked electronic component, fired to form the main body, and external electrodes are formed on the main body to manufacture the stacked electronic component.

[0084] On the other hand, the In content of the internal electrode paste P1, which has a high In content, does not need to be particularly limited. For example, the In content of the internal electrode paste P1 may be 0.5 to 1.5 wt%.

[0085] Furthermore, the average thickness of the cover portions 112 and 113 is not particularly limited. For example, the thickness tc of the cover portions 112 and 113 may be 10 to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the average thickness tc of the cover portions 112 and 113 may be 15 μm or less. That is, the average thickness tc of the upper cover portion 112 may be 15 μm or less, and the average thickness tc of the lower cover portion 113 may also be 15 μm or less.

[0086] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and can be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0087] Furthermore, margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0088] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 may be located on both end surfaces in the width direction of the main body 110.

[0089] As shown in Figure 3, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0090] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0091] The margin portions 114 and 115 may be formed by applying a conductive paste to the ceramic green sheet, except for the areas where the margin portions are formed, to form internal electrodes.

[0092] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0093] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. For example, the width of the margin portions 114 and 115 may be 5 to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average width Wm of the margin portions 114 and 115 may be 15 μm or less.

[0094] The average width Wm of the margin portions 114 and 115 can represent the average size of the margin portions 114 and 115 in the third direction, and can be the average value of the sizes of the margin portions 114 and 115 in the third direction measured at five equally spaced points on one side surface of the volume forming portion Ac.

[0095] The internal electrodes 121 and 122 may be stacked alternately with the dielectric layer 111.

[0096] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0097] The first internal electrode 121 is exposed via the third surface 3, separated from the fourth surface 4, and the second internal electrode 122 can be exposed via the fourth surface 4, separated from the third surface 3. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0098] In other words, the first internal electrode 121 is not connected to the second external electrode 132 but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131 but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance from the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance from the third surface 3.

[0099] In this case, the first internal electrode 121 and the second internal electrode 122 can be electrically isolated from each other by the dielectric layer 111 placed in between them.

[0100] On the other hand, the internal electrodes 121 and 122 may include a first-first internal electrode 121a and a second-first internal electrode 122a, which are arranged with the first dielectric layer 111a in between. In this case, the first-first internal electrode 121a and the second-first internal electrode 122a contain Ni and In, and at least a portion of the In contained in the first-first internal electrode 121a and the second-first internal electrode 122a may exist in the form of an alloy with Ni. This may be because In is added to the first conductive paste P1 for forming the first-first internal electrode 121a and the second-first internal electrode 122a, and during the sintering process, In diffuses to the interface with the dielectric layer, and a portion remains in the internal electrodes, forming an alloy with Ni. Whether or not Ni and In exist in the form of an alloy can be confirmed by whether or not the peak position of Ni has shifted during analysis by XRD (X-ray diffraction). As a concrete example, after crushing the internal electrode to obtain a powder, the powder can be analyzed by XRD (X-ray diffraction) to confirm whether or not the peak position of Ni has shifted.

[0101] However, this is not limited to the above, and it is also possible that all of the In contained in the conductive paste for forming the first-first internal electrode 121a and the second-first internal electrode 122a diffuses into the first dielectric layer 111a, and the first-first internal electrode 121a and the second-first internal electrode 122a may substantially contain no In.

[0102] Furthermore, the material may include first-second internal electrodes 121b and second-second internal electrodes 122b, which are arranged on either side of the second dielectric layer 111b. The first-second internal electrodes 121b and second-second internal electrodes 122b may have an In content of 0.04 at% or less, and may be substantially In-free.

[0103] On the other hand, the average thickness te of the internal electrodes 121 and 122 does not need to be particularly limited and can be set arbitrarily according to the desired characteristics and application. For example, the average thickness te of the internal electrodes 121 and 122 may be 300 nm or more and 3 μm or less. Also, the average thickness te of at least one of the multiple internal electrodes 121 and 122 may be 300 nm or more and 3 μm or less.

[0104] The thickness of the internal electrodes 121 and 122 can refer to the size of the internal electrodes 121 and 122 in the first direction. The average thickness of the internal electrodes 121 and 122 can be measured by scanning an image of the cross-section of the main body 110 in the length and thickness direction (LT) with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, in the scanned image, the thickness of one internal electrode can be measured at 30 equally spaced points in the length direction, and the average value can be calculated. These 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes and measuring the average value, the average thickness of the internal electrodes can be further generalized.

[0105] External electrodes 131 and 132 can be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0106] The external electrodes 131 and 132 are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and may include a first external electrode 131 and a second external electrode 132 that are connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0107] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed depending on the form of the internal electrodes 121 and 122 and other purposes.

[0108] On the other hand, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as metal, and the specific material may be determined by considering electrical properties, structural stability, etc., and may also have a multilayer structure.

[0109] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0110] As a more specific example for electrode layers 131a and 132a, electrode layers 131a and 132a may be firing electrodes containing conductive metal and glass, or resin-based electrodes containing conductive metal and resin.

[0111] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode. Furthermore, the electrode layers 131a and 132a may be formed as a plating layer, or as layers formed using a vapor deposition method such as sputtering or ALD (Atomic Layer Deposition).

[0112] While any material with excellent electrical conductivity can be used as the conductive metal in the electrode layers 131a and 132a, it is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0113] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and may be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and may be formed in multiple layers.

[0114] As a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers, and may be in a form in which Ni plating layers and Sn plating layers are sequentially formed on the electrode layers 131a and 132a, or in a form in which Sn plating layers, Ni plating layers and Sn plating layers are sequentially formed. Furthermore, the plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers. Also, the plating layers 131b and 132b may be in a form in which Ni plating layers and Pd plating layers are sequentially formed on the electrode layers 131a and 132a.

[0115] The size of the stacked electronic component 100 is not particularly limited. According to the present invention, it is advantageous for miniaturization and high capacity, so it can be applied to the size of small IT products, and because high reliability can be ensured in a variety of environments, it can also be applied to the size of automotive electronic products where high reliability is required.

[0116] The present invention will be explained in more detail below with reference to experimental examples, but these are intended to aid in a concrete understanding of the invention, and the scope of the present invention is not limited by these experimental examples.

[0117] (Example of experiment) First, we prepared a first internal electrode paste P1 with an In content of 1 wt% and a second internal electrode paste P2 with an In content of 0 wt%.

[0118] In test number 1, a laminate was formed by stacking the volume-forming sections using only ceramic gri sheets coated with the second internal electrode paste P2, while in test number 3, a laminate was formed by stacking the volume-forming sections using only ceramic green sheets coated with the first internal electrode paste P1.

[0119] In the case of test number 2, the ceramic green sheets 11 coated with the first internal electrode paste P1 were stacked to form the upper and lower regions of the volume-forming area, and the ceramic green sheets 12 coated with the second internal electrode paste P2 were stacked to form the central region of the volume-forming area to form a laminate. At this time, the thickness of the upper region and the thickness of the lower region were each 50% of the thickness of the central region to form the laminate.

[0120] Subsequently, the laminate was cut to the size of the laminated electronic component, then fired to form the main body, and external electrodes were formed on the main body to manufacture a sample chip.

[0121] After polishing the sample chips for each test number to the center in the width direction to expose the cross-sections in the length and thickness directions (LT cross-sections), the dielectric layer was analyzed using SEM-EDS on the LT cross-sections. The region where the average In content measured at the center of the dielectric layer in the first direction was 0.08 at% or more was divided into an upper region and a lower region, and the region where the average In content measured at the center of the dielectric layer in the first direction was 0.04 at% or less was divided into a central region. Furthermore, the average thickness of the capacitance-forming portion Ac in the first direction was defined as Ta, the average thickness of the upper region Up in the first direction as T1, and the average thickness of the lower region Lp in the first direction as T2, and the value of (T1+T2) / Ta is shown in Table 1 below.

[0122] Furthermore, the capacitance and reliability of each test number for the sample chip were evaluated and are listed in Table 1 below.

[0123] Capacitance was measured for 10 sample chips per test number. An LCR meter was used to measure the capacitance under AC voltage of 1Vrms and 1kHz, and the average value for each test number was calculated. The capacitance of test number 1 was set as the baseline value of "100%", and the values ​​for test numbers 2 and 3 are listed relative to the capacitance of test number 1.

[0124] Reliability was measured on 40 sample chips per test number. A high-temperature load test was performed for 100 hours under conditions of 125°C and 30V. Samples with an insulation resistance of 10kΩ or less were judged as "defective," and the number of samples judged as "defective" was recorded.

[0125] [Table 1]

[0126] In the case of test number 1, which does not have a dielectric layer containing In, the capacitance is excellent, but 19 samples were judged as "defective" in the reliability evaluation, confirming that the reliability has deteriorated.

[0127] In test number 3, where all dielectric layers contained In, the number of samples judged as "defective" in the reliability evaluation was 0, indicating excellent reliability. However, the capacitance performance degraded to 88.16% compared to test number 1.

[0128] In contrast, in test number 2, where at least one of the dielectric layers arranged in the upper and lower regions is a first dielectric layer containing In, and at least one of the dielectric layers arranged in the central region is a second dielectric layer that does not contain In or has a lower atomic percentage of average In content than the first dielectric layer, it can be confirmed that not only is reliability superior, but the decrease in capacitance is also suppressed.

[0129] Figure 9 shows SEM images of the upper region and upper cover of test number 2. Figure 10 shows SEM images of the central region of test number 2. Table 2 below shows the results of the analysis of the dielectric layers in the upper and central regions.

[0130] After polishing the sample chip of test number 2 to the center in the width direction to expose the cross-section in the length and thickness direction (LT cross-section), the Ar1 and Ar2 regions in the central thickness direction of the dielectric layer were analyzed by SEM-EDS on the LT cross-section, and the In content was measured and recorded in Table 2 below.

[0131] Furthermore, images obtained by scanning the above LT cross-section with a scanning electron microscope (SEM) were analyzed using ImageJ to determine the maximum ferret diameter, minimum ferret diameter, and size of each dielectric crystal grain and core. The average size of the dielectric crystal grains and the average size of the core are listed in Table 2 below.

[0132] The area and number of secondary phases were determined using SEM-EDS in the above LT cross-section, per unit area (100 μm²). 2 The values ​​measured at 10 μm × 10 μm are listed in Table 2 below.

[0133] [Table 2]

[0134] Referring to Figures 9 and 10 and Table 2 above, it can be confirmed that the dielectric layer in the upper region contains In, while the dielectric layer in the central region contains substantially no In. Furthermore, it can be confirmed that the average size of the crystal grains in the upper region is smaller than that of the central region, but the average size of the core in the upper region is larger than that of the central region. In addition, it can be confirmed that the presence of In in the dielectric layer of the upper region suppresses the formation of secondary phases, resulting in a reduction in the area and number of secondary phases.

[0135] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided herein. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0136] Furthermore, the expression "one embodiment" as used in this invention does not mean that each embodiment is the same as another, but is provided to emphasize and describe the unique and distinct features of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the features of other embodiments. For example, even if a matter described in a particular embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, as long as there is no description in the other embodiment that contradicts or is contrary to that matter.

[0137] The terms used in this invention are used solely to describe one embodiment and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0138] 100: Stacked Electronic Components 110: Main unit 111: Dielectric layer 112: Upper cover section 113: Lower cover section 114, 115: Margin section 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: Electrode layer 131b, 132b: Plating layer

Claims

1. A main body including a capacitance forming section in which dielectric layers and internal electrodes are alternately arranged in a first direction, an upper cover section positioned above the capacitance forming section in the first direction, and a lower cover section positioned below the capacitance forming section in the first direction, The body includes an external electrode disposed on the main body, The volume-forming portion includes an upper region adjacent to the upper cover portion, a lower region adjacent to the lower cover portion, and a central region located between the upper region and the lower region. At least one of the dielectric layers arranged in the upper and lower regions is a first dielectric layer containing In. A stacked electronic component in which at least one of the dielectric layers arranged in the central region is a second dielectric layer that does not contain In, or has a lower atomic percentage of average In content than the first dielectric layer.

2. The stacked electronic component according to claim 1, wherein the first dielectric layer has an average In content of 0.08 at% or more measured at the center in the first direction, and the second dielectric layer has an average In content of 0.04 at% or less measured at the center in the first direction.

3. The stacked electronic component according to claim 2, wherein the second dielectric layer has an average In content of 0.01 at% or less.

4. The stacked electronic component according to claim 1, wherein the first dielectric layer has an average In content of 0.08 at% or more and 0.12 at% or less, measured at the center in the first direction.

5. The laminated electronic component according to claim 1, wherein the dielectric layers arranged in the upper and lower regions have an average In content of 0.08 at% or more, measured at the center in the first direction, and the dielectric layer arranged in the central region has an average In content of 0.04 at% or less, measured at the center in the first direction.

6. The laminated electronic component according to claim 5, wherein when the average thickness of the capacitance forming portion in the first direction is Ta, the average thickness of the upper region in the first direction is T1, and the average thickness of the lower region in the first direction is T2, (T1 + T2) / Ta is 0.3 or more and 0.7 or less.

7. The stacked electronic component according to claim 6, wherein Ta, T1, and T2 satisfy 0.15 ≤ T1 / Ta ≤ 0.35 and 0.15 ≤ T2 / Ta ≤ 0.

35.

8. The stacked electronic component according to any one of claims 1 to 7, wherein the atomic percentage of the average In content of the dielectric layers arranged in the upper and lower regions is at least twice the atomic percentage of the average In content of the dielectric layer arranged in the central region.

9. The stacked electronic component according to any one of claims 1 to 7, wherein the average size of the dielectric crystal grains included in the upper region and the lower region is smaller than the average size of the dielectric crystal grains included in the central region.

10. The dielectric layer contains dielectric crystal grains with a core-shell structure. The stacked electronic component according to any one of claims 1 to 7, wherein the average size of the cores of the dielectric crystal grains of the core-shell structure included in the upper region and the lower region is greater than the average size of the cores of the dielectric crystal grains of the core-shell structure included in the central region.

11. The dielectric layer includes a secondary phase, The stacked electronic component according to any one of claims 1 to 7, wherein at least one of the dielectric layers arranged in the upper region and the lower region has an average number of secondary phases less than at least one of the dielectric layers arranged in the central region.

12. The dielectric layer includes a secondary phase, The stacked electronic component according to any one of claims 1 to 7, wherein the average area of ​​the secondary phase contained in at least one of the dielectric layers arranged in the upper region and the lower region is smaller than the average area of ​​the secondary phase contained in at least one of the dielectric layers arranged in the central region.

13. The stacked electronic component according to any one of claims 1 to 7, wherein the average porosity of at least one dielectric layer arranged in the upper region and the lower region is lower than the average porosity of at least one dielectric layer arranged in the central region.

14. The stacked electronic component according to any one of claims 1 to 7, wherein the average In content measured at the center of the upper cover portion and the lower cover portion in the first direction is 0.04 at% or less.

15. The internal electrodes include a first-first internal electrode and a second-first internal electrode, which are arranged with the first dielectric layer in between. The stacked electronic component according to any one of claims 1 to 7, wherein the first-1 internal electrode and the second-1 internal electrode contain Ni and In, and at least a portion of the In contained in the first-1 internal electrode and the second-1 internal electrode exists in the form of an alloy with Ni.

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