Semiconductor equipment

Abstract

The present invention provides a semiconductor device that achieves high integration and high-speed operation of integrated circuits while reducing standby power consumption. [Solution] A semiconductor device that uses a transistor having an oxide semiconductor 101 as an active layer as a switching element, and controls the supply of power voltage to a circuit 100 constituting an integrated circuit using the switching element, wherein the switching element supplies power voltage to the circuit when the circuit is operating, and stops supplying power voltage to the circuit when the circuit is stopped. The circuit to which the power voltage is supplied has one or more semiconductor elements, which are the smallest units that constitute an integrated circuit, such as transistors, diodes, capacitive elements, resistive elements, and inductors, formed using semiconductors. The semiconductor material of the semiconductor element is crystalline silicon, specifically including microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon.

Description

Technical Field

[0001] Relates to a semiconductor device using a semiconductor film of a thin film.

Background Art

[0002] A thin film transistor using a semiconductor film formed on an insulating surface is an essential semiconductor element for a semiconductor device. Since the manufacturing of a thin film transistor has a constraint of the heat resistance temperature of a substrate, a thin film transistor having an active layer made of amorphous silicon, polycrystalline silicon obtained by crystallization using a laser beam or a catalyst element, etc., which can be formed at a relatively low temperature, has become the mainstream of transistors used in semiconductor display devices. In recent years, as a new semiconductor material that can obtain higher mobility than amorphous silicon and still has uniform device characteristics obtained by amorphous silicon, attention has been focused on metal oxides showing semiconductor characteristics called oxide semiconductors. Metal oxides are used in various applications. For example, indium oxide, which is a well-known metal oxide, is used as a transparent electrode material in liquid crystal display devices, etc. Metal oxides showing semiconductor characteristics include, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor using such a metal oxide showing semiconductor characteristics in a channel formation region has already been known (Patent Document 1 and Patent Document 2).

[0003]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, the power consumption of a semiconductor integrated circuit (hereinafter referred to as an integrated circuit) fabricated using a silicon wafer, an SOI (Silicon on Insulator) substrate, a thin film semiconductor film on an insulating surface, etc. is approximately equal to the sum of the power consumption that occurs when the circuit is in an operating state and the power consumption that occurs when the circuit is in a stopped state (hereinafter referred to as standby power). As the integrated circuit undergoes advanced microfabrication and its integration density increases, the operating voltage decreases. Therefore, when the circuit is in an operating state the former power consumption tends to decrease. Thus, the proportion of standby power in the total power consumption is increasing, and reducing standby power has become an important issue in order to further reduce power consumption. Standby power can be classified into static standby power and dynamic standby power. Static standby power is the power consumed due to leakage current occurring between the source and drain electrodes, between the gate and source electrodes, and between the gate and drain electrodes in a state where no voltage is applied between the electrodes of a transistor, which is a three-terminal element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). As high integration progresses, the channel length of the transistor becomes short, and each

[0006] represented by the gate insulating film, etc. element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit). element, that is, in a state where the voltage between the gate electrode and the source electrode is almost 0. Also, dynamic standby power is the power consumed when the gate capacitance of a transistor and the parasitic capacitance of wiring, etc. are charged and discharged due to the continuous supply of voltages of various signals such as clock signals and the power supply voltage to a circuit in a stopped state (hereinafter referred to as a non-operating circuit).

[0007] As high integration progresses, the channel length of the transistor becomes short, and each The thickness of the insulating film of the type decreases. Therefore, the leakage current of the transistor is increasing. Static standby power consumption is on the rise.

[0008] Furthermore, in order to reduce dynamic standby power, the supply of power voltage to non-operating circuits is stopped, It is effective to prevent unnecessary charging and discharging from occurring in the various capacities of the operating circuit. However, the switching element used to stop the power supply voltage also typically uses a transistor. The transistor is used. And, as mentioned above, with increased integration, transistor leakage Because the current is increasing, the above leakage current prevents a dynamic reduction in standby power. Yes, they are.

[0009] In view of the above-mentioned problems, the present invention discloses a semiconductor device and its operation that achieves a reduction in standby power. One of the objectives is to provide a manufacturing method. [Means for solving the problem]

[0010] A transistor having an oxide semiconductor as its active layer is used as a switching element, and the A switching element controls the supply of power voltage to the circuits that make up the integrated circuit. Specifically, When the circuit is in operation, the switching element supplies power voltage to the circuit. i. When the circuit is stopped, the switching element supplies power voltage to the circuit. Stop it. Also, the circuit to which the power voltage is supplied is a transistor formed using semiconductors. The smallest components that make up an integrated circuit, such as diodes, capacitive elements, resistive elements, and inductors. It has one or more unit semiconductor elements. And the semiconductor contained in the above semiconductor element is , crystalline silicon (crystalline silicon), specifically microcrystalline silicon, polycrystalline silicon It contains re-con and single crystal silicon.

[0011] Then, in the oxide semiconductor film, in the gate insulating film, or at the interface between the oxide semiconductor film and another insulating film and in its vicinity, impurities such as moisture or hydrogen are removed by heat treatment or the like. Existing moisture or hydrogen and other impurities, which act as electron donors (donors), are desorbed by heat treatment or the like. It becomes.

[0012] The oxide semiconductor (purified OS) with reduced and highly purified impurities such as moisture or hydrogen that serve as electron donors (donors) is of type i (intrinsic semiconductor) or extremely close to type i. Therefore, the transistor using the above oxide semiconductor has the characteristic of extremely low off-current. Specifically, the highly purified oxide semiconductor has a measured hydrogen concentration by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) of 5×10 / cm or less, preferably 5×10 / cm 19 or less, more 3 preferably 5×10 18 / cm 3 or less, even more preferably 5×10 17 / cm 3 or less, still more preferably 1×10 16 / cm 3 or less. Also, the carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 / cm 3 less than, preferably 1×10 12 / cm 3 less than, even more preferably 1×10 1 1 3 / cm 6 less than. Also, the band gap of the oxide semiconductor is over 2 eV, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film with a sufficiently reduced and highly purified impurity concentration such as moisture or hydrogen, the transistor's​​ The off-current can be reduced.

[0013] Specifically, the off-current of a transistor using a highly purified oxide semiconductor film as the active layer. The low value can be proven through various experiments. For example, if the channel width is 1 × 10⁻⁶ 6 μm Even with an element with a channel length of 10 μm, the voltage between the source electrode and the drain electrode (drain) When the off-voltage is in the range of 1V to 10V, the off-current (voltage between the gate electrode and source electrode) The drain current (when the voltage is set to 0V or less) is below the measurement limit of the semiconductor parameter analyzer. That is, 1 × 10 -13 A characteristic of A or less can be obtained. In this case, the off-current is The off-current density, which corresponds to the value obtained by dividing by the transistor channel width, is 100 zA / μm or less. It can be seen that it is below. Also, connect the capacitive element and the transistor and let the current flow into the capacitive element. Alternatively, using a circuit that controls the charge flowing out of a capacitive element with the transistor, off-current density can be reduced. A measurement was performed. In this measurement, a highly purified oxide semiconductor film was applied to the transistor. Used in the channel formation region, the transition of the charge amount per unit time of the capacitive element is used to determine the transient. The off-current density of the transistor was measured. As a result, the current between the source and drain electrodes of the transistor was measured. When the voltage is 3V, an even lower off-current density of several tens of yA / μm can be obtained. Understood. Therefore, in a semiconductor device according to one aspect of the present invention, highly purified oxide semiconductor The off-current density of a transistor using a conductive film as the active layer is measured between the source electrode and the drain electrode. Depending on the voltage between them, the current may be 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably Alternatively, it can be reduced to 1 yA / μm or less. Therefore, the highly purified oxide semiconductor film The transistor used as the active layer has an off-current, and uses crystalline silicon. It is significantly lower compared to transistors. On the other hand, transistors using crystalline silicon, Compared to transistors with oxide semiconductors, it has higher mobility and higher on-current.

[0014] Therefore, a circuit is formed using semiconductor elements having crystalline silicon, and a to A transistor is used as a switching element, and the power supply voltage to the above circuit is controlled by the switching element. By controlling the supply, high integration and high-speed operation of integrated circuits are achieved while controlling leakage current. This can suppress the resulting increase in standby power consumption.

[0015] Furthermore, oxide semiconductors are quaternary metal oxides, specifically In-Sn-Ga-Zn-O system oxide semiconductors. Conductors, and ternary metal oxides such as In-Ga-Zn-O oxide semiconductors and In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors Conductors, and binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxide semiconductors. Monocrystalline semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors and Using In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. It is possible to be. In this specification, for example, In-Sn-Ga-Zn-O system Oxide semiconductors include indium (In), tin (Sn), gallium (Ga), and zinc (Zn). This means a metal oxide having [a certain characteristic], and the composition ratio is not particularly specified. Semiconductors may contain silicon.

[0016] Alternatively, oxide semiconductors have the chemical formula InMO3(ZnO). m It can be expressed as (m>0) Here, M is one or more metallic elements selected from Ga, Al, Mn, and Co. This indicates.

[0017] Transistors using oxide semiconductors may be bottom-gate or top-gate type. It can be a bottom-gate type transistor, or it can be a bottom-contact type transistor. This includes a gate electrode on an insulating surface, a gate insulating film on the gate electrode, and a gate insulating film on the gate insulating film. The oxide semiconductor film overlapping the gate electrode, and the source electrode and drain electrode on the oxide semiconductor film. It comprises a source electrode, a drain electrode, and an insulating film on an oxide semiconductor film. Top gate A transistor of this type has an oxide semiconductor film on an insulating surface, and a source electrode on the oxide semiconductor film and A drain electrode, an oxide semiconductor film, a gate insulating film on the source electrode and drain electrode, and On the insulating film, the gate electrode overlaps with the oxide semiconductor film, and the insulating film on the gate electrode It has. A bottom-contact type transistor has a gate electrode on an insulating surface and on the gate electrode The gate insulating film, the source electrode on the gate insulating film, the drain electrode, the source electrode, the drain An oxide semiconductor film located on the electrode and overlapping with the gate electrode on the gate insulating film. It comprises a source electrode, a drain electrode, and an insulating film on an oxide semiconductor film. [Effects of the Invention]

[0018] By suppressing the leakage current of transistors used as switching elements, the high performance of integrated circuits can be improved. This enables integration and high-speed operation while reducing the standby power consumption of semiconductor devices. [Brief explanation of the drawing]

[0019] [Figure 1] Block diagram of a semiconductor device. [Figure 2] A diagram showing the configuration and operation of a semiconductor device using an inverter. [Figure 3] A diagram showing the configuration and operation of a semiconductor device using NAND. [Figure 4] A diagram showing the configuration and operation of a semiconductor device using NOR. [Figure 5] A diagram showing the configuration of a semiconductor device using flip-flops. [Figure 6] A diagram illustrating the configuration and operation of a semiconductor device using flip-flops. [Figure 7] A diagram illustrating the configuration and operation of a semiconductor device using flip-flops. [Figure 8] A diagram illustrating the method for fabricating a semiconductor device. [Figure 9] A diagram illustrating the method for fabricating a semiconductor device. [Figure 10] A diagram illustrating the method for fabricating a semiconductor device. [Figure 11] A diagram illustrating the method for fabricating a semiconductor device. [Figure 12] A diagram illustrating the method for fabricating a semiconductor device. [Figure 13] A diagram illustrating the method for fabricating a semiconductor device. [Figure 14] A diagram showing the configuration of a semiconductor display device. [Figure 15] A diagram showing the configuration of a semiconductor display device. [Figure 16] A diagram of an electronic device. [Figure 17] A diagram illustrating the configuration and operation of a semiconductor device using flip-flops. [Modes for carrying out the invention]

[0020] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0021] The present invention relates to integrated circuits such as microprocessors and image processing circuits, as well as RF tags and semiconductors. It can be used in the manufacture of all kinds of semiconductor devices, such as display devices. This refers to a display device that has light-emitting elements in each pixel, such as liquid crystal displays and organic light-emitting elements (OLEDs). Optical devices, electronic paper, DMD (Digital Micromirror Device) e), PDP (Plasma Display Panel), FED (Field E Mission Display, etc., and those that have drive circuits using semiconductor elements. Other semiconductor display devices fall into that category.

[0022] (Embodiment 1) Figure 1 shows a semiconductor device according to one aspect of the present invention in block diagram form. This includes silicon wafers, SOI (Silicon on Insulator) substrates, and insulation. A circuit 100 fabricated using a silicon thin film on the surface, and the power supply voltage to the circuit 100 It has a switching element 101 that controls the supply. The switching element 101 controls the supply Switching is performed according to the code. Specifically, when circuit 100 is in operation, the control signal is Consequently, the switching element 101 turns on, and power voltage is supplied to the circuit 100. Furthermore, when circuit 100 is in a stopped state, the switching element 101 is turned off according to the control signal. As a result, the supply of power voltage to circuit 100 is stopped.

[0023] Circuit 100 includes transistors, diodes, capacitive elements, resistive elements, inductors, etc. The circuit has one or more semiconductor elements, which are the smallest units that make up the circuit. The semiconductor material of the device is crystalline silicon (crystalline silicon), specifically microcrystals. It contains silicon, polycrystalline silicon, and monocrystalline silicon.

[0024] Circuit 100 uses basic logic such as inverter, NAND, NOR, AND, and OR. It could be a logic gate, or a flip-flop which is a combination of these logic gates. It can be a logic circuit like a register or a shift register, or a combination of multiple logic circuits. It could even be a large-scale computational circuit.

[0025] The switching element 101 has a transistor with an oxide semiconductor as the active layer, and It also has one more. When the switching element 101 has multiple of the above transistors. Multiple transistors may be connected in parallel or in series. The connections may be a combination of series and parallel.

[0026] Note that the state in which transistors are connected in series refers to the source electrode of the first transistor. Only one of the two electrodes, the source electrode and the drain electrode of the second transistor. This means that only one of the two is connected. It also means that the transistors are connected in parallel. The state in which this occurs is when the source electrode of the first transistor is connected to the source electrode of the second transistor. The electrodes are connected, with the drain electrode of the first transistor being connected to the drain electrode of the second transistor. It means being connected.

[0027] Furthermore, the source and drain electrodes of a transistor are related to the polarity of the transistor and each electrode The name changes depending on the difference in potential applied to the poles. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the source electrode. The electrode that is subjected to low potential is called the drain electrode. Also, in a p-channel transistor, the potential is low. The electrode to which the current is applied is called the drain electrode, and the electrode to which a higher potential is applied is called the source electrode. It will be discovered. For convenience, in this specification, we assume that the source electrode and drain electrode are fixed. Although the connection relationship of the transistor is explained, in reality, the potential relationship described above is followed by The terms "drain electrode" and "coating electrode" are reversed.

[0028] As mentioned above, in transistors using oxide semiconductors, the leakage current is crystalline. It is significantly lower compared to transistors using silicon. Therefore, transistors with oxide semiconductors A transistor is used as a switching element 101, and the above circuit is performed using the switching element 101. By controlling the supply of power voltage to 100, the leakage current of the switching element 101 is controlled. This can suppress the resulting increase in standby power consumption.

[0029] Furthermore, by reducing the power consumption of circuit 100, the power consumption of other circuits that control the operation of circuit 100 is reduced. The load can be reduced. Therefore, the entire integrated circuit using circuit 100 and other circuits that control it This will allow for the enhancement of bodily functions.

[0030] On the other hand, transistors using crystalline silicon are different from transistors using oxide semiconductors. Compared to silicon, it generally has higher mobility and higher on-current. Therefore, it has crystalline silicon. By forming the circuit 100 with semiconductor elements, the integration of the integrated circuit using the circuit 100 is made highly integrable. This enables high-speed operation.

[0031] Next, we will take the case where circuit 100 is an inverter as an example and explain the specific configuration of the semiconductor device and The operation will be explained using Figure 2.

[0032] The semiconductor device shown in Figure 2(A) has a circuit 100 which includes a p-channel type transistor 110, It has an n-channel type transistor 111. Transistor 110 and transistor 11 1 uses silicon, which is crystalline, as the active layer. And transistor 110 The inverter is constructed using transistor 111.

[0033] Specifically, the drain electrode of transistor 110 and the drain electrode of transistor 111. The drain electrode of transistor 110 and transistor 111 The potential of the drain electrode is supplied to the subsequent circuit as the potential of the output signal. The resulting wiring or electrodes have various capacitances, such as parasitic capacitance, as shown in Figure 2(A). The capacity is shown as load 112.

[0034] Furthermore, the gate electrodes of transistor 110 and transistor 111 receive the input signal. A potential of VDD is applied. The source electrode of transistor 110 is connected to a high-level power supply voltage VDD. A switching element 101 is provided to the source electrode of transistor 111. A low-level power supply voltage VSS is applied through this.

[0035] In this specification, "connection" means an electrical connection, and it is possible to transmit current or voltage. This corresponds to a state of being able to do something.

[0036] In Figure 2(A), the switching element 101 switches the low-level power supply voltage VS to the circuit 100. This illustrates the case where the supply of S is controlled. Next, Figure 2(B) shows the switching element 10 When 1 controls the supply of a high-level power supply voltage VDD to circuit 100, the semiconductor device The configuration is shown. The semiconductor device shown in Figure 2(B) is similar to Figure 2(A), with circuit 100 being p It has a channel-type transistor 110 and an n-channel-type transistor 111. Both transistor 110 and transistor 111 use crystalline silicon as the active layer. And transistors 110 and 111 constitute the inverter. .

[0037] Specifically, the drain electrode of transistor 110 and the drain electrode of transistor 111. The drain electrode of transistor 110 and transistor 111 The potential of the drain electrode is supplied to the subsequent circuit as the potential of the output signal. The resulting wiring or electrodes have various capacitances, such as parasitic capacitance, as shown in Figure 2(B). The capacity is shown as load 112.

[0038] Furthermore, the gate electrodes of transistor 110 and transistor 111 receive the input signal. A potential is applied. A switching element 101 is connected to the source electrode of transistor 110. A high-level power supply voltage VDD is applied through this. Also, the source of transistor 111 A low-level power supply voltage VSS is applied to the electrodes.

[0039] The switching element 101 switches according to the control signal. Semiconductor shown in Figure 2(A) Taking a device as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped (non-operating period) Figure 2 shows the timing chart of the potentials of the input signal, output signal, and control signal during the production period. (C) is shown.

[0040] During the operating period, the control signal has a potential such that the switching element 101 turns on. Specifically, Figure 2(C) illustrates the case where the control signal has a high potential. Therefore, during the operating period, the power supply voltage VSS is supplied to the source electrode of transistor 111. It can be obtained. And when the potential of the input signal is low level, the output has a high potential. A signal is obtained. Also, when the potential of the input signal is high, a low potential is obtained. An output signal is obtained.

[0041] During the non-operating period, the control signal has a potential such that the switching element 101 is turned off. Specifically, Figure 2(C) illustrates the case where the control signal has a low potential. Therefore, during the non-operating period, the power supply voltage VSS is the source electrode of transistor 111. Since no power is supplied, the source electrode of transistor 111 is in a floating state. Therefore, whether the input signal's potential is low or high, the output signal's potential The ranking remains high.

[0042] As described above, during the non-operating period, the supply of power voltage to circuit 100 is stopped. This reduces the dynamic standby power consumed by circuit 100. Also, the switch Since element 101 is made of a semiconductor element using an oxide semiconductor film, leakage current etc. The static standby power that depends on the power supply voltage to the non-operating circuit can be reduced. By stopping the power supply, both static and dynamic standby power consumed by non-operating circuits are reduced. This makes it possible to provide a semiconductor device that can reduce the overall power consumption of the circuit.

[0043] Next, we will use the case where circuit 100 is a NAND gate as an example to explain the specific configuration and operation of the semiconductor device. The process will be explained using Figure 3.

[0044] The semiconductor device shown in Figure 3(A) has a circuit 100 which includes a p-channel type transistor 120, p-channel transistor 121, n-channel transistor 122, and n-channel It has a transistor 123 of type 120, transistor 121, and Transistors 122 and 123 both use crystalline silicon as the active layer. And there are transistors 120, 121, 122, and The NAND is constructed using ZISTA123.

[0045] Specifically, the source electrodes of transistor 120 and transistor 121 are: A high-level power supply voltage VDD is applied. The gate electrode of transistor 120 and the transistor The gate electrode of transistor 122 is supplied with the potential of input signal 1. The drain electrode of transistor 121 and the drain electrode of transistor 122 The drain electrodes are connected, and the potential of these drain electrodes is used as the potential of the output signal in the subsequent stage. The output signal is supplied to the circuit. The wiring or electrodes to which the output signal is supplied have various capacitances, such as parasitic capacitance. These capacitances are shown as load 124 in Figure 3(A). The source electrode of transistor 122 is connected to the drain electrode of transistor 123. The gate electrode of transistor 121 and the gate electrode of transistor 123 are at the potential of input signal 2. The source electrode of transistor 123 is connected to the switching element 10. A low-level power supply voltage VSS is supplied via 1.

[0046] In Figure 3(A), the switching element 101 switches the low-level power supply voltage VS to the circuit 100. This illustrates the case where the supply of S is controlled. Next, Figure 3(B) shows the switching element 10 When 1 controls the supply of a high-level power supply voltage VDD to circuit 100, the semiconductor device The configuration is shown. The semiconductor device shown in Figure 3(B) is similar to Figure 3(A), with circuit 100 being p A channel-type transistor 120, a p-channel type transistor 121, and an n-channel transistor It has a type 122 transistor and an n-channel type transistor 123. Transistors 120, 121, 122, and 123 are all crystal The active layer uses silicon which has properties. And transistor 120, transistor The NAND is composed of transistors 121, 122, and 123.

[0047] Specifically, the source electrode of transistor 120 is connected via the switching element 101a. A high-level power supply voltage VDD is applied. The source electrode of transistor 121 is connected to A high-level power supply voltage VDD is applied via the switching element 101b. In 3(B), the power supply voltage VDD is supplied to the circuit 100 by multiple switching elements 101 a. An example is shown where it is controlled by a switching element 101b, but the switching element It may be singular. Also, the gate electrode of transistor 120 and transistor 122 The gate electrode is supplied with the potential of input signal 1. The drain voltage of transistor 120 The electrode, the drain electrode of transistor 121, and the drain electrode of transistor 122 are in contact. The potential of these drain electrodes is supplied to the subsequent circuit as the potential of the output signal. The wiring or electrodes to which the output signal is applied have various capacitances, such as parasitic capacitance. In Figure 3(B), these capacitances are shown as load 124. The drain electrode of transistor 123 is connected to the drain electrode of transistor 121. The gate electrode of the transistor and the gate electrode of transistor 123 are given the potential of input signal 2. Also, a low-level power supply voltage VSS is applied to the source electrode of transistor 123. It is possible.

[0048] The switching element 101 switches according to the control signal. Semiconductor shown in Figure 3(A) Taking a device as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped (non-operating period) Figure 3 shows the timing chart of the potentials of the input signal, output signal, and control signal during the production period. (C) is shown.

[0049] During the operating period, the control signal has a potential such that the switching element 101 turns on. Specifically, Figure 3(C) illustrates the case where the control signal has a high potential. Therefore, during the operating period, the power supply voltage VSS is supplied to the source electrode of transistor 123. It can be obtained. And, when the potential of input signal 1 is high level and the potential of input signal 2 is high level When the potential of input signal 1 is low, an output signal with a low potential is obtained. In a bell, when the potential of input signal 2 is high, an output signal with a high potential is obtained. It is possible.

[0050] During the non-operating period, the control signal has a potential such that the switching element 101 is turned off. Specifically, Figure 3(C) illustrates the case where the control signal has a low potential. Therefore, during the non-operating period, the power supply voltage VSS is the source electrode of transistor 123. Since no power is supplied, the source electrode of transistor 123 is in a floating state. Therefore, whether the potentials of input signal 1 and input signal 2 are low level or high level The output signal's potential remains at a high level.

[0051] As described above, during the non-operating period, the supply of power voltage to circuit 100 is stopped. This reduces the dynamic standby power consumed by circuit 100. Also, the switch Since element 101 is made of a semiconductor element using an oxide semiconductor film, leakage current etc. The static standby power that depends on the power supply voltage to the non-operating circuit can be reduced. By stopping the power supply, both static and dynamic standby power consumed by non-operating circuits are reduced. This makes it possible to provide a semiconductor device that can reduce the overall power consumption of the circuit.

[0052] Next, we will use the case where circuit 100 is a NOR gate as an example to explain the specific configuration and operation of the semiconductor device. This will be explained using Figure 4.

[0053] The semiconductor device shown in Figure 4(A) has a circuit 100 which includes a p-channel type transistor 130, p-channel transistor 131, n-channel transistor 132, and n-channel It has a transistor 133 of type 130, transistor 131, and Transistor 132 and transistor 133 both use crystalline silicon as the active layer. And there are transistors 130, 131, 132, and The NOR gate is configured using ZISTA133.

[0054] Specifically, a high-level power supply voltage VDD is applied to the source electrode of transistor 130. The gate electrodes of transistor 130 and transistor 133 are connected to the input. The potential of signal 1 is applied. The drain electrode of transistor 130 and transistor 1 The source electrode of transistor 131 is connected. The gate electrode of transistor 131 and transistor The gate electrode of transistor 132 is given the potential of input signal 2. The drain electrode of transistor 132 and the drain electrode of transistor 133 The electrodes are connected, and the potential of these drain electrodes is used as the potential of the output signal in the subsequent circuit. The output signal is supplied to the wiring or electrodes to which it is supplied, and these wiring or electrodes have various capacitances such as parasitic capacitance. These capacitances are shown as load 134 in Figure 4(A). Transistor 13 The source electrode of 2 receives a low-level power supply voltage VSS via the switching element 101a. The source electrode of transistor 133 is connected via switching element 101b. Then, a low-level power supply voltage VSS is applied. Note that in Figure 4(A), the power supply voltage VSS The supply to circuit 100 is provided by multiple switching elements 101a and switching elements 101b The example shows a case where control is performed using a single switching element, but the switching element can also be a single element.

[0055] In Figure 4(A), the switching elements 101a and 101b provide low-level signals to the circuit 100. This example illustrates the case of controlling the supply of the power voltage VSS. Next, Figure 4(B) shows a switch. When the ng element 101 controls the supply of a high-level power supply voltage VDD to the circuit 100, The configuration of the semiconductor device is shown. The semiconductor device shown in Figure 4(B) is similar to the circuit in Figure 4(A). 100 is a p-channel transistor 130 and a p-channel transistor 131 It has an n-channel transistor 132 and an n-channel transistor 133. Transistor 130, Transistor 131, Transistor 132, Transistor 133 Both use silicon, which has crystalline properties, as the active layer. And transistor 130, Transistors 131, 132, and 133 form a NOR gate. .

[0056] Specifically, the source electrode of transistor 130 is connected via switching element 101, A high-level power supply voltage VDD is applied. The gate electrode of transistor 130 and the transistor The gate electrode of transistor 133 is supplied with the potential of input signal 1. Transistor 130 The drain electrode of the transistor is connected to the source electrode of transistor 131. The gate electrode of transistor 131 and the gate electrode of transistor 132 are given the potential of input signal 2. The drain electrode of transistor 131 and the drain electrode of transistor 132 are connected. The drain electrode of transistor 133 is connected, and the potential of these drain electrodes is The potential of the output signal is then supplied to the subsequent circuit. The output signal is supplied to the wiring or electrode. It has various capacities, such as parasitic capacity, and in Figure 4(B), these capacities are shown as load 134 and This is shown. Source electrode of transistor 132 and source electrode of transistor 133. A low-level power supply voltage VSS is applied to it.

[0057] The switching element 101 switches according to the control signal. Semiconductor shown in Figure 4(A) Taking a device as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped (non-operating period) Figure 4 shows the timing chart of the potentials of the input signal, output signal, and control signal during the production period. (C) is shown.

[0058] During operation, the control signal is transmitted to switching element 101a and switching element 101b. It has a potential such that it turns on. Specifically, in Figure 4(C), the control signal is at a high level of voltage. This illustrates the case where there is a position. Therefore, during the operating period, the power supply voltage VSS is, It is supplied to the source electrode of transistor 132 and the source electrode of transistor 133. When the potential of input signal 1 is low and the potential of input signal 2 is low, a high level An output signal with an electric potential is obtained. Also, when the electric potential of input signal 1 is high, input signal 2 When the potential is low, an output signal with a low potential is obtained.

[0059] During the non-operating period, the control signal is transmitted to switching element 101a and switching element 101 b has a potential such that it turns off. Specifically in Figure 4(C), the control signal is at a low level. This illustrates the case where there is a potential. Therefore, during the non-operating period, the power supply voltage VSS is The source electrode of transistor 132 and the source electrode of transistor 133 are not supplied. The source electrodes of transistor 132 and transistor 133 are floating It is in a high state. Therefore, even if the potentials of input signal 1 and input signal 2 are at a low level, Even at low levels, the potential of the output signal remains at a low level.

[0060] As described above, during the non-operating period, the supply of power voltage to circuit 100 is stopped. This reduces the dynamic standby power consumed by circuit 100. Also, the switch Since element 101 is made of a semiconductor element using an oxide semiconductor film, leakage current etc. The static standby power that depends on the power supply voltage to the non-operating circuit can be reduced. By stopping the power supply, both static and dynamic standby power consumed by non-operating circuits are reduced. This makes it possible to provide a semiconductor device that can reduce the overall power consumption of the circuit.

[0061] Next, we will take the case where circuit 100 is a flip-flop as an example and explain the specific structure of a semiconductor device. The formation and operation will be explained using Figures 5 and 6.

[0062] The semiconductor device shown in Figure 5(A) has a flip-flop in circuit 100, and input signal to terminal D. A clock signal is input to terminal CK, output signal 1 is output from terminal Q, and output signal Qb is output from terminal Qb. The output is 2. The specific circuit configuration of the flip-flop is 1B, utilizing the feedback mechanism. Any circuit configuration is acceptable as long as it can hold the data for that many units. Figure 5(B) shows the circuit. A more specific configuration of 100 is shown. The circuit 100 shown in Figure 5(B) is NAND140, N This is a D flip-flop using AND141, NAND142, and NAND143. The potential of the input signal is applied to the first input terminal of the AND140. The clock signal potential is applied to input terminal 2 and the second input terminal of the NAND142. The output terminal of NAND140 connects to the first input terminal of NAND142 and NAND141 It is connected to the first input terminal of NAND142. The output terminal of NAND143 is connected to the first input terminal of NAND143. It is connected to input terminal 2. The output terminal of NAND141 is the first of NAND143. It is connected to the input terminal, and the potential of the output terminal of NAND141 is the same as the potential of output signal 1. As a position, it is supplied to the subsequent circuit. The output terminal of NAND143 is the position of NAND141. It is connected to input terminal 2, and the potential of the output terminal of NAND143 is the output signal 2 This potential is then supplied to the subsequent circuit.

[0063] The circuit 100 shown in Figure 5(B) is configured to produce output signal 1 and output signal 2. However, if necessary, you can use only one output signal.

[0064] Then, power supply to NAND140, NAND141, NAND142, and NAND143 The pressure supply is controlled by the switching element 101. In Figure 5(A), the Lore For example, consider the case where the supply voltage VSS of the bell is controlled by the switching element 101. As shown, the supply of a high-level power voltage is controlled by the switching element 101. It's okay to be there.

[0065] Figure 6(A) shows an example of a more detailed circuit diagram of a semiconductor device. NAND140, NAND Regarding the transistor connection relationships in 141, NAND142, and NAND143: See Figures 3(A) and 3(B). NAND140, NAND141, Each transistor that makes up NAND142 and NAND143 is made of crystalline silicon. The active layer uses [this]. Also, in Figure 6(A), unlike Figure 5(A), the switching element Using sub-elements 101a to 101d, NAND140, NAND141, N When controlling the supply of power voltage VSS to AND142 and NAND143 respectively. This illustrates the point.

[0066] Taking the semiconductor device shown in Figure 6(A) as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped The timing of the potentials of the input signal, output signal, and control signal during the stop state period (non-operating period). The chart is shown in Figure 6(B). Switching elements 101a to 101 d is switching according to the control signal.

[0067] During operation, the control signal is transmitted to switching elements 101a to 101d. It has a potential such that it turns on. Specifically, in Figure 6(B), the control signal is at a high level of voltage. This illustrates the case where there is a position. Therefore, during the operating period, the power supply voltage VSS is NAN It is applied to D140~NAND143. And the clock signal potential is high level. When the input signal potential is low, the output signal has a high potential. 1. An output signal 2 with a low potential is obtained. Also, the clock signal potential is high. Level or low level; when the potential of the input signal is low level, it has a low potential. Output signal 1 and output signal 2 with a high potential are obtained.

[0068] During the non-operating period, the control signal is transmitted to switching elements 101a to 101. The potential is such that d is turned off. Specifically, in Figure 6(B), the control signal is at a low level. This illustrates the case where there is a potential. Therefore, during the non-operating period, the power supply voltage VSS is N Not supplied to AND140~NAND143. That is, power supply during operation The source electrode of a transistor to which pressure VSS is applied floats during the non-operating period. This results in a ping state. Therefore, even if the potential of the clock signal and the input signal is low, Even at the 1 level, the potentials of output signal 1 and output signal 2 are the same as the potential just before entering the non-operating period. To hold.

[0069] As described above, during the non-operating period, the supply of power voltage to circuit 100 is stopped. This reduces the dynamic standby power consumed by circuit 100. Also, the switch Since element 101 is made of a semiconductor element using an oxide semiconductor film, leakage current etc. The static standby power that depends on the power supply voltage to the non-operating circuit can be reduced. By stopping the power supply, both static and dynamic standby power consumed by non-operating circuits are reduced. This makes it possible to provide a semiconductor device that can reduce the overall power consumption of the circuit.

[0070] Furthermore, in the semiconductor device of the present invention, when the circuit 100 is in a stopped state, an oxide semiconductor film is used A configuration has been added that stops the supply of the clock signal to the circuit 100 using a semiconductor element. It is also acceptable to have it. Next, let's take the case where circuit 100 is a flip-flop as an example, and then circuit 10 A semiconductor device that can control the supply of power voltage to 0 and the supply of a clock signal. The specific configuration and operation will be explained using Figure 7.

[0071] The semiconductor device shown in Figure 7(A) includes circuit 100 and switching element 101, in addition to circuit 10 It has a control circuit 102 that can control the supply of a clock signal to 0. In addition to the clock signal, the path 102 also carries control signals 1 for controlling the operation of the control circuit 102. The following is input. Figure 7(A) shows an example where AND is used in the control circuit 102. As shown, both the clock signal and the control signal are input to AND. The signal output from is input to circuit 100. Circuit 100 is a flip-flow This is a top-end, with the input signal at terminal D, the signal output from control circuit 102 at terminal CK, and terminal Q An output signal is being output from there.

[0072] For the specific configuration of the circuit 100 shown in Figure 7(A), please refer to Figure 5(B). Yes. The specific circuit configuration of a flip-flop uses feedback to process 1 bit of data. Any circuit configuration is acceptable as long as it can hold the [value]. Also, the circuit 100 shown in Figure 5(B) The configuration is such that output signal 1 and output signal 2 can be obtained, but the circuit 10 shown in Figure 7(A) In setting 0, only one output signal was used.

[0073] The power supply voltage to circuit 100 is controlled by the switching element 101. In 7(A), the low-level power supply voltage VSS is supplied by the switching element 101. The example shows a case where control is applied, but the supply of a high-level power voltage is applied to the switching element. It may also be controlled by 101.

[0074] Figure 7(A) shows an example where the control circuit 102 uses AND, but control circuit 10 2 is a circuit configuration that can control the supply of a clock signal to circuit 100 according to control signal 1. Any such device is acceptable, and it is not limited to AND gates. For example, control circuit 102 could use NO instead of AND gates. Using R is also acceptable.

[0075] Furthermore, the control circuit 102 has fewer transistors that have an oxide semiconductor film as the active layer. They both have one. Transistors that have an oxide semiconductor film as the active layer have leakage current However, this is significantly lower compared to transistors using crystalline silicon. Therefore, oxidation A transistor having a semiconductor material is used as the control circuit 102, and the above rotation is performed by the control circuit 102. By controlling the supply of the clock signal to path 100, the leakage current of the control circuit 102 is reduced. This can suppress the increase in standby power consumption.

[0076] Taking the semiconductor device shown in Figure 7(A) as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped Data of input signals, data of output signals, and control signals during the stopped state (non-operating period). The timing chart of the potential of signal 1 and the potential of control signal 2 is shown in Figure 7(B).

[0077] During operation, the potential of control signal 1 is high, and the clock signal is controlled by control circuit 10 Through 2, it is supplied to circuit 100, which is a flip-flop. Also, the potential of control signal 2. The voltage is high, and the power supply voltage VSS is supplied to circuit 100. Therefore, circuit 100 is It enters an operating state. Then, the flip-flop circuit 100 receives the input clock signal. Based on the number, the data is retained. During operation, the data of the input signal is D0 to D1. As it changes to D0, the data contained in the output signal also changes from D0 to D1.

[0078] Next, during the non-operating period, the potential of control signal 1 is low, and the clock signal circuit The supply to 100 is stopped. That is, the control circuit 102 is stopped from the flip-flop a certain number of times. A potential fixed at a low level is supplied to the circuit 100. Also, during the non-operating period, The potential of signal 2 is low, and the supply of power supply voltage VSS to circuit 100 is stopped. Therefore, since circuit 100 is in a non-operating state, the output signal data remains as D1. Note that the state in which the supply of the clock signal is stopped is defined as the state in which the control circuit 102 is stopped during the operating period. The potential supplied to circuit 100 does not change between low and high levels. This refers to a state where something is fixed at a low or high level.

[0079] As described above, during the non-operating period, the supply of the clock signal to circuit 100 is stopped. This is due to so-called clock gating, which reduces the dynamic standby power consumed by circuit 100. This can be reduced. And, by stopping the supply of power voltage to circuit 100, The dynamic standby power consumed by circuit 100 can be reduced. Also, the switching element Since child 101 and control circuit 102 are made of semiconductor devices using oxide semiconductor films, Therefore, static standby power, which depends on leakage current, etc., can be reduced. The supply of clock signals and power voltage to the circuit is stopped, and static standby power consumed by non-operating circuits is reduced. By reducing both dynamic and standby power, semiconductor devices can reduce the overall power consumption of the circuit. We can provide a place for you.

[0080] Furthermore, even if the control circuit 102 uses NOR instead of AND, the clock signal The signal and control signal are both input to the NOR gate. The signal output from the NOR gate is then used in the circuit. It is input to 100. In Figure 17(A), in the semiconductor device shown in Figure 7(A), the control circuit The configuration when 102 uses a NOR gate is shown. Circuit 100 and switching element 101 The configuration is the same as in Figure 7(A), so a detailed explanation will be omitted. Taking a semiconductor device as an example, the period during which circuit 100 is in operation (operating period) and the period during which it is stopped. During the (non-operating period), the input signal data, the output signal data, the potential of control signal 1, and control The timing chart of the potential of signal 2 is shown in Figure 17(B).

[0081] When a NOR gate is used in the control circuit 102, the potential of the control signal 1 is low during the operating period. The clock signal is transmitted through the control circuit 102 to the flip-flop circuit 100. It is supplied to the circuit 10. Also, the potential of control signal 2 is high level, and the power supply voltage VSS is high. It is supplied to 0. Therefore, circuit 100 enters an operating state. And, with a flip-flop Circuit 100 holds data based on the input clock signal. During operation, Since the data in the input signal changes from D0 to D1, the data in the output signal It also changes from D0 to D1.

[0082] Next, during the non-operating period, the potential of control signal 1 is high, and the clock signal circuit The supply to 100 is stopped. That is, the control circuit 102 is stopped from the flip-flop a certain number of times. A potential fixed at a low level is supplied to the circuit 100. Also, during the non-operating period, The potential of signal 2 is low, and the supply of power supply voltage VSS to circuit 100 is stopped. Therefore, since circuit 100 is in a non-operating state, the output signal data remains as D1. ru.

[0083] (Embodiment 2) This embodiment describes a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0084] A semiconductor device according to one aspect of the present invention comprises a transistor using silicon and an oxide semiconductor It has a transistor made of silicon. A transistor made of silicon has a silicon wafer, S OI (Silicon on Insulator) substrate, silicon thin film on insulating surface It can be formed using [a specific method / tool].

[0085] SOI substrates include, for example, UNIBOND, ELTRAN (E), which are represented by SmartCut. Pitaxial Layer Transfer, dielectric separation method, PACE (Pla Methods such as SMA (Assisted Chemical Etching) and SIMOX (S It is prepared using methods such as (e.g., separation by implanted oxygen). It is possible.

[0086] A silicon semiconductor film formed on a substrate having an insulating surface is crystallized by known techniques. It is also possible to do so. Known crystallization methods include laser crystallization using laser light and using catalytic elements. There are crystallization methods that exist. Alternatively, a combination of crystallization methods using catalytic elements and laser crystallization methods can be used. It can also be used in combination. Furthermore, when using a substrate with excellent heat resistance such as quartz, Thermal crystallization method using a heat furnace, lamp annealing crystallization method using infrared light, and using catalytic elements A crystallization method combining a regular crystallization method and a high-temperature annealing method at around 950°C may also be used.

[0087] Furthermore, the semiconductor device manufactured using the above method is made from a flexible base such as plastic. A semiconductor device may be formed by transferring the material onto a plate. Transfer is performed by placing a metal between the substrate and the semiconductor element. A method for forming an oxide film, weakening the metal oxide film by crystallization, and then peeling off and transferring a semiconductor element. An amorphous silicon film containing hydrogen is provided between the substrate and the semiconductor element, and then irradiated with laser light or etched. A method for separating and transferring a semiconductor element from a substrate by removing the amorphous silicon film using a grease trap. The substrate on which the element is formed is removed mechanically or by etching with a solution or gas. Various methods can be used, such as methods for separating and transferring semiconductor elements from the substrate.

[0088] In this embodiment, an SOI (Silicon on Insulator) substrate is used After fabricating a transistor with silicon, then fabricating a transistor with oxide semiconductor We will explain the method of manufacturing semiconductor devices, using the case of manufacturing as an example.

[0089] First, as shown in Figure 8(A), after cleaning the bond substrate 200, the surface of the bond substrate 200 An insulating film 201 is formed on the surface.

[0090] A silicon single-crystal semiconductor substrate can be used as the bond substrate 200. The substrate 200 is silicon with strain in its crystal lattice, and germanium relative to silicon. A semiconductor substrate such as silicon germanium with added material may also be used.

[0091] Furthermore, the single-crystal semiconductor substrate used in the bond substrate 200 has a crystal axis direction within the substrate. While it is desirable for them to be aligned, lattice defects such as point defects, line defects, and surface defects must be completely eliminated. It does not need to be a perfectly formed crystal.

[0092] The shape of the bond substrate 200 is not limited to a circle; it may be processed into a shape other than a circle. For example, the shape of the base substrate 203 to be bonded later is generally rectangular, and shrinkage Considering that the exposure area of ​​exposure equipment such as a small projection type exposure apparatus is rectangular, bond substrate 2 The shape of 00 may be processed so that it becomes a rectangle. The processing of the shape of the bond substrate 200 is This can be done by cutting a commercially available circular single-crystal semiconductor substrate.

[0093] Even if the insulating film 201 uses a single insulating film, it can also be used by stacking multiple insulating films. It may be a material. The thickness of the insulating film 201 is such that the region containing impurities is later removed. Taking that into consideration, a range of 15nm to 500nm is recommended.

[0094] The films constituting the insulating film 201 include silicon oxide film, silicon nitride film, silicon oxide nitride film, and silicon nitride film. germanium oxide film, germanium nitride film, germanium oxide nitride film, germanium nitride film, germanium oxide nitride Insulating films containing silicon or germanium in their composition, such as luminium films, can be used. In addition, insulation made of metal oxides such as aluminum oxide, tantalum oxide, and hafnium oxide. Films, insulating films made of metal nitrides such as aluminum nitride, aluminum oxide nitride films, etc. insulating films made of metal oxides, such as aluminum nitride films, are made of metal nitride oxides. An insulating film can also be used.

[0095] For example, in this embodiment, silicon oxide is formed by thermal oxidation of the bond substrate 200. An example of using the element as the insulating film 201 is shown. Note that in Figure 8(A), the insulating film 201 is made of bon. The insulating film 201 is formed to cover the entire surface of the bond substrate 200, but the bond substrate 200 It is sufficient if it is formed on at least one surface.

[0096] In this specification, an oxidized nitride is defined as a compound in which the oxygen content is higher than the nitrogen content. It is a substance, and nitride oxides have a higher nitrogen content than oxygen in their composition. It refers to a substance.

[0097] Furthermore, when forming an insulating film 201 by thermal oxidation of the surface of the bond substrate 200, Oxidation can be performed using dry oxidation with low water content oxygen, or by using a halo such as hydrogen chloride in an oxygen atmosphere. Thermal oxidation with the addition of a gas containing hydrogen can be used. Alternatively, hydrogen can be burned with oxygen. Pyrogenic oxidation, which produces water by heating high-purity pure water to over 100 degrees Celsius, is used. Wet oxidation, such as steam oxidation, which involves oxidation in a wet state, may also be used to form the insulating film 201.

[0098] The reliability of semiconductor devices such as alkali metals or alkaline earth metals is determined on the base substrate 203. When using a substrate containing impurities that reduce the level of impurities, the above impurities separate from the base substrate 203. A barrier film that can prevent diffusion into the semiconductor film formed after separation, at least 1 Preferably, the insulating film 201 has one or more layers. An insulating film that can be used as a barrier film. The film may be a silicon nitride film, a silicon oxide nitride film, an aluminum nitride film, or an aluminum oxide nitride film. Examples include film. The insulating film used as a barrier film has a thickness of, for example, 15 nm to 300 nm. It is preferable to form it with a film thickness of m. Also, between the barrier film and the bond substrate 200, It is also acceptable to form an insulating film with a lower nitrogen content than the barrier film, such as a silicon film or a silicon oxidizride film. The thickness of the insulating film with a low nitrogen content should be between 5 nm and 200 nm.

[0099] When silicon oxide is used as the insulating film 201, the insulating film 201 consists of silane and oxygen, and TEOS (Te Using a mixed gas of traethoxysilane and oxygen, thermal CVD, plasma CVD, and atmospheric pressure CVD are performed. D, can be formed by vapor phase growth methods such as bias ECRCVD. In this case, The surface of the edge film 201 may be densified by oxygen plasma treatment. Alternatively, silicon nitride may be used in the insulating film 20 When used as 1, a mixed gas of silane and ammonia is used, and vapor phase formation such as plasma CVD is performed. It can be formed by a long method.

[0100] Also, silicon oxide produced by chemical vapor deposition using an organic silane gas may be used as the insulating film 20 1. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetrame thylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3) and other silicon -containing compounds can be used.

[0101] By using an organic silane as the source gas, a silicon oxide film having a smooth surface can be formed at a process temperature of 350 °C or lower. Also, by the thermal CVD method, an LTO (low temperature oxide) formed at a heating temperature of 200 °C or higher and 500 °C or lower can be used. For the formation of LTO, monosilane (SiH4) or disilane (Si2H6) etc. can be used as the silicon source gas, and nitrogen dioxide (NO2) etc. can be used as the oxygen source gas.

[0102]

[0103] For example, when forming the insulating film 201 made of a silicon oxide film using TEOS and O2 as the source gases, the flow rate of TEOS may be 15 sccm, the flow rate of O2 may be 750 sccm, the film formation pressure may be 100 Pa

[0103] In addition, a silicon oxide film formed using an organic silane, or a silicon oxynitride film formed at a low temperature Insulating films deposited at relatively low temperatures, such as those mentioned above, have many OH groups on their surface. OH groups are water molecules. By forming hydrogen bonds, silanol groups are created, and the base substrate and insulating film are joined at low temperatures. And finally, the siloxane bond, which is a covalent bond, forms between the base substrate and the insulating film. Therefore, a silicon oxide film formed using the above-mentioned organic silane, or at a relatively low temperature Insulating films such as LTO that are formed using this method have OH groups used in Smart Cut and other applications. It can be said that it is more suitable for bonding at low temperatures than thermal oxide films, which are absent or drastically less numerous.

[0104] The insulating film 201 is a film for forming a smooth, hydrophilic bonding surface on the surface of the bond substrate 200. Therefore, the average roughness Ra of the insulating film 201 is 0.7 nm or less, more preferably 0. A thickness of 4 nm or less is preferred. Furthermore, the thickness of the insulating film 201 is 5 nm or more and 500 nm or less. More preferably, the wavelength should be between 10 nm and 200 nm.

[0105] Next, as shown in Figure 8(B), the bond substrate 200 is bonded to an ion accelerated by an electric field. The beam is irradiated onto the bond substrate 200 through the insulating film 201 as indicated by the arrow, and the bond A brittle layer 202 having minute voids is formed in a region of a certain depth from the surface of the substrate 200. For example, a brittle layer refers to a layer that has been locally weakened due to a disruption of its crystal structure. The state varies depending on the means used to form the embrittlement layer. Furthermore, from one surface of the bond substrate to the embrittlement layer... The region may also be weakened to some extent, but the embrittlement layer is the region that will later be fractured and the layers near it. It refers to.

[0106] The depth of the region where the embrittlement layer 202 is formed depends on the acceleration energy of the ion beam and the ion beam The angle of incidence can be adjusted. The acceleration energy can be adjusted by the acceleration voltage. A brittle layer 202 is formed in a region with a depth approximately the same as the average ion penetration depth. The thickness of the semiconductor film 204 that is later separated from the bond substrate 200 is determined by the depth at which this occurs. The depth to which the embrittlement layer 202 is formed can be, for example, 50 nm to 500 nm. The preferred depth range is between 50 nm and 200 nm.

[0107] Ions are implanted into the bond substrate 200 using an ion doping method that does not involve mass separation. While this is desirable in terms of shortening the cycle time, the present invention involves ion separation with mass separation. Injection methods may also be used.

[0108] When hydrogen (H2) is used as the source gas, the hydrogen gas is excited and H + H2 + H3 + to produce This can be achieved. The proportion of ion species generated from the source gas is related to the plasma excitation method. By adjusting the pressure of the atmosphere that generates the plasma, the amount of source gas supplied, etc., the changes can be made. It can be done. When ion implantation is performed using the ion doping method, H is added to the ion beam. + H2 + H3 + H3 + It contains 50% or more, more preferably 80% or more. It is preferable that it is H3 + By making the proportion of 80% or more, the ion beam contains H2 + Because the proportion of ions becomes relatively small, hydrogen ions contained in the ion beam Because the variability in the average penetration depth is reduced, the ion implantation efficiency is improved, and the cycle time is reduced. This can be shortened.

[0109] Also, H3 + is heavier than H + and H2 + . Therefore, in an ion beam, when the proportion of H3 + is high and when the proportion of H + and H2 + is high, even if the acceleration voltage during doping is the same, hydrogen can be implanted into the shallow region of the bond substrate 200 more easily in the former case. Also, in the former case, since the concentration distribution of the hydrogen implanted into the bond substrate 200 in the thickness direction becomes steeper, the thickness of the embrittlement layer 202 itself can be made thinner. When ion implantation is performed by the ion doping method using hydrogen gas, by setting the acceleration voltage to 10 kV or more and 200 kV or less, and the dose amount to 1×10 ions / cm

[0110] or more and 6×10 ions / cm 16 or less, depending on the ion species and their proportions contained in the ion beam and the film thickness of the insulating film 201, the embrittlement layer 202 can be formed in the region of the bond substrate 200 at a depth of 50 nm or more and 500 nm or less. 2 or more and 6×10 16 ions / c m 2 For example, when the bond substrate 200 is a single crystal silicon substrate and the insulating film 201 is formed of a thermal oxide film with a thickness of 100 nm , at a flow rate of 50 sccm of 100% hydrogen gas as the source gas, a beam current density of 5 μA / cm , an acceleration voltage of 50 kV, and a dose amount of 2.0×10

[0111] atoms / cm , a semiconductor film with a thickness of about 146 nm can be separated from the bond substrate 200. When the conditions for adding hydrogen to the bond substrate 200 are the same and 2 , at an acceleration voltage of 50 kV and a dose amount of 2.0×10 16 a toms / cm 2 , a semiconductor film with a thickness of about 146 nm can be separated from the bond substrate 200. Note that when the conditions for adding hydrogen to the bond substrate 200 are the same , Also, by increasing the thickness of the insulating film 201, the thickness of the semiconductor film can be reduced. It is possible.

[0112] Helium (He) can also be used as the source gas for the ion beam. The ion species produced is He + Since this is mostly the case, ion doping does not involve mass separation. Even in the G law, He + It can be implanted into the bond substrate 200 as the main ion. Therefore, by ion doping, minute pores can be efficiently formed in the embrittlement layer 202. When performing ion implantation using helium via ion doping, the acceleration voltage is 10kV. Above 200kV or less, dose 1 × 10⁻¹⁰ 16 ions / cm 2 The above 6 x 10 16 ions / cm 2 The following is possible:

[0113] Halogen gases such as chlorine gas (Cl2 gas) and fluorine gas (F2 gas) are used as the source gas. It is possible to stay there.

[0114] Furthermore, when ion implantation is performed on the bond substrate 200 using the ion doping method, ion doping Because impurities present in the apparatus are injected into the workpiece along with ions, the surface of the insulating film 201 Impurities such as S, Ca, Fe, and Mo may be present near the surface. Therefore, insulating film 20 The region near the surface of 1, which is thought to have the most impurities, is removed by etching, polishing, etc. It is also acceptable to leave it as is. Specifically, from 10 nm to 100 nm from the surface of insulating film 201, Ideally, the area should be removed to a depth of approximately 30-70 nm. This is done using dry etching. and the Reactive Ion Etching (RIE) method ICP (Inductively Coupled Plasma) etching method, E CR (Electron Cyclotron Resonance) etching method, flat Plate-type (capacitively coupled) etching method, magnetron plasma etching method, dual-frequency plasma Zuma etching or helicon wave plasma etching can be used. For example, when removing the surface area of ​​a silicon nitride oxide film using ICP etching, the etching gas The flow rate of CHF3 is 7.5 sccm, the flow rate of He is 100 sccm, and the reaction pressure is 5.5 Pa, lower electrode temperature 70°C, RF (13.56MHz) power applied to the coil-type electrode. 475W, 300W power applied to the lower electrode (bias side), etching time 10 sec By setting it to a certain extent, it is possible to remove areas from the surface to a depth of about 50 nm.

[0115] In addition to the fluorine-based gas CHF3, other etching gases include Cl2, BCl3, and SiC. Chlorine-based gases such as l4 and CCl4, fluorine-based gases such as CF4, SF6, and NF3, and O2 It can be used as appropriate. Furthermore, an inert gas other than He can be added to the etching gas used. This is also good. For example, one of the inert elements selected from Ne, Ar, Kr, and Xe as the added element. Alternatively, multiple elements can be used. Furthermore, the area near the surface of the silicon nitride film can be wetted. When removing by scrubbing, hydrofluoric acid containing ammonium hydrogen fluoride, ammonium fluoride, etc. The system solution can be used as the etchant. Polishing can be done using chemical mechanical polishing (CMP). (Chemical Mechanical Polishing) or liquid jet This can be done by polishing or other methods.

[0116] After the formation of the embrittlement layer 202, the heavily contaminated areas near the surface of the insulating film 201 are etched. The semiconductor film 2 formed on the base substrate 203 is removed by polishing or other means. This reduces the amount of impurities mixed into 04. Furthermore, it also helps to control the final semiconductor device that is formed. So, due to the influence of impurities, transistors exhibit behaviors such as fluctuations in threshold voltage and increased leakage current. This prevents a decrease in electrical characteristics and reliability.

[0117] Next, as shown in Figure 8(C), the bonding substrate 200 and the insulating film 201 are sandwiched in between. - Attach the substrate 203.

[0118] Before bonding the base substrate 203 and the bond substrate 200, the bonding process is performed. The surface, that is, in this embodiment, the insulating film 201 formed on the bond substrate 200 and - To improve the bonding strength between the insulating film 201 and the base substrate 203, It is preferable to apply a surface treatment.

[0119] Surface treatments include wet treatment, dry treatment, or a combination of wet and dry treatment. Combinations are possible. This could involve combining different wet treatments or different dry treatments. It is permissible to do so. As for wet treatment, ozone treatment using ozonated water (ozonated water cleaning) Ultrasonic cleaning such as megasonic cleaning, or two-fluid cleaning (using functional water such as pure water or hydrogenated water) Methods such as spraying with a carrier gas like nitrogen, and cleaning using hydrochloric acid and hydrogen peroxide. Examples include: dry treatments such as inert gas neutral atomic beam treatment and inert gas ion treatment. Beam treatment, ultraviolet treatment, ozone treatment, plasma treatment, bias-applied plasma treatment, and Examples include radical treatment. By performing the above surface treatments, the bonding process is improved. This improves the hydrophilicity and cleanliness of the surface, thereby increasing the bonding strength.

[0120] The bonding process involves tightly adhering the base substrate 203 to the insulating film 201 on the bond substrate 200. Then, a 1 N / cm² load is applied to a portion of the superimposed base substrate 203 and bond substrate 200. 2 The above 50 0 N / cm 2 Preferably 11 N / cm 2 More than 20N / cm 2 Apply the following pressure When pressure is applied, the base substrate 203 and the insulating film 201 begin to bond from that point. Ultimately, the bonding extends to the entire surface that is in contact with the other material.

[0121] The bonding is achieved using van der Waals forces and hydrogen bonds, resulting in a strong bond even at room temperature. A bond is formed. Since the above bonding can be performed at a low temperature, the base substrate 203 Various materials can be used. For example, as the base substrate 203, aluminum foil can be used. Glass, barium borosilicate glass, aluminoborosilicate glass, etc. for the electronics industry. In addition to various glass substrates used in the application, other substrates such as quartz substrates, ceramic substrates, and sapphire substrates are also used. Furthermore, silicon, gallium arsenide, and ion can be used as the base substrate 203. Semiconductor substrates such as phosphate substrates can be used. Alternatively, a stainless steel substrate can be used. A metal substrate may be used as the base substrate 203. The glass substrate has a thermal expansion coefficient of 25 × 10 -7 / ℃ or higher 50×10 -7 / ℃ or lower (preferably) 30×10 -7 / ℃ or higher 40×10 -7(below / ℃), and the strain point is 580℃ or higher 6 It is preferable to use a substrate with a temperature of 80°C or lower (preferably 600°C to 680°C). Furthermore, if an alkali-free glass substrate is used as the glass substrate, the semiconductor device will be affected by impurities. This can help reduce pollution.

[0122] As for the glass substrate, a mother glass substrate developed for the manufacture of liquid crystal panels can be used. Yes, it's possible. For example, the mother glass could be the 3rd generation (550mm x 650mm), the 3rd generation... 5th generation (600mm x 720mm), 4th generation (680mm x 880mm or 730mm) mm x 920 mm), 5th generation (1100 mm x 1300 mm), 6th generation (1500 mm) m x 1850mm), 7th generation (1870mm x 2200mm), 8th generation (2200m Substrates of sizes such as m x 2400 mm are known. Large-area mother glass substrates are used. By using substrate 203 to manufacture SOI substrates, it is possible to increase the area of ​​SOI substrates. Yes, it is possible. If the SOI substrate can be made to a large area, it will be possible to manufacture a large number of ICs, LSIs, and other chips at once. This allows for the creation of chips from a single substrate, dramatically increasing productivity. It can be improved.

[0123] Like the EAGLE2000 (manufactured by Corning), the heat treatment significantly increases the size. When using a glass substrate that can be linked as the base substrate 203, the bonding process is performed after the bonding step. Failures in bonding may occur. Therefore, avoid bonding failures caused by shrink wrapping. To achieve this, the base substrate 203 may be preheated before bonding.

[0124] In addition, an insulating film may be formed on the base substrate 203. An insulating film does not necessarily have to be formed on the surface, but an insulating film is required on the surface of the base substrate 203. By forming this layer, alkali metals and aluminum are transferred from the base substrate 203 to the bond substrate 200. This prevents impurities such as potassium-earth metals from entering. Also, the surface of the base substrate 203 When an insulating film is formed on the surface, the insulating film on the base substrate 203 is bonded to the insulating film 201. Therefore, the types of substrates that can be used as the base substrate 203 are further expanded. Substrates made of flexible synthetic resins such as bucks generally tend to have a low heat resistance temperature, If it can withstand the processing temperature in the subsequent semiconductor device fabrication process, then on the base substrate 203 When forming an insulating film, it can be used as the base substrate 203. Polyester, such as polyethylene terephthalate (PET), is used as a plastic substrate. Polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate Bonate (PC), polyetheretherketone (PEEK), polysulfone (PSF) Polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate Polyurethane (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride Examples include polypropylene, polyvinyl acetate, and acrylic resin. Base substrate 20 When forming an insulating film on 3, surface treatment is performed on the surface of the insulating film, similar to the insulating film 201. It is best to do this before gluing them together.

[0125] After bonding the bond substrate 200 to the base substrate 203, the base substrate 203 and insulating film 20 It is preferable to perform a heat treatment to increase the bonding force at the interface with 1. The temperature should be such that cracks do not occur in the embrittlement layer 202, and should be between 200°C and 400°C. It can be processed within this temperature range. Also, while heating within this temperature range, the base substrate 203 By bonding the bond substrate 200, the bond between the base substrate 203 and the insulating film 201 This can strengthen the bonding force of the joint.

[0126] When bonding the bond substrate 200 and the base substrate 203, if any dust or debris is present on the bonding surface, If the joint surface becomes contaminated, the contaminated area will not bond. To prevent contamination of the joint surface, The bonding of the bond substrate 200 and the base substrate 203 is preferably performed in an airtight processing chamber. It is also the case that when bonding the bond substrate 200 and the base substrate 203, the processing chamber 5.0×10 -3 Even if you reduce the pressure to around Pa and clean the atmosphere during the bonding process good.

[0127] Next, by performing a heat treatment, adjacent microvoids in the embrittlement layer 202 bond together. As a result, the volume of the minute voids increases. Consequently, as shown in Figure 8(D), the embrittlement layer 202 In this case, the semiconductor film 204, which is part of the bond substrate 200, separates from the bond substrate 200. The insulating film 201 is bonded to the base substrate 203, so there is a bond on the base substrate 203. The semiconductor film 204, separated from the bond substrate 200, is fixed. The heat treatment temperature for separating from 200 is a temperature that does not exceed the strain point of the base substrate 203. Let's assume that.

[0128] This heat treatment involves an RTA (Rapid Thermal Annealing) device and a resistance heating device. A furnace or microwave heating device can be used. The RTA device uses GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid A Thermal Anneal (GRTA) device can be used. The heating temperature must be between 550°C and 650°C, and the processing time between 0.5 minutes and 60 minutes. Yes, it is possible. When using a resistance heating device, the heating temperature should be between 200°C and 650°C, and the processing time should be 2 It can be between 1 hour and 4 hours.

[0129] Furthermore, the above heat treatment may be carried out using dielectric heating with high-frequency waves such as microwaves. The heating treatment by dielectric heating is performed using a high-frequency generator that produces a frequency of 300 MHz or higher. This can be done by irradiating the bond substrate 200 with a high frequency of 3 THz. Specifically, For example, by irradiating with 2.45 GHz microwaves at 900 W for 14 minutes, the embrittlement layer Adjacent microvoids are bonded together, ultimately separating the bond substrate 200 in the embrittlement layer. It can be made to happen.

[0130] This section describes a specific heat treatment method using a vertical furnace with resistance heating. Bonded substrate 2 The base substrate 203 with 00 attached is placed on the boat of the vertical furnace, and the boat is placed in the vertical furnace It is then transported into the chamber. In order to suppress oxidation of the bond substrate 200, first the inside of the chamber is Evaporate the system to create a vacuum. The vacuum level is 5 × 10⁻⁶. -3 It should be around Pa. After creating a vacuum, Nitrogen is supplied into the chamber to create a nitrogen atmosphere at atmospheric pressure. During this time, Raise the temperature to 200°C.

[0131] After creating a nitrogen atmosphere at atmospheric pressure inside the chamber, heat it at 200°C for 2 hours. Then, The temperature is raised to 400°C over 1 hour. Once the heating temperature stabilizes at 400°C, 1 hour Heat it up to 600°C. Once the heating temperature stabilizes at 600°C, 2 Heat for a specified time. Then, gradually reduce the heating temperature to 400°C over 1 hour, and continue for 10 to 30 minutes. After a while, the boats are removed from the chamber. Under an open atmosphere, the boats are lined up on the boats. The end substrate 200 and the base substrate 203 to which the semiconductor film 204 is attached are cooled.

[0132] The heat treatment using the resistance heating furnace described above strengthens the bonding force between the insulating film 201 and the base substrate 203. A heat treatment to convert the material and a heat treatment to separate the embrittlement layer 202 are performed in succession. If the two heat treatments are performed in different devices, for example, in a resistance heating furnace, the treatment temperature is 20 After heat treatment at 0°C for 2 hours, the bonded base substrate 203 and bond The substrate 200 is removed from the furnace. Next, it is processed in an RTA device at a processing temperature of 600°C to 700°C. Below, heat treatment is performed for a processing time of approximately 1 minute to several hours to create a brittle layer 20 on the bond substrate 200. Divide them at point 2.

[0133] Note that the peripheral portion of the bond substrate 200 may not be bonded to the base substrate 203. This means that the peripheral edge of the bond substrate 200 is beveled or has curvature. Therefore, the base substrate 203 and the insulating film 201 do not adhere closely, or the periphery of the bond substrate 200 This is thought to be due to reasons such as the difficulty in dividing the embrittlement layer 202 at the edges. The reason for this is that polishing such as CMP performed when manufacturing the bond substrate 200 causes the bond base The surface quality of the periphery of plate 200 is insufficient, and the surface is rougher at the periphery compared to the center. It can be done. Also, when transporting the bond substrate 200, the periphery of the bond substrate 200 is controlled by a carrier, etc. If the edges are scratched, this scratch can also be a reason why the surrounding area is difficult to bond to the base substrate 203. It is thought that the base substrate 203 will be larger than the bond substrate 200. A small semiconductor film 204 is attached.

[0134] Furthermore, before separating the bond substrate 200, the bond substrate 200 is subjected to a hydrogenation treatment. It is permissible to do so. Hydrogenation treatment can be carried out, for example, at 350°C for about 2 hours in a hydrogen atmosphere.

[0135] Furthermore, when bonding the base substrate 203 to a plurality of bond substrates 200, the plurality of bond The substrate 200 may have different crystal plane orientations. Mobility varies depending on the crystal plane orientation. Therefore, the crystal plane orientation suitable for the semiconductor device to be formed is important. A bond substrate 200 having the above characteristics can be appropriately selected to form a semiconductor film 204. For example, a semi If an n-type semiconductor device is formed using the conductive film 204, then the semiconductor will have a {100} plane. By forming the film 204, the mobility of majority carriers in the semiconductor device can be increased. Yes, it is possible. Also, for example, if a p-type semiconductor device is formed using semiconductor film 204, {1 By forming a semiconductor film 204 having 10 planes, the majority carriers in the semiconductor device are formed. The mobility can be increased. And if you form a transistor as a semiconductor element Then, considering the channel orientation and crystal plane orientation, the direction of bonding of the semiconductor film 204 is determined. Make it so.

[0136] Next, the surface of the semiconductor film 204 may be planarized by polishing. Planarization is not necessarily required. However, by performing planarization, the semiconductor films 206 and 207 that are formed later will be able to interact with each other. The properties of the interface of the insulating film can be improved. Specifically, polishing is chemical mechanical polishing. CMP (Chemical Mechanical Polishing) or liquid polishing This can be done by jet polishing, etc. The thickness of the semiconductor film 204 is obtained by the above planarization. The film is thinned. The above planarization may be performed on the semiconductor film 204 before etching, but after The process may also be applied to semiconductor films 206 and 207 formed by etching.

[0137] Alternatively, instead of polishing, etching the surface of the semiconductor film 204 can also be used to modify the semiconductor film 204. The surface can be planarized. For etching, for example, reactive ion etching (RI) can be used. E:Reactive Ion Etching) method, ICP(Inductively Coupled Plasma etching method, ECR (Electron Cycling) otron Resonance etching method, parallel plate type (capacitive coupling type) etching Methods include magnetron plasma etching, dual-frequency plasma etching, or helicon wave Dry etching methods such as plasma etching can be used.

[0138] For example, when using the ICP etching method, the flow rate of the etching gas, chlorine, is 40 sccm. ~100 sccm, power applied to coil-type electrode 100W~200W, lower electrode (by A power input of 40W to 100W and a reaction pressure of 0.5Pa to 1.0Pa (on the asphalt side) would be appropriate. For example, if the etching gas is chlorine at a flow rate of 100 sccm and the reaction pressure is 1.0 Pa, The electrode temperature is 70°C, and the RF (13.56MHz) power applied to the coil-type electrode is 150W. The power applied to the lower electrode (bias side) is 40W, and the etching time is 25 sec to 27 se. By setting c, the semiconductor film 204 can be thinned to a thickness of approximately 50 nm to 60 nm. Etching gases include chlorine-based gases such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride. Use appropriate fluorine-based gases such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, as well as oxygen. It is possible.

[0139] The above etching process is used to create a semiconductor film with a thickness that is optimal for the semiconductor device that will be formed later. Not only can 204 be made into a thin film, but the surface of the semiconductor film 204 can also be planarized.

[0140] Furthermore, the semiconductor film 204 in close contact with the base substrate 203 forms an embrittlement layer 202, and the embrittlement layer 2 The fragmentation at 02 may result in the formation of crystal defects or damage to the flatness of the surface. Therefore, in one aspect of the present invention, crystal defects are reduced and flatness is improved. Therefore, a process to remove oxide films such as native oxide films formed on the surface of the semiconductor film 204. After this, the semiconductor film 204 is irradiated with laser light.

[0141] In this embodiment of the present invention, a semiconductor film 204 is added to DHF with a hydrogen fluoride concentration of 0.5 wt%. Expose for 10 seconds to remove the oxide film.

[0142] The laser beam irradiation is performed at an energy density sufficient to partially melt the semiconductor film 204. This is preferable. If it is completely melted, disorderly nucleation will occur in the liquid phase semiconductor film 204. Therefore, when the semiconductor film 204 is recrystallized, microcrystals are formed, and its crystallinity decreases. By partially melting the semiconductor film 204, crystallization occurs from the unmelted solid phase portion. A growth process called longitudinal growth occurs. Recrystallization due to longitudinal growth causes the semiconductor film 20 The number of crystal defects is reduced, and the crystallinity is restored. Note that the semiconductor film 204 is in a completely molten state. In this case, the semiconductor film 204 is melted up to the interface with the insulating film 201 and is in a liquid state. This refers to the state in which the semiconductor film 204 is partially molten, while the upper layer is molten and in the liquid phase. This refers to a state in which the lower layer is in a solid phase.

[0143] This laser beam irradiation uses pulsed oscillation to partially melt the semiconductor film 204. It is desirable to irradiate with light. For example, in the case of pulsed oscillation, the repetition frequency should be 1 MHz. The pulse width is between 10 nanoseconds and 500 nanoseconds, with a frequency of z being less than or equal to z. For example, a repetition frequency of 10 Hz. This uses a XeCl excimer laser with a frequency of ~300Hz, pulse width of 25 ns, and wavelength of 308 nm. It is possible.

[0144] Laser light is the fundamental or second harmonic of a solid-state laser that is selectively absorbed by a semiconductor. This is desirable. Specifically, for example, a laser with a wavelength in the range of 250 nm to 700 nm. The laser light can be used. Also, the energy of the laser light is the wavelength of the laser light, the laser light This can be determined by considering the skin depth, the thickness of the semiconductor film 204, etc. The body membrane 204 is approximately 120 nm thick, and the laser beam has a wavelength of 308 nm. When using this method, the energy density of the laser light should be 600 mJ / cm². 2 ~700 mJ / cm 2 That would be good.

[0145] Examples of pulsed lasers include Ar lasers, Kr lasers, excimer lasers, and CO2 lasers. Lasers, YAG lasers, Y2O3 lasers, YVO4 lasers, YLF lasers, YAlO3 lasers Glass laser, ruby ​​laser, alexandrite laser, Ti: sapphire laser A copper vapor laser or a gold vapor laser can be used.

[0146] In this embodiment, when the thickness of the semiconductor film 204 is about 146 nm, the laser light irradiation is performed. This can be done as follows: A XeCl excimer laser is used as the laser oscillator for the laser light. The optical system uses (wavelength: 308 nm, pulse width: 20 n seconds, repetition frequency: 30 Hz). This shapes the cross-section of the laser beam into a linear shape of 0.4 mm x 120 mm. Laser beam scanning speed The laser beam is set to 0.5 mm / second and irradiated onto the semiconductor film 204. As shown in Figure 8(E), a semiconductor film 205 with repaired crystal defects is formed.

[0147] Laser irradiation should be performed in an inert atmosphere such as a rare gas or nitrogen atmosphere, or in a reduced pressure atmosphere. It is preferable to perform the procedure in an airtight environment. To irradiate laser light in the above atmosphere, an airtight chamber is required. The atmosphere inside the chamber can be controlled by irradiating it with laser light. If not using this method, an inert gas such as nitrogen gas can be blown onto the surface to be irradiated by the laser beam. Laser irradiation in an active atmosphere can be achieved. In an inert atmosphere or reduced pressure atmosphere By irradiating with laser light in this environment, the formation of a native oxide film is reduced compared to when performed in an atmospheric environment. This further suppresses cracking or pinpointing in the semiconductor film 205 formed after laser irradiation. This suppresses the occurrence of fringes and improves the flatness of the semiconductor film 205, and laser light This can broaden the usable energy range.

[0148] The optical system makes the energy distribution of the laser light uniform and gives the cross-sectional shape a linear form. This is preferable. This allows for high throughput and uniform irradiation of the laser light. This can be done. The beam length of the laser light is made longer than one side of the base substrate 203, so that once During scanning, laser light is irradiated onto all semiconductor films 204 attached to the base substrate 203. If the beam length of the laser light is shorter than one side of the base substrate 203, multiple times During scanning, laser light is irradiated onto all semiconductor films 204 attached to the base substrate 203. It should be made to a length that allows it to be done.

[0149] Irradiate with laser light in an inert atmosphere such as a noble gas or nitrogen atmosphere, or in a reduced pressure atmosphere. To do this, a laser beam is irradiated into an airtight chamber, and the atmosphere inside this chamber is changed. It just needs to be controlled. If a chamber is not used, an inert gas such as nitrogen gas should be placed on the surface to be irradiated with the laser beam. By blowing a neutral gas, it is possible to achieve laser light irradiation in an inert atmosphere. By irradiating with laser light in an active atmosphere or a reduced-pressure atmosphere, the process can be performed in an air atmosphere. Rather than combining, it further suppresses the formation of the native oxide film, and the semiconductor film 205 formed after laser light irradiation This suppresses the occurrence of cracks or pitch fringes, improving the flatness of the semiconductor film 205. This allows for a wider usable energy range for laser light.

[0150] Before irradiating with laser light, the surface of the semiconductor film 204 is planarized by dry etching. In this case, dry etching causes damage such as crystal defects near the surface of the semiconductor film 204. This can sometimes occur. However, the irradiation of the above-mentioned laser light can cause damage caused by dry etching. It is also possible to repair damage.

[0151] Next, after irradiating with laser light, the surface of the semiconductor film 205 may be etched. When etching the surface of the semiconductor film 205 after irradiation, it is not always necessary to irradiate it with laser light. It is not necessary to etch the surface of the semiconductor film 204 beforehand. Also, when irradiating with laser light... If the surface of the semiconductor film 204 was etched previously, it does not necessarily mean that the semiconductor will etch after irradiation with laser light. It is not necessary to etch the surface of film 205. Alternatively, after irradiation with laser light, The surface of the semiconductor film 205 may be etched before injection.

[0152] The above etching process is used to create a semiconductor film with a thickness that is optimal for the semiconductor device that will be formed later. Not only can 205 be made into a thin film, but the surface of the semiconductor film 205 can also be planarized.

[0153] After irradiating with laser light, the semiconductor film 205 is subjected to a heat treatment at a temperature of 500°C to 650°C. This is preferable. This heat treatment restores the semiconductor film 2 that was not restored by laser irradiation. This can eliminate defects in 05 and alleviate the strain on the semiconductor film 205. RTA (Rapid Thermal Anneal) equipment, resistance heating furnace, microwave A heating device can be used. The RTA device includes GRTA (Gas Rapid Thunder). thermal annealing) equipment, LRTA (Lamp Rapid Thermal) An Anneal device can be used. For example, if a resistance heating furnace is used, 600 It is best to heat it at ℃ for 4 hours.

[0154] Next, as shown in Figure 9(A), the semiconductor film 205 is partially etched, Island-like semiconductor films 206 and semiconductor film 207 are formed from the body membrane 205. Further etching removes areas where the bonding strength is insufficient at the edges of the semiconductor film 205. The region can be removed. In this embodiment, one semiconductor film 205 is etched. By doing so, semiconductor films 206 and 207 are formed, but the semiconductor film that is formed The number is not limited to this.

[0155] Furthermore, the bond substrate 200, after the semiconductor film 205 has been separated, has its surface planarized. Then, the semiconductor film 205 can be separated again.

[0156] Specifically, the insulating film 201 remaining mainly at the edges of the bond substrate 200 is etched, etc. Further removal. The insulating film 201 is formed of silicon oxide, silicon oxide nitride, and silicon oxide nitride. In some cases, wet etching using hydrofluoric acid can be used.

[0157] Next, the protrusions formed at the edge of the bond substrate 200 by the separation of the semiconductor film 205, and hydrogen Remove any excess or remaining brittle layer. For etching the bond substrate 200, It is preferable to use wet etching, and the etching solution should contain tetramethylammonium hydroxide. Monium (tetramethylammonium hydroxide, abbreviation: TM) AH) solution can be used.

[0158] Next, the surface of the bond substrate 200 is polished. Polishing can be done using CMP. To smooth the surface of the substrate 200, it is desirable to polish it to a thickness of approximately 1 μm to 10 μm. After polishing, polishing particles remain on the surface of the bond substrate 200, so RCA using hydrofluoric acid, etc. Perform cleaning.

[0159] By reusing bond substrate 200, the material cost of semiconductor substrates can be reduced. .

[0160] Semiconductor films 206 and 207 contain boron and aluminum to control the threshold voltage. Alternatively, p-type impurities such as gallium, or n-type impurities such as phosphorus or arsenic, may be added. The addition of impurities to control the threshold voltage is performed on the semiconductor film before patterning. Alternatively, you can perform the same procedure on the semiconductor film 206 and semiconductor film 207 formed after patterning. It is also permissible to add impurities to the bond substrate to control the threshold voltage. Alternatively, adding impurities to the bond substrate to roughly adjust the threshold voltage is also a good option. After doing so, in order to fine-tune the threshold voltage, the semiconductor film before patterning is subjected to... Alternatively, this can also be done on semiconductor films 206 and 207 formed by patterning. You can do that too.

[0161] Next, as shown in Figure 9(B), a gate insulating film is placed over semiconductor film 206 and semiconductor film 207. A border film 208 is formed. The gate insulating film 208 is semi-permeable by high-density plasma treatment. The conductive film 206 and the semiconductor film 207 can be formed by oxidizing or nitriding the surfaces of the two films. High-density plasma processing involves noble gases such as He, Ar, Kr, and Xe, along with oxygen and nitrogen oxides. This is done using a mixed gas such as ammonia, nitrogen, and hydrogen. In this case, the plasma excitation is performed using By introducing microwaves, it is possible to generate a high-density plasma at a low electron temperature. In such high-density plasmas, oxygen radicals (including OH radicals) are generated. Acids (or nitrogen radicals, which may include NH radicals) can damage the surface of a semiconductor film. By nitriding or otherwise, an insulating film of 1-20 nm, preferably 5-10 nm, is produced in the semiconductor. It is formed in contact with the film. This 5-10 nm insulating film is used as the gate insulating film 208. Yes. For example, diluting nitrous oxide (N2O) with Ar to a ratio of 1 to 3 times (flow rate ratio) results in 10 to 3 Applying microwave power of 3-5 kW (2.45 GHz) at a pressure of 0 Pa to the semiconductor film 2 The surfaces of 06 and semiconductor film 207 are oxidized or nitrided. This process results in a range of 1 nm to 10 nm. An insulating film of m (preferably 2 nm to 6 nm) is formed. Furthermore, nitrous oxide (N2O) and s By introducing a ran (SiH4) and applying a 3-5kW microwave (2.4) at a pressure of 10-30 Pa, Applying 5GHz power, a silicon oxidizride film is formed by vapor phase growth to create a gate insulating film. It forms. By combining solid-phase reactions and reactions by vapor phase growth, the interface state density is It is possible to form a gate insulating film with low dielectric strength and excellent dielectric breakdown voltage.

[0162] The oxidation or nitridation of semiconductor films by the high-density plasma treatment described above proceeds as a solid-phase reaction, The interface state density between the insulating film 208 and the semiconductor films 206 and 207 is made extremely low. It is possible to perform high-density plasma treatment on semiconductor films 206 and 207. Direct oxidation or nitriding can suppress variations in the thickness of the insulating film formed. Furthermore, if the semiconductor film has crystalline properties, high-density plasma treatment can be used to treat the surface of the semiconductor film. By inducing oxidation through solid-phase reactions, the rapid oxidation that occurs only at grain boundaries is suppressed. It is possible to form a gate insulating film with good uniformity and low interfacial state density. The insulating film formed by the lazma process is incorporated into part or all of the gate insulating film. Transistors can suppress variations in their characteristics.

[0163] Alternatively, the gate insulating film 208 can be created by thermal oxidation of semiconductor films 206 and 207. It may also be formed using methods such as plasma CVD or sputtering. Silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide A gate insulating film 20 is formed by applying a film containing luminescent material or tantalum oxide, either as a single layer or in a stacked manner. You may also form an 8.

[0164] Next, as shown in Figure 9(C), after forming a conductive film on the gate insulating film 208, the conductive film By processing (patterning) it into a predetermined shape, the semiconductor film 206 and semiconductor film 207 are processed on top of each other. An electrode 209 is formed on the side. The conductive film is formed using methods such as CVD and sputtering. This can be done. The conductive film is made of tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum. Butene (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb) The above can be used. Alternatively, an alloy with the above metal as the main component may be used, or the above metal Compounds containing the above may be used. Alternatively, impurity elements such as phosphorus that impart conductivity to the semiconductor film may be used. It may also be formed using a semiconductor such as polycrystalline silicon that has been doped with [a specific substance].

[0165] As a combination of two conductive films, the first layer is tantalum nitride or tantalum, and the second layer is tantalum Tungsten can be used. In addition to the above examples, tungsten nitride and tungsten, nitride can be used. Examples include molybdenum oxide and molybdenum, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so after forming a two-layer conductive film... During the process, a heat treatment can be performed for the purpose of thermal activation. Furthermore, a two-layer conductive film is formed. One example of such a combination is silicon doped with an impurity that imparts n-type properties, and nickel. Silicides, silicon doped with impurities that impart n-type properties, and tungsten silicides, etc. It can also be used.

[0166] Furthermore, in this embodiment, the electrode 209 is formed from a single-layer conductive film, but this embodiment The configuration is not limited to this. The electrode 209 may be formed from multiple stacked conductive films. In the case of a three-layer structure with three conductive films stacked on top of each other, the layers are molybdenum film, aluminum film and molybdenum film. A layered film structure is recommended.

[0167] Furthermore, when forming electrode 209, a droplet ejection method is used to selectively form electrode 2 without using a mask. You may also form 09.

[0168] The droplet dispensing method involves dispensing or ejecting droplets containing a predetermined composition from a pore. This refers to methods for forming patterns, and inkjet printing is one example of this category.

[0169] Furthermore, after forming a conductive film on electrode 209, ICP (Inductively Coupled Plasma (Inductively coupled plasma) etching method is used, etching conditions (coil type) The amount of power applied to the electrode layer, the amount of power applied to the electrode layer on the substrate side, the electrode temperature on the substrate side, etc. By adjusting the appropriate settings, etching can be performed to obtain the desired tapered shape. Yes, it is possible. Furthermore, the tapered shape can be controlled by the shape of the mask, including its angle. The etching gases used include chlorine, boron chloride, silicon chloride, or carbon tetrachloride. Suitable chlorine-based gases, fluorine-based gases such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen. It can be used as appropriate.

[0170] Next, as shown in Figure 9(D), impurity elements that impart a single conductivity type are used with electrode 209 as a mask. n is added to semiconductor film 206 and semiconductor film 207. In this embodiment, n is added to semiconductor film 206. An impurity element that imparts a type (e.g., phosphorus or arsenic) is added to the semiconductor film 207 to impart a p-type. An impurity element (e.g., boron) is added. Note that the impurity element that imparts the p-type is added to the semiconductor film 2 When adding to 07, the semiconductor film 206 to which the n-type impurity is added is covered with a mask or the like, and the p-type is added. The addition of impurity elements to be added is selective. Conversely, the impurity elements that contribute to the n-type When adding the element to the semiconductor film 206, the semiconductor film 207 to which the p-type impurity is added is a mask, etc. Cover with a material to allow for the selective addition of impurity elements that confer the n-type. Alternatively, first Impurities that impart either p-type or n-type properties to semiconductor films 206 and 207 After adding the element, a higher concentration of either p-type or n-type particles is selectively added to only one of the semiconductor films. It is also possible to add one of the impurity elements that impart the other of the above impurities. The addition of impurities creates an impurity region 210 in semiconductor film 206 and an impurity region 211 in semiconductor film 207. A formation is created.

[0171] Next, as shown in Figure 10(A), a sidewall 212 is formed on the side surface of the electrode 209. The sidewall 212 is newly made to cover, for example, the gate insulating film 208 and the electrode 209. Furthermore, an insulating film is formed, and a newly formed film is created by anisotropic etching mainly in the vertical direction. The insulating film can be formed by partially etching the above anisotropic etching. The newly formed insulating film is partially etched by the process, and a steatosis occurs on the side surface of electrode 209. The id wall 212 is formed. Furthermore, the gate insulating film 20 is formed by the above anisotropic etching. 8 may also be partially etched. The insulating film for forming the sidewall 212 is By methods such as LPCVD, plasma CVD, and sputtering, silicon films, silicon oxide films, and acid Silicon nitride films, silicon oxide nitride films, and films containing organic materials such as organic resins are used in single-layer or multi-layer configurations. It can be formed by plasma. In this embodiment, a silicon oxide film with a thickness of 100 nm is plasma It is formed by the CVD method. A mixture of CHF3 and helium is used as the etching gas. A can be used. However, the process of forming the sidewall 212 is not limited to these. It is not something that should be done.

[0172] Next, as shown in Figure 10(B), the electrode 209 and the sidewall 212 are used as a mask. Furthermore, impurity elements that impart a single conductivity type to semiconductor films 206 and 207 are added. Semiconductor film 206 and semiconductor film 207 each contain the same impurity element as added in the previous step. The p-type impurity elements are added at a higher concentration. When adding to film 207, the semiconductor film 206 to which n-type impurities are added is covered with a mask or the like, p The addition of impurity elements that confer a specific type is made selectively. Conversely, impurities that confer the n-type are added. When adding a physical element to the semiconductor film 206, the semiconductor film 207 to which the p-type impurity is added is mass The material is covered with a material such as a sieve to allow for the selective addition of impurity elements that impart the n-type.

[0173] The addition of the above impurity elements results in a pair of high-concentration impurity regions 213 and a single high-concentration impurity region 213 in the semiconductor film 206. A pair of low-concentration impurity regions 214 and a channel-forming region 215 are formed. By adding pure elements, the semiconductor film 207 has a pair of high-concentration impurity regions 216 and a pair of low-concentration impurity regions. A high-concentration impurity region 217 and a channel-forming region 218 are formed. 13. The high-concentration impurity region 216 functions as either a source region or a drain region, while the low-concentration impurity region functions as a source region or drain region. The impurity region 214 and the low concentration impurity region 217 are LDD (Lightly Doped Dra). It functions as an in) area. Note that the LDD area does not necessarily need to be provided; it functions as a source area. Alternatively, only an impurity region that functions as a drain region may be formed. Or, the source region and The LDD region may be formed on only one side of the drain region.

[0174] Sidewalls 212 formed on semiconductor film 207 and formed on semiconductor film 206 The sidewall 212 is formed so that its width is the same in the direction in which the carrier moves. It is also possible to form them with different widths. Semiconductor film 20 that will become a p-type transistor The width of the sidewall 212 on 7 is the side of the semiconductor film 206 which will become an n-type transistor. It is better to make it longer than the width of Wall 212. This is because in a p-type transistor, Boron injected to form the drain region and short channel This is because it easily induces the effect. In a p-type transistor, the width of the sidewall 212 By making the circuit longer, it becomes possible to add high concentrations of boron to both the source and drain regions. This makes it possible to reduce the resistance of the source and drain regions.

[0175] Next, in order to further reduce the resistance of the source region and drain region, the semiconductor film 206, semiconductor A silicide layer may be formed by silicideizing membrane 207. By bringing a metal into contact with the semiconductor film and performing heat treatment, GRTA method, LRTA method, etc., the semiconductor film is subjected to This is carried out by reacting silicon with a metal. As the silicide layer, cobalt silicide or Nickel silicide can be used. This applies when the thickness of semiconductor film 206 and semiconductor film 207 is thin. Even if the silicide reaction proceeds to the bottom of semiconductor films 206 and 207 in this region Good. As metal materials used in silicide formation, titanium (Ti), nickel (Ni), and Lungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), H f (hafnium), tantalum (Ta), vanadium (V), neodymium (Nd), chromium ( Materials such as Cr, platinum (Pt), and palladium (Pd) can be used. Furthermore, laser irradiation... Silicides may also be formed by light irradiation, such as from a lamp.

[0176] Through the series of steps described above, an n-channel transistor 220 and a p-channel transistor A sta 221 is formed.

[0177] Once the process shown in Figure 10(B) is completed, then transistor 220, transistor 2 A transistor using an oxide semiconductor is fabricated on 21.

[0178] First, as shown in Figure 11(A), cover transistors 220 and 221 An insulating film 230 is formed on it. By providing the insulating film 230, the electrode 209 during the heat treatment This prevents the surface from oxidizing. Specifically, the insulating film 230 is silicon nitride, nitride Silicon oxide, silicon oxide nitride, aluminum nitride, aluminum oxide, silicon oxide, etc. are used. This is desirable. In this embodiment, a silicon oxide nitride film with a thickness of about 50 nm is used as the insulating film 230 It is used as such.

[0179] Next, as shown in Figure 11(B), cover transistors 220 and 221 Then, insulating film 231 and insulating film 232 are formed on insulating film 230. 32 uses a material that can withstand the heat treatment temperature in the later manufacturing process. Specifically, insulation The film 231 and insulating film 232 are, for example, silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride Inorganic insulating films such as aluminum nitride and aluminum nitride oxide can be used.

[0180] In this embodiment, insulating film 231 and insulating film 232 are laminated on insulating film 230. However, the insulating film formed on the insulating film 230 may be a single-layer insulating film, or it may be three or more layers of insulating film. The film can be layered.

[0181] The insulating film 232 may have its surface planarized by methods such as CMP.

[0182] Next, as shown in Figure 11(C), after forming the conductive film on the insulating film 232, etching is performed. This removes unnecessary parts to form the wiring 233 and gate electrode 234. The gate electrode 234 is etched so that a tapered shape is formed at its end.

[0183] The materials used for the above conductive film include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Metallic materials such as zinc and scandium, alloy materials mainly composed of these metallic materials, or The metal nitride can be used in a single layer or in a multilayer structure. If it can withstand the heat treatment temperature, aluminum and copper can be used as the above metal material. It is also possible to do so.

[0184] For example, as a conductive film having a two-layer laminated structure, molybdenum is laminated on aluminum. A two-layer laminated structure, or a two-layer structure in which molybdenum is laminated on a copper layer, or a nitride on copper. A two-layer structure consisting of laminated tan or tantalum nitride, or a two-layer structure consisting of laminated titanium nitride and molybdenum. A layered structure is preferable. A three-layer laminated structure can be aluminum, aluminum and Silicon alloys, aluminum and titanium alloys, or aluminum and neodymium alloys are used. The interlayer consists of tungsten, tungsten nitride, titanium nitride, or titanium stacked as upper and lower layers. A layered structure is preferable.

[0185] Furthermore, the aperture ratio can be improved by using a light-transmitting oxide conductive film on some electrodes and wiring. It is also possible. For example, oxide conductive films include indium oxide, indium oxide tin oxide alloy, and acid Indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride Alternatively, zinc gallium oxide or the like can be used.

[0186] The film thickness of the wiring 233 and gate electrode 234 is 10 nm to 400 nm, preferably 100 nm. The wavelength is set to m~200nm. In this embodiment, a sputtering method using a tungsten target is used. After forming a conductive film for a 100 nm gate electrode by this method, the conductive film is etched by this method. By processing (patterning) it into the desired shape, the wiring 233 and gate electrode 234 are formed. ru.

[0187] Next, as shown in Figure 11(D), a gate insulating film is placed on the wiring 233 and the gate electrode 234. Forming 240. The gate insulating film 240 is formed by plasma CVD or sputtering, etc. Using silicon oxide film, silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, hafnium oxide, Aluminum oxide or tantalum oxide can be formed as a single layer or in layers. The insulating film 240 should preferably contain as few impurities as possible, such as water, hydrogen, and oxygen. Insulating film using a highly barrier material, silicon oxide film with a low nitrogen content, and oxidative nitridation. A gate insulating film 240 having a structure in which an insulating film such as a silicon film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxide nitride films have barrier properties and oxidation It is formed between semiconductor films. Examples of highly barrier insulating films include silicon nitride films and silicon nitride films. Examples include silicon films, aluminum nitride films, or aluminum nitride oxide films. By using an insulating film with properties, moisture, hydrogen, and other impurities in the atmosphere, or the substrate, can be filtered out. Impurities such as alkali metals and heavy metals contained within the film are present in the oxide semiconductor film and gate insulating film 2. To prevent penetration into the 40, or into the interface between the oxide semiconductor film and other insulating films, and its vicinity. This can be done. In addition, silicon oxide films with a low nitrogen ratio that come into contact with oxide semiconductor films, and oxidative nitridation can be made. By forming an insulating film such as a silicon film, the insulating film using a highly barrier material directly penetrates the oxide. This prevents contact with the semiconductor film.

[0188] In this embodiment, a silicon nitride film with a thickness of 50 nm formed by sputtering is applied to the film. A gate insulating film 24 has a structure in which silicon oxide films with a thickness of 100 nm formed by stacking. Forms 0.

[0189] Next, an oxide semiconductor film is formed on the gate insulating film 240, and then the desired film is formed by etching or the like. By processing the oxide semiconductor film into the above shape, an island-shaped structure is formed at a position overlapping with the gate electrode 234. An oxide semiconductor film 241 is formed. The oxide semiconductor film targets an oxide semiconductor. The film is formed by sputtering using a noble gas (e.g., argon). Spa It can be formed by the tta method.

[0190] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced to form plasma Reverse sputtering is performed to generate sputter, removing dust and dirt adhering to the surface of the gate insulating film 240. It is preferable to remove the staining material. Reverse sputtering is a method in which voltage is not applied to the target side. Under an argon atmosphere, a voltage is applied to the substrate using an RF power supply to cause Ar ions to collide with the substrate. This is a method of modifying the surface. Note that nitrogen, helium, etc., can be used instead of an argon atmosphere. It is acceptable to do so. Alternatively, the procedure can be carried out in an argon atmosphere with added oxygen, nitrous oxide, etc. Alternatively, the procedure may be carried out in an atmosphere containing argon, chlorine, carbon tetrafluoride, etc.

[0191] The oxide semiconductor film used to form the channel formation region has the semiconductor properties described above. You can use an oxide material that possesses this property.

[0192] The thickness of the oxide semiconductor film is 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, an oxide semiconductor target containing In, Ga, and Zn is used. (The molar ratio is In2O3:Ga2O3:ZnO=1:1:1, In2O3:Ga2O3: Using ZnO (1:1:2), the distance between the substrate and the target is 100 mm, and the pressure is 0. The film is deposited under a pressure of 6 Pa, a DC power supply of 0.5 kW, and an oxygen atmosphere (oxygen flow rate ratio of 100%). Furthermore, using a pulsed DC power supply can reduce dust and ensure a more uniform film thickness distribution. Therefore, it is preferable. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O based acid Using a synthetic semiconductor target, a 30nm film thickness of In-Ga-Zn-O is produced by sputtering. A non-single crystal film is deposited.

[0193] Furthermore, by forming an oxide semiconductor film without exposure to the atmosphere after plasma treatment, gate isolation is achieved. This prevents dust and moisture from adhering to the interface between the edge film 240 and the oxide semiconductor film. Using a pulsed direct current (DC) power supply is preferable because it reduces dust and results in a more uniform film thickness distribution. It seems so.

[0194] Furthermore, the relative density of the oxide semiconductor target is 80% or more, preferably 95% or more, and Preferably, it should be 99.9% or higher. When using a target with a high relative density, The impurity concentration in the formed oxide semiconductor film can be reduced, improving electrical properties or reliability. High-performance thin-film transistors can be obtained.

[0195] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0196] Furthermore, a sputtering apparatus that uses the magnetron sputtering method, which has a magnetic mechanism inside the chamber. Alternatively, ECR sputtering uses plasma generated with microwaves instead of glow discharge. There are sputtering machines that use this method.

[0197] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas components are deposited during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the circuit board.

[0198] Furthermore, during film deposition by sputtering, the substrate temperature is increased to between 100°C and 700°C using light or a heater. Heating may be performed. Heating during film formation allows for the repair of sputtering damage simultaneously with film formation. ru.

[0199] Furthermore, before depositing the oxide semiconductor film, the inner wall of the sputtering apparatus, the target surface and the target It is advisable to preheat the material to remove any remaining moisture or hydrogen. The preheating process involves heating the deposition chamber to 200°C to 600°C under reduced pressure. Methods include the law and the repeated introduction and exhaust of nitrogen or inert gas while heating. After processing is complete, the substrate or sputtering equipment is cooled and then the oxide semiconductor is discharged without being exposed to the atmosphere. A body membrane is formed. In this case, it is preferable to use oil or grease as the target coolant instead of water. While some effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is recommended to do so while heating is involved. That would be even better.

[0200] Furthermore, before, during, or after deposition of oxide semiconductor films, inside the sputtering apparatus It is preferable to remove any remaining moisture and other substances inside using a cryopump.

[0201] The formation of the island-shaped oxide semiconductor film 241 is performed, for example, by using a solution of phosphoric acid, acetic acid, and nitric acid. This can be done by etching. The island-shaped oxide semiconductor film 241 is the gate electrode. It is formed so as to overlap with 234. Also, for etching oxide semiconductor films, citric acid and citric acid are used. Organic acids such as oxalic acid can be used as etching agents. In this embodiment, ITO Unwanted parts are removed by wet etching using 07N (manufactured by Kanto Chemical Co., Ltd.) to form island-like structures. An oxide semiconductor film 241 is formed. The etching here is wet etching. Dry etching may also be used, but this method is not limited to it.

[0202] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0203] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF4)) 6) Nitrogen fluoride (NF3), trifluoromethane (CHF3), etc., hydrogen bromide (HBr ), oxygen (O2), and noble gases such as helium (He) and argon (Ar) are added to these gases. Added gases, etc., can be used.

[0204] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0205] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor film can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0206] To process the material into the desired shape, etching conditions (etching solution, etching) are adjusted according to the material. Adjust the cooking time, temperature, etc. as appropriate.

[0207] Next, under a reduced pressure atmosphere, under an inert gas atmosphere such as nitrogen or a noble gas, under an oxygen gas atmosphere, This uses ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter) The moisture content when measured is 20 ppm or less (equivalent to a dew point of -55°C), preferably 1 ppm. The oxide semiconductor film 241 is then added to the atmosphere (preferably air) at a pressure of 10 ppb or less. Heat treatment may be applied. By applying heat treatment to the oxide semiconductor film 241, as shown in Figure 12(A) As shown, an oxide semiconductor film 242 with reduced content of impurities such as hydrogen and water is formed. Specifically, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.). In this case, heat at a temperature between 300°C and 750°C (or below the strain point of the glass substrate) for 1 minute. For a period of 10 minutes or less, preferably at 650°C, and for a period of 3 minutes to 6 minutes or less, RTA (Ra This can be done using pid (thermal annealing) processing. Using the RTA method, Because dehydration or dehydrogenation can be performed in a short time, processing can be carried out even at temperatures exceeding the strain point of the glass substrate. This can be done. Note that the above heat treatment is performed at the timing after the formation of the island-shaped oxide semiconductor film 241. This can be performed not only on the oxide semiconductor film before etching, but also on the oxide semiconductor film before etching. The heat treatment may be performed multiple times after the formation of the island-shaped oxide semiconductor film 241.

[0208] In this embodiment, under a nitrogen atmosphere, the substrate temperature reaches 600°C. The product is subjected to a heat treatment for 6 minutes in this state. The heat treatment is performed using an electric furnace, and the heated gas The GRTA (Gas Rapid Thermal Anneal) method or lamp used Light-based methods such as LRTA (Lamp Rapid Thermal Anneal) Instantaneous heating methods can be used. For example, when performing heat treatment using an electric furnace, The heating characteristic is 0.1°C / min to 20°C / min, and the cooling characteristic is 0.1°C / min or more. It is preferable to keep the temperature at 15°C / min or lower.

[0209] In addition, during the heat treatment, water is added to nitrogen or a noble gas such as helium, neon, or argon. It is preferable that it does not contain hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, The purity of noble gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0210] Next, the insulating film 230, insulating film 231, insulating film 232, and gate insulating film 240 are partially etched. By ching, the high-concentration impurity region 213 of transistor 220 and the transistor The high-concentration impurity region 216 of TA 221 and the contact hole that reaches the wiring 233 form This is achieved. Then, on the oxide semiconductor film 242, a source electrode or drain electrode is used. After forming a conductive film using sputtering or vacuum deposition, the conductive film is then processed by etching or other methods. By turning, as shown in Figure 12(B), the source electrode or drain electrode can be used. This forms conductive films 245 to 249 that function as conductive films.

[0211] Specifically, conductive films 245 and 246 provide a pair of high-concentration materials for the transistor 220. Each is connected to the pure material region 213. Furthermore, the conductive film 246 is also connected to the wiring 233. They are connected. Conductive film 247 and conductive film 248 are connected to a pair of high-frequency components of transistor 221. Each is connected to the concentration impurity region 216. Furthermore, the conductive film 248 is connected to the conductive film 2 It is connected to the oxide semiconductor film 242, along with 49.

[0212] Examples of conductive films 245 to 249 include aluminum, chromium, tantalum, and titanium. Manganese, magnesium, molybdenum, tungsten, zirconium, beryllium, Using elements selected from lium, or alloys containing one or more of the above elements as components. It is possible to do so. Furthermore, if heat treatment is performed after the formation of the conductive film, the following measures are necessary for this heat treatment. It is preferable to give the conductive film heat resistance. Aluminum alone has poor heat resistance, Because of issues such as susceptibility to corrosion, if heat treatment is performed after the formation of the conductive film, heat-resistant conductive film is required. It forms a conductive film when combined with electrical materials. Heat-resistant conductive material when combined with aluminum. The materials include titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and sulfite. Elements selected from zinc, or alloys containing one or more of the above elements as components, Nitrides containing the above elements as components are preferred.

[0213] The thickness of conductive films 245 to 249 is 10 nm to 400 nm, preferably 100 nm to The nm is set to 200 nm. In this embodiment, a titanium film, a titanium nitride film, and an axle are formed by sputtering. Conductive material for source and drain electrodes obtained by sequentially stacking luminium and titanium films. By processing (patterning) the film into the desired shape by etching, conductive film 245~ A conductive film 249 is formed.

[0214] For etching to form conductive films 245 to 249, wet etching or Dry etching can be used. Using dry etching, conductive film 245~ When forming the electrical film 249, a gas containing chlorine (Cl2), boron chloride (BCl3), etc. is used. It would be good to have it. In this etching process, some of the exposed areas of the oxide semiconductor film 241 are also etched. This is chapping to form island-shaped oxide semiconductor films 250. Thus, conductive films 248 and 249 In the region located between these points, the oxide semiconductor film 250 becomes thinner.

[0215] As shown in Figure 12(C), after forming conductive films 245 to 249, conductive film 245 An insulating film 251 is formed to cover the conductive film 249 and the oxide semiconductor film 250. 251 should preferably contain as few impurities as possible, such as moisture, hydrogen, and oxygen, and should be a single-layer insulating material. It may be a film, or it may be composed of multiple stacked insulating films. The insulating film 25 For 1, it is desirable to use a material with high barrier properties. For example, a highly barrier insulating film is used. so, silicon nitride film, silicon oxide nitride film, aluminum nitride film, or aluminum oxide nitride film The above can be used. When using multiple stacked insulating films, the above high barrier properties can be used. Insulating films such as silicon oxide films and silicon oxidnitride films, which have a lower nitrogen ratio than insulating films, are used as insulating films. It is formed on the side closer to the conductive film 250. Then, an insulating film with a low nitrogen ratio is sandwiched in between to create a conductive film. A barrier-type insulating film is placed so as to overlap with films 245 to conductive film 249 and oxide semiconductor film 250. A border film is formed. By using an insulating film with barrier properties, within the oxide semiconductor film 250, Within the insulating film 240, or at and near the interface between the oxide semiconductor film 250 and other insulating films, It can prevent impurities such as moisture or hydrogen from entering. Also, oxide semiconductor film Insulating films such as silicon oxide films and silicon oxide-nitride films with a low nitrogen ratio are formed so as to be in contact with 250. This allows the insulating film made of a highly barrier material to come into direct contact with the oxide semiconductor film 250. This can prevent it.

[0216] In this embodiment, on a silicon oxide film with a thickness of 200 nm formed by sputtering, An insulating film 251 having a structure in which silicon nitride films with a thickness of 100 nm formed by the method are stacked. Formed. The substrate temperature during film formation should be between room temperature and 300°C, and in this embodiment... Set the temperature to 100°C.

[0217] The exposed region of the oxide semiconductor film 250 provided between the conductive film 248 and the conductive film 249, and the insulating By being provided in contact with the silicon oxide constituting the film 251, the insulating film 251 is in contact with the silicon oxide The oxide semiconductor film 250 has increased resistance in certain regions, and the region has increased resistance, forming an oxide channel. A monosemiconductor film 250 can be formed.

[0218] Next, after forming the insulating film 251, a heat treatment may be performed. The heat treatment is performed in an atmospheric environment. , or under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), The process should be carried out at a temperature between 200°C and 400°C, for example, between 250°C and 350°C. Heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Alternatively, the oxide semiconductor film 241 is subjected to Similar to the heat treatment performed earlier, a high-temperature, short-duration RTA treatment may also be performed. When this is done, the oxide semiconductor film 250 is heated while in contact with the silicon oxide constituting the insulating film 251. This will result in increasing the resistance of the oxide semiconductor film 250, thereby improving the electrical characteristics of the transistor. This process improves performance and reduces variations in electrical properties. After the formation of 251, there are no particular limitations, and other processes such as heat treatment during resin film formation, By combining this process with a heat treatment to reduce the resistance of the transparent conductive film, the number of steps can be increased. It is possible.

[0219] Through the above process, a transistor 260 is produced using an oxide semiconductor film 250 as the active layer. It can be manufactured.

[0220] Next, after forming a conductive film on the insulating film 251, the conductive film is patterned, and acid A back gate electrode may be formed at a position overlapping with the semiconductor film 250. The electrodes use the same material and structure as gate electrode 234 or conductive films 245 to 249. It is possible to form it this way.

[0221] The film thickness of the back gate electrode is 10 nm to 400 nm, preferably 100 nm to 200 nm. For example, a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are laminated. After forming the mask, a resist mask is formed by photolithography, and then etched. By removing unnecessary parts and processing (patterning) the conductive film into the desired shape, You just need to form a gate electrode.

[0222] When forming a back gate electrode, an insulating film is formed to cover the back gate electrode. This is desirable. The insulating film is protected from moisture, hydrogen, oxygen, etc. in the atmosphere, which affects the characteristics of transistor 260. It is desirable to use high-barrier materials that can prevent the effects from being felt. For example For example, as insulating films with high barrier properties, silicon nitride film, silicon oxide nitride film, aluminum nitride film, Alternatively, aluminum nitride oxide films, etc., can be processed by plasma CVD or sputtering. It can be formed as a single layer or by lamination. To obtain a barrier effect, the insulating film is For example, it is preferable to form it with a film thickness of 15 nm to 400 nm.

[0223] Furthermore, the back gate electrode may be formed to cover the entire oxide semiconductor film 250. However, if it overlaps with at least a part of the channel formation region of the oxide semiconductor film 250 That's fine.

[0224] The back gate electrode may be in an electrically insulated floating state, or It is also possible that the position is given. In the latter case, the back gate electrode has gate electrode 2 It may be given the same potential as 34, or a fixed potential such as ground may be given. It is also acceptable to do so. By controlling the height of the potential applied to the back gate electrode, transistor 2 It can control threshold voltages of 60.

[0225] Furthermore, by partially etching the insulating film 251, the conductive films 245 to 249 After forming a contact hole that reaches the offset, a conductive film is formed on the insulating film 251, and the conductive film By patterning the film, wiring connected to one of the conductive films 245 to 249 is created. It is also possible to form it.

[0226] In this embodiment, after forming a transistor using silicon, an oxide semiconductor is used. Although the present invention involves stacking transistors using films, the present invention is not limited to this configuration. A transistor using [a specific material] and a transistor using an oxide semiconductor film are placed on the same insulating surface. Alternatively, you can form it, or you can form a transistor using an oxide semiconductor film and then use silicon. It is also acceptable to stack transistors. However, transistors using oxide semiconductor films may be formed When stacking transistors using silicon after this process is completed, the silicon is microcrystalline silicon Use either silicon or polycrystalline silicon.

[0227] This embodiment can be implemented in combination with the above embodiment.

[0228] (Embodiment 3) In this embodiment, the structure of the transistor using an oxide semiconductor film is different from that of Embodiment 2. Let's explain the configuration of a transistor.

[0229] The semiconductor device shown in Figure 13(A) uses n-crystalline silicon, similar to Embodiment 2. It has a channel-type transistor 220 and a p-channel-type transistor 221. In Figure 13(A), an n-channel transistor 220 and a p-channel transistor 2 A bottom-gate type transistor with a channel protection structure using an oxide semiconductor film is placed on 21. 310 is formed.

[0230] The transistor 310 has a gate electrode 311 formed on the insulating film 232, and a gate electrode 3 The gate insulating film 312 on 11 and the gate electrode 311 overlapping on the gate insulating film 312 The oxide semiconductor film 313 and the island-shaped oxide at a position overlapping with the gate electrode 311 A channel protection film 314 formed on the semiconductor film 313, and formed on the oxide semiconductor film 313 It has conductive films 315 and 316. Furthermore, transistor 310 is oxidized An insulating film 317 formed on the semiconductor film 313 may also be included as a component.

[0231] By providing the channel protection film 314, the channel formation region of the oxide semiconductor film 313 is protected. Damage to the part in subsequent processes (plasma and etching during etching) This prevents film thinning caused by grafting agents, etc., thus improving transistor reliability. It is possible.

[0232] The channel protective film 314 contains an inorganic material containing oxygen (silicon oxide, silicon oxide nitride, silicon oxide nitride). Aluminum oxide, aluminum oxide, or aluminum nitride (such as charcoal) can be used. The Nell protective film 314 is produced by vapor phase growth methods such as plasma CVD and thermal CVD, as well as sputtering. It can be formed using the method. The channel protective film 314 is shaped by etching after film formation. The shape is processed. Here, a silicon oxide film is formed by sputtering and then photolithography is performed. A channel protective film 314 is formed by etching using a mask.

[0233] Furthermore, oxygen is brought into contact with the island-shaped oxide semiconductor film 313 by sputtering or PCVD. When a channel protection film 314, which is an insulating film containing the above, is formed, the island-shaped oxide semiconductor film 313 In this region, at least the area in contact with the channel protective film 314 becomes highly resistive, and the highly resistive oxide semiconductor The body region is formed. Due to the formation of the channel protective film 314, the oxide semiconductor film 313 becomes the channel A high-resistivity oxide semiconductor region can be provided near the interface with the protective film 314.

[0234] Furthermore, transistor 310 has a back gate electrode on the insulating film 317. This is also good. The back gate electrode should overlap with the channel formation region of the oxide semiconductor film 313. Forms. The back gate electrode is in an electrically insulated floating state. It's fine, and it's also fine if an electric potential is applied. In the latter case, the back gate electrode has a The potential may be the same as that of electrode 311, or it may be a fixed potential such as ground. It may also be given. By controlling the height of the potential applied to the back gate electrode, The threshold voltage of the inverter 310 can be controlled.

[0235] The semiconductor device shown in Figure 13(B) is similar to Embodiment 2 in that it uses n-crystalline silicon. It has a channel-type transistor 220 and a p-channel-type transistor 221. In Figure 13(B), an n-channel transistor 220 and a p-channel transistor 2 A bottom-contact type transistor 320 made of an oxide semiconductor film is formed on 21. It is.

[0236] The transistor 320 has a gate electrode 321 formed on the insulating film 232, and a gate electrode 3 21 The gate insulating film 322, the conductive film 323 and conductive film 324 on the gate insulating film 322 It has an oxide semiconductor film 325 that overlaps with the gate electrode 321. Furthermore, The sta 320 includes an insulating film 326 formed on the oxide semiconductor film 325 as one of its components. You can do that.

[0237] Furthermore, in the case of the bottom-contact type transistor 320, the conductive film 323 and conductive film 324 The film thickness is designed to prevent the oxide semiconductor film 325 that is formed later from breaking down into segments. It is desirable to make it thinner than the bottom-gate type shown in Form 2. Specifically, 10nm~ The wavelength is 200 nm, preferably 50 nm to 75 nm.

[0238] Furthermore, transistor 320 has a back gate electrode on the insulating film 326. This is also good. The back gate electrode should overlap with the channel formation region of the oxide semiconductor film 325. Forms. The back gate electrode is in an electrically insulated floating state. It's fine, and it's also fine if an electric potential is applied. In the latter case, the back gate electrode has a The potential may be the same as that of electrode 321, or it may be a fixed potential such as ground. It may also be given. By controlling the height of the potential applied to the back gate electrode, The threshold voltage of the inverter 320 can be controlled.

[0239] The semiconductor device shown in Figure 13(C) uses n-crystalline silicon, similar to Embodiment 2. It has a channel-type transistor 220 and a p-channel-type transistor 221. In Figure 13(C), an n-channel transistor 220 and a p-channel transistor 2 A top-gate type transistor 330 made of an oxide semiconductor film is formed on 21. ru.

[0240] The transistor 330 has conductive films 331 and 332 formed on the insulating film 232, and An oxide semiconductor film 333 formed on the electrical film 331 and the conductive film 332, and an oxide semiconductor film 33 3 The gate insulating film 334 on the gate insulating film 334 and the oxide semiconductor film 333 overlapping It has a gate electrode 335. Furthermore, transistor 330 has a gate electrode 3 An insulating film 336 formed on 35 may also be included as a component.

[0241] Furthermore, in the case of the top-gate type transistor 330, the thickness of the conductive film 331 and conductive film 332 This is to prevent the oxide semiconductor film 333 that is formed later from undergoing step breaks, in the embodiment It is desirable to make it thinner than the bottom-gate type shown in 2. Specifically, 10nm to 20nm. The wavelength should be 0 nm, preferably 50 nm to 75 nm.

[0242] Furthermore, in the semiconductor device shown in Figure 13(C), the gate electrode 335 and the transistor 220 A contact hole reaching the conductive film 338, which functions as a source electrode or drain electrode After being formed on the insulating film 336 and gate insulating film 334, the gate electrode 335 and conductive film 338 It may also form a connected wiring 337.

[0243] This embodiment can be implemented in combination with the above embodiment.

[0244] (Embodiment 4) In this embodiment, an electronic paper or digital paper according to one aspect of the present invention is used. This document describes the configuration of a semiconductor display device.

[0245] Electronic paper allows for control of grayscale levels by applying voltage and also possesses memory capabilities. The display element used is a non-aqueous electrophoretic display element. Specifically, the display element used in electronic paper is a non-aqueous electrophoretic display element. A dynamic display element, a PD with liquid crystal droplets dispersed in a polymer material between two electrodes. Table of LC (polymer dispersed liquid crystal) method Display element, display having chiral nematic liquid crystal or cholesteric liquid crystal between two electrodes. The element has charged microparticles between two electrodes, and the microparticles are moved in the powder by an electric field. A powder transfer type display element can be used. In addition, a non-aqueous electrophoretic type display element can be used. This is a display element in which a dispersion of charged fine particles is sandwiched between two electrodes, and charged A display element having a dispersion of fine particles on two electrodes with an insulating film in between, A twisting ball, having two hemispheres of different colors charged with different charges, is placed between two electrodes. A display element dispersed in a solvent, and multiple charged microparticles dispersed in a solution. This includes display elements that have a chlorocapsule between two electrodes.

[0246] Figure 14(A) shows the pixel section 700 of the electronic paper, the signal line driving circuit 701, and the scan line driving circuit. A top view of circuit 702 is shown.

[0247] The pixel section 700 has multiple pixels 703. In addition, multiple signals are transmitted from the signal line drive circuit 701. The signal line 707 is routed into the pixel section 700. Multiple signals are transmitted from the scan line drive circuit 702. The scan line 708 is routed into the pixel area 700.

[0248] Each pixel 703 has a transistor 704, a display element 705, and a holding capacitor 706. The gate electrode of transistor 704 is connected to one of the scan lines 708. The source electrode and drain electrode of the transistor 704 are connected such that one is connected to one of the signal lines 707, and the other is connected to It is connected to the pixel electrode of the display element 705.

[0249] In Figure 14(A), the voltage applied between the pixel electrode and the counter electrode of the display element 705 is maintained. In order to hold, a holding capacitor 706 is connected in parallel with the display element 705, but the display element 7 If the memory capacity of 05 is high enough to maintain the display, then the retention capacity is 70 It is not always necessary to include a 6.

[0250] Note that in Figure 14(A), each pixel has one transistor that functions as a switching element. The configuration of the provided active matrix type pixel section has been described, but this is only one aspect of the present invention. Electronic paper is not limited to this configuration. The number of transistors provided in each pixel may vary. It's fine to do that, and it's also fine to connect elements other than transistors, such as capacitors, resistors, and coils. stomach.

[0251] Figure 14(B) shows an example of electrophoretic electronic paper with microcapsules, and each image Cross-sectional view of the display element 705 provided on element 703, and the signal line drive circuit 701 or scan line drive This shows a cross-sectional view of a semiconductor element used in drive circuits such as the drive circuit 702.

[0252] In a pixel, the display element 705 comprises a pixel electrode 710, a counter electrode 711, and a pixel electrode 71 It has a 0 and a microcapsule 712 to which a voltage is applied by a counter electrode 711. Either the source electrode or the drain electrode of the lampistor 704, or the conductive film 713 One end is connected to the pixel electrode 710.

[0253] The transistor 704 uses an oxide semiconductor film as its active layer. Therefore, the gate electrode and the socket - The off-current, i.e., the leakage current, when the voltage between the electrodes is nearly zero, exhibits crystalline properties. It is significantly lower compared to transistors using silicon.

[0254] Inside the microcapsule 712 are positively charged white pigments such as titanium dioxide and carbon Negatively charged black pigments such as black are sealed together with a dispersion medium such as oil. The video signal voltage applied to the pixel electrode 710 is used to determine the relationship between the pixel electrode and the counter electrode. By applying a voltage between them, the black pigment is attracted to the positive electrode and the white pigment to the negative electrode. It can display gradations.

[0255] Furthermore, in Figure 14(B), the microcapsule 712 is located between the pixel electrode 710 and the counter electrode 711. It is fixed in between by a translucent resin 714. However, the present invention is this structure Not limited to the form, the shape is formed by the microcapsule 712, the pixel electrode 710, and the counter electrode 711. The resulting space may be filled with gases such as air or inert gases. However, this In this case, the microcapsule 712 is attached to the pixel electrode 710 and the counter electrode 711 by an adhesive or the like. It is desirable to fix both, or at least one of them.

[0256] The number of microcapsules 712 in the display element 705 is as shown in Figure 14(B). There are not necessarily multiple microcapsules. One display element 705 has multiple microcapsules 712. Alternatively, multiple display elements 705 may have one microcapsule 712. This is also good. For example, two display elements 705 share one microcapsule 712, and one of them A positive voltage is applied to the pixel electrode 710 of the display element 705, and to the other display element 705. Assume that a negative voltage was applied to the pixel electrode 710. In this case, a positive voltage is In the region overlapping with the applied pixel electrode 710, a black color is observed within the microcapsule 712. The pigment is attracted towards the pixel electrode 710, and the white pigment is attracted towards the counter electrode 711. Conversely, in the region overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcap Within cell 712, the white pigment is attracted to the pixel electrode 710, and the black pigment is attracted to the counter electrode 71 It is pulled towards side 1.

[0257] Furthermore, the drive circuit consists of a transistor 720 that uses an oxide semiconductor film as the active layer, and silicon A transistor 721 is formed in the active layer. By using transistor 720 as a switching element to control the supply of power voltage to the circuit, It is possible.

[0258] During the non-operating period, the power supply voltage to the above circuit is stopped by a switching element. This reduces the dynamic standby power consumed by the circuit. Since the Ta720 uses an oxide semiconductor film as the active layer, the electrical current between the gate electrode and the source electrode is The off-current, or leakage current, at a pressure of nearly zero, is present in crystalline silicon. The voltage is significantly lower compared to the transistor 721 used. Therefore, switch transistor 720. By using it in switching elements, static currents that depend on leakage current etc. generated in switching elements are eliminated. The power consumption can be reduced. Therefore, the supply of power voltage to the non-operating circuit is stopped, and the non-operating circuit By reducing both static and dynamic standby power consumed in the circuit, the entire circuit This technology can provide a semiconductor device that can reduce the power consumption of the device.

[0259] In particular, compared to other semiconductor display devices such as liquid crystal displays and light-emitting devices, electronic paper has Because it has a display element with high molybdenum, when displaying, the signal line drive circuit 701 or The period during which the operation of drive circuits such as the scan line drive circuit 702 can be stopped tends to be long. By applying the configuration of the present invention, standby power consumption can be made more efficient compared to other semiconductor display devices. It can be reduced significantly.

[0260] Furthermore, transistor 721, which uses crystalline silicon, has an oxide semiconductor. Compared to transistor 720, it has higher mobility and higher on-current. Therefore, transistor 7 By forming a circuit using 21, high integration and high-speed driving of integrated circuits using the said circuit can be achieved. This can be achieved.

[0261] Next, regarding the specific driving method of the electronic paper, the electrophoretic type electronic paper described above... Let me explain with an example.

[0262] The operation of e-paper can be explained by dividing it into an initialization period, a writing period, and a retention period. Yes, it's possible.

[0263] Before switching the displayed image, the gradation of each pixel within the pixel area is first reset during the initialization period. By unifying, the display elements are initialized. By initializing the display elements, afterimages remain. This can be prevented. Specifically, in electrophoretic imaging, each pixel is displayed as either white or black. The gradation displayed by the microcapsules 712 of the display element 705 is adjusted.

[0264] In this embodiment, after inputting an initialization video signal that displays black to the pixels, white is displayed This section describes the initialization process when an initialization video signal, as shown, is input to a pixel. For example, an electrophoretic electronic paper that displays images toward the opposing electrode 711. In this case, first, the black pigment in the microcapsule 712 is directed toward the counter electrode 711, and the white pigment is directed toward the counter electrode 711. A voltage is applied to the display element 705 so that it faces the electrode 710 side. Next, the microcap The white pigment in cell 712 faces the opposing electrode 711, and the black pigment faces the pixel electrode 710. Next, a voltage is applied to the display element 705.

[0265] Also, if the video signal for initialization is input to the pixel only once, it will be displayed before the initialization period. Depending on the gradation, the movement of the white and black pigments within the microcapsule 712 may be incomplete. It ends up being the case that even after the initialization period has ended, the gradation displayed between pixels remains A difference may occur. Therefore, a negative voltage is applied to the common voltage Vcom. By applying Vp to the pixel electrode 710 multiple times, black is displayed, and relative to the common voltage Vcom... It is desirable to display white by applying a positive voltage Vp to the pixel electrode 710 multiple times. It seems so.

[0266] Furthermore, if the grayscale displayed by each pixel's display element is different before the initialization period, The minimum number of times a video signal needs to be input will also vary. Therefore, display before the initialization period. The number of times an initialization video signal is input between pixels is changed to match the grayscale level. This is also acceptable. In this case, pixels that no longer require an initialization video signal will have the same It's a good idea to input the voltage Vcom.

[0267] Furthermore, the voltage Vp or voltage -Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. In order to do this, during the period in which the selection signal pulse is applied to each scan line, the scan line is This process involves repeatedly performing a series of operations: inputting an initialization video signal to the pixels of the lines that the line has. The voltage Vp or voltage -Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. This converges the movement of the white and black pigments within the microcapsule 712, thereby inter-pixel This prevents differences in gradation from occurring and allows the pixels in the pixel area to be initialized.

[0268] During the initialization period, instead of displaying black followed by white for each pixel, white is displayed. Alternatively, during the initialization period, each pixel Alternatively, you could display white first, then black, and then white again.

[0269] Furthermore, the timing at which the initialization period begins is the same for all pixels within the pixel area. It's not necessary. For example, you could do it pixel by pixel, or pixel by pixel belonging to the same line. You can also vary the timing at which the initialization period begins.

[0270] Next, during the write period, a video signal containing image information in each pixel is input.

[0271] When displaying an image across the entire pixel area, all scan lines must be powered sequentially within one frame period. A selection signal with a shifted pressure pulse is input. Then, a pulse appears in the selection signal. During the 1-line period, video signals containing image information are input to all signal lines. ru.

[0272] According to the voltage of the video signal applied to the pixel electrode 710, the white inside the microcapsule 712 As the color pigment and black pigment move towards the pixel electrode 710 side or the opposing electrode 711 side, the display element Child 705 displays grayscale.

[0273] Furthermore, during the writing period, similar to the initialization period, the video signal voltage is applied to the pixel electrode 710 multiple times. It is desirable to apply the signal. Therefore, during the period when the selection signal pulse is applied to each scan line In this process, a series of operations is performed in which a video signal is input to the pixels of the line having the scan line. Perform this multiple times.

[0274] Next, during the retention period, a common voltage Vcom is input to all pixels via the signal line, and then scanning... No selection signals are input to the lines, nor are video signals input to the signal lines. Therefore, the display element The white pigment and black pigment within the microcapsule 712 of 705 are paired with the pixel electrode 710. The arrangement is maintained unless a positive or negative voltage is applied between the forward electrodes 711. Therefore, the gradation displayed by the display element 705 is preserved. Thus, during the writing period, the data is written. The selected image will remain displayed even during the retention period.

[0275] Furthermore, the display elements used in electronic paper require a voltage that changes the grayscale, while liquid crystal displays (LCDs) require a voltage that changes the grayscale. Light-emitting elements such as liquid crystal elements used in display devices and organic light-emitting elements used in light-emitting devices Compared to others, the transistors of pixels used as switching elements In the Ta704, the potential difference between its source electrode and drain electrode increases during the writing period. Therefore, the off-current increases, causing the potential of the pixel electrode 710 to fluctuate and easily resulting in display distortion. However, as described above, in one aspect of the present invention, the oxide semiconductor film is used in the transistor 704 It is used in the active layer. Therefore, the voltage between the gate electrode and the source electrode of transistor 704 The off-current, i.e., leakage current, when the current is nearly zero, is used in crystalline silicon. It is significantly lower compared to the transistors used. Therefore, during the writing period, transistor 70 Even if the potential difference between the source electrode and drain electrode of 4 becomes large, the off-current is suppressed, and the pixel electrode This prevents display malfunctions caused by fluctuations in the 710 potential.

[0276] In this embodiment, electronic paper was given as an example of the semiconductor display device of the present invention, The semiconductor display device of the present invention is a light-emitting device, such as a liquid crystal display device or an organic light-emitting device (OLED). A light-emitting device equipped with an element in each pixel, DMD (Digital Micromirror D device), PDP (Plasma Display Panel), FED (Fie (e.g., ld Emission Display) and other devices, and a drive circuit using semiconductor elements. Other semiconductor display devices fall into that category.

[0277] For example, a power supply voltage is provided to a semiconductor display device, such as a screen saver. However, when temporarily stopping the display of images, the standby power consumed is reduced. It is possible.

[0278] This embodiment can be implemented in combination with the above embodiment.

[0279] (Embodiment 5) The configuration of a liquid crystal display device according to one aspect of the present invention will be described.

[0280] Figure 15 is an example of a perspective view showing the structure of the liquid crystal display device of the present invention. The display device includes a liquid crystal panel 1601 in which liquid crystal elements are formed between a pair of substrates, and a first diffuser plate 1 602, prism sheet 1603, second diffuser plate 1604, light guide plate 1605, It comprises a ray plate 1606, a light source 1607, and a circuit board 1608.

[0281] A liquid crystal panel 1601, a first diffuser plate 1602, a prism sheet 1603, and a second diffuser The diffuser plate 1604, the light guide plate 1605, and the reflector plate 1606 are stacked in that order. Light source 1 607 is provided at the end of the light guide plate 1605, and the light source diffused inside the light guide plate 1605 Light from 1607 passes through the first diffuser 1602, the prism sheet 1603, and the second diffuser. The liquid crystal panel 1601 is uniformly illuminated by 1604.

[0282] In this embodiment, a first diffuser plate 1602 and a second diffuser plate 1604 are used. However, the number of diffusers is not limited to this; it can be one or three or more. The light guide plate only needs to be placed between the light guide plate 1605 and the liquid crystal panel 1601. Therefore, Even if the diffuser is provided only on the side closer to the liquid crystal panel 1601 than the zoom sheet 1603, That's good, and the diffuser is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's okay to be there.

[0283] Furthermore, the prism sheet 1603 is not limited to having a sawtooth cross-section as shown in Figure 15, and the light guide It is sufficient if the board 1605 has a shape that can concentrate the light from it towards the liquid crystal panel 1601.

[0284] The circuit board 1608 includes circuits for generating various signals that are input to the liquid crystal panel 1601, and The circuit board 16 is equipped with circuits for processing these signals. And in Figure 15, the circuit board 16 08 and LCD panel 1601 are FPC (Flexible Printed Circular Printer) It is connected via uit)1609. Note that the above circuit is COG (Chip ON It may also be connected to the liquid crystal panel 1601 using the Glass method, or one of the above circuits Even if the part is connected to the FPC1609 using the COF (Chip ON Film) method good.

[0285] In Figure 15, a control system circuit for controlling the drive of the light source 1607 is provided on the circuit board 1608. In this example, the control system circuit and the light source 1607 are connected via the FPC 1610. This indicates that the above control system circuit may also be formed on the liquid crystal panel 1601. In this case, the LCD panel 1601 and the light source 1607 are connected by an FPC or the like. ru.

[0286] Figure 15 shows an edge-lit type light source 1607 positioned at the edge of the liquid crystal panel 1601. Although the source is illustrated, in the liquid crystal display device of the present invention, the light source 1607 is located directly below the liquid crystal panel 1601. It may also be a direct-type display positioned at the same location. Furthermore, a liquid crystal display device according to one aspect of the present invention is a transparent It can be a single-layer type, or it can be semi-transparent or reflective.

[0287] Furthermore, the liquid crystal display device may be of the TN (Twisted Nematic) type. VA (Vertical Alignment) type, OCB (optically co mpensated birefringence) type, IPS (In-Plane S It can also be a witching type, etc.

[0288] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so chiral agents and purple The temperature range is improved by adding an externally curing resin. The liquid crystal exhibits a blue phase, and chiral agents and ultraviolet light are used. A liquid crystal composition containing a curing resin has a response speed of 10 μsec. to 100 μsec. Because it is short and optically isotropic, orientation processing is unnecessary, and it is preferable because it has little dependence on the viewing angle. stomach.

[0289] This embodiment can be implemented in appropriate combination with the above embodiment. [Examples]

[0290] By using a semiconductor device according to one aspect of the present invention, it is possible to prevent increased power consumption and achieve high functionality. We can provide electronic equipment, especially for those who have difficulty receiving a constant power supply. In the case of portable electronic devices, a semiconductor device according to one aspect of the present invention can be added as a component. This also offers the advantage of longer continuous usage time.

[0291] A semiconductor device according to one aspect of the present invention is a display device, a notebook personal computer, and a recording device. Image playback device equipped with a media (typically DVD: Digital Versatile) (A device that plays recording media such as discs and has a display capable of displaying the images thereof) It is possible to use a semiconductor device according to one aspect of the present invention. As sub-devices, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, etc. Digital still camera, goggle-type display (head-mounted display), navigation Audio systems, sound reproduction devices (car audio, digital audio players, etc.) , photocopiers, fax machines, printers, multifunction printers, ATMs (A Examples include electronic devices (TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 16.

[0292] Figure 16(A) is an e-book, which has a housing 7001, a display unit 7002, etc. One of the present inventions The semiconductor display device according to this embodiment can be used in the display unit 7002. By using a semiconductor display device according to one aspect of the present invention, a high-performance electric device with low power consumption can be obtained. It can provide sub-books. Furthermore, a semiconductor device according to one aspect of the present invention can provide ebooks. It can be used in integrated circuits for controlling the drive. For controlling the drive of ebooks. By using a semiconductor device according to one aspect of the present invention in an integrated circuit, high functionality with low power consumption can be achieved. It is possible to provide ebooks. Furthermore, by using a flexible substrate, semiconductors can be used. Because it can give flexibility to the body device and semiconductor display device, it is flexible and lightweight. We can provide user-friendly e-books.

[0293] Figure 16(B) shows a display device, which includes a housing 7011, a display unit 7012, a support base 7013, etc. A semiconductor display device according to one aspect of the present invention can be used in the display unit 7012. By using a semiconductor display device according to one aspect of the present invention in the display unit 7012, low power consumption and high performance A display device having a certain function can be provided. Furthermore, a semiconductor device according to one aspect of the present invention The device can be used in an integrated circuit for controlling the driving of a display device. By using a semiconductor device according to one aspect of the present invention in an integrated circuit for controlling low power consumption, This enables the provision of a display device with high functionality. Furthermore, the display device includes a personal This includes all information display devices, such as those for computer use, TV broadcast reception, and advertising displays. It can be done.

[0294] Figure 16(C) shows a display device, which includes a housing 7021, a display unit 7022, etc. One of the present inventions The semiconductor display device according to this embodiment can be used in the display unit 7022. By using a semiconductor display device according to one aspect of the present invention, a display device with low power consumption and high functionality can be obtained. A display device can be provided. Furthermore, a semiconductor device according to one aspect of the present invention is a display device. It can be used in integrated circuits for controlling the drive. For controlling the drive of a display device. By using a semiconductor device according to one aspect of the present invention in an integrated circuit, high functionality with low power consumption can be achieved. A display device can be provided. Furthermore, by using a flexible substrate, semiconductors can be used. Because it can give flexibility to the body device and semiconductor display device, it is flexible and lightweight. A user-friendly display device can be provided. Therefore, as shown in Figure 16(C), The display device can be fixed to fabric or other materials, significantly expanding the range of applications for the display device. ru.

[0295] Figure 16(D) shows a portable game console, comprising a casing 7031, casing 7032, display unit 7033, Display unit 7034, microphone 7035, speaker 7036, operation key 7037, stand It has illustration 7038, etc. A semiconductor display device according to one aspect of the present invention has a display unit 7033, It can be used in the display unit 7034. One aspect of the present invention can be used in the display unit 7033 and the display unit 7034. By using semiconductor display devices related to this, a portable game console with low power consumption and high functionality can be created. It can provide the following. Furthermore, a semiconductor device according to one aspect of the present invention is a portable game console. It can be used in integrated circuits for controlling the drive. For example, to control the drive of a portable game console. By using a semiconductor device according to one aspect of the present invention in an integrated circuit for this purpose, low power consumption and high performance can be achieved. A portable game console with the following capabilities can be provided. Note that the portable type shown in Figure 16(D) The game console has two display units 7033 and 7034, but it is a portable game console. The number of display units it has is not limited to this.

[0296] Figure 16(E) is a mobile phone, comprising a housing 7041, a display unit 7042, an audio input unit 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received into an electrical signal, external images can be captured. A semiconductor display device according to one aspect of the invention can be used in the display unit 7042. By using a semiconductor display device according to one aspect of the present invention in 042, high functionality can be achieved with low power consumption. A mobile phone can be provided. Furthermore, a semiconductor device according to one aspect of the present invention can be provided. It can be used in integrated circuits for controlling the operation of mobile phones. By using a semiconductor device according to one aspect of the present invention in an integrated circuit for this purpose, low power consumption and high performance We can provide a mobile phone with the necessary functions.

[0297] Figure 16(F) shows a portable information terminal, consisting of a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in Figure 16(F) has a modem built into the casing 7051. It is also possible. A semiconductor display device according to one aspect of the present invention can be used in the display unit 7052. By using a semiconductor display device according to one aspect of the present invention in the display unit 7052, low power consumption is achieved. This makes it possible to provide a mobile information terminal with high functionality. Furthermore, according to one aspect of the present invention Semiconductor devices can be used in integrated circuits for controlling the operation of portable information terminals. A semiconductor device according to one aspect of the present invention is used in an integrated circuit for controlling the operation of a mobile information terminal. This makes it possible to provide a portable information terminal with low power consumption and high functionality.

[0298] This embodiment can be implemented in appropriate combination with the above embodiment. [Explanation of Symbols]

[0299] 100 circuits 101 Switching element 101a Switching element 101b Switching element 101c switching element 101d switching element 102 Control circuits 110 transistors 111 transistors 112 load 120 transistors 121 transistors 122 transistors 123 Transistors 124 load 130 transistors 131 transistors 132 transistors 133 transistors 134 load 140 NAND 141 NAND 142 NAND 143 NAND 200 bonded substrates 201 Insulating film 202 Brittle layer 203 Base board 204 Semiconductor film 205 Semiconductor film 206 Semiconductor film 207 Semiconductor film 208 Gate Insulator 209 Electrode 210 Impurity region 211 Impurity region 212 Sidewall 213 High concentration impurity region 214 Low concentration impurity region 215 Channel formation region 216 High concentration impurity region 217 Low concentration impurity region 218 Channel formation region 220 transistors 221 transistors 230 insulating film 231 Insulating film 232 Insulating film 233 Wiring 234 Shutdown 240 Gate Insulator 241 Oxide semiconductor film 242 Oxide semiconductor film 245 Conductive film 246 Conductive film 247 Conductive film 248 Conductive film 249 Conductive film 250 Oxide semiconductor film 251 Insulating film 260 transistors 310 transistors 311 gate 312 Gate Insulator 313 Oxide semiconductor film 314 channel protective film 315 Conductive film 316 Conductive film 317 Insulating Film 320 transistors 321 Terminal 322 Gate insulating film 323 Conductive film 324 Conductive film 325 oxide semiconductor film 326 Insulating film 330 transistors 331 Conductive film 332 Conductive film 333 Oxide semiconductor film 334 Gate insulating film 335 gate 336 Insulating Film 337 Wiring 338 Conductive film 700 pixel section 701 Signal Line Drive Circuit 702 Scan Line Drive Circuit 703 pixels 704 Transistors 705 display elements 706 Holding capacity 707 Signal Line 708 scan lines 710 Pixel Electrodes 711 Counter electrode 712 microcapsules 713 Conductive film 714 Resin 720 transistors 721 transistors 1601 LCD panel 1602 First diffuser 1603 Prism Sheet 1604 Second diffuser 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit board 1609 FPC 1610 FPC 7001 enclosure 7002 Display section 7011 enclosure 7012 Display section 7013 Support stand 7021 enclosure 7022 Display section 7031 enclosure 7032 enclosure 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Keys 7038 Stylus 7041 enclosure 7042 Display section 7043 Voice Input Section 7044 Audio output section 7045 Operation Keys 7046 Light receiving section 7051 enclosure 7052 Display section 7053 Operation Keys

Claims

[Claim 1] A circuit having a first transistor, It includes a second transistor that controls the supply of power voltage to the circuit, The channel formation region of the first transistor contains crystalline silicon, The channel formation region of the second transistor is a semiconductor device containing an oxide semiconductor.

Images