Nitride semiconductor equipment

Abstract

Increase pressure resistance. [Solution] The nitride semiconductor device 1 comprises a first nitride semiconductor layer 21 having an n-type conductivity, a second nitride semiconductor layer 22 having a p-type conductivity provided above the first nitride semiconductor layer 21, and a source electrode 23 that is in direct contact with the second nitride semiconductor layer 22. Two or more mesa structures 30 are provided in the terminal region 12 between the active region 10 of the nitride semiconductor device 1 and the inert region 11 surrounding the active region 10. In the mesa structure 30, the lower end 32 of the side wall 31 of the first mesa 30A is located in the second nitride semiconductor layer 22, the lower end 35 of the side wall 34 of the second and subsequent mesa 30B reach the first nitride semiconductor layer 21, and the mesa depth of the first stage is more than half the thickness of the second nitride semiconductor layer 22.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising an n-type GaN layer and a p-type GaN layer laminated on the n-type GaN layer. In the semiconductor device disclosed in Patent Document 1, the p-type GaN layer is thinned in a termination region surrounding the device region, and a gradient low-concentration p-region, where the carrier concentration is lower than the surrounding area, is provided in the thinned portion of the p-type GaN layer. Because the carrier concentration in the gradient low-concentration p-region is low and the region is thin, it is said that the gradient low-concentration p-region is easily depleted when a reverse voltage is applied, which contributes to mitigating electric field concentration. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6524950 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, the structure disclosed in Patent Document 1 does not adequately improve pressure resistance.

[0005] Therefore, this disclosure provides a nitride semiconductor device that can increase the voltage withstand capability. [Means for solving the problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor layer having an n-type conductivity type, a second nitride semiconductor layer having a p-type conductivity type provided above the first nitride semiconductor layer, and a source electrode in direct contact with the second nitride semiconductor layer. A termination region between the active region of the nitride semiconductor device and an inactive region surrounding the active region is provided with a mesa structure having two or more steps. In the mesa structure, the lower end of the side wall of the first-stage mesa is located in the second nitride semiconductor layer, the lower end of the side wall of the second-stage and subsequent mesas reaches the first nitride semiconductor layer, and the depth of the first-stage mesa is at least half the thickness of the second nitride semiconductor layer.

Advantages of the Invention

[0007] According to the present disclosure, a nitride semiconductor device capable of increasing the breakdown voltage can be provided.

Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a main part of the nitride semiconductor device according to Embodiment 1. [Figure 3] FIG. 3 is an enlarged cross-sectional view of a main part of the nitride semiconductor device according to Embodiment 2. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a main part of the nitride semiconductor device according to Embodiment 3. [Figure 5] FIG. 5 is a cross-sectional view of a nitride semiconductor device according to Embodiment 4. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Embodiment 5. [Figure 7] FIG. 7 is a cross-sectional view of a nitride semiconductor device according to Embodiment 6. [Figure 8] FIG. 8 is a diagram showing the relationship between the ratio of the depths of the first-stage mesa and the second-stage mesa and the electric field strength. [Figure 9] FIG. 9 is a diagram showing the relationship between the taper angle of the side wall of the second-stage mesa and the electric field strength. [Figure 10] FIG. 10 is a diagram showing the relationship between the taper angle of the side wall of the second mesa and the electric field strength.

Embodiments for Carrying Out the Invention

[0009] (Findings on which the present disclosure is based) The present inventors have found that the following problems occur with the conventional semiconductor device described in the "Background Art" section.

[0010] In the semiconductor device disclosed in Patent Document 1, an inclined distribution low-concentration p-region is formed by performing ion implantation on a thinned portion of the p-type GaN layer. Since the GaN layer is likely to be damaged by ion implantation, there is a risk of reducing the breakdown voltage.

[0011] On the other hand, a nitride semiconductor device according to a first aspect of the present disclosure includes a first nitride semiconductor layer having an n-type conductivity type, a second nitride semiconductor layer having a p-type conductivity type provided above the first nitride semiconductor layer, and a source electrode in direct contact with the second nitride semiconductor layer. In a termination region between an active region of the nitride semiconductor device and an inactive region surrounding the active region, a mesa structure of two or more steps is provided. In the mesa structure, the lower end of the side wall of the first mesa is located in the second nitride semiconductor layer, the lower end of the side wall of the second and subsequent mesas reaches the first nitride semiconductor layer, and the depth of the first mesa is at least half of the film thickness of the second nitride semiconductor layer.

[0012] Thereby, the electric field concentration in the termination region can be further alleviated, so that the breakdown voltage of the nitride semiconductor device can be further increased. In addition, since the breakdown voltage can be increased by adjusting the depth of the first mesa, it is not necessary to form regions with different carrier concentrations by ion implantation. Therefore, an increase in the number of manufacturing steps can be suppressed.

[0013] A nitride semiconductor device according to a second aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the mesa depth of the first stage is two-thirds or more of the film thickness of the second nitride semiconductor layer.

[0014] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0015] A nitride semiconductor device according to a third aspect of the present disclosure is a nitride semiconductor device according to the first or second aspect, wherein the second nitride semiconductor layer is a current blocking layer between the source and drain.

[0016] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0017] A nitride semiconductor device according to a fourth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to third aspects, wherein the concentration of the p-type dopant in the second nitride semiconductor layer is 5 × 19 cm⁻¹ -3 The following applies:

[0018] This reduces the leakage current between the source and drain.

[0019] A nitride semiconductor device according to a fifth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fourth aspects, wherein the mesa depth of the first stage is shallower than the mesa depth of the second stage.

[0020] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0021] A nitride semiconductor device according to a sixth aspect of this disclosure is a nitride semiconductor device according to the first to fifth aspects, wherein the length of the bottom surface of the first mesa is 10 μm or less.

[0022] This allows for a reduction in the area of ​​the termination region, thereby enabling miniaturization of nitride semiconductor devices or a larger area of ​​the active region.

[0023] A nitride semiconductor device according to a seventh aspect of the present disclosure is a nitride semiconductor device according to any one of the first to sixth aspects, wherein the sidewall of the outermost mesa in the mesa structure has a forward tapered shape.

[0024] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0025] The nitride semiconductor device according to the eighth aspect of the present disclosure is the nitride semiconductor device according to the seventh aspect, wherein the taper angle of the side wall of the outermost mesa is 35 degrees or less.

[0026] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0027] A nitride semiconductor device according to the ninth aspect of this disclosure is a nitride semiconductor device according to the eighth aspect, wherein the taper angle of the side wall of the outermost mesa is 10 degrees or more.

[0028] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0029] A nitride semiconductor device according to the tenth aspect of this disclosure is a nitride semiconductor device according to the seventh or eighth aspect, wherein the taper angle of the side wall of the outermost mesa is 50 degrees or more.

[0030] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0031] A nitride semiconductor device according to the eleventh aspect of the present disclosure is a nitride semiconductor device according to any one of the first to tenth aspects, wherein the sidewall of the first stage mesa of the mesa structure and the sidewall of the second stage mesa are continuously connected.

[0032] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0033] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to eleventh aspects, wherein the taper angles of the side walls of the first and second stages of the mesa structure are continuously reduced.

[0034] This further reduces electric field concentration in the terminal region, thereby increasing the breakdown voltage of nitride semiconductor devices.

[0035] The embodiments will be described in detail below with reference to the drawings.

[0036] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0037] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0038] Furthermore, in this specification, terms indicating relationships between elements such as parallel and perpendicular, terms indicating the shapes of elements such as rectangles and trapezoids, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0039] Furthermore, in this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction." In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction." A "vertical" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the vertical direction, that is, a device in which the main current passes through the substrate in the vertical direction. A "horizontal" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the horizontal direction, that is, a device in which the main current does not pass through the substrate.

[0040] Furthermore, in this specification, the side of the substrate on which the mesa structure according to this disclosure is provided is considered to be the "upper" or "upper side," and the opposite side is considered to be the "lower" or "lower side." The terms "upper" and "lower" do not refer to the absolute upward (vertically upward) and downward (vertically downward) directions in spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact and touching each other.

[0041] Furthermore, in this specification, unless otherwise specified, "plan view" refers to a view of the nitride semiconductor device from a direction perpendicular to the main surface of the substrate, that is, a view of the main surface of the substrate from the front.

[0042] Furthermore, n-type and p-type represent the conductivity types of semiconductors, and they are conductivity types with opposite polarities. +The "type" represents a state where an n-type dopant is added to a semiconductor at a high concentration, i.e., so-called heavy doping. Also, the n - "type" represents a state where an n-type dopant is added to a semiconductor at a low concentration, i.e., so-called light doping. The n + "type" and the n - "type" are both examples of the n-type, and may be described as the n-type without distinguishing them. Also, the same applies to the p-type, p + "type", and p - "type".

[0043] Also, in this specification, the "main component" means the component with the highest content rate among all the components constituting the member. For example, a component with a content rate of 50% or more is the main component. The component is a material, an element, a compound, etc. Also, "member A is composed of component B" means that member A substantially contains only component B. However, member A may contain impurities that are unavoidably mixed in during manufacturing in addition to component B. The content rate of such unavoidable impurities is, for example, 1% or less.

[0044] Also, in this specification, AlGaN represents ternary mixed crystal Al x Ga 1-x N (0 < x < 1). Hereinafter, the multi-component mixed crystal is abbreviated with the arrangement of the respective constituent element symbols, for example, AlInN, GaInN, etc. For example, Al x Ga 1-x-y In y N (0 < x < 1, 0 < y < 1, and 0 < x + y < 1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN. x, 1 - x - y, and y represent the composition ratios of Al, Ga, and In, respectively.

[0045] Also, in this specification, ordinal numbers such as "first", "second", etc. do not mean the number or order of the components, unless otherwise specified, and are used for the purpose of avoiding confusion and distinguishing the same kind of components.

[0046] (Embodiment 1) First, the nitride semiconductor device according to Embodiment 1 will be described using Figure 1. Figure 1 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment.

[0047] The nitride semiconductor device 1 shown in Figure 1 includes an active region 10, an inactive region 11, and a terminal region 12.

[0048] The active region 10 is the main operating region of the nitride semiconductor device 1 and is also called the device region. The active region 10 includes, for example, a vertical field-effect transistor (FET). When the nitride semiconductor device 1 is operating, a drain current flows within the active region 10.

[0049] The inactive region 11 is the region surrounding the active region 10, and is also called the peripheral region or element isolation region.

[0050] The termination region 12 is located between the active region 10 and the inactive region 11. The termination region 12 is provided with two or more mesa structures 30. This increases the breakdown voltage of the nitride semiconductor device 1. Details of the mesa structure 30 will be described later.

[0051] As shown in Figure 1, the nitride semiconductor device 1 comprises a substrate 20, a first nitride semiconductor layer 21, a second nitride semiconductor layer 22, a source electrode 23, a drain electrode 24, and an insulating film 25.

[0052] The substrate 20 is a substrate mainly composed of a conductive nitride semiconductor. Specifically, the substrate 20 is a substrate mainly composed of GaN doped with n-type dopants such as Si. The planar shape of the substrate 20 is, for example, rectangular, but is not limited to this. For example, the substrate 20 has a thickness of 300 μm and a carrier concentration of 5 × 10⁻¹⁶ 18 cm -3 n +The substrate is made of GaN of type 1, but is not limited to this. The substrate 20 may also be a Si substrate, SiC substrate, ZnO substrate, gallium oxide substrate, or diamond substrate, etc. Furthermore, the substrate 20 may be a conductive substrate such as a graphite substrate containing graphene.

[0053] The first nitride semiconductor layer 21 is a first nitride semiconductor layer having an n-type conductivity, and is sometimes called a drift layer. The first nitride semiconductor layer 21 is provided above the substrate 20. Specifically, the first nitride semiconductor layer 21 is provided in contact with the upper surface of the substrate 20, but is not limited to this. One or more other layers, such as a buffer layer, may be provided between the first nitride semiconductor layer 21 and the substrate 20.

[0054] The first nitride semiconductor layer 21 is a layer mainly composed of GaN with an n-type dopant added. For example, the first nitride semiconductor layer 21 has a film thickness of 8 μm. - The film is composed of n-type GaN. The concentration of the n-type dopant in the first nitride semiconductor layer 21 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the first nitride semiconductor layer 21 is, for example, 1 × 10 15 cm -3 The above 2 x 10 17 cm -3 The following applies:

[0055] The film thickness of the first nitride semiconductor layer 21 and the concentration of the n-type dopant are not particularly limited. The concentration of the n-type dopant in the first nitride semiconductor layer 21 is uniform within the layer, but is not limited to this. For example, the concentration of the n-type dopant in the first nitride semiconductor layer 21 may decrease or increase in the depth direction. Alternatively, the first nitride semiconductor layer 21 may have a stacked structure of multiple nitride semiconductor layers with different n-type dopant concentrations.

[0056] The second nitride semiconductor layer 22 is a second nitride semiconductor layer having a p-type conductivity, and is sometimes called a blocking layer or current blocking layer. The second nitride semiconductor layer 22 is provided to block leakage current between the source and drain. The second nitride semiconductor layer 22 is provided above the first nitride semiconductor layer 21. Specifically, the second nitride semiconductor layer 22 is provided in contact with the upper surface of the first nitride semiconductor layer 21, but is not limited to this. Between the second nitride semiconductor layer 22 and the first nitride semiconductor layer 21, one or more other layers may be provided, such as an undoped nitride semiconductor layer and a nitride semiconductor layer with carbon added to increase resistance. For example, an i-type GaN layer or a C-doped GaN layer may be provided on the upper surface of the first nitride semiconductor layer 21.

[0057] The second nitride semiconductor layer 22 is a layer mainly composed of GaN with a p-type dopant added. For example, the second nitride semiconductor layer 22 is a film made of p-type GaN with a thickness of 300 nm. The concentration of the p-type dopant in the second nitride semiconductor layer 22 is, for example, 5 × 10⁻⁶. 19 cm -3 The following applies. Furthermore, the concentration of the p-type dopant in the second nitride semiconductor layer 22 is, for example, 2 × 10 16 cm -3 That concludes the explanation. As an example, the concentration of the p-type dopant in the second nitride semiconductor layer 22 is 1 × 10⁻⁶. 17 cm -3 This is possible, but is not limited to this. Furthermore, the thickness of the second nitride semiconductor layer 22 is, for example, 100 nm to 500 nm, but is not limited to this.

[0058] In this embodiment, the concentration of the p-type dopant in the second nitride semiconductor layer 22 is uniform within the layer. Uniformity here means not only completely uniform, but also substantially uniform. A substantially uniform concentration range can be considered, for example, when obtaining a concentration distribution in the depth direction, where the maximum value is less than or equal to twice the average value, and the minimum value is greater than or equal to half the average value. The concentration of the p-type dopant in the second nitride semiconductor layer 22 does not necessarily have to be uniform; for example, it may continuously change in a predetermined direction such as the thickness direction, or it may be a layered structure with multiple concentrations, or the concentration may differ locally. If the concentration of the p-type dopant is non-uniform, the example value for the concentration of the p-type dopant in the second nitride semiconductor layer 22 is represented by the average value of the concentration of the p-type dopant in the second nitride semiconductor layer 22.

[0059] The source electrode 23 is an example of a first electrode that is in direct contact with the second nitride semiconductor layer 22. Specifically, the source electrode 23 is in contact with the upper surface of the second nitride semiconductor layer 22 within the active region 10. In this embodiment, the source electrode 23 covers a portion of the upper surface of the insulating film 25 in the terminal region 12. The source electrode 23 is also electrically connected to a channel layer, which is not shown in Figure 1, within the active region 10. The source electrode 23 is an electrode mainly composed of conductive materials such as metals like Ti, Al, Hf, Ni, Pt, Au, Mo, and Pd. The source electrode 23 has a single-layer or multi-layer structure of conductive film.

[0060] The drain electrode 24 is an example of a second electrode provided below the substrate 20. Specifically, the drain electrode 24 is provided in contact with the lower surface of the substrate 20. The drain electrode 24 is provided, for example, entirely or partially on the lower surface of the substrate 20. The drain electrode 24 is an electrode mainly composed of a conductive material such as a metal that makes ohmic contact with the substrate 10, such as Ti, Al, Hf, Ni, Pt, Au, Mo, or Pd. The drain electrode 24 has a single-layer or multi-layer structure of conductive film.

[0061] The insulating film 25 is provided in the termination region 12 and the inert region 11. In this embodiment, the end of the contact surface between the source electrode 23 and the second nitride semiconductor layer 22 that is closest to the inert region 11 in a plan view is considered to be the boundary between the active region 10 and the termination region 12. In a plan view, the boundary between the termination region 12 and the inert region 11 is considered to be the lower end 35 of the side wall 34 of the second mesa of the mesa structure 30.

[0062] The insulating film 25 is not required. The insulating film 25 may have a single-layer or multi-layer structure, for example, an insulating film mainly composed of SiO2, SiN, SiON, Al2O3, etc.

[0063] Although not shown in Figure 1, the active region 10 is provided with a channel layer and a gate electrode. The channel layer is a nitride semiconductor layer containing a channel. The channel is a path that can electrically connect the source electrode 23 and the drain electrode 24, and its conduction (on) and non-conductivity (off) are switched depending on the potential applied to the gate electrode.

[0064] For example, the channel layer has a stacked structure including a third nitride semiconductor layer and a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer. For example, the third nitride semiconductor layer mainly contains undoped GaN, and the fourth nitride semiconductor layer mainly contains undoped AlGaN. Due to piezoelectric polarization caused by the difference in lattice constants between GaN and AlGaN, and spontaneous polarization caused by the atomic arrangement of GaN, a two-dimensional electron gas (2DEG) is generated near the heterointerface between GaN and AlGaN. This 2DEG is used as the channel of the nitride semiconductor device 1. That is, by partially controlling the generation of 2DEG by the potential applied to the gate electrode, it is possible to switch between conduction and non-conductivity between the source and drain.

[0065] The active region 10 is provided with an opening for the channel layer to contact the first nitride semiconductor layer 21. This opening may be called a gate opening, a longitudinal conduction opening, or a conduction opening. For example, the conduction opening is formed to penetrate the second nitride semiconductor layer 22 and reach the first nitride semiconductor layer 21. The channel layer is provided along the inner surface of the conduction opening, contacting the first nitride semiconductor layer 21 at the bottom of the conduction opening and contacting the source electrode 23 on the outside of the conduction opening. This reduces the on-resistance.

[0066] The gate electrode is located above the channel layer. The gate electrode is an electrode mainly composed of a conductive material such as a metal like Pd or Ni. The gate electrode may, but is not limited to, be located in contact with the upper surface of the channel layer. For example, a p-type nitride semiconductor layer may be provided between the gate electrode and the channel layer. The p-type nitride semiconductor layer is also called a p-type gate layer and is, for example, a layer mainly composed of p-type GaN or p-type AlGaN. By providing a p-type nitride semiconductor layer, the 2DEG in the direction directly below it can be eliminated, enabling the FET to be normally off. In a plan view, the gate electrode and / or p-type gate layer may be located on the bottom surface of the conductive opening, or on the outside of the conductive opening. The gate electrode and / or p-type gate layer are electrically isolated from the source electrode 23.

[0067] Instead of a p-type gate layer, an insulating oxide film, nitride film, or oxynitride film may be provided. Furthermore, 2DEG does not necessarily have to be used as the channel; the channel layer may be, for example, an n-type nitride semiconductor layer or a p-type nitride semiconductor layer. An inversion channel may be formed within the channel layer by the potential applied to the gate electrode.

[0068] A method for manufacturing the nitride semiconductor device 1 according to this embodiment is as follows, for example.

[0069] First, semiconductor films that will form the basis for the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 are formed on the substrate 20 by crystal growth using methods such as MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). By adjusting the growth conditions such as raw materials, growth temperature, and growth time, the composition, film thickness, and impurity concentration can be set to values ​​suitable for each layer.

[0070] Next, an FET structure is formed within the active region 10. For example, after forming a conductive opening by dry etching, a channel layer is formed by crystal regrowth of the nitride semiconductor. At this time, a p-type gate layer may be formed continuously from the channel layer.

[0071] Next, a mesa structure 30 is formed in the terminal region 12. The mesa structure 30 can be formed by etching multiple times depending on the number of mesa stages. After forming the mesa structure 30, an insulating film 25 is formed by plasma CVD (Chemical Vapor Deposition), thermal CVD, sputtering, coating, etc. After forming the insulating film 25, a portion of the insulating film 25 is removed by etching. Then, a source electrode 23 and a gate electrode are formed. The source electrode 23 and the gate electrode are formed by forming a conductive film by EB (Electron Beam) deposition or sputtering, etc., and then patterning the conductive film into a predetermined shape by lift-off or etching, etc. Note that the mesa structure 30 may be formed after the source electrode 23 and the gate electrode are formed. Then, a drain electrode 24 is formed on the lower surface of the substrate 20 by EB deposition or sputtering, etc.

[0072] As described above, the nitride semiconductor device 1 shown in Figure 1 can be manufactured. Note that the above-described method for manufacturing the nitride semiconductor device 1 is merely an example and can be modified as appropriate.

[0073] Next, the details of the mesa structure 30 will be explained using Figure 2. Figure 2 is an enlarged cross-sectional view of the main part of the nitride semiconductor device 1 according to this embodiment. Specifically, Figure 2 shows the mesa structure 30 provided in the terminal region 12 and its surrounding structure.

[0074] The mesa structure 30 is a structure that includes two or more mesas. A mesa means a step formed by partially removing one or more semiconductor layers. A mesa is part of the surface of a semiconductor layer and has at least a side wall that is inclined or perpendicular to the main surface of the semiconductor layer. In this embodiment, the mesa further includes an upper surface connected to the upper end of the side wall and a bottom surface connected to the lower end of the side wall. For example, both the upper and bottom surfaces of a mesa are planes parallel to the main surface of the substrate. The upper surface of a mesa is the bottom surface of the mesa one step above it. In other words, the bottom surface of a mesa is the upper surface of the mesa one step below it. The number of mesa steps is expressed by a number counted from the top. That is, mesas with larger ordinal numbers are closer to the substrate 20 than mesas with smaller ordinal numbers.

[0075] In the example shown in Figures 1 and 2, the mesa structure 30 includes two mesa stages, 30A and 30B. Mesa 30A is the first stage mesa, and mesa 30B is the second stage mesa. Mesa 30A includes a side wall 31 and a bottom surface 33. The lower end 32 of the side wall 31 is located in the second nitride semiconductor layer 22. The bottom surface 33 extends from the lower end 32 of the side wall 31 toward the inert region 11. Both the side wall 31 and the bottom surface 33 are part of the surface of the second nitride semiconductor layer 22. The bottom surface 33 is also the top surface of mesa 30B. Mesa 30B includes a side wall 34. The lower end 35 of the side wall 34 reaches the first nitride semiconductor layer 21. In other words, the interface edge 36, which is the end of the interface between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22, is visible on the side wall 34.

[0076] The upper surface 37 of the first mesa 30A is, for example, a part of the uppermost surface of the second nitride semiconductor layer 22, but is not limited to this. In the example shown in Figure 1, the source electrode 23 is in contact with the uppermost surface of the second nitride semiconductor layer 22, so the lower surface of the source electrode 23 and the upper surface 37 of the first mesa 30A are at the same height. In this specification, "height" refers to the distance from the main surface of the substrate 20 unless otherwise specified.

[0077] As shown in Figure 2, the mesa depth Dm1 of the first mesa 30A is more than half the film thickness T of the second nitride semiconductor layer 22. Mesa depth is expressed as the distance between the top and bottom surfaces of the mesa in the thickness direction of the semiconductor layer. Since the mesa depth Dm1 is more than half the film thickness T, the remaining film thickness (T-Dm1) of the second nitride semiconductor layer 22 becomes thinner due to the formation of the first mesa 30A. The remaining portion of the second nitride semiconductor layer 22 is a part of the second nitride semiconductor layer 22, with the bottom surface 33 of the mesa 30A as its top surface.

[0078] In the terminal region 12, the concentration of electric fields is mitigated by providing two or more mesa structures 30. Specifically, the electric field is distributed between the lower end 32 of the side wall 31 of the first mesa 30A and the lower end 35 of the side wall 34 of the second mesa 30B. When the mesa depth Dm1 is shallow, a larger electric field tends to be applied to the lower end 32 of the first mesa 30A than to the lower end 35 of the second mesa 30B, and when the mesa depth Dm1 is deep, a larger electric field tends to be applied to the lower end 35 of the second mesa 30B than to the lower end 32 of the first mesa 30A. Thus, the location where the electric field tends to concentrate changes depending on the depth of the mesa depth Dm1. Therefore, by making the mesa depth Dm1 more than half of the film thickness T, the difference between the electric field applied to the lower end 32 of the first mesa 30A and the electric field applied to the lower end 35 of the second mesa 30B can be reduced. This allows the electric field in the terminal region 12 to be effectively dispersed to the lower ends 32 and 35, respectively, thereby increasing the breakdown voltage of the nitride semiconductor device 1.

[0079] In this embodiment, the mesa depth Dm2 of the second mesa 30B is equal to the mesa depth Dm1 of the first mesa 30A, but this is not limited to this. The mesa depth Dm2 of the second mesa 30B may be deeper than the mesa depth Dm1 of the first mesa 30A.

[0080] Furthermore, in this embodiment, the length L of the bottom surface 33 of the first stage mesa 30A is 10 μm or less. This makes it possible to reduce the area of ​​the termination region 12, thereby enabling miniaturization of the nitride semiconductor device 1 or increasing the area of ​​the active region 10.

[0081] The shorter the length L of the base 33, the smaller the area of ​​the terminal region 12 can be. For this reason, the length L may be 5 μm or less, 3 μm or less, or 2 μm or less. The length L of the base 33 may also be, for example, 1 μm or more.

[0082] (Embodiment 2) Next, Embodiment 2 will be described.

[0083] Embodiment 2 differs from Embodiment 1 primarily in that the first mesa depth is greater. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of commonalities.

[0084] Figure 3 is an enlarged cross-sectional view of the main part of the nitride semiconductor device 2 according to this embodiment. In this embodiment, as shown in Figure 3, the mesa depth Dm1 of the first mesa 30A is two-thirds or more of the film thickness T of the second nitride semiconductor layer 22. That is, in this embodiment, the remaining film thickness (T-Dm1) of the second nitride semiconductor layer 22 is one-third or less of the film thickness T. The remaining film thickness (T-Dm1) is at least 1 nm, but may be 5 nm or more or 10 nm or more.

[0085] As will be discussed in more detail later along with the results of the electric field simulation, there may be an optimal ratio of mesa depth Dm1 / Dm2. The remaining film thickness (T-Dm1) can be determined based on the mesa depth ratio Dm1 / Dm2. For example, the remaining film thickness (T-Dm1) may be less than or equal to one-quarter, one-fifth, or one-tenth of the film thickness T. On the other hand, by making the remaining film thickness (T-Dm1) somewhat thicker, for example, 5 nm or more, it becomes easier to adjust the remaining film thickness. In other words, the tolerance range for manufacturing errors during the formation of mesa 30A is widened, and the yield can be increased.

[0086] In this embodiment, the mesa depth Dm2 of the second mesa 30B is shallower than the mesa depth Dm1 of the first mesa 30A, but this is not limited to this. The mesa depth Dm2 of the second mesa 30B may be equal to the mesa depth Dm1 of the first mesa 30A.

[0087] (Embodiment 3) Next, Embodiment 3 will be described.

[0088] In Embodiment 3, the main difference compared to Embodiment 1 is the relative size of the first mesa depth and the second mesa depth. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0089] Figure 4 is an enlarged cross-sectional view of the main part of the nitride semiconductor device 3 according to this embodiment. In this embodiment, as shown in Figure 4, the mesa depth Dm1 of the first stage mesa 30A is shallower than the mesa depth Dm2 of the second stage mesa 30B. As a result, the electric field is more easily evenly distributed between the lower end 32 of the first stage mesa 30A and the lower end 35 of the second stage mesa 30B. Therefore, the breakdown voltage of the nitride semiconductor device 3 can be further increased.

[0090] As will be discussed in detail later along with the results of the electric field simulation, the mesa depth Dm1 may be less than half of the mesa depth Dm2. Alternatively, the mesa depth Dm1 may be less than one-third or one-quarter of the mesa depth Dm2. Within the range where the mesa depth Dm1 is more than half of the film thickness T, an optimal ratio of mesa depth Dm1 / Dm2 may exist.

[0091] (Embodiment 4) Next, Embodiment 4 will be described.

[0092] Embodiment 4 differs from Embodiment 1 mainly in that the taper angles of the first and second mesa stages are different. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0093] Figure 5 is a cross-sectional view of the nitride semiconductor device 4 according to this embodiment. In this embodiment, as shown in Figure 5, both the side wall 31 of the first mesa 30A and the side wall 34 of the second mesa 30B have a forward taper shape. That is, the taper angle θ1 of the side wall 31 and the taper angle θ2 of the side wall 34 are both greater than 0 degrees and less than 90 degrees. The taper angle θ1 is the angle within the second nitride semiconductor layer 22 of the angle between the side wall 31 and the plane parallel to the main surface of the substrate 20. The taper angle θ1 is the value obtained by subtracting the angle between the side wall 31 and the bottom surface 33 from 180 degrees. The taper angle θ2 is the angle within the first nitride semiconductor layer 21 of the angle between the side wall 34 and the plane parallel to the main surface of the substrate 20. The taper angle θ2 is the value obtained by subtracting the angle between the side wall 34 and the bottom surface of mesa 30B from 180 degrees. Note that the side walls 31 and 34 do not necessarily have to be straight lines (not shown). In that case, the taper angle of the side wall 31 of the first mesa 30A and the taper angle of the side wall 34 of the second mesa 30B are not constant values. When the taper angle changes continuously, the taper angle θ1 of the side wall 31 is considered to be the taper angle at the midpoint of the side wall 31 in a cross-sectional view. The taper angle θ2 of the side wall 34 is considered to be the taper angle at the midpoint of the side wall 34 in a cross-sectional view.

[0094] The taper angle θ1 may be 90 degrees. That is, the side wall 31 and the bottom surface 33 may be perpendicular. In this embodiment, the side wall 34 of the outermost mesa in the mesa structure 30, i.e., the mesa 30B, may have a forward taper shape. That is, the taper angle θ2 of the side wall 34 may be less than 90 degrees. The taper angle θ2 is smaller than the taper angle θ1. Since the side wall 34 of the outermost mesa 30B has a forward taper shape, the electric field concentration in the terminal region 12 can be further reduced, and the breakdown voltage of the nitride semiconductor device 4 can be further increased.

[0095] As will be explained in detail later along with the results of the electric field simulation, within the range where the taper angle θ2 is less than 90 degrees, the electric field strength tends to increase around 45 degrees. For this reason, for example, the taper angle θ2 may be 35 degrees or less. Alternatively, the taper angle θ2 may be 10 degrees or more. By making the slope of the side wall 34 gentler, electric field concentration can be further mitigated. Alternatively, the taper angle θ2 may be 50 degrees or more. By making the slope of the side wall 34 steeper, electric field concentration can be further mitigated. In addition, by making the slope of the side wall 34 steeper, the area of ​​the terminal region 12 can be reduced, thereby enabling miniaturization of the nitride semiconductor device 4 or increasing the area of ​​the active region 10.

[0096] The sizes of the taper angles θ1 and θ2 can be adjusted by the shape of the edges of the openings in the resist pattern formed when the mesas 30A and 30B are formed by etching. Specifically, a slope is formed at the edges of the openings in the resist pattern. When the second nitride semiconductor layer 22 and the first nitride semiconductor layer 21 are removed by etching, the slope at the edges of the openings in the resist pattern is transferred to the semiconductor layer, forming the sloped sidewalls 31 and 34. The slope at the edges of the openings in the resist pattern can be adjusted, for example, by the bake temperature of the resist pattern. For example, baking at a high temperature makes the slope gentler, while baking at a low temperature makes the slope steeper or perpendicular.

[0097] Furthermore, in the nitride semiconductor device 4 according to this embodiment, similar to the nitride semiconductor devices 1 to 3 according to embodiments 1 to 3, the mesa depth Dm1 may be half or more of the film thickness T of the second nitride semiconductor layer 22, or two-thirds or more. Also, the mesa depth Dm1 of the first mesa 30A may be shallower than the mesa depth Dm2 of the second mesa 30B.

[0098] (Embodiment 5) Next, Embodiment 5 will be described.

[0099] Embodiment 5 differs from Embodiment 1 mainly in that the bottom surface of the first mesa, i.e., the top surface of the second mesa, is not provided. Below, we will focus on explaining the differences from Embodiment 1, and will omit or simplify the explanation of the common points.

[0100] Figure 6 is a cross-sectional view of the nitride semiconductor device 5 according to this embodiment. As shown in Figure 6, the bottom surface 33 of the mesa 30A is not provided. The lower end 32 of the side wall 31 of the first stage mesa 30A and the upper end of the side wall 34 of the second stage mesa 30B are continuous. The lower end 32 of the side wall 31 is the connection point of the side wall 31 and the side wall 34, and can be considered as a point of change in inclination.

[0101] In this embodiment, similar to Embodiment 4, the taper angle θ1 of the side wall 31 is greater than the taper angle θ2 of the side wall 34. The taper angles θ1 and θ2 are 0 degrees or more and less than 90 degrees. The taper angle θ2 is, for example, 10 degrees or more and 35 degrees or less, but may be 50 degrees or more and less than 90 degrees.

[0102] Thus, even when the bottom surface 33 of the mesa 30A is not provided, the electric field concentration in the mesa structure 30 can be mitigated, as in other embodiments, and the breakdown voltage of the nitride semiconductor device 5 can be increased. Furthermore, since the bottom surface 33 is not provided, the length L of the bottom surface 33 can be considered to be 0 μm. For this reason, the area of ​​the termination region 12 can be reduced, thereby enabling miniaturization of the nitride semiconductor device 5 or increasing the area of ​​the active region 10.

[0103] In the nitride semiconductor device 5 according to this embodiment, similar to the nitride semiconductor devices 1 to 3 according to embodiments 1 to 3, the mesa depth Dm1 may be half or more of the film thickness T of the second nitride semiconductor layer 22, or it may be two-thirds or more. Also, the mesa depth Dm1 of the first mesa 30A may be shallower than the mesa depth Dm2 of the second mesa 30B.

[0104] (Embodiment 6) Next, Embodiment 6 will be described.

[0105] Embodiment 6 differs from Embodiment 5 primarily in that the taper angles of the side walls of the first and second mesa are continuously gentler. Below, we will focus on explaining the differences from Embodiment 5, and omit or simplify the explanation of the common points.

[0106] Figure 7 is a cross-sectional view of the nitride semiconductor device 6 according to this embodiment. As shown in Figure 7, the taper angle of the side wall 31 of the first stage mesa 30A and the taper angle of the side wall 34 of the second stage mesa 30B are not constant values. Specifically, the taper angles of the side walls 31 and 34 are continuously gradual. When the taper angle changes continuously in this way, for example, the position where the taper angle is 45 degrees is considered to be the lower end 32 of the side wall 31. The taper angle θ1 of the side wall 31 is considered to be the taper angle at the midpoint of the side wall 31 in a cross-sectional view. The taper angle θ2 of the side wall 34 is considered to be the taper angle at the midpoint of the side wall 34 in a cross-sectional view. In this embodiment, for example, the rate of change of the taper angle of the side wall 31 is greater than the rate of change of the taper angle of the side wall 34. That is, the inclination of the side wall 31 changes steeply, while the inclination of the side wall 34 changes gradually.

[0107] Thus, even when the bottom surface 33 of the mesa 30A is not provided and the taper angle changes continuously, the electric field concentration in the mesa structure 30 can be mitigated, as in other embodiments, and the breakdown voltage of the nitride semiconductor device 6 can be increased. Furthermore, since the bottom surface 33 is not provided, the length L of the bottom surface 33 can be considered to be 0 μm. Therefore, the area of ​​the termination region 12 can be reduced, which enables miniaturization of the nitride semiconductor device 6 or a larger area of ​​the active region 10.

[0108] In the nitride semiconductor device 6 according to this embodiment, similar to the nitride semiconductor devices 1 to 3 according to embodiments 1 to 3, the mesa depth Dm1 may be half or more of the film thickness T of the second nitride semiconductor layer 22, or two-thirds or more. Also, the mesa depth Dm1 of the first mesa 30A may be shallower than the mesa depth Dm2 of the second mesa 30B.

[0109] (Simulation results) Next, we will explain the results of several electric field simulations conducted by the inventors.

[0110] Multiple electric field simulations were conducted to calculate the distribution of electric field strength generated in and around the mesa structure 30 under various conditions. The changes in electric field strength between the lower end 32 of the side wall 31 of mesa 30A and the lower end 35 of the side wall 34 of mesa 30B under different conditions were examined.

[0111] The main conditions common to multiple electric field simulations are as follows: The structure of the nitride semiconductor device to be simulated is similar to the nitride semiconductor device 1 shown in Figure 1. Specifically, the substrate 20 is n - This is a GaN substrate. The first nitride semiconductor layer 21 has a thickness of 10 μm. - The first is a p-type GaN layer. The second nitride semiconductor layer 22 is a p-type GaN layer with a thickness of 300 nm. The length of the top surface 37 is 40 μm, which is the length from the end of the source electrode 23 to the top of the side wall 31.

[0112] First, we will explain the results of an electric field simulation that examined the relationship between the ratio of mesa depths Dm1 and Dm2 and the electric field strength. In this electric field simulation, in addition to the common conditions mentioned above, the following conditions were set as fixed values: The taper angle θ1 of the side wall 31 of mesa 30A and the taper angle θ2 of the side wall 34 of mesa 30B were set to 20 degrees. The voltage Vd applied between the drain electrode 24 and the source electrode 23 was set to 1200V. The parameters to be varied were the length L of the bottom surface 33 of mesa 30A and the ratio of mesa depths Dm1 / Dm2. The length L of the bottom surface 33 was set to either 2 μm or 5 μm. The ratio of mesa depths Dm1 / Dm2 was set to a range from 0.1 μm / 0.9 μm to 1.0 μm / 0.0 μm.

[0113] Figure 8 shows the relationship between the ratio of the mesa depths of the first mesa 30A and the second mesa 30B and the electric field strength. In Figure 8, the horizontal axis represents the ratio of the mesa depths, specifically the mesa depth Dm1 of mesa 30A and the mesa depth Dm2 of mesa 30B. The units for mesa depths Dm1 and Dm2 are μm. The vertical axis represents the electric field strength applied to the lower end 32 of the first mesa 30A and the lower end 35 of the second mesa 30B. The unit for electric field strength is MV / cm. Figure 8 shows the case where the length L of the bottom surface 33 of mesa 30A is 5 μm.

[0114] As a common condition, as mentioned above, the second nitride semiconductor layer 22 is a p-type GaN layer with a thickness of 300 nm. Therefore, in the range where the mesa depth Dm1 of the first-stage mesa 30A is between 0.0 μm and 0.3 μm, the lower end 32 of mesa 30A is located within the first nitride semiconductor layer 21. As shown in Figure 8, as the ratio of mesa depths Dm1 / Dm2 increases, the electric field strength concentrated at the lower end 32 of the first-stage mesa 30A tends to decrease. Also, as the ratio of mesa depths Dm1 / Dm2 increases, the relative magnitudes of the electric field strength concentrated at the lower end 32 of mesa 30A and the electric field strength concentrated at the lower end 35 of mesa 30B are reversed. This reversal phenomenon is called electric field redistribution. The electric field relaxation effect is high in the range before and after the electric field redistribution occurs. Specifically, in the range where the ratio Dm1 / Dm2 is between 0.15 / 0.85 and 0.3 / 0.7, the higher of the two electric field strengths related to the lower ends 32 and 35 decreases, indicating that localized electric field concentration is suppressed.

[0115] Even when the length L of the base 33 was 2 μm, results equivalent to those shown in Figure 8 were obtained. Note that the ratio Dm1 / Dm2 of the mesa depths at which the electric field strengths concentrated at the lower ends 32 and 35 are equal changes depending on the length L of the base 33 of the mesa 30A. Specifically, the longer the length L, the shallower the mesa depth Dm1 of the mesa 30A tends to be. For example, as shown in Figure 8, when the length L is 5 μm, the electric field strengths concentrated at the lower ends 32 and 35 are equal when the ratio Dm1 / Dm2 = 0.2 μm / 0.8 μm, resulting in a high electric field concentration mitigation effect. Also, when the length L is 2 μm, the electric field strengths concentrated at the lower ends 32 and 35 are equal when the ratio Dm1 / Dm2 = 0.3 μm / 0.7 μm, resulting in a high electric field concentration mitigation effect.

[0116] Next, we will explain the results of an electric field simulation that examined the relationship between the taper angle θ2 of the side wall 34 of the second stage mesa 30B and the electric field strength. In this electric field simulation, in addition to the common conditions mentioned above, the following conditions were set as fixed values: The taper angle θ1 of the side wall 31 of mesa 30A was set to 70 degrees. The ratio of mesa depths Dm1 / Dm2 was set to 0.2 μm / 1.0 μm. The length L of the bottom surface 33 of mesa 30A was set to 5 μm. The parameters that were set to vary were the voltage Vd applied between the drain electrode 24 and the source electrode 23, and the taper angle θ2 of the side wall 34 of mesa 30B. Specifically, the voltage Vd was set to either 600V or 1200V. The taper angle θ2 was set to a range of 10 degrees or more and 70 degrees or less.

[0117] Figures 9 and 10 both show the relationship between the taper angle θ2 of the side wall 34 of the second mesa 30B and the electric field strength. Figure 9 shows the case when the voltage Vd is 600V, and Figure 10 shows the case when the voltage Vd is 1200V. In Figures 9 and 10, the horizontal axis represents the taper angle θ2. The vertical axis represents the electric field strength applied to the lower end 32 of the first mesa 30A, the lower end 35 of the second mesa 30B, and the lower end of the p-type GaN layer, i.e., the interface end 36, as well as the maximum electric field strength at the termination.

[0118] As shown in Figure 9, the maximum electric field strength is highest near a taper angle θ2 of 45 degrees. Specifically, in the range where the taper angle θ2 is greater than 35 degrees and less than 50 degrees, the maximum electric field strength exceeds approximately 4 MV / cm. In the range where the taper angle θ2 is 35 degrees or less, and preferably between 10 degrees and 35 degrees, the maximum electric field strength is suppressed to a low level. Furthermore, in the range where the taper angle θ2 is 50 degrees or more, and preferably between 50 degrees and 70 degrees, the maximum electric field strength is suppressed to a low level. In other words, it can be seen that the mesa structure 30 mitigates electric field concentration, thereby increasing the breakdown voltage of the nitride semiconductor device. A similar trend was confirmed in the example shown in Figure 10.

[0119] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as configurations constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0120] For example, in each embodiment, the mesa structure 30 may include three or more mesa layers. In this case, the lower end of the first mesa layer is located at the second nitride semiconductor layer 22, and the lower ends of the second and third mesa layers reach the first nitride semiconductor layer 21. That is, the interface between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 is visible on the side wall of the second mesa layer. The bottom surface of the second mesa layer, as well as the side wall and bottom surface of the third mesa layer, are all part of the surface of the first nitride semiconductor layer 21. Similarly, when the mesa structure 30 includes four or more mesa layers, the interface between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 is visible on the side wall of the second mesa layer, and the bottom surfaces of the second and subsequent mesa layers, as well as the side walls of the third and subsequent mesa layers, are all part of the surface of the first nitride semiconductor layer 21. In at least one of the mesas included in the mesa structure 30, the taper angle of the sidewall may not be constant but may vary.

[0121] Furthermore, when the mesa structure 30 includes n or more mesas, it may include mesas that do not have a bottom surface. That is, similar to the nitride semiconductor devices 5 and 6 shown in Figures 6 and 7, the sidewall of the m-1 stage mesa and the sidewall of the m stage mesa may be continuous. Here, n is a natural number greater than or equal to 2, and m is a natural number between 2 and n.

[0122] Furthermore, a nitride semiconductor device according to one aspect of the present disclosure comprises a first nitride semiconductor layer having an n-type conductivity, a second nitride semiconductor layer having a p-type conductivity provided above the first nitride semiconductor layer, and a source electrode in direct contact with the second nitride semiconductor layer. The terminal region between the active region of the nitride semiconductor device and the inert region surrounding the active region is provided with two or more sidewalls with different inclination angles, the two or more sidewalls include a first sidewall and a second sidewall continuous from the lower end of the first sidewall, the upper end of the first sidewall is located on the upper surface of the second nitride semiconductor layer, the lower end of the first sidewall is located in the second nitride semiconductor layer, and the lower end of the second sidewall reaches the first nitride semiconductor layer. In addition, in the nitride semiconductor device, the taper angles of the first sidewall and the second sidewall may be continuously gradual. An example of a first side wall is side wall 31 in each embodiment, and an example of a second side wall is side wall 34 in each embodiment. In other words, the height of the first side wall corresponds to the mesa depth Dm1 in each embodiment, and the height of the second side wall corresponds to the mesa depth Dm2 in each embodiment.

[0123] Furthermore, for example, the nitride semiconductor device according to each embodiment may include a vertical diode in addition to, or instead of, a vertical FET. In this case, an anode electrode electrically connected to the p-type second nitride semiconductor layer 22 and a cathode electrode electrically connected to the n-type first nitride semiconductor layer 21 are connected, and a forward current flows between the anode electrode and the cathode electrode within the active region 10. The source electrode 23 and the anode electrode may be integrated, and the drain electrode 24 and the cathode electrode may be integrated. Furthermore, for example, the nitride semiconductor device according to each embodiment may include a horizontal FET or horizontal diode in addition to, or instead of, a vertical FET or vertical diode. Furthermore, the nitride semiconductor device may include elements other than FETs or diodes.

[0124] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalents thereof. [Industrial applicability]

[0125] The nitride semiconductor device described herein can be used, for example, as a power device used in power supply circuits, inverter circuits, and the like in electrical equipment. [Explanation of Symbols]

[0126] 1, 2, 3, 4, 5, 6 Nitride semiconductor devices 10 Active area 11 Inactive area 12 Termination area 20 circuit boards 21 First nitride semiconductor layer 22 Second nitride semiconductor layer 23 Source electrode 24 Drain electrodes 25 Insulating film 30 Mesa structure 30A, 30B Mesa 31, 34 side wall 32, 35 bottom edge 33 Bottom 36 Interface edge 37 Top

Claims

1. Nitride semiconductor device, A first nitride semiconductor layer having an n-type conductivity, A second nitride semiconductor layer having a p-type conductivity is provided above the first nitride semiconductor layer, The invention comprises a source electrode that is in direct contact with the second nitride semiconductor layer, In the terminal region between the active region of the nitride semiconductor device and the inactive region surrounding the active region, two or more mesa structures are provided. In the mesa structure, the lower end of the sidewall of the first mesa is located in the second nitride semiconductor layer, and the lower end of the sidewall of the second and subsequent mesas reaches the first nitride semiconductor layer. The first stage mesa depth is more than half the thickness of the second nitride semiconductor layer. Nitride semiconductor equipment.

2. The mesa depth of the first stage is two-thirds or more of the film thickness of the second nitride semiconductor layer. The nitride semiconductor device according to claim 1.

3. The second nitride semiconductor layer is a current blocking layer between the source and drain. The nitride semiconductor device according to claim 1.

4. The concentration of the p-type dopant in the second nitride semiconductor layer is 5 × 19 cm². －３ The following is: The nitride semiconductor device according to claim 1.

5. The depth of the first mesa is shallower than the depth of the second mesa. The nitride semiconductor device according to claim 1.

6. The length of the bottom surface of the first mesa is 10 μm or less. The nitride semiconductor device according to claim 1.

7. In the aforementioned mesa structure, the sidewall of the outermost mesa has a forward tapered shape. A nitride semiconductor device according to any one of claims 1 to 6.

8. The taper angle of the side wall of the outermost mesa is 35 degrees or less. The nitride semiconductor device according to claim 7.

9. The taper angle of the side wall of the outermost mesa is 10 degrees or more. The nitride semiconductor device according to claim 8.

10. The taper angle of the side wall of the outermost mesa is 50 degrees or more. The nitride semiconductor device according to claim 7.

11. The side walls of the first mesa and the second mesa of the mesa structure are continuously connected. The nitride semiconductor device according to any one of claims 1 to 5.

12. The taper angles of the side walls of the first and second stages of the mesa structure gradually decrease. The nitride semiconductor device according to any one of claims 1 to 5.

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