Oxidation-enhanced doping

Abstract

Embodiments of the present technology include a semiconductor processing method. The method may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The method may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The method may include forming a doped silicon-containing material on the silicon-containing material. The method may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The method may include etching the oxidized doped silicon-containing material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 973,927, filed October 26, 2022, entitled "OXIDATION ENHANCED DOPING," which is incorporated herein by reference in its entirety.

[0002] The present technology relates to deposition and removal processes and chambers, and more particularly to systems and methods for enhancing doping in silicon materials by oxidation. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods for forming and removing materials. Material properties can affect how a device operates and can also affect how films are removed relative to each other. Deposition processes create films with certain properties. Many films formed require additional processing to adjust or enhance the material properties of the film to provide the appropriate properties.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technique addresses these and other needs. Summary of the Invention

[0005] Embodiments of the present technology include a semiconductor processing method. The method may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The method may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The method may include forming a doped silicon-containing material on the silicon-containing material. The method may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The method may include etching the oxidized doped silicon-containing material.

[0006] In some embodiments, the pressure within the semiconductor processing chamber may be maintained at less than or about 760 Torr. The temperature within the semiconductor processing chamber may be maintained at less than or about 1200° C. Silicon-containing precursors include silane (SiH), disilane (SiH), trisilane (SiH), tetrasilane (SiH), and the like. 10 ), dichlorosilane (SiH2Cl2) or trichlorosilane (SiHCl3), or silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10), dichlorosilane (SiH2Cl2), or trichlorosilane (SiHCl3). The dopant precursor may include phosphorus. The dopant precursor includes boron. The method may include providing an etchant precursor along with the silicon-containing precursor and the dopant precursor. The etchant precursor may be an oxygen-containing precursor or a chlorine-containing precursor, or may include an oxygen-containing precursor or a chlorine-containing precursor. Oxidizing the substrate may include contacting the substrate with an oxygen-containing precursor or treating the substrate with a laser. Oxidizing the substrate may increase doping depth in the silicon-containing material to greater than or about 10 nm. The method may include removing defective silicon-containing material formed on a silicon nitride material formed on the substrate.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include supplying a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A silicon-containing material may be deposited on a substrate disposed in the semiconductor processing chamber. The silicon-containing material may be a silicon channel of a 3D DRAM structure. The method may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The method may include forming a doped silicon-containing material on the silicon-containing material. The method may include oxidizing the substrate. The oxidation may form an oxidized doped silicon-containing material.

[0008] In some embodiments, doped silicon-containing materials may be formed by chemical vapor deposition. The dopant precursor may be or may include phosphine (PH), arsine (AsH), nitrogen (N), ammonia (NH), germane (GeH), borane (BH), diborane (BH), trimethylgallium (Ga(CH)), aluminum chloride (AlCl), trimethylaluminum (CHAl), or methylsilane (CHSiH). The 3D DRAM structure further includes silicon- and germanium-containing materials deposited above and below the silicon-containing material, and silicon- and nitrogen-containing materials extending from the silicon- and germanium-containing materials. Silicon channels may extend between individual portions of the silicon- and nitrogen-containing materials. The silicon channels may be characterized by a depth of greater than or about 300 nm and a width of greater than or about 5 nm. The method may include removing oxidized doped silicon-containing material from the silicon-containing material. The method may include removing silicon-containing by-products from the silicon- and nitrogen-containing material.

[0009] Some embodiments of the present technology may include a semiconductor structure. The structure may include a silicon-containing substrate. The structure may include a silicon- and germanium-containing material extending into a recess formed in the silicon-containing substrate. The structure may include a silicon- and nitrogen-containing material extending from the silicon- and germanium-containing material. The silicon- and nitrogen-containing material may define a channel. The structure may include a doped silicon-containing material in the channel extending from the silicon-containing substrate.

[0010] In some embodiments, the silicon-containing substrate may be doped with a dopant from a doped silicon-containing material to a doping depth of greater than or about 10 nm, which may be formed by chemical vapor deposition.

[0011] Such techniques may offer numerous benefits over conventional processing methods. For example, an oxidation process after depositing a doped silicon-containing material may drive the dopants further into the underlying material. This increased doping depth may reduce resistivity and ohmic contact between the silicon channel and the metal silicide. In addition, the oxidation process may oxidize by-product materials formed on other materials in the structure. Subsequent removal or etching of the oxidized material may also remove by-product materials formed during deposition of the doped silicon-containing material. These and other embodiments, along with many of the advantages and features of those embodiments, are described in more detail in connection with the following description and accompanying figures.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2] 1 is a schematic cross-sectional view of an exemplary plasma system in accordance with some embodiments of the present technique; [Figure 3] 1A-1D illustrate operations of an exemplary semiconductor processing method in accordance with some embodiments of the present technique. [Figures 4A-4D] 1 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some of these figures are included as schematic diagrams. It is understood that these figures are for illustrative purposes and should not be considered to be at scale unless specifically stated to be at scale. Additionally, as schematic diagrams, these figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated content for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished by tracing the reference numerals with a letter that distinguishes between the similar components. When only the first reference numeral is used herein, the description applies to any one of the similar components having the same first reference numeral, regardless of the letter.

[0016] As the size of 3D DRAM structures increases, the aspect ratios of silicon channels and other structures increase, sometimes dramatically. During 3D DRAM processing, silicon channels are formed when other materials, such as silicon nitride and silicon oxide, form high-aspect-ratio features with silicon materials, such as the substrate, that form the bottom of the feature. Subsequent processing forms source and drain regions by doping the underlying silicon-containing material. Subsequent processing may also form contacts on the source and drain regions.

[0017] Conventional doping of the underlying silicon-containing material may be performed by epitaxial growth of doped silicon. Depending on whether a source or drain is to be formed, the underlying silicon may be doped to be p-type or n-type silicon. Conventional doping involves epitaxially depositing doped silicon onto the underlying silicon-containing material. Some of the dopants in the silicon may migrate into the underlying silicon-containing material, thereby doping the underlying silicon-containing material. However, as structure sizes increase and demands for high-quality structures increase, these conventional techniques may not provide sufficient doping depth or concentration. Additionally, conventional techniques may deposit by-product materials elsewhere on the structure, which may result in subsequent processing failures, the need for intermediate processing to remove the by-product materials, or reduced final device functionality.

[0018] The present technology solves these problems by performing an oxidation process after depositing doped silicon. The oxidation can drive additional dopants into the underlying silicon-containing material through bonding between the doped silicon and the oxidized silicon material. In addition to increasing the doping depth, the oxidation can drive an increased amount of dopants into the underlying silicon-containing material, thereby increasing the dopant concentration. The increased doping depth and increased dopant concentration can lead to lower resistivity and ohmic contact with the silicon channel and contacts such as metal silicides. Additionally, the oxidation can oxidize by-product materials deposited elsewhere on the structure. A subsequent etching operation that removes the oxidized material near the doped silicon can also remove the oxidized by-product material.

[0019] While the remainder of this disclosure routinely identifies specific deposition and etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition and etching chambers and processes that may be performed in the described chambers. Accordingly, the present technology should not be considered limited to use solely with these specific deposition processes or chambers. This disclosure discusses one possible system and chamber that may be used to perform a deposition process according to embodiments of the present technology, followed by additional details according to embodiments of the present technology.

[0020] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In this illustration, a pair of front-opening unified pods 102 provide substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 and then into one of the substrate processing chambers 108a-f arranged in tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back again. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing operations, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, alignment, and other substrate processes including annealing, ashing, and the like, as well as the formation of stacks of semiconductor materials as described herein.

[0021] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a hard mask layer on a substrate. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit a hard mask layer on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited hard mask (i.e., a hard mask opening operation). In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit a hard mask layer on a substrate and etch the hard mask layer on the substrate. Any one or more of the described processes may be performed in chambers separate from the fabrication system shown in different embodiments. It is understood that additional configurations of deposition, etching, annealing, and curing chambers for hard mask layers are contemplated by system 100.

[0022] 2 shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the present technique. The plasma system 200 may show a pair of processing chambers 108, which may be nested in one or more of the tandem sections 109 described above and may include lid stack components, which may be further described below, in accordance with embodiments of the present technique. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0023] For example, processing region 220B may include a pedestal 228 disposed therein through a passageway 222 formed in the bottom wall 216 of plasma system 200, and processing region 220A may also include components of processing region 220B. Pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface, e.g., a body portion, of the pedestal. Pedestal 228 may include a heating element 232, e.g., a resistive heating element, which may heat and control the substrate temperature to a desired process temperature. Pedestal 228 may be further heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0024] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system to control the height and movement of the pedestal 228 within the processing region 220B. The stem 226 may further include a power interface for supplying power to the pedestal 228. The power box 203 may further include an interface for a power and temperature indicator, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to removably couple to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0025] A rod 230 may be included that extends through a passageway 224 formed in the bottom wall 216 of the processing region 220B and may be used to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively space the substrate 229 from the pedestal to facilitate exchange of the substrate 229 with a robot that is used to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0026] A chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled to the lid 204. The precursor delivery system 208 may include a precursor inlet passage 240 that may supply reactant and cleaning precursors to the processing region 220B through a dual channel showerhead 218. The dual channel showerhead 218 may include an annular base plate 248 having a shielding plate 244 disposed intermediate a faceplate 246. A radio frequency (“RF”) source 265 may be coupled to the dual channel showerhead 218, and the RF source 265 may provide power to the dual channel showerhead 218 to facilitate generating a plasma region between the faceplate 246 and the pedestal 228 of the dual channel showerhead 218. The dual channel showerhead 218 and / or faceplate 246 may include one or more openings to allow precursors to flow from the precursor delivery system 208 to the processing regions 220A and / or 220B. In some embodiments, the openings may include at least one of straight and conical openings. In some embodiments, an RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent RF power from being conducted to the lid 204. A shadow ring 206 may be disposed around the periphery of the pedestal 228 and engaged with the pedestal 228.

[0027] Optional cooling channels 247 may be formed in the annular base plate 248 of the precursor delivery system 208 to cool the annular base plate 248 during operation. A heat transfer fluid, such as water, ethylene glycol, or gas, may be circulated through the cooling channels 247 to maintain the base plate 248 at a predetermined temperature. A liner assembly 227 may be positioned in close proximity to the sidewalls 201, 212 of the chamber body 202 within the processing region 220B to prevent exposure of the sidewalls 201, 212 to the processing environment within the processing region 220B. The liner assembly 227 may include a circumferential pumping cavity 225, which may be coupled to a pumping system 264 configured to evacuate gases and byproducts from the processing region 220B and control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. The exhaust outlet 231 may be configured to allow gas to flow from the processing region 220 B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200 .

[0028] As described above, the present technique may form doped silicon-containing materials that may drive dopants into the underlying material after oxidation. Referring to FIG. 3 , exemplary operations of a method 300 of forming a semiconductor structure according to an embodiment of the present technique are shown. Method 300 may include one or more operations prior to beginning the method, including front-end processing, deposition, etching, polishing, cleaning, or other operations that may be performed before the described operations. For example, the method may begin after depositing several layers, such as several layers for fabricating a 3D DRAM structure. However, as explained above, it should be understood that the figure shows only one exemplary process that may use a process according to an embodiment of the present technique, and the description is not intended to limit the present technique to only this process. Some or all of the operations may be performed within a previously described chamber or system tool, or some or all of the operations may be performed in different chambers on the same system tool, and different chambers on the same system tool may include chambers in which operations of method 300 may be performed.

[0029] Method 300 may include several optional operations shown, which may or may not be explicitly related to some embodiments of the method according to the present technology. For example, many of the operations are described to provide a broader scope for structure formation but are not critical to the present technology, or many of the operations may be performed by alternative methodologies discussed further below. Method 300 describes the operations shown generally in FIGS. 4A-4D, and the illustrations in FIGS. 4A-4D are described with reference to the operations of method 300. It should be understood that FIGS. 4A-4D show only partial schematic views, and that a substrate may include any number of structural sections having alternative structural aspects that may still benefit from the aspects shown in the figures and the operations of the present technology.

[0030] Method 300 may or may not include optional operations to enhance the semiconductor structure for a particular fabrication operation. It should be understood that method 300 may be performed on any number of semiconductor structures or substrates 405 shown in FIG. 4A , including the exemplary structure on which oxidation-enhanced doping may be formed. As shown in FIG. 4A , substrate 405 may have several layers of material deposited thereon. Substrate 405 may be any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing.

[0031] Structure 400 may depict a partial view of a stack of alternating layers of materials, which in some embodiments may be used in 3D DRAM memory formation. As shown in FIG. 4A , structure 400 may include a material extending into a recess formed in substrate 405. This material may be silicon- and germanium-containing material 410. Extending from silicon- and germanium-containing material 410 may be silicon- and nitrogen-containing material 415, which may define a silicon channel of the structure, such as a silicon channel of a 3D DRAM structure. That is, the silicon channel may extend between individual portions of silicon- and nitrogen-containing material 415. The silicon channel may be characterized by a depth of greater than or about 300 nm, e.g., greater than or about 400 nm, greater than or about 500 nm, greater than or about 600 nm, greater than or about 700 nm, or even greater. The silicon channel may be characterized by a width or critical dimension of greater than or about 5 nm, e.g., greater than or about 25 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, or even greater.

[0032] In operation 305, the method 300 may include supplying a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber, such as the processing region of a chamber of the plasma system 200. The substrate 405 and previously discussed layers may be present in the substrate processing region of the semiconductor processing chamber when these deposition precursors flow into the chamber. The silicon-containing precursors that may be used in operation 305 may be or include any number of silicon-containing precursors. For example, any silicon-containing precursor for depositing a silicon-containing material, such as a doped silicon-containing material, may be used. By way of non-limiting example, in embodiments of the present technology, the silicon-containing precursor may be silane (SiH), disilane (SiH), trisilane (SiH), tetrasilane (SiH), or tetrasilane (SiH). 10 ), dichlorosilane (SiH2Cl2) or trichlorosilane (SiHCl3), or silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), dichlorosilane (SiH2Cl2), or trichlorosilane (SiHCl3). The flow rate of the silicon-containing precursor may be greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 2500 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 2500 sccm, greater than or about 5000 sccm, greater than or about 10000 sccm, or more than 10000 sccm.

[0033] The dopant precursor that may be used in operation 305 may be or include any number of dopant precursors. For example, any dopant precursor for depositing a doped silicon-containing material may be used. As a non-limiting example, in embodiments of the present technology, the dopant precursor may include phosphorus or boron, such as phosphorus or boron for forming doped source or drain regions. For example, the dopant precursor may be or may include phosphine (PH), arsine (AsH), nitrogen, (N), ammonia (NH), germane (GeH), borane (BH), diborane (BH), trimethylgallium (Ga(CH)), aluminum chloride (AlCl), trimethylaluminum (CHAl), or methylsilane (CHSiH). The flow rate of the dopant precursor may be greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1000 sccm, greater than or about 2500 sccm, greater than or about 5000 sccm, greater than or about 10000 sccm, or even higher. The flow rate of the dopant precursor may depend on the target doping concentration and other process conditions, such as temperature and pressure. However, due to the effects of the subsequent oxidation described herein, lower dopant precursor flow rates may be required compared to conventional epitaxial growth processes.

[0034] In optional operation 310, method 300 may include delivering an etchant precursor along with the silicon-containing precursor and the dopant precursor. The etchant precursor may maintain selective deposition of material. As previously discussed, structure 400 includes multiple materials, and delivering the etchant precursor may reduce and / or remove material undesirably deposited on other materials of structure 400. For example, by way of non-limiting example, any etchant precursor for reducing and / or removing material from silicon- and nitrogen-containing material 415 may be delivered along with the silicon-containing precursor and the dopant precursor. By way of non-limiting example, in embodiments of the present technology, the etchant precursor may include an oxygen-containing precursor or a chlorine-containing precursor. For example, the etchant precursor may be or include molecular oxygen (O), hydrogen chloride (HCl), or diatomic chlorine (Cl). However, in some embodiments, the etchant precursor may not include an oxygen-containing precursor to maintain the semiconductor processing chamber oxygen-free. By maintaining the semiconductor processing chamber oxygen-free, the silicon-containing material being deposited may be oxygen-free, which may increase the drive of dopants into the underlying material as discussed herein.

[0035] A carrier gas may be combined with the silicon-containing precursor and / or dopant precursor flowing into the substrate processing region of the substrate processing chamber. In embodiments, the carrier gas may be one or more of helium, argon, molecular nitrogen (N), and molecular hydrogen (H), among others. The carrier gas may benefit the mechanical properties of the film. In addition, the carrier gas may also facilitate easier plasma ignition.

[0036] After delivering the silicon-containing precursor and the dopant precursor to the processing region, the method 300 may include forming a plasma of the silicon-containing precursor and the dopant precursor within the processing region. The plasma of the silicon-containing precursor and the dopant precursor may be generated at a plasma power suitable for depositing a doped silicon-containing material. Generating a plasma of the silicon-containing precursor and the dopant precursor may increase the deposition rate and promote interaction between the precursors, thereby increasing the concentration of boron or phosphorus in the deposited material.

[0037] In operation 315, the method 300 may include contacting a substrate 405, which may be a silicon-containing material, with a silicon-containing precursor and a dopant precursor. As shown in FIG. 4B, in operation 320, the method 300 may include forming a doped silicon-containing material 420. The doped silicon-containing material 420 may be formed on the silicon-containing material of the substrate 405. The doped silicon-containing material may be formed by chemical vapor deposition (CVD), which may include atomic layer epitaxy (ALE). Chemical vapor deposition includes the use of many techniques, such as plasma-assisted CVD (PACVD), plasma-enhanced CVD (PECVD), atomic layer CVD (ALCVD), metalorganic or metalorganic CVD (OMCVD or MOCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire CVD (HWCVD), reduced pressure CVD (RP-CVD), and ultra-high vacuum CVD (UHV-CVD).

[0038] The thickness of the doped silicon-containing material 420 can affect the doping depth of the dopant into the underlying material, such as the carbon-containing material of the substrate 405. A greater thickness of the doped silicon-containing material 420 can further drive the dopant to a greater doping depth into the underlying material and / or increase the dopant concentration in the underlying material. In embodiments, the thickness of the doped silicon-containing material 420 can be greater than or about 5 nm, e.g., greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, greater than or about 35 nm, greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm, or even greater than or about 50 nm. Although greater thicknesses are contemplated, a thickness of less than or about 50 nm or less than or about 25 nm can be sufficient.

[0039] During the formation of the doped silicon-containing material 420, by-product material 425 may deposit on other materials of the structure 400, such as the silicon- and nitrogen-containing material 415. As previously discussed, an etchant precursor may be supplied along with the silicon-containing precursor and the dopant precursor, but some deposition of material on surrounding materials may still occur. The by-product material 425, or defect material, may include polycrystalline or amorphous silicon-containing material.

[0040] The deposition temperature of the material can affect deposition on exposed material. Thus, in some embodiments, the formation of doped silicon-containing materials may be carried out at temperatures less than or about 1200° C., and the process may be carried out at temperatures less than or about 1100° C., less than or about 1000° C., less than or about 900° C., less than or about 800° C., less than or about 700° C., less than or about 600° C., less than or about 500° C., less than or about 400° C., less than or about 300° C., less than or about 200° C., or lower.

[0041] Deposition pressure can also affect deposition on exposed materials, for example, higher pressure can increase the directionality of silicon-containing and dopant precursors. Thus, in some embodiments, forming a carbon-containing material may include a particular material provided at a pressure of less than or about 760 Torr, or less than or about 700 Torr, less than or about 600 Torr, less than or about 500 Torr, less than or about 400 Torr, less than or about 300 Torr, less than or about 200 Torr, less than or about 100 Torr, less than or about 50 Torr, less than or about 10 Torr, less than or about 5 Torr, less than or about 5 Torr, less than or about 1 Torr, less than or about 5 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 100 mTorr, less than or about 1 mTorr, less than or about 0.1 mTorr, or even lower. Higher pressures, such as pressures greater than 760 Torr, may result in reduced selectivity. Lower pressures, such as pressures below 0.1 mTorr, may result in reduced doping concentrations, and therefore the pressure may be maintained between about 0.1 mTorr and about 760 Torr, or in other ranges between these values.

[0042] As shown in FIG. 4C , in operation 325, the method 300 may include oxidizing the substrate 405. In embodiments, the method 300 may include transferring the substrate 405 from a first chamber to a second chamber before oxidizing the substrate 405. However, it is contemplated that the substrate 405 may be maintained in a single chamber for both deposition and oxidation. The silicon-containing precursor and / or dopant precursor may continue to be supplied during the oxidation process in operation 325. The continued supply of the silicon-containing precursor and / or dopant precursor allows the silicon- and oxygen-containing material 430 to form on top of the previously deposited doped silicon-containing material 420. Alternatively, if the silicon-containing precursor is not supplied, the silicon- and oxygen-containing material 430 may form by interaction with the underlying doped silicon-containing material 420. Oxidizing the structure 400 including the substrate 405 may drive dopant materials, such as phosphorus or boron, into the material underlying the doped silicon-containing material 420, e.g., the silicon-containing material of the substrate 405. The formation of silicon- and oxygen-containing material 430 may result in bonding with doped silicon-containing material 420. This bond may be an Si-O bond, which may have a lower activation energy than the bond between silicon and the dopant. This lower activation energy allows the dopant, such as phosphorus or boron, to be released and driven into the underlying material. During the oxidation of substrate 405, by-product material 425 may also be oxidized to form oxidized by-product material 435.

[0043] Oxidizing the substrate 405 in operation 325 may include contacting the substrate 405 with an oxygen-containing precursor or treating the substrate 405 with a laser. In embodiments where oxidizing the substrate 405 includes contacting the substrate 405 with an oxygen-containing precursor, the oxygen-containing precursor may be any oxygen-containing precursor operable to form an oxidized material. For example, the oxygen-containing precursor may be steam or water (HO), molecular oxygen (O), or any other oxygen-containing precursor used in semiconductor processing. The oxygen-containing precursor, which may or may not be delivered together with the silicon-containing precursor, may form the silicon- and oxygen-containing material 430 on the doped silicon-containing material 420. In embodiments where oxidizing the substrate 405 includes treating the substrate 405 with a laser, ultraviolet (UV) pulsed laser excitation in an oxygen environment may form the silicon- and oxygen-containing material 430 on the doped silicon-containing material 420. Contacting the substrate 405 with an oxygen-containing precursor or treating the substrate 405 with a laser may both form a silicon- and oxygen-containing material 430 on the doped silicon-containing material 420. As previously discussed, forming and bonding the silicon- and oxygen-containing material 430 on the doped silicon-containing material 420 may drive dopants into the underlying material.

[0044] Similar to the doped silicon-containing material 420, the thickness of the silicon- and oxygen-containing material 430 can also affect the doping depth of the dopant into the underlying material, such as the carbon-containing material of the substrate 405. A greater thickness of the silicon- and oxygen-containing material 430 can further drive the dopant to a greater doping depth into the underlying material and / or increase the dopant concentration in the underlying material. In embodiments, the thickness of the silicon- and oxygen-containing material 430 can be greater than or about 10 nm, e.g., greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, greater than or about 100 nm, or more. Although larger thicknesses are contemplated, a thickness of less than or about 50 nm or less than or about 20 nm may be sufficient. In embodiments, the thickness of silicon- and oxygen-containing material 430 may be at least twice the thickness of doped silicon-containing material 420, which may allow silicon- and oxygen-containing material 430 and the resulting bonds to drive the dopant material into the underlying material.

[0045] The oxidation temperature of a material can affect dopant incorporation on underlying materials, such as substrate 405. Thus, in some embodiments, oxidation of substrate 405 may be performed at temperatures greater than or about 500°C, and the oxidation process may be performed at temperatures greater than or about 550°C, greater than or about 600°C, greater than or about 650°C, greater than or about 700°C, greater than or about 750°C, greater than or about 800°C, greater than or about 850°C, greater than or about 900°C, greater than or about 950°C, greater than or about 1000°C, or higher. In embodiments, oxidation of substrate 405 may be performed at a temperature between about 650°C and about 750°C. At higher oxidation temperatures, it may be easier to oxidize structure 400 and form silicon- and oxygen-containing material 430. However, thermal budget may limit the temperature at which the oxidation process may be carried out. Thus, in some embodiments, oxidation of substrate 405 may be carried out at temperatures greater than or about 1000°C, and the oxidation process may be carried out at temperatures greater than or about 950°C, greater than or about 950°C, greater than or about 900°C, greater than or about 850°C, greater than or about 850°C, greater than or about 800°C, greater than or about 750°C, greater than or about 700°C, greater than or about 650°C, greater than or about 600°C, greater than or about 550°C, greater than or about 500°C, or lower. However, lower oxidation temperatures may slow the formation of silicon- and oxygen-containing material 430, which may limit the driving of dopants into the underlying material.

[0046] The oxidation pressure can also affect dopant incorporation on the underlying material, such as the substrate 405. The oxidation pressure may be maintained at greater than or about 1 Torr, greater than or about 5 Torr, greater than or about 10 Torr, greater than or about 50 Torr, greater than or about 100 Torr, greater than or about 200 Torr, greater than or about 300 Torr, greater than or about 400 Torr, greater than or about 500 Torr, greater than or about 600 Torr, greater than or about 700 Torr, greater than or about 760 Torr, or even higher. Higher pressures, which may indicate higher oxidizer flow rates, may increase the oxidation rate. The increased oxidation rate may further drive dopants into the underlying material, which may increase doping depth and / or concentration.

[0047] The oxidation in operation 325 may continue for a time sufficient to form the silicon- and oxygen-containing material to a desired thickness. In embodiments, the oxidation may continue for more than or about 1 minute, e.g., more than or about 5 minutes, more than or about 10 minutes, more than or about 15 minutes, more than or about 20 minutes, more than or about 25 minutes, more than or about 30 minutes, more than or about 35 minutes, more than or about 40 minutes, more than or about 45 minutes, more than or about 50 minutes, more than or about 55 minutes, more than or about 60 minutes, or more. However, at longer durations, the increased oxidation duration may highly oxidize the substrate 405 or damage the structure 400 due to thermal history. Thus, in some embodiments, oxidation may continue for less than or about 30 minutes, e.g., less than or about 25 minutes, less than or about 20 minutes, less than or about 15 minutes, less than or about 10 minutes, or less than or about 10 minutes.

[0048] After the oxidation process, the doping depth within the silicon-containing material of the substrate 405 can be greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, greater than or about 35 nm, greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm, greater than or about 55 nm, greater than or about 60 nm, greater than or about 65 nm, greater than or about 70 nm, greater than or about 75 nm, greater than or about 80 nm, or even greater. The doping depth and concentration provided by this embodiment can be significantly increased compared to conventional techniques that do not perform a post-deposition oxidation step. Conventional techniques may limit the doping depth to less than or equal to 10 nm. This increased doping depth and concentration can result in low resistivity and ohmic contact with metal silicides, such as silicon channels and contacts in subsequently formed 3D DRAM structures.

[0049] As shown in FIG. 4D , in operation 330, the method 300 may include etching the silicon- and oxygen-containing material 430. In embodiments, the method 300 may include transferring the substrate 405 from a first chamber to a second chamber prior to etching. However, it is contemplated that the substrate 405 may be maintained in one chamber for both oxidation and etching. The etching operation may include any wet or dry etching process. For example, a wet etching process using a fluorine-containing precursor, such as dilute hydrofluoric acid (DHF), may be performed to etch and remove the oxidized doped silicon-containing material 420. The underlying doped silicon-containing material 420 may act as an etch stop and may remain after operation 330. In embodiments, a dry etching operation may be performed using a fluorine-containing precursor, such as difluoromethane (CHF), or any other fluorine-containing precursor. To maximize etch selectivity between the silicon- and oxygen-containing material 430 and other materials of the structure 400, such as the silicon- and nitrogen-containing material 415, the fluorine-containing precursor used in the dry etching operation may include a fluorocarbon with a high carbon-fluorine ratio, such as greater than 1:2. While etching the oxidized doped silicon-containing material 420, oxidized by-product material 435 may also be removed. For example, this carbon-fluorine ratio may be greater than 1:2, such as SiO2:SiN x The etch selectivity may be maintained at greater than 5:1 or even greater than 10:1.

[0050] Compared to conventional techniques, the present embodiments may be successful in further driving dopants into the underlying material. Conventional techniques also generate unwanted by-product material on other materials during the deposition of doped material that drives into the underlying material. In addition to further driving dopants into the underlying material through the oxidation step, the present embodiments may also oxidize the unwanted by-product material. During a subsequent etching or removal operation, this oxidized unwanted by-product material may also be removed, which may result in a cleaner, more desirable structure.

[0051] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it should be understood that certain embodiments may be practiced without some of these details or may be practiced with additional details.

[0052] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be taken as limiting the scope of the technology.

[0053] Where a range of values ​​is provided, unless otherwise clear from the context, it is understood that each intervening value, down to the smallest decimal point of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Narrower ranges between any stated or intervening value in a stated range and any other stated or intervening value in that stated range are also encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded from the range, and each range in which either limit, neither limit, or both limits are included in the smaller range is also encompassed within the technology, subject to the specifically excluded limit in the stated range. If the stated range includes one or both of these limits, ranges excluding either or both of those included limits are also included.

[0054] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a material" includes a plurality of such materials, reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0055] Furthermore, as used in this specification and the appended claims, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)" and "including" are intended to specify the presence of stated features, integers, components or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, acts or groups.

Claims

1. delivering a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the semiconductor processing chamber and a silicon-containing material is formed on the substrate; contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor; forming a doped silicon-containing material on the silicon-containing material; oxidizing the substrate, wherein the oxidizing forms an oxidized doped silicon-containing material; and Etching the oxidized doped silicon-containing material; and A semiconductor processing method comprising:

2. 10. The semiconductor processing method of claim 1, wherein a pressure within the semiconductor processing chamber is maintained at less than or about 760 Torr.

3. 10. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained below or at about 1200°C.

4. The silicon-containing precursor is silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), dichlorosilane (SiH 2 Cl 2 ) or trichlorosilane (SiHCl 3 10. The semiconductor processing method of claim 1, comprising:

5. The semiconductor processing method of claim 1 , wherein the dopant precursor comprises phosphorus.

6. The semiconductor processing method of claim 1 , wherein the dopant precursor comprises boron.

7. providing an etchant precursor together with the silicon-containing precursor and the dopant precursor, the etchant precursor comprising an oxygen-containing precursor or a chlorine-containing precursor.

10. The semiconductor processing method of claim 1, further comprising:

8. 10. The semiconductor processing method of claim 1, wherein oxidizing the substrate comprises contacting the substrate with an oxygen-containing precursor or treating the substrate with a laser.

9. 10. The semiconductor processing method of claim 1, wherein oxidizing the substrate increases the doping depth in the silicon-containing material to greater than or about 10 nm.

10. removing defective silicon-containing material formed on a silicon nitride material formed on the substrate; 10. The semiconductor processing method of claim 1, further comprising:

11. delivering a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber, wherein a silicon-containing material is deposited on a substrate disposed in the semiconductor processing chamber, the silicon-containing material comprising a silicon channel of a 3D DRAM structure; contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor; forming a doped silicon-containing material on the silicon-containing material; oxidizing the substrate, wherein the oxidizing forms an oxidized doped silicon-containing material; and A semiconductor processing method comprising:

12. 12. The semiconductor processing method of claim 11, wherein the doped silicon-containing material is formed by chemical vapor deposition.

13. The dopant precursor is phosphine (PH 3 ), arsine (AsH 3 ), nitrogen, (N 2 ), ammonia (NH 3 ), Germanium (GeH 4 ), Borane (BH 3 ), diborane (B 2 H 6 ), trimethylgallium (Ga(CH 3 ) 3 ), aluminum chloride (AlCl 3 ), trimethylaluminum (C 6 H1 5 Al) or methylsilane (CH 3 SiH 3 12. The semiconductor processing method of claim 11, comprising:

14. the 3D DRAM structure comprising: silicon- and germanium-containing materials deposited above and below the silicon-containing material; a silicon and nitrogen-containing material extending from the silicon and germanium-containing material; and 12. The semiconductor processing method of claim 11, further comprising:

15. the silicon channels extend between the individual portions of the silicon and nitrogen-containing material; the silicon channel is characterized by a depth of greater than or about 300 nm and a width of greater than or about 5 nm; 15. The semiconductor processing method of claim 14.

16. removing the oxidized doped silicon-containing material from the silicon-containing material; 12. The semiconductor processing method of claim 11, further comprising:

17. removing silicon-containing by-products from said silicon and nitrogen-containing material; 15. The semiconductor processing method of claim 14, further comprising:

18. a silicon-containing substrate; a silicon- and germanium-containing material extending into a recess formed in the silicon-containing substrate; a silicon and nitrogen containing material extending from the silicon and germanium containing material, the silicon and nitrogen containing material defining a channel; a doped silicon-containing material in the channel extending from the silicon-containing substrate; and 1. A semiconductor structure comprising:

19. 20. The semiconductor structure of claim 18 wherein said silicon-containing substrate is doped with dopants from said doped silicon-containing material to a doping depth of greater than or about 10 nm.

20. 20. The semiconductor structure of claim 18 wherein said doped silicon-containing material is formed by chemical vapor deposition.

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