Optimizing reactor design using DC bias pulsing on the pedestal

Abstract

The plasma processing system includes a main plasma chamber configured to generate a main plasma, the plasma chamber including a lower electrode located within an electrostatic chuck (ESC). The system includes a direct current (DC) generator that supplies a pulsed DC bias signal to the lower electrode over a plurality of cycles. The plasma processing system includes a neutralization source external to the main plasma chamber, the neutralization source configured to supply a neutralization current to the main plasma chamber, the neutralization current electrically coupled to the main plasma.

Description

[Technical Field]

[0001] The present embodiments relate to semiconductor fabrication, and more particularly to a system and method for minimizing neutralization time in a plasma processing system using DC bias pulsing to a pedestal by effectively maximizing the effective counter electrode area seen by the plasma, thereby achieving high duty cycle operation of the DC bias signal while maintaining a monoenergetic IEDF or ion population. [Background technology]

[0002] Many modern semiconductor chip fabrication processes, such as plasma etching processes, are performed in a plasma processing chamber in which a substrate (e.g., a wafer) is supported on an electrostatic chuck (ESC). In a plasma etching process, the wafer is exposed to a plasma generated in the plasma processing volume. The plasma contains various types of radicals, electrons, and positive and negative ions. Various chemical reactions of the radicals, electrons, positive ions, and negative ions are used to etch features, surfaces, and materials of the wafer.

[0003] For example, when a process gas is supplied to a plasma processing chamber, a radio frequency (RF) signal is applied to at least one electrode of the plasma processing chamber to provide power and form an electric field between the electrodes. The process gas is converted into a plasma by the RF signal, thereby performing plasma etching on a predetermined layer disposed on a wafer. A bias signal may be applied to control the ion distribution and / or ion density. However, the effectiveness of the bias signal is limited by the wafer's charging (e.g., due to positive ions) and its discharge (e.g., electron current to the chamber wall limited by Bohm flux), which can lead to undesirable ion energy distribution. A means to effectively increase the discharge rate of the wafer is desired.

[0004] It is in these situations that embodiments of the present disclosure arise. Summary of the Invention

[0005] The present embodiments relate to a method and apparatus for minimizing neutralization time in a plasma processing system utilizing DC bias pulsing to a pedestal by effectively maximizing the effective counter electrode area seen by the plasma. In this manner, effectively maximizing the counter electrode area enables high performance DC bias signal pulsing to achieve a monoenergetic ion energy distribution function (IEDF) or ion population. Several inventive embodiments of the present disclosure are described below.

[0006] An embodiment of the present disclosure provides a plasma processing system. The plasma processing system includes a main plasma chamber configured to generate a main plasma. The plasma chamber includes a lower electrode located within an electrostatic chuck (ESC). The plasma processing system includes a direct current (DC) generator that supplies a pulsed DC bias signal to the lower electrode over a plurality of cycles. The plasma processing system includes a neutralization source external to the main plasma chamber. The neutralization source is configured to supply a neutralization current to the main plasma chamber. The neutralization current is electrically coupled to the main plasma.

[0007] Another embodiment of the present disclosure provides another plasma processing system configured to use two plasmas. The two-plasma plasma processing system includes a main plasma chamber configured to generate a main plasma, the main plasma chamber including a lower electrode located within an electrostatic chuck (ESC). The two-plasma plasma processing system includes a direct current (DC) generator that supplies a pulsed DC bias signal to the lower electrode over multiple cycles. The pulsed DC bias signal has an on period and an off period in each of the multiple cycles. The two-plasma plasma processing system includes a secondary plasma chamber external to the main plasma chamber, the secondary plasma chamber configured to generate a secondary plasma that is more negatively charged than the main plasma. In some embodiments, the space potential (e.g., negative charge) on the secondary plasma can vary over time, such as in a manner synchronized with the pulsed DC bias signal. The two-plasma plasma processing system includes a pump for delivering the secondary plasma to the main plasma chamber to provide a neutralizing current electrically coupled to the main plasma.

[0008] Yet another embodiment of the present disclosure provides a method for plasma processing. The method includes generating a main plasma in a main plasma chamber, the main plasma chamber including a lower electrode located within an electrostatic chuck (ESC). The method includes generating a pulsed DC bias signal delivered to the lower electrode over a plurality of cycles. The method includes providing a neutralization current generated from a neutralization source external to the main plasma chamber. The neutralization current is electrically coupled to the main plasma.

[0009] These and other advantages will be appreciated by those skilled in the art upon reading the entire specification and claims. [Brief explanation of the drawings]

[0010] The embodiments can be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0011] [Figure 1] FIG. 1 illustrates an embodiment of a capacitively coupled plasma (CCP) processing system utilized for etching operations, according to an embodiment of the present disclosure.

[0012] [Figure 2] FIG. 2 illustrates a plasma processing system having a large wall area to increase electron current discharge to the chamber walls, thereby increasing the discharge and / or neutralization of positive ions on the surface of the wafer, in accordance with one embodiment of the present disclosure.

[0013] [Figure 3A] FIG. 3A illustrates a plasma processing system including chamber wall features that increase the effective area of ​​the chamber wall for the purpose of increasing the discharge and / or neutralization of positive ions on the surface of the wafer, according to one embodiment of the present disclosure.

[0014] [Figure 3B] FIG. 3B illustrates various configurations of chamber wall features according to embodiments of the present disclosure. [Figure 3C-1] 3C-1 are diagrams illustrating various configurations of chamber wall features according to embodiments of the present disclosure. [Figure 3C-2] 3C-2 are diagrams illustrating various configurations of chamber wall features according to embodiments of the present disclosure. [Figure 3D] FIG. 3D illustrates various configurations of chamber wall features according to embodiments of the present disclosure.

[0015] [Figure 4A] FIG. 4A illustrates a plasma processing system including an external neutralization source configured to provide a neutralization current that effectively discharges and / or neutralizes positive ions on the surface of a wafer, according to one embodiment of the present disclosure.

[0016] [Figure 4B]FIG. 4B illustrates a plasma processing system utilizing two plasmas, including a secondary plasma supplied by an externally coupled plasma source, in accordance with one embodiment of the present disclosure.

[0017] [Figure 4C] FIG. 4C illustrates a plasma processing system including an external neutralization source configured as an annular ring surrounding the main plasma chamber, in accordance with one embodiment of the present disclosure, where the neutralization source provides a neutralization current to effectively discharge and / or neutralize positive ions on the surface of the wafer.

[0018] [Figure 5] FIG. 5 is a flow diagram illustrating a method for plasma processing configured to increase the discharge and / or neutralization of positive ions on the surface of a wafer, according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] Although the following detailed description contains many specific details for purposes of illustration, those skilled in the art will appreciate that many variations and modifications to the following details are within the scope of the present disclosure. Accordingly, the aspects of the disclosure described below are set forth without any loss of generality to, and without imposing limitations on, the scope of the claims that follow this description.

[0020] Generally speaking, various embodiments of the present disclosure describe methods and apparatus for providing arbitrarily high duty cycle operation while maintaining a monoenergetic IEDF (e.g., an ion population generated at approximately a desired energy level) in plasma processing systems providing DC pulsing applications. Generally, limitations on the maximum duty cycle of a DC bias signal are influenced by wafer charging (e.g., by positive ions) during the on-period of the DC bias signal's cycle and wafer discharging during the off-period of the DC bias signal's cycle. In particular, the discharge rate of positive ions from the wafer's surface is limited by the electron flux delivered to the wafer during the pulse-off time (i.e., the off-period) of the DC bias signal. For illustrative purposes, a negative DC square pulse can be applied to the wafer chuck electrode during the on-period. Ions swarm to the wafer surface according to the Bohm current. The high negative wafer surface potential momentarily lowers the plasma potential (the on-period negative DC square pulse duration can be several orders of magnitude longer than the RF period). This action propels an excess amount of electrons toward the chamber walls, where they remain as negative electrostatic charge. The negative electrostatic charge on the surface is "different" from the surface potential of the chamber walls, which is the instantaneous floating surface potential. The floating surface potential is determined, in part, by the instantaneous plasma potential, the electron temperature (assuming a single-temperature Maxwellian plasma), and the wall capacitance (the inverse of the wall dielectric coating thickness). Typically, during the "off" period of a pulsing scheme (e.g., a DC bias signal), a high positive DC square pulse can be applied (i.e., switching from a negative DC square pulse). At the onset of the high positive DC square pulse, the wafer surface potential approximately follows the square pulse to a high positive potential (i.e., due to capacitive coupling). Due to the high electron mobility, plasma electrons immediately swarm to the wafer surface. This action immediately raises the plasma potential (also called the "boundary-driven plasma potential"). Typically, such an instantaneous artificial plasma potential is several volts higher than the wafer surface potential, according to global models. Therefore, plasma electrons (i.e., electrons in the energy tail) still swarm and neutralize wafer surface ions.The problem is that if the negative static charge on the chamber walls is not completely neutralized during the off-period, it continues to grow over several pulsing periods until an equilibrium state is reached. The net effect when equilibrium is reached is that the ion energy of the narrow IEDF becomes significantly lower than the negative DC square pulse voltage level, rendering DC pulsing ineffective. In an embodiment, a solution involves having a highly asymmetric reactive ion (RIE) chamber in which the area of ​​the chamber walls grounded (e.g., capacitively) is much larger than the wafer chuck area. Generally, for a 90% duty cycle, the chamber wall area is approximately 10 times the wafer chuck area. During the on-period, negative charges (e.g., electrons) accumulate as static charges on the chamber walls (on the insulator surface), and these negative charges (e.g., electrons) do not dissipate during the off-period. Generally, plasma ions (e.g., positive ions) are required to remove the negative static charge accumulated on the chamber walls. The Bohm current (or current density) is constant for the plasma. Therefore, the larger the chamber wall area, the faster the ion current can neutralize the negative electrostatic charge accumulated on the chamber wall. In other embodiments, because very large forces (e.g., atomic scale for a given bond potential) are required to strip the electrostatic charge from the chamber wall, electrostatic charge removal can be achieved at the quantum level, i.e., by the photoelectric effect. In one embodiment, a high-intensity pulsed lamp can be used during the off period to eject static surface electrons as photoelectrons.

[0021] Embodiments of the present disclosure overcome this limitation on the maximum duty cycle of the DC bias signal, enabling previously unavailable process regimes. In particular, embodiments of the present disclosure enable minimizing neutralization time in high-performance DC pulsed bias plasma processing systems by effectively maximizing the opposing electrode area to achieve and / or maintain a mono-energy IEDF.

[0022] Advantages of various embodiments include methods and apparatus configured to provide arbitrarily high duty cycle operation of a pulsed DC bias signal while maintaining a mono-energetic IEDF (e.g., ion population at a desired energy level) in a plasma processing system configured for DC pulsing applications. In embodiments, the duty cycle (percentage of on-time in one cycle) of the pulsed DC bias signal is greater than 40%, or greater than 50%, or greater than 60%, or greater than 70%, or greater than 80%, or greater than 90%.

[0023] Given the above general understanding of various embodiments, illustrative details of the embodiments will now be described with reference to various drawings. In one or more figures, like-numbered elements and / or components are intended to generally have the same configuration and / or function. Furthermore, the figures may not be drawn to scale, but are intended to illustrate and emphasize novel concepts. It will be apparent that the present embodiments can be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present embodiments.

[0024] FIG. 1 illustrates an exemplary substrate processing or reactor system 100 that may be used to process a wafer to include etched features in a masked substrate, such as when performing a high-aspect ratio dielectric etch and / or when depositing or forming a film on the wafer, in accordance with one embodiment of the present disclosure. For example, the substrate processing system 100 may be used to process a substrate or wafer 101, such as by performing plasma processing of the wafer 101, and, depending on the design, may be modified to generate plasma by various methods, such as capacitively coupled plasma (CCP) or inductively coupled plasma (ICP), which includes an inductive coil used to excite the plasma instead of an electrode. For simplicity and clarity, embodiments of the present disclosure configured to minimize neutralization time in processing operations utilizing DC bias pulsing on the pedestal are described as being implemented in a CCP processing system, although it is understood that other embodiments are also suitable for implementation in other plasma processing systems (e.g., ICP, etc.). It is also understood that other configurations of plasma processing systems may utilize various combinations of high-frequency RF power, low-frequency RF power, and / or DC power to supply power, and each power source may be pulsed or non-pulsed.

[0025] As shown, the system 100 includes a plasma chamber 172, which is a CCP chamber. The plasma chamber 172 includes a substrate support or pedestal 140, such as an electrostatic chuck (ESC) or a magnetic chuck. A lower electrode 146 may be embedded within the pedestal 140. A substrate 101 may be placed on the pedestal 140 for processing, and the substrate 101 is processed to fabricate one or more semiconductor chips. An upper electrode 171 of the plasma chamber 172 is disposed facing the pedestal. As shown, the upper electrode may be grounded to facilitate RF energy return. In other embodiments, the upper electrode 171 may be coupled to an RF power source (e.g., to provide radio frequency power). A gap exists between the upper electrode 171 and the lower electrode 146, forming a process volume in which a plasma 178 can form. A gas pump (not shown) may be used to remove gases and byproducts from the plasma chamber 172.

[0026] A control module 110 is configured to operate the substrate processing system 100 by executing process input and control 108. In one embodiment, the control module 110 is connected to generators (e.g., main RF generator 174, DC source generator 184), gas sources 182, and other components. The controller 110 includes a processor, memory, software logic, hardware logic, and input / output subsystems that communicate with, monitor, and control the plasma processing system 100. Depending on the process being performed, the control module 110 controls the delivery of process gases from the gas sources 182 to achieve designed process conditions. The selected gases are then distributed within a volume defined between the upper electrode 171 and the wafer 101 placed on the pedestal 140. As an example of plasma formation, after one or more signals (e.g., RF, DC, etc.) are supplied to the lower electrode 146 and process gases are injected into the plasma processing chamber 172, a plasma 178 is formed between the upper electrode 171 and the pedestal 140. The plasma 178 can be used to etch the surface of the wafer 101. In particular, the process input and control 108 can include a process recipe, such as power levels, timing parameters, process gases, mechanical movement of the wafer 101, etc., for etching features in the stack of the wafer 101 and / or depositing or forming a film on the wafer 101. In particular, the control module 110 can be configured to operate the substrate processing system 100 to perform etching of high aspect ratio features in a stack of masked substrates, including adjusting the composition of the etch chemistry at various cycling stages, as well as adjusting pulsing parameters of the RF power source 174 (e.g., source generator) and the pulsed DC bias power source 184.

[0027] The source RF power supply 174 (e.g., a source power generator) is coupled to an impedance matching network 176, which is further coupled to the plasma chamber 172. The matching network enables dynamic adjustment of the power supplied to the lower electrode 146 by matching the impedance between the load (e.g., the plasma chamber and any connecting cables) and the source (e.g., the source RF power supply and any connecting cables). In particular, the impedance matching network 176 is coupled to the lower electrode 146, which is located within the pedestal 140 (e.g., an ESC). The source RF power supply 174 is typically used to generate a plasma 178 using a process gas delivered from a gas source 182. For example, the source RF power supply 174 may be a high-frequency (HF) RF generator that supplies power via a sine wave or alternating current (AC) signal (i.e., a sinusoidal variable voltage signal) and may be further configured to generate a high-frequency (HF) RF signal in the range of 13 megahertz (MHz) to 120 MHz. For example, the HF frequency may be a baseline frequency of 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz. In one embodiment, the source RF power supply 174 provides pulsed RF power.

[0028] The DC power supply 184 provides a pulsed DC bias signal. In particular, a constant voltage DC signal can be pulsed to provide the pulsed DC bias signal. The pulsed bias voltage is applied to the lower electrode to attract ions to the wafer 101 positioned on the pedestal 140 and / or to control ion distribution. In one embodiment, the pulsed DC bias signal is provided to the matching network 176, while in another embodiment, the pulsed DC bias signal bypasses the impedance matching network 176. In either case, the RF signal from the source RF power supply 174 is combined with the pulsed DC bias signal from the DC power supply 184 to drive the lower electrode 146 to generate the plasma 178.

[0029] 2 illustrates a plasma processing system 200 having a large wall area to increase electron current discharge to the chamber walls, thereby increasing the discharge and / or neutralization of positive ions on the surface of the wafer, in accordance with one embodiment of the present disclosure. As previously described, the plasma processing system 200 utilizes DC bias pulsing to the pedestal 140 to achieve monoenergetic ion excitation of ions at the wafer surface (e.g., controllable monoenergetic IEDF at a desired energy level).

[0030] In particular, plasma processing system 200 includes, in part, a chamber 210 configured to generate plasma 178, a pedestal 140 configured to support wafer 101, and a pump port 220 configured to evacuate gases and / or by-products from chamber 210. Plasma processing system 200 may be similar to plasma processing system 100 of FIG. 1, such that both systems are configured for plasma processing (e.g., generating plasma using a CCP chamber, an ICP chamber, etc.), and like components are represented by like reference numerals. However, plasma processing system 200 includes chamber 210 that is larger relative to the surface of wafer 101 than chamber 172 of FIG. 1.

[0031] In particular, without wishing to be bound by theory or mechanism of action, it is believed that control of the IEDF at a given energy level is limited by the maximum duty cycle of the pulsed DC bias signal, which is correlated with the area ratio between the wafer 101 and the chamber 210. Steady-state operation of the pulsed DC bias signal to generate a monoenergetic ion population requires that the net charge at the wafer does not change over time, despite the presence of a DC component in the bias drive circuit. This requires that the ion flux be nearly or exactly balanced with the electron flux at the wafer surface during each pulse cycle of the DC bias signal. For example, during the off period of each cycle of the DC bias signal, positive ions on the wafer surface are discharged to the wall through a Bohm flux or current (flow of positive ions). In particular, the area ratio indicates the level of asymmetry between the lower and upper electrodes, or between the surface area of ​​the wafer 101 and the chamber 210. More specifically, a desired increase in the maximum duty cycle can be achieved by increasing the asymmetry between the wafer and the chamber, and more specifically, by increasing the surface area of ​​the chamber 210 for a given wafer size. That is, the chamber 210 is intentionally made larger (e.g., more than 10 times larger) relative to the surface of the wafer 101 to facilitate rapid discharge of negative static charge on the chamber walls during the off-period of the pulsed DC bias signal, and charging of the chamber walls (i.e., accumulation of negative static charge on the walls) occurs during the previous on-period of the pulsed DC bias signal. In this way, the negative static charge accumulated during the previous on-period is "neutralized" during the subsequent off-period. For example, the area ratio between the surface area of ​​the chamber 210 and the wafer surface can range from 2:1 to greater than 10:1, including area ratios of greater than 2:1, greater than 3:1, greater than 4:1, greater than 5:1, greater than 6:1, greater than 7:1, or greater than 10:1.In particular, increasing the area ratio increases the Bohm current from the plasma 178 (e.g., particularly at the wafer surface) to the walls of the chamber 210 (e.g., providing a larger ground electrode), thereby minimizing the neutralization time of positive ions at the surface of the wafer (e.g., minimizing the off period of each cycle of the pulsed DC bias signal), which in turn corresponds to an increase in the duty cycle of the pulsed DC bias signal.

[0032] Generally, the Bohm current to the wall discharges the negative (electron) electrostatic charge accumulated during the previous ON period. Additionally, during the subsequent OFF period, the wafer chuck can be swung to a positive voltage, resulting in plasma electrons swarming the wafer surface and neutralizing the positive ions accumulated on the wafer surface during the previous ON period. This process is fast and easy to implement. In particular, the plasma electrons swarming the wafer surface originate from a high-energy tail population, which can easily cross the wafer sheath to reach the wafer surface and neutralize the previously accumulated positive ions. Although this electron population is very small compared to the bulk of the Maxwellian distribution, even in collisionless conditions, particularly those that do not account for electron-electron thermalization and electron-neutral thermalization, the depleted tail population is replenished with electrons within a fraction of a nanosecond, and the electron flux continues across the wafer sheath. In other words, the tail population remains essentially unchanged.

[0033] 3A illustrates a plasma processing system 300A including chamber wall features that increase the effective area of ​​the chamber walls for the purpose of increasing the discharge and / or neutralization of positive ions on the surface of the wafer, in accordance with one embodiment of the present disclosure. As previously described, the plasma processing system 300A utilizes DC bias pulsing on the pedestal to achieve monoenergetic ion excitation of ions at the wafer surface (e.g., controllable monoenergetic IEDF at a desired energy level).

[0034] In particular, plasma processing system 300A includes, in part, a chamber 310 configured to generate plasma 178, a pedestal 140 configured to support wafer 101, and a pump port 320 configured to evacuate gases and / or by-products from chamber 310. Plasma processing system 300A may be similar to plasma processing system 100 of FIG. 1, and thus both systems are configured for plasma processing (e.g., generating plasma using a CCP chamber, an ICP chamber, etc.), and like components are represented by like reference numerals. In particular, the volume of vacuum chamber 310 may be similar to chamber 172 of FIG. 1, and both chambers are conventionally sized (i.e., relative to the surface area of ​​wafer 101).

[0035] Similar to various other embodiments of the present disclosure described throughout this specification, the plasma processing system 300A is configured to increase the discharge rate of positive ions from the wafer's surface by increasing the available electron flux to the wafer (e.g., plasma electrons from the tail population can easily swarm to the wafer surface), and also increase the ion flux to the chamber walls during the pulse-off period of a corresponding cycle of the pulsed DC bias signal. In this manner, ion neutralization time is minimized (i.e., neutralization of wafer surface ions is substantially instantaneous, and neutralization of negative static charge accumulated on the chamber walls is accelerated by incident ions due to the increased ion flux to the walls), achieving arbitrarily high duty cycle operation of the pulsed DC bias signal while maintaining a monoenergetic IEDF for plasma processing systems serving DC pulsing applications.

[0036] As previously mentioned, a desired increase in the maximum duty cycle of the pulsed DC bias signal can be achieved by increasing the asymmetry between the wafer 101 and the chamber 310, more specifically, by increasing the effective surface area of ​​the chamber 310 for a given wafer size (i.e., to increase the area ratio). In this manner, an increase in the asymmetry between the surface area of ​​the wafer 101 and the surface area of ​​the chamber 310 (e.g., increasing the area of ​​the ground electrode) is achieved.

[0037] 3A , in one embodiment, the increased asymmetry can be achieved by increasing the effective surface area of ​​a surface 335 of the chamber 310 without necessarily increasing the volume of the chamber 310. For example, an inner layer 330 may be provided adjacent the wall of the chamber 310, the inner layer 330 including a surface 335 that faces the plasma 178. In other embodiments, the surface 335 corresponds to the surface of the wall of the chamber 310, and no inner layer is introduced. In particular, the surface 335 includes a plurality of features 340, which effectively increase the surface area within the chamber 310 that faces and / or is exposed to the plasma 178 (i.e., compared to a surface that does not include the features).

[0038] The features 350 may be configured in various shapes and positioned in various configurations relative to the surface 355 to increase the effective surface area of ​​the surface 335 exposed to the plasma. In one embodiment, at least one dimension of each feature in the features 340 is on the order of a Debye length to allow the plasma to penetrate into the area surrounding the features 340 (i.e., to increase the effective surface area of ​​the features exposed to the plasma). For example, the features may extend above a planar surface associated with the surface 335 (e.g., the surface of a corresponding area), below the planar surface, recessed into the planar surface, etc. For example, FIGS. 3B, 3C-1, 3C-2, and 3D show various configurations of surface features according to embodiments of the present disclosure.

[0039] In particular, Figure 3B illustrates a surface 335B (e.g., of an interior layer or wall of a chamber) including an exemplary plurality of features 340B configured as a one-dimensional (1D) lattice. Figure 3C-1 illustrates a surface 335C-1 (e.g., of an interior layer or wall of a chamber) including an exemplary plurality of features 340C-1 configured as a two-dimensional (2D) lattice or protrusion. More specifically, the plurality of features 340C-1 may extend from or be recessed into (i.e., in and out of) the surface 335C-1. Figure 3C-2 illustrates a surface 335C-2 including another exemplary plurality of features 340C-2 configured as a 2D lattice or protrusion, where the features may be configured as hollow protrusions, such as in the form of a honeycomb (i.e., an inverted honeycomb), extending outward from or inward from the surface 335C-2. 3D also illustrates a surface 335D (e.g., of a chamber lining or wall) including exemplary features 340D configured in three dimensions (3D). As shown, features 340D may be configured as a "log pile" structure, a Yablonovite structure, or any suitable 3D structure.

[0040] 4A illustrates a plasma processing system 400A including an external neutralization source 430 configured to provide a neutralization current that effectively discharges and / or neutralizes positive ions on the surface of the wafer, according to one embodiment of the present disclosure. The external neutralization source 430 effectively increases the area ratio between the surface of the wafer and the walls of the chamber 410 by introducing electrons into the volume of the chamber 410. As previously described, the plasma processing system 400A utilizes DC bias pulsing to the pedestal 140 to achieve monoenergetic ion excitation of ions at the wafer surface (e.g., controllable monoenergetic IEDF at a desired energy level).

[0041] In particular, the plasma processing system 400A includes, in part, a main chamber 410, a pedestal 140 configured to support the wafer 101, and a pump port 420 configured to evacuate gases and / or by-products from the main chamber 410. For example, the main chamber 410 may include a lower electrode within the pedestal 140 or the ESC to receive a high-frequency RF signal used to generate the plasma 178. A DC generator may supply a pulsed DC bias signal to the lower electrode over multiple cycles, the pulsed DC bias signal having an on period and an off period in each of the multiple cycles. The plasma processing system 400A may be similar to the plasma processing system 100 of FIG. 1; thus, both systems are configured for plasma processing (e.g., generating plasma using a CCP chamber, an ICP chamber, etc.), and similar components are represented by similar reference numerals. However, the plasma processing system 400A includes a neutralization source 430 that is external to the main chamber 410. The neutralization source 430 can include a pump port 435 configured to pump electrons generated by the neutralization source 430 through a channel 440 into the main chamber 410 (eg, to pump an electron current 450).

[0042] As with various other embodiments of the present disclosure described throughout this specification, the plasma processing system 400A is configured to increase the discharge rate of positive ions from the wafer surface by increasing the available electron flux to the wafer during the pulse-off period of a corresponding cycle of the pulsed DC bias signal, thereby correspondingly increasing the ion flux to the chamber walls. In particular, the ion flux to any surface in a thermal plasma (isotropic) is primarily fixed by the Bohm flux, which is driven by the Maxwellian electron temperature. Unless a significant high-energy electron flux is intentionally directed toward the surface, the thermal plasma Bohm criterion is not modified, and the thermal plasma Bohm flux cannot change. The ion Bohm flux is essentially determined by the thermionic flux entering the pre-sheath. In a global model, one way to change the thermionic flux entering the pre-sheath is to change the thermionic temperature (e.g., at a given plasma density). By intentionally directing a sizable (i.e., relative to the bulk of the Maxwellian distribution) high-energy electron flux (e.g., energy equal to or greater than the energy of the tail population) toward the wall, the Bohm criterion becomes a modified Bohm criterion (i.e., the Sheath-Poisson equation is rewritten), allowing for a true increase in the ion Bohm flux. In this way, the overall electron flux (to the wafer and / or main plasma chamber) during the off-period can be significantly increased, thereby enabling a duty cycle of greater than 90% for the DC bias signal.

[0043] In this way, ion neutralization time is minimized, achieving arbitrarily high duty cycle operation of the pulsed DC bias signal while maintaining a mono-energy IEDF for plasma processing systems serving DC pulsing applications. In particular, introducing electrons into the chamber 410 volume via the neutralization source 430 increases electron flux to the wafer and / or main plasma chamber. For example, the introduction of electrons significantly increases electron flux to the main chamber during the off-period, neutralizing the sudden rise in the plasma potential of the main plasma chamber (e.g., achieving a main chamber plasma potential that does not substantially rise during the 10% neutralization off-period by neutralizing the buildup of negative electron electrostatic charge on the chamber walls during the previous on-period), achieving a duty cycle of greater than 90% for the pulsed DC bias signal.

[0044] Notably, the neutralization source 430 may be external to the main chamber 410 and self-contained. The neutralization source 430 effectively increases the area ratio between the surface of the wafer and the walls of the chamber 410 by introducing electrons or neutralizing charges into the volume of the chamber 410. That is, the neutralization source 430 is configured to generate electrons and provide a neutralizing current or electron current 450 to the main chamber 410. Additionally, the neutralization source 430 can physically increase the surface area of ​​the combined surfaces (e.g., the wall of the chamber 410 and the wall of the neutralization source 430) exposed to the plasma 178. More specifically, the neutralization current 450 is electrically coupled to the main plasma 178. In one embodiment, the neutralization current 450 is continuously delivered to the main chamber 410 during the on and off periods of each of the multiple cycles of the pulsed DC bias signal, and is continuously electrically coupled to the plasma accordingly. In some embodiments, the space potential (e.g., negative charge) on the secondary plasma can vary in time, such as in a manner synchronous with the pulsed DC bias signal. In one embodiment, the neutralization current 450 is configured to neutralize ions in the multiple ions in the main plasma 178 during the off periods of each of the multiple cycles of the pulsed DC bias signal.

[0045] In one embodiment, the neutralization source 430 is configured as an electron gun capable of generating electrons for the electron current 450 (e.g., by firing an electron beam into the main chamber 410). The electron gun can operate under conditions decoupled from the process conditions required for the main chamber 410. In this manner, the electron gun can operate independently and generate a large neutralization current. In one embodiment, the electron gun is external to the main chamber 410 and can supply electrons to an annular ring adjacent to the main chamber 410, with multiple channels between the annular ring and the main chamber 410 allowing electrons to flow into the main chamber 410 from different points within the annular ring (e.g., different and / or periodic angular points between 0 degrees and 360 degrees of the annular ring). In another embodiment, the electron gun can be located within the main chamber 410 and can generate electrons within the chamber to supply a neutralizing charge to the main plasma 178.

[0046] In yet other embodiments, neutralization source 430 can utilize any suitable technique for generating electrons. For example, neutralization source 430 can be configured to generate electrons through thermal emission. Neutralization source 430 can also be configured to generate electrons through a secondary plasma, as described in connection with FIG. 4B below.

[0047] 4B illustrates a plasma processing system 400B utilizing two plasmas, including a secondary plasma provided by an externally coupled plasma source, according to one embodiment of the present disclosure. The external neutralization source 430B effectively increases the area ratio between the wafer surface and the walls of the chamber 410B by introducing electrons into the volume of the chamber 410B via the secondary plasma 460. As previously described, the plasma processing system 400B utilizes DC bias pulsing to the pedestal 140 to achieve monoenergetic ion excitation of ions at the wafer surface (e.g., controllable monoenergetic IEDF at a desired energy level).

[0048] In particular, the plasma processing system 400B includes, in part, a main plasma chamber 410B configured to generate a main plasma 178, a pedestal 140 configured to support a wafer 101, and a pump port 420B configured to evacuate gases and / or by-products from the main chamber 410. For example, the main chamber 410B may include a lower electrode within the pedestal 140 or the ESC to receive a high-frequency RF signal used to generate the plasma 178. A DC generator may supply a pulsed DC bias signal to the lower electrode over multiple cycles, the pulsed DC bias signal having an on period and an off period in each of the multiple cycles. The plasma processing system 400B may be similar to the plasma processing system 100 of FIG. 1; thus, both systems are configured for plasma processing (e.g., generating plasma using a CCP chamber, an ICP chamber, etc.), and similar components are represented by similar reference numerals. However, the plasma processing system 400B includes a neutralization source 430B that is external to the main chamber 410. The neutralization source 430B may include a pump port 435B configured to pump electrons generated by the neutralization source 430B through a channel 440B into the main chamber 410B (e.g., pump an electron current 450B). That is, the plasma processing system 400B may include a pump that accesses the secondary plasma chamber of the neutralization source 430B to pump the secondary plasma 460 into the main plasma chamber 410B to provide a neutralization current electrically coupled to the main plasma.

[0049] As with various other embodiments of the present disclosure described throughout this specification, the plasma processing system 400B is configured to increase the discharge rate of positive ions from the wafer's surface by increasing the available electron flux to the wafer during the pulse-off period of a corresponding cycle of the pulsed DC bias signal, thereby correspondingly increasing the ion flux to the chamber walls. In this manner, ion neutralization time is minimized, achieving arbitrarily high duty cycle operation of the pulsed DC bias signal while maintaining a monoenergetic IEDF for plasma processing systems serving DC pulsing applications. In particular, the electron flux to the wafer is increased by introducing electrons into the chamber 410B volume via the secondary plasma 460 generated by the neutralization source 430B.

[0050] In particular, the neutralization source 430B is external to the main chamber 410B and configured as a secondary plasma chamber. The neutralization source 430B effectively increases the area ratio between the wafer surface and the walls of the chamber 410B by introducing electrons or neutralizing charges into the volume of the chamber 410B. That is, the neutralization source 430B is configured to generate electrons via the secondary plasma 460 and supply a neutralizing or electron current 450B to the main chamber 410B. In one embodiment, the secondary plasma 460 is more negatively charged than the main plasma 178. In this manner, electrons or neutralizing charges can be introduced into the main chamber 410B to neutralize ions in the plasma 178, such as near the surface of the wafer 101. Additionally, the neutralization source 430B can physically increase the surface area of ​​the combined surfaces (e.g., the walls of the chamber 410B and the walls of the neutralization source 430B) exposed to the plasma 178.

[0051] In particular, neutralization source 430B can generate plasma using RF power. In one embodiment, an RF power generator is shared between main chamber 410B and neutralization source 430B to generate main plasma 178 and secondary plasma 460. In another embodiment, the secondary plasma chamber of neutralization source 430B includes an independent RF power generator. Furthermore, neutralization source 430B may only be electrically coupled to main plasma 178, whereby the neutralization source provides neutralization current 450B electrically coupled to main plasma 178. In one embodiment, neutralization current 450B is continuously delivered to main chamber 410B during the on and off periods of each of the multiple cycles of the pulsed DC bias signal and is accordingly continuously electrically coupled to the plasma. In one embodiment, neutralization current 450B is configured to neutralize ions in the multiple ions in main plasma 178 during the off period of each of the multiple cycles of the pulsed DC bias signal.

[0052] Additionally, the neutralization source 430B can operate under conditions that are decoupled from the process conditions required for the main chamber 410B. In this manner, the secondary plasma chamber of the neutralization source 430B can operate independently and generate a large neutralization current. For example, the secondary plasma chamber need not be at the same pressure as the main chamber 410B or contain the same gases for plasma generation. In particular, the main plasma 178 can be generated in the main chamber 410B from a first gas mixture under first process conditions, while the secondary plasma 460 can be generated in the secondary plasma chamber of the neutralization source 430B from a second gas mixture under second process conditions.

[0053] FIG. 4C illustrates a plasma processing system 400C including an external neutralization source 430C configured as an annular ring 480 surrounding a main plasma chamber 410C. The neutralization source, according to one embodiment of the present disclosure, provides a neutralization current 450C to effectively discharge and / or neutralize positive ions (e.g., ions on the surface of a wafer) in the main plasma 178. The neutralization source may represent the neutralization sources of FIGS. 4A-4C. In particular, the neutralization source provides electrons to the annular ring 480 adjacent to the main chamber 410C, and multiple channels 470 between the annular ring 480 and the main chamber 410C allow electrons to flow into the main chamber 410C from different points within the annular ring 480 (e.g., different and / or periodic angular points between 0 degrees and 360 degrees of the annular ring). The neutralization source 430C is configured to generate electrons to provide the neutralization current 450C. For example, the neutralization source 430C may be configured as an electron gun, may be configured to generate electrons through thermal emission, or may be configured to generate electrons through a secondary plasma. As shown, the annular ring 480 may include a medium (e.g., a secondary plasma) containing a charge P1 that is more negatively charged than the charge P2 on the primary plasma 178. In this manner, electrons or neutralizing charges may be introduced into the primary chamber 410C to neutralize ions in the plasma 178, such as near the surface of the wafer 101.

[0054] 5 is a flow diagram 500 illustrating a method for plasma processing configured to increase the discharge and / or neutralization of positive ions on a surface of a wafer, according to one embodiment of the present disclosure. The method of flow diagram 500 can be implemented to control processes in the plasma processing systems of FIGS. 1, 2, 3A, and 4A-4C, as well as other plasma processing systems. For example, the method of flow diagram 500 can be stored in computer-readable form in a memory accessible by control module 110 of FIG. 1 to perform the operations of flow diagram 500.

[0055] At 510, the method includes generating a main plasma in a main plasma chamber, the main plasma chamber including a lower electrode located within an electrostatic chuck (ESC). The main plasma chamber can be configured as a CCP chamber, an ICP chamber, or any type of chamber suitable for generating plasma. As previously described, the plasma processing system utilizes DC bias pulsing to the pedestal to achieve monoenergetic ion excitation of ions at the wafer surface (e.g., controllable monoenergetic IEDF at a desired energy level). In particular, at 520, the method includes generating a pulsed DC bias signal delivered to the lower electrode over multiple cycles. In particular, the pulsed DC bias signal has an on period and an off period in each of the multiple cycles of the bias signal.

[0056] As with various other embodiments of the present disclosure described throughout this specification, the flow diagram 500 implemented in a corresponding plasma processing system is configured to increase the discharge rate of positive ions from the surface of the wafer by increasing the available electron flux to the wafer and correspondingly increasing the ion flux to the chamber walls during the pulse-off period of a cycle of the corresponding pulsed DC bias signal. In this manner, ion neutralization time is minimized, achieving arbitrarily high duty cycle operation of the pulsed DC bias signal while maintaining a mono-energy IEDF for plasma processing systems serving DC pulsing applications.

[0057] At 530, the method includes providing a neutralization current generated from a neutralization source external to the main plasma chamber. The neutralization source effectively increases the area ratio between the surface of the corresponding wafer and the wall of the corresponding chamber used to generate the plasma by introducing electrons into the chamber volume as the neutralization current. In particular, the neutralization current is electrically coupled to the main plasma. In one embodiment, the neutralization current is continuously delivered to the main plasma during the on-period and the off-period of each of a plurality of cycles of a pulsed DC bias signal. Furthermore, the neutralization current is configured to neutralize ions in the plurality of ions of the main plasma (e.g., at the surface of the corresponding wafer) during the off-period of each of the plurality of cycles.

[0058] For example, the neutralization source may be configured as an electron gun configured to generate electrons, and the method, in one embodiment, includes pumping the electrons into the main plasma chamber (e.g., using a pump or by firing electrons into the chamber using an electron gun). In another embodiment, the neutralization source may be a secondary plasma chamber configured to generate a secondary plasma. In one embodiment, the main plasma is generated from a first gas mixture under first process conditions in the main plasma chamber, and the secondary plasma is generated from a second gas mixture under second process conditions in the neutralization source. In one embodiment, the secondary plasma is more negatively charged than the main plasma in the main plasma chamber. Additionally, the method, in one embodiment, includes pumping electrons into the main plasma chamber (e.g., using a pump).

[0059] In embodiments, the program may include program code for controlling chamber components used in plasma processing, which may be implemented by the control system 110 of FIG. 1 . In some implementations, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a substrate pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling operations before, during, and after semiconductor wafer or substrate processing. The controller may be programmed to control any of the processes disclosed herein, as well as processes implemented to operate the plasma chamber, depending on the processing requirements and / or type of system. Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor substrate or system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0060] The controller, in some embodiments, may be part of, connected to, or a combination of a computer integrated with or otherwise networked to the system. For example, the controller may reside in the "cloud" of all or part of a fab host computer system, thereby enabling remote access to substrate processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet.

[0061] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, a plasma-enhanced chemical vapor deposition (PECVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0062] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment and, where applicable, may be interchangeable and used in selected embodiments even if not specifically shown or described. The same may also be modified in many ways. Such variations are not to be considered a departure from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

[0063] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments should be considered illustrative and not restrictive, and the embodiments should not be limited to the details set forth herein but may be modified within the scope of the claims and their equivalents.

Claims

1. 1. A system comprising: a main plasma chamber configured to generate a main plasma, the plasma chamber including a lower electrode located within an electrostatic chuck (ESC); a direct current (DC) generator that supplies a pulsed DC bias signal to the lower electrode over a plurality of cycles; a neutralization source external to the main plasma chamber, the neutralization source configured to supply a neutralization current to the main plasma chamber; Equipped with the neutralizing current is electrically coupled to the main plasma; system.

2. 10. The system of claim 1, The system wherein the main plasma chamber is configured as a capacitively coupled plasma (CCP) chamber.

3. 10. The system of claim 1, The system wherein the main plasma chamber is configured as an inductively coupled plasma (ICP) chamber.

4. 10. The system of claim 1, The system, wherein the neutralization source includes an electron gun configured to generate electrons.

5. 10. The system of claim 1, the neutralization source includes a secondary plasma chamber configured to generate a secondary plasma; the secondary plasma being more negatively charged than the main plasma; system.

6. 6. The system of claim 5, a pump for pumping the secondary plasma into the main plasma chamber The system further comprises:

7. 6. The system of claim 5, the primary plasma is generated from a first gas mixture under first process conditions; the secondary plasma is generated from a second gas mixture under second process conditions; system.

8. 10. The system of claim 1, the pulsed DC bias signal having an on period and an off period in each cycle of the plurality of cycles; the neutralizing current is continuously delivered to the primary plasma during the on period and the off period of each cycle of the plurality of cycles; the neutralization current is configured to neutralize ions in the plurality of ions in the primary plasma during the off period in each of the plurality of cycles. system.

9. 1. A system comprising: a main plasma chamber configured to generate a main plasma, the main plasma chamber including a lower electrode located within an electrostatic chuck (ESC); a direct current (DC) generator that supplies a pulsed DC bias signal to the lower electrode over a plurality of cycles, the pulsed DC bias signal having an on period and an off period in each of the plurality of cycles; a secondary plasma chamber external to the main plasma chamber, the secondary plasma chamber configured to generate a secondary plasma that is more negatively charged than the main plasma; a pump for delivering the secondary plasma to the main plasma chamber to provide a neutralizing current electrically coupled to the main plasma; A system comprising:

10. 10. The system of claim 9, The system wherein the main plasma chamber is configured as a capacitively coupled plasma (CCP) chamber.

11. 10. The system of claim 9, The system wherein the main plasma chamber is configured as an inductively coupled plasma (ICP) chamber.

12. 10. The system of claim 9, the primary plasma is generated from a first gas mixture under first process conditions; the secondary plasma is generated from a second gas mixture under second process conditions; system.

13. 10. The system of claim 9, the secondary plasma chamber is configured to continuously generate the secondary plasma such that the neutralizing current is continuously delivered to the primary plasma during the on period and the off period of each cycle of the plurality of cycles; the neutralization current is configured to neutralize ions in the plurality of ions in the primary plasma during the off period in each of the plurality of cycles. system.

14. 1. A method comprising: generating a main plasma in a main plasma chamber, the main plasma chamber including a lower electrode located within an electrostatic chuck (ESC); generating a pulsed DC bias signal delivered to the lower electrode over a plurality of cycles; providing a neutralization current generated from a neutralization source external to the main plasma chamber; Including, the neutralizing current is electrically coupled to the main plasma; method.

15. 15. The method of claim 14, The method wherein the main plasma chamber is configured as a capacitively coupled plasma (CCP) chamber.

16. 15. The method of claim 14, The method wherein the main plasma chamber is configured as an inductively coupled plasma (ICP) chamber.

17. 15. The method of claim 14, the neutralization source includes an electron gun configured to generate electrons; The method further includes pumping the electrons into the main plasma chamber. method.

18. 15. The method of claim 14, the neutralization source includes a secondary plasma chamber configured to generate a secondary plasma; the secondary plasma being more negatively charged than the main plasma; The method further includes pumping the secondary plasma into the main plasma chamber. method.

19. 20. The method of claim 18, the primary plasma is generated from a first gas mixture under first process conditions; the secondary plasma is generated from a second gas mixture under second process conditions; method.

20. 15. The method of claim 14, the pulsed DC bias signal having an on period and an off period in each cycle of the plurality of cycles; a neutralizing current is continuously delivered to the primary plasma during the on period and the off period of each cycle of the plurality of cycles; the neutralization current is configured to neutralize ions in the plurality of ions of the primary plasma during the off period in each of the plurality of cycles. method.

Images