Systems and methods for improving integrated circuit yield

Abstract

A system and method for increasing the yield of manufactured integrated circuits by providing corrective circuit elements, including replacement planar transistors, fabricated by mid-off-line and / or back-end off-line processes to enable and disable corrective circuit elements that provide additional circuit functionality as needed, as determined by post-manufacturing testing of the integrated circuit and / or in-operation monitoring of circuit operation. The system and method can address the distribution of power and signals, such as clock signals and / or high-speed I / O signals, through problem areas resulting from failures due to suboptimal design, circuit aging, and / or manufacturing process variations.

Description

[Technical Field]

[0001] The present invention relates to systems and methods for improving yield in the manufacture of integrated circuits, and more particularly to employing alternate plane transistors and circuit elements to improve performance and / or correct erroneous behavior in integrated circuits. [Background technology]

[0002] Semiconductor manufacturers refer to Moore's Law to describe the ongoing reduction in size and corresponding increase in density of semiconductor components such as transistors and interconnects on integrated circuits. Moore's Law states that approximately every two years, the number of transistors on a chip die doubles.

[0003] To achieve this increase in size, much technological effort has been made to reduce the size of the components that make up semiconductor integrated circuits. However, despite significant reductions in component size, the overall size of many integrated circuits is still increasing significantly, resulting in larger die sizes as more features and capabilities are added to devices. For example, the Apple M1 processor used in some Apple devices is reported to have 11.8 billion transistors and a die size of approximately 120 square mm, while the Apple M1 Max processor is reported to have 57 billion transistors and a die size of approximately 490 square mm. Other advanced semiconductor devices have similar numbers of transistors and die sizes.

[0004] This combination of smaller components on a larger die presents many challenges to semiconductor designers and manufacturers. In fact, a significant percentage of manufactured devices do not operate properly or at the desired speed due to a variety of factors, including slight undesirable variations in the process used to manufacture the devices, overly optimistic design rules employed in the software used to design the circuits that result in flawed designs, circuit designer errors, and so on.

[0005] Thus, yields (the percentage of manufactured devices that operate within certain tolerance parameters, as determined by post-manufacturing testing) for the manufacture of these semiconductor devices are typically lower than desired. For integrated circuits whose designs are at the limits of manufacturing technology, yields can be much lower than desired. Lower yields mean that manufacturers' profits are reduced and that the supply of such advanced devices may be smaller than desired. Summary of the Invention

[0006] It is an object of the present invention to provide a novel method and system for increasing the yield of manufactured integrated circuits that avoids or mitigates at least one disadvantage of the prior art.

[0007] According to a first aspect of the present invention, there is provided a system for increasing yield of manufactured integrated circuits, each integrated circuit comprising: a designed set of circuits implemented as front-end-of-line manufactured circuit elements, the designed set of circuits including at least one front-end-of-line circuit element that is a corrective element, and at least one transistor manufactured as a replacement planar transistor, the at least one transistor operable to selectively activate or deactivate the at least one corrective front-end-of-line circuit element according to results of tests performed on the integrated circuits after fabrication of the integrated circuits.

[0008] Preferably, the corrective circuit element comprises an additional buffer for strengthening the signal at the at least one front end element, and preferably, the system further comprises a programmable memory element for controlling selective activation and deactivation of the at least one corrective front end of line circuit element.

[0009] According to another aspect of the present invention, there is provided an integrated circuit comprising: at least two circuits, each circuit designed to implement a function, wherein a first circuit of the at least two circuits is designed to implement an optional function, at least one alternative planar transistor operable to selectively enable and disable the first circuit of the at least two circuits, and programmable means for controlling the at least one alternative planar transistor to enable and disable said first circuit of the at least two circuits.

[0010] According to another aspect of the present invention, there is provided a method for manufacturing an integrated circuit, the method comprising the steps of: designing circuitry necessary to implement desired functionality of the integrated circuit, examining the design of the necessary circuitry to determine areas that may have operational problems due to manufacturing process variations, adding corrective elements to the design of the circuitry necessary to provide the functionality of the corrective circuit in the determined areas, performing front-end of line manufacturing of the designed integrated circuit, fabricating, for at least each determined area, a replacement planar transistor operable to selectively enable and disable the corrective circuit in the determined area, completing the manufacturing process to obtain a completed integrated circuit, and testing the completed integrated circuit to identify designated areas that do not meet predetermined test criteria for the determined areas, wherein, for each identified designated area, testing is performed by programming transistors associated with each identified designated area to enable the respective corrective elements.

[0011] Preferably, testing of the completed integrated circuit is performed dynamically on the operating circuit.

[0012] According to yet another aspect of the present invention, there is provided a method for increasing yield in manufacturing integrated circuits, the method comprising the steps of designing a MOS logic integrated circuit, determining at least one possible point of circuit failure in the designed MOS logic integrated circuit, modifying the design of the MOS logic integrated circuit by adding a corrective element to the design of the MOS logic integrated circuit at the determined at least one possible failure point, where the corrective element is located on a plane of the MOS logic integrated circuit other than the plane of the MOS logic integrated circuit in which the MOS logic is located, fabricating the MOS logic integrated circuit using the modified design, determining whether the at least one possible failure point is a failure point, testing the fabricated integrated circuit to detect whether the at least one possible failure point is a failure point, and connecting the corrective element to the determined failure point in the fabricated MOS logic to correct the failure.

[0013] Preferably, the corrective element is connected to the determined fault location via a transistor formed in a plane other than the plane in which the MOS logic of the MOS logic integrated circuit is located.

[0014] The present invention provides a system and method for increasing the yield of manufactured integrated circuits by providing transistors fabricated on alternate planes of a die to enable and disable redundant circuit elements that provide additional circuit functionality when needed, as determined by post-manufacturing testing of the integrated circuit or dynamically during operation of the integrated circuit. [Brief explanation of the drawings]

[0015] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 shows a schematic example of a prior art clock tree for an integrated circuit. [Figure 2] FIG. 2 shows a schematic diagram of a buffer for use in an integrated circuit according to one embodiment of the present invention. [Figure 3a] FIG. 3a shows a schematic diagram of a variant of the buffer of FIG. [Figure 3b] FIG. 3b shows a schematic diagram of a variation of the buffer of FIG. [Figure 4] FIG. 4 shows a schematic example of a clock tree for an integrated circuit using buffers according to one embodiment of the present invention. [Figure 5] FIG. 5 illustrates a block diagram of a clock management system according to one embodiment of the present invention. [Figure 6] FIG. 6 illustrates a power supply decoupler according to one embodiment of the present invention. [Figure 7] FIG. 7 shows a flow chart of a method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] As briefly mentioned above, the ongoing trend to reduce the size of circuit components within integrated circuits while increasing the number of circuit elements and the size of the die on which the circuits that make them up are formed leads to challenges in manufacturing properly working instances of those integrated circuits.

[0017] The present invention addresses these challenges by providing remedial circuit elements that are fabricated on planes of an integrated circuit other than the planes on which conventional MOS logic is formed. As described below, these remedial elements can address one or more common causes of circuit failure and can be switched into or, in some cases, out of MOS logic circuitry as needed.

[0018] One common example of a challenge in the design of modem integrated circuit systems is the issue of system clocking. A typical digital synchronous system critically depends on a periodic signal called a clock ("CLK") that is available throughout the circuit for fault-free operation of the circuit. For example, system memory storage elements such as registers and latches are typically updated on the arrival of the CLK signal.

[0019] A typical ideal clock signal is a square wave, and system elements typically respond to either the rising (positive-going) or falling (negative-going) side of the square wave pulse. For example, a register may be designed to update its output upon the arrival of the positive-going edge of the CLK signal. Ideally, this clock edge must arrive at exactly the same time throughout the system of integrated circuits, or unintended behavior, including erroneous outputs, race conditions, etc., may occur. Distribution of clock signals and ensuring their substantially simultaneous arrival are significant challenges when designing modem integrated circuits.

[0020] Specially designed clock distribution networks called clock trees ("CTs") are often designed and used to provide clock signals across integrated circuits and limit the movement of clock signal edges away from their ideal arrival times (a.k.a. clock skew).

[0021] An alternative clock distribution network called a clock mesh ("CM") is also sometimes implemented. Compared to a clock tree, it is generally accepted that a clock mesh has better skew management, but it has higher power consumption and requires more area on the chip die to implement. Thus, integrated circuit designers typically must make compromises related to performance, available area, power consumption, and product yield when designing clock signal distribution across a die.

[0022] FIG. 1 shows an idealized example of a particular type of CT, generally designated 20, called an H-tree clock distribution network. In an H-tree, a clock signal 24 is input to a set of clock buffers 28 (often just simple inverters), which then distribute the clock pulses to various circuit components 32 as needed. While the idealized example of FIG. 1 appears to be a simple (direct, straightforward) solution, in most practical complex integrated circuits, the H-tree 20 must drive different sets of circuit components 32a, 32b, 32c, or 32d, which may have large, uneven, and distributed capacitive loads at high switching frequencies. As a result, buffers 28 of various strengths must be designed into the H-tree (or other CT) to reliably drive the expected loads of circuit elements 32, such as registers, latches, and dynamic logic gates.

[0023] This requires the circuit designer to estimate the capacitive load that will be applied to each buffer 28 and then design each buffer 28 to have enough capacitance to meet that estimated load. Providing more capacitance for a buffer 28 requires more area on the die and consumes more power. Therefore, the designer must carefully balance the needs to ensure adequate drive for the capacitive load while avoiding over-designing the buffer 28, thereby wasting die area and power.

[0024] Additionally, while clock skew can be reduced using optimally designed H-trees with properly sized and placed buffers, the skew still cannot be eliminated. Further complicating this issue is the fact that manufacturing process variations in producing integrated circuits can result in some circuit dies having clock trees that operate according to specification, while other circuit dies having the exact same design fail post-manufacturing testing, thus reducing chip yield.

[0025] Furthermore, necessarily sophisticated CT implementations such as large H-trees consume a significant portion of the overall power consumed in complex integrated circuits, and in some applications the CTs themselves account for more than one-quarter of the total power consumption of an integrated circuit. This is highly problematic because power consumption and related thermal management issues are significant design-limiting factors.

[0026] A further challenge arises, ironically, from the fact that while CTs play a critical role in synchronous sequential integrated circuits, their functionality generally cannot be directly observed for post-fabrication testing purposes. Poorly designed CTs can lead to circuit failures due to timing errors that are extremely difficult to debug. Unfortunately, the distributed nature of CTs and their design complexity can also lead to intermittent failures that result in poor yield and / or reliability of the integrated circuit; these problems are exacerbated as circuit density and die size increase.

[0027] A known attempt to address some of these problems is to use active and / or passive clock de-skewing circuits. However, closed-loop de-skewing techniques also consume valuable and limited die area, consume significant amounts of power, and require non-trivial design effort.

[0028] All manufactured integrated circuits must be tested after manufacture for specification compliance. Testing and qualification of integrated circuits is typically done in several stages and can be expensive and time-consuming, adding significantly to the overall cost of manufacturing integrated circuits.

[0029] During the testing process, locations on the integrated circuit being tested may be identified where the circuit timing margins do not meet specifications, resulting in a failure of the integrated circuit or necessitating the sale of the integrated circuit with reduced operating speed or functionality. Currently, it is not technically / economically feasible to repair such integrated circuits.

[0030] Integrated circuit designers sometimes add additional circuitry to improve timing margins. These techniques include the aforementioned active deskew circuitry or programmable buffers with non-volatile memory elements. However, all of these known techniques must be incorporated early in the integrated circuit design process and therefore cannot address timing issues that are determined after the design is complete. Also, as noted above, such techniques require otherwise valuable die area and increase the integrated circuit's power consumption. Therefore, designers attempt to employ such solutions only when they anticipate timing issues. Therefore, the design process requires best-effort estimation by the designer to guess where timing margins may be compromised, potentially leading to over-provisioning of buffers and the like that wastes die area and power, or a device under test that fails to meet specifications.

[0031] The inventors have discovered that repair, salvage, modification, compensation, remediation of integrated circuits to correct design and manufacturing problems, such as clock skew or other errors, can be performed after primary fabrication is complete. Specifically, as disclosed herein, repair of integrated circuits to address such clock skew or other problems can be performed after MOS transistor-based logic circuits are formed on the integrated circuit die.

[0032] As is known, the conventional manufacturing process of integrated circuits is divided into the front-end-of-line ("FEOL") stage, the front-end-of-line mid-end-of-line ("MOL") stage, and the back-end-of-line ("BEOL") stage. In the front-end-of-line ("FEOL") stage, circuits based on MOS transistors are formed in a first plane of the die. In the back-end-of-line (BEOL) stage, other features and requirements, such as metal layers and insulating layers, are added in another plane of the die, typically on top of the first plane, to complete the integrated circuit. In the mid-end-of-line ("MOL") stage, which is between the FEOL and BEOL stages, other processes are performed.

[0033] The present invention allows for the addition of corrective circuitry (described further below) to integrated circuits having identified or potential problems by providing devices fabricated during the MOL or BEOL stages of device fabrication. Such devices are disclosed in published PCT application WO 2023 / 285936 (Barlage et al.) and published PCT application WO 2023 / 285951 (Barlage and Shoute), and are referred to herein as "alternate planar" ("AP") transistors because they are fabricated in a plane of a semiconductor die that is above or below the plane of the die in which conventional devices are fabricated during the FEOL manufacturing stage.

[0034] FIG. 2 shows a schematic diagram of an example of a corrective technique for addressing faults or problems involving clock skew. In FIG. 2, a novel buffer is generally designated 100, and in this example, buffer 100 functions as a clock buffer. Buffer 100 includes two inverters 104 and 108, with the output of inverter 104 applied to the input of inverter 108 in a manner similar to conventional clock and other signal buffers. However, each inverter 104 and 108 is further paired with a respective MOS transistor 112 and 116. The inverters 104 and 108 and their corresponding MOS transistors 112 and 116 are expected to be fabricated on an integrated circuit die at the FEOL stage, along with the logic circuitry clocked by inverters 104 and 108 and MOS transistors 112 and 116.

[0035] MOS transistors 112 and 116 have control transistors 120 and 124, respectively, which are AP transistors fabricated during the MOL and / or BEOL stages of fabrication (shown in FIG. 2 by dashed line 128). It is also contemplated that control transistors 120 and 124 may be formed as active vias, if desired.

[0036] In operation of clock buffer 100, when control signal CTRL1 is applied to AP transistor 120, the rise time of the positive-going edge of the clock signal output from buffer 100 may be reduced in proportion to the combined strength of transistors 112 and 120. Similarly, when control signal CTRL2 is applied to AP transistor 124, the fall time of the negative-going edge of the clock signal output from buffer 100 is reduced in proportion to the combined strength of transistors 116 and 124.

[0037] As will be apparent, either or both of the control signals CTRL1 and CTRL2 may be applied to buffer 100 as needed to ensure that the clock signal from buffer 100 has the timing / strength required for the circuitry it drives. When control signals CTRL1 and / or CTRL2 are not applied to AP transistors 120 and / or 124, no power is consumed by MOS transistors 112 and 116. Only when one or both of the control signals CTRL1 and CTRL2 are applied does buffer 100 draw additional power.

[0038] As will be apparent to those skilled in the art, in most cases, the control signals CTRL1 and CTRL2 will be DC signals, but in some circumstances, either or both of the control signals CTRL1 and CTRL2 may be toggled at a desired frequency by either a square wave or a pulse width modulated (PWM) signal. When toggled, output capacitance may be provided to buffer 100 intermittently as needed.

[0039] If an area of ​​the circuit design is responsive to only one side of the clock signal (positive-going or negative-going), the design of clock buffer 100 can be simplified by removing unnecessary circuitry to reduce the required die area in the plane of the logic circuitry. Figure 3a shows clock buffer 150 when the logic circuitry receiving the clock signal does not respond to the negative-going side of the clock signal, and Figure 3b shows clock buffer 170 when the logic circuitry receiving the clock signal does not respond to the positive-going side of the clock signal.

[0040] Thus, buffers 100, 150, and / or 170 allow integrated circuit designers to provide additional capacitance to clock buffers that likely require additional strength without incurring additional fixed amounts of power consumption. In some cases where the designer's estimate of the required clock buffer capacitance is overly optimistic, CTRL1 and / or CTRL2 for one or more buffers 100 can be asserted for all manufactured instances of the device, thus providing a corrective design “fix.” In other cases, post-fabrication testing may determine that, due to process variations or other effects, some identified devices require CTRL1 and / or CTRL2 to be asserted to ensure proper operation of the device. Clearly, additional power consumption (and associated increased thermal issues) only occurs if, during post-fabrication testing, it is determined that additional capacitance is needed at the output of buffers 100, 150, and / or 170.

[0041] In this way, a designer of a complex integrated circuit can provide a level of additional potential buffering capacity in his or her design, and selectively activate that additional capacity only if it is subsequently determined that additional buffering capacity is needed. A complex integrated circuit can have many instances where additional potential buffering capacity is provided, and thus tens, hundreds, or even more instances of additional potential buffering capacity can be provided, as desired. By using AP transistors, the die area of ​​the plane on which the MOS logic circuitry is fabricated is minimized by the use of buffers 100, 150, and / or 170.

[0042] As mentioned above, in some cases this additional buffer capacity may be required for all integrated circuits due to design errors (such as optimistic estimates of clock loading), but more commonly this additional buffer capacity may only be required for a certain percentage of the integrated circuits manufactured as a result of variations in the manufacturing process, as determined by post-manufacturing testing.

[0043] Specifically, depending on the integrated circuit design and its fabrication, post-fabrication testing of the integrated circuit may determine that a particular instance of additional buffer capacity is not needed (i.e., the original design was appropriately sized and implemented), that the original design was overly optimistic and that some or all of the particular instances of additional buffer capacity will always be needed, or that some instances of the integrated circuit will require activation of some instances of additional potential buffer capacity, such as due to process variations across a silicon wafer, while other instances of the integrated circuit will not require activation. For those instances of the integrated circuit that do not require activation, as part of the test process, the appropriate control signal (CTRL1 and / or CTRL2) for each one instance of additional potential buffer capacity may be enabled or disabled according to the needs determined by testing of the particular chip.

[0044] Providing a control signal to turn on the additional potential buffer capacity can be accomplished in a variety of ways, as will be understood by those skilled in the art, such as by burning a "fuse" on the integrated circuit, appropriately setting control bits in SRAM circuitry on the integrated circuit, etc.

[0045] FIG. 4 illustrates an H-tree clock distribution network using clock buffers 100, 150, and 170 according to one embodiment of the present invention. As shown, buffer 100a, which receives clock input 24 and distributes the clock signal through the illustrated tree, can enhance both the rising and falling edges of the clock signal, if desired, and thus has input signals 204 and 208 corresponding to the CTRL1 and CTRL2 control signals described above. In contrast, circuit element 32b responds only to the falling edge of the clock signal, and thus buffer 170b has input 220 corresponding to input CTRL2, and buffer 170b can enhance the falling edge of the clock signal, if desired. Circuit element 32c includes elements that respond to both the rising and falling edges of the clock signal, and thus buffer 100c can enhance both sides of the clock signal, and has inputs 212 and 216 corresponding to the CTRL1 and CTRL2 inputs to enable such enhancement, if desired. The designers of the integrated circuit embodying clock tree 200 have determined that circuit elements 32d can be properly clocked without requiring additional enhancement of the clock signals, and therefore, their clock signals are provided via conventional buffers 28.

[0046] As will be apparent to those skilled in the art, by enhancing the rising and / or falling edges of the clock signal, the present invention also addresses clock skew (i.e., timing variations when the rising or falling edges of the clock signal are detected).

[0047] 5 illustrates an example clock management system 300 that can generate CTRL1 and / or CTRL2 signals for each buffer 100, 150, and / or 170 to enhance respective clock edges and / or address clock skew as needed. As shown, system 300 includes a clock signal generator 304 that generates a clock signal 306 for an integrated circuit in which it is located. Clock signal 306 is provided to both a clock distribution network 308, which may be an H-tree, clock mesh, or other suitable distribution network, and to a clock management controller 312. Clock management controller 312 is connected to nodes of interest within clock distribution network 308 (i.e., nodes where a chip designer desires to provide selectable enhancements) and is provided with measurements 316 of clock signal 306 from those nodes. In response to measurements 316, clock management controller 312 generates appropriate CTRL1 and / or CTRL2 signals 320 for appropriate instances of buffers 100, 150, and / or 170 on the integrated circuit.

[0048] The clock management controller 312 can be implemented in a variety of ways, as will be apparent to those skilled in the art. For example, the clock management controller 312 can include a set of "fuses" that "blow" the CTRL1 and / or CTRL2 signals for each buffer 100, 150, and / or 170 to allow for clock distribution problems identified by post-manufacturing testing to be addressed. Similarly, the clock management controller 312 can include clock skew detection circuitry implemented by phase-locked loop and / or delay-locked loop circuitry, temperature sensors, and / or other inputs to allow for dynamic identification and subsequent correction of the clock signal 306 by asserting an associated signal of the CTRL1 and / or CTRL2 signals.

[0049] Furthermore, the present invention is not limited to use in addressing problems related to clock signal levels; instead, the present invention may be employed to address problems related to a wide variety of control or other signals in complex integrated circuits. For example, high-speed input / output (I / O) pins are prevalent in modem chip designs to enable the movement of large amounts of data in and out of integrated circuits. Some examples of such I / O systems are commonly known as SERelizers and DESerilizers ("SERDES"). Current state-of-the-art SERDES and similar systems can support data rates in excess of 100 Gb / s. At these speeds, optimizing timing to reduce crosstalk, bit error rates, and the like is extremely challenging.

[0050] Accordingly, such I / Os utilize signal processing, noise shaping, and filtering techniques to mitigate the aforementioned timing challenges. However, process variations in manufacturing such integrated circuits and non-ideal modeling / simulation during the design of the associated circuits can make practical implementation of such high-speed signal processing circuits difficult. In accordance with the present invention, a set of buffers, such as buffer 100 described above, can be integrated at critical locations in a high-speed I / O circuit to provide programmable levels of required output signal enhancement, as determined by testing of the actual completed integrated circuit. These buffers are controlled to provide the signal levels required for the specified operation of the I / O circuit as a result of post-manufacture testing of the I / O circuit. Thus, once the design is manufactured and the resulting integrated circuit instance is tested, the signals can be "tuned" to provide the required performance by activating or deactivating signal enhancement buffer 100.

[0051] It is believed that one of the key advantages of employing AP transistor-based circuits as described above is the ability to take corrective action after all FEOL MOS transistors have been integrated, connected, and their performance tested.

[0052] Thus, as described above, it is contemplated that a structured approach for improving the yield of properly functioning instances of an integrated circuit may include the steps of identifying areas of the integrated circuit design where problems may occur with the provision of signals, such as clock signals or other signals on the chip, and providing additional potential buffering and / or output capacity in those identified locations, which additional potential buffering capacity may be selectively activated as needed; testing each manufactured integrated circuit to determine whether a tested performance problem resulted in failure due to improper performance of a signal for which additional potential buffer capacity was provided; and, if so, activating the additional potential buffer capacity to address the determined improper performance, thus increasing the number of integrated circuits that pass the test requirements, i.e., the yield.

[0053] The use of AP transistor-based circuits can also be leveraged to ensure the continued operation of deployed integrated circuits in production processes. Specifically, all semiconductor integrated circuits, once deployed, can suffer reliability failures to varying degrees over their lifetime. These reliability failures are generally caused by various aging mechanisms, such as electromigration, hot carriers, and gate oxide damage, to name a few. Typically, these failures occur gradually and are often preceded by performance degradation. Higher on-chip current densities, high-speed signal switching, and high operating temperatures are major factors that accelerate these aging and failure mechanisms. Therefore, high-speed I / O, clock networks, and high-speed on-chip bus drivers are easily susceptible to such failures.

[0054] The use of AP transistor-based circuits in combination with devices provided in FEOL MOS circuits for redundancy and / or buffering or other programmably activated functions can result in a highly reliable architecture of circuit elements. Such highly reliable circuit elements can include spare drivers, buffers, and transistors that are enabled by the AP transistors when the original drivers begin to show signs of aging / failure.

[0055] In a preferred implementation of such a high reliability design, non-volatile programmable memory may be employed in conjunction with AP transistor-based circuitry so that associated circuit elements can be dynamically activated and / or deactivated in production. However, as will be apparent to those skilled in the art, such architectures may also be deterministically programmed in production by a variety of mechanisms, such as fuses, antifuses, and SRAM cells.

[0056] Thus, an overall high availability system can include one or more AP transistor-based circuits, programmable devices, and MOS circuits, which can be used to mitigate reliability failures in chip circuits.

[0057] Another problem that can be addressed by the present invention is that of effective power delivery. Implementing a power delivery system on a state-of-the-art integrated circuit with billions of transistors is another complex and difficult problem, and a poorly designed power delivery network can cause power supply voltage droop, power supply noise, etc. Such power delivery problems can lead to intermittent failures that are difficult or impossible to debug, and can cause timing-based and other failures.

[0058] To address noise in power supply designs, conventional integrated circuit designs utilize a large portion of the on-chip area to implement decoupling capacitors to reduce such power supply noise, and designing these noise reduction and distribution systems requires significant design effort.

[0059] In conventional integrated circuit manufacturing, power supply noise measurement and characterization is one of the test parameters that integrated circuits must typically pass. If, despite the designer's efforts, the tested power supply noise level is unacceptably high for a given integrated circuit, the integrated circuit is typically scrapped, reducing the yield of the production run.

[0060] Using the present invention, after testing and characterization of a pre-manufactured instance of an integrated circuit, AP transistors and associated devices, such as filter capacitors, can be subsequently integrated onto the BEOL or MOL planes to correct any circuit areas that testing indicates have inadequate power delivery. By employing AP transistors and devices, there is no need to redesign the FEOL logic circuitry of the integrated circuit, nor is there any need to redesign the associated masks and other tools used to fabricate that FEOL logic circuitry. This is believed to be a significant advantage of the present invention.

[0061] It is also contemplated that power supply issues may be addressed dynamically in a manner similar to that described above for clock signals. Specifically, FIG. 6 illustrates an example of a programmable power supply decoupler 400. In this example, a load 404 is connected to a power supply 408 via a power supply lead 412, and power supply decoupler 400 is connected to power supply lead 412, preferably near load 408. Power supply decoupler 400 includes a capacitor 416 and an AP transistor 420, which is controlled by a signal CTRL3 applied to its gate. Capacitor 416 may be formed in MOS circuits formed in a FEOL process, but is more preferably formed in MOL and / or BEOL processes on another plane of the integrated circuit. In such a case, power supply decoupler 400 would occupy little, if any, of the die area on which FEOL MOS devices are fabricated.

[0062] As will be apparent to those skilled in the art, capacitor 416 is switched in or out of the power circuit formed between power supply 404 and load 408 by asserting or removing the CTRL3 signal to filter noise and / or prevent spikes or dropouts on power lead 412.

[0063] It is contemplated that in many cases, capacitor 416 may be shared by several instances of power supply decoupler 400, any or all of which may be activated or deactivated as needed for a particular integrated circuit. Similar to the CTRL1 and CTRL2 signals described above, the CTRL3 signal of each power supply decoupler 400 may be generated in any suitable manner and may be dynamically set (as needed) by the power management system. The power management system monitors power supply performance in relevant portions of the integrated circuit after post-manufacturing testing has determined one or more problem areas on the manufactured integrated circuit under test, or permanently (such as by fuses or anti-fuse devices) monitors power supply performance.

[0064] In another aspect of the present invention, it is often desirable to tailor an otherwise large integrated circuit to a specific application domain. Traditionally, this has required the creation and manufacturing of different versions of a base architecture. For example, a microprocessor may be optimized for desktop, laptop, or server applications. Even within these specific domains, it is known to create several variants to cater to different market segments, such as low-cost consumer devices, industrial use cases, server applications, etc.

[0065] Conventional integrated circuit manufacturing processes create various design variants that require different sets of expensive masks, different test regimes, etc. In contrast, according to the present invention, integrated circuits can be fabricated with a conventional MOS transistor architecture supplemented by AP transistors that can have programmability capabilities in-field or during the test phase. The programmability capabilities can activate or deactivate features on the integrated circuit to achieve a desired variant. Thus, a single integrated circuit can be designed, manufactured, and tested, reducing manufacturing costs such as the requirement for additional mask sets and / or test systems while still allowing a manufacturer to sell multiple variants.

[0066] Furthermore, if a manufactured integrated circuit fails a test related to the performance requirements of one variant (e.g., a high-speed server variant), it is contemplated that the integrated circuit may be programmably reconfigured via AP transistors into a variant (e.g., a desktop computer processor) where the failed test is not related to successful performance of that variant.

[0067] For example, a server variant may specify a certain number of operational processor cores, while a desktop variant may specify fewer cores. If one or more cores of a particular manufactured integrated circuit fail a test, the failed cores may be deactivated by AP transistors and effectively removed from the integrated circuit, allowing the integrated circuit to be reconfigured as another variant, such as a desktop computer variant intended and provided with a reduced number of processing cores. In such a case, the AP transistors may, for example, disable the power supplied to the disabled cores. Such a capability would effectively lead to increased yields, as more manufactured devices could be sold, albeit perhaps at a lower price.

[0068] 7 shows a flowchart of a method according to one embodiment of the present invention. The method begins in step 500, where a MOS logic circuit is designed. In step 504, points in the designed circuit that may require correction are identified. This identification can be performed by reviewing the design using simulation tools, designer-led reviews, etc., or by using the design to manufacture a "first silicon" run of an integrated circuit and then testing that first silicon run instance to identify areas that may require correction.

[0069] In step 508, the design of the integrated circuit is modified to include corrective elements at the points determined in step 504. In step 512, instances of the integrated circuit are manufactured using the design modified in step 508.

[0070] In step 516, the integrated circuit instance manufactured in step 512 is tested to identify points in the circuit where it is desired to activate corrective elements, and in element step 520, the corrective elements at those identified points are connected to the MOS logic circuitry of the integrated circuit.

[0071] 7 is directed to improving the yield of manufactured integrated circuits through post-manufacturing verification and correction, as noted above, the present invention can also be used to correct faults and failures in integrated circuits while they are in use. Specifically, steps 516 and 520 can be performed dynamically while the integrated circuit is in use to correct problems and failures that arise due to aging, environmental conditions, etc.

[0072] The above-described embodiments of the invention are intended to be examples of the invention, and changes and modifications may be made by those skilled in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims

1. 1. A system for increasing the yield of manufactured integrated circuits, wherein each integrated circuit comprises: a designed set of circuits implemented as front-end-of-line manufactured circuit elements, the circuit elements including at least one of the front-end-of-line circuit elements being a corrective element; at least one transistor fabricated as a replacement planar transistor, the at least one transistor operable to selectively activate or deactivate at least one corrective front end of line circuit element according to results of tests performed on the integrated circuit after fabrication of the integrated circuit.

2. 10. The system of claim 1, wherein the corrective circuitry comprises an additional buffer for strengthening the signal in the at least one front-end element.

3. The system of claim 2 , wherein the buffer is a clock buffer.

4. the integrated circuit includes at least two corrective front-end circuit elements and at least two alternative planar transistors; a first alternative planar transistor of the at least two alternative planar transistors operable to selectively activate or deactivate a first corrective front end of line circuit element of the at least two corrective front end of line circuit elements to increase a rate of a rising edge of a clock signal passing through the buffer; 4. The system of claim 3, wherein a second of the at least two alternative planar transistors is operable to selectively activate or deactivate a second of the at least two corrective front end of line circuit elements to increase a rate of a falling edge of the clock signal passing through the buffer.

5. 10. The system of claim 1, further comprising a programmable memory element for controlling selective activation and deactivation of at least one of said corrective front end of line circuit elements.

6. 3. The system of claim 2, wherein the redundant front end of line circuit element is an additional reinforced buffer for the input / output signal.

7. 1. An integrated circuit comprising: at least two circuits, each circuit designed to implement a function, the first of the at least two circuits being designed to implement an optional function; at least one alternative planar transistor operable to selectively enable and disable the first circuit of the at least two circuits; programmable means for controlling said at least one alternative planar transistor to enable and disable said first circuit of said at least two circuits; 1. An integrated circuit comprising:

8. 8. The integrated circuit of claim 7, wherein the programmable means is responsive to an input from the test of the first of the at least two circuits to deactivate the first of the at least two circuits if the first of the at least two circuits fails a test.

9. 1. A method for manufacturing an integrated circuit, comprising: designing the circuitry necessary to achieve the desired functionality of the integrated circuit; examining the design of the required circuit to determine areas that may have operational problems due to manufacturing process variations; adding corrective elements to the design of the required circuit to provide corrective circuit functionality in the determined region; performing front-end-of-line manufacturing of the designed integrated circuit; fabricating, for at least each determined region, an alternative planar transistor, the alternative planar transistor operable to selectively enable and disable the correction circuitry within the determined region; completing the manufacturing process to obtain the completed integrated circuit; testing the completed integrated circuit to identify designated areas that do not meet predetermined test criteria for the determined areas, and for each identified designated area, testing to program the transistor associated with each identified designated area to enable the respective corrective element.

10. 10. The method of claim 9, wherein the corrective element is a clock buffer.

11. The method of claim 9 , wherein the corrective element is a power decoupler.

12. 10. The method of claim 9, wherein the step of testing the completed integrated circuit is performed dynamically during operation of the integrated circuit.

13. 1. A method for increasing yield in manufacturing integrated circuits, comprising: designing a MOS logic integrated circuit; determining at least one possible point of circuit failure in the designed MOS logic integrated circuit; modifying the design of the MOS logic integrated circuit by adding a corrective element to the design of the MOS logic integrated circuit at the determined at least one possible failure point, the corrective element being to be located on a plane of the MOS logic integrated circuit other than a plane of the MOS logic integrated circuit in which MOS logic is located; fabricating the MOS logic integrated circuit using the modified design; determining whether the at least one possible failure point is a failure point and testing the manufactured integrated circuit to detect whether the at least one possible failure point is a failure point; connecting the corrective element to the determined fault point in the fabricated MOS logic to correct the fault.

14. 14. The method of claim 13, wherein the corrective element is connected to the determined fault point through a transistor formed in a plane of a MOS logic integrated circuit other than the plane in which the MOS logic is located.

15. 15. The method of claim 14, wherein the transistor connects the corrective element in response to a dynamic signal.

16. 16. The method of claim 15, wherein the dynamic signal is provided in response to a measured function of the MOS logic circuit during operation.

17. 14. The method of claim 13, wherein the corrective element is a clock buffer.

18. 20. The method of claim 17, wherein the clock buffer is operable to strengthen a rising edge of a clock signal.

19. 20. The method of claim 17, wherein the clock buffer is operable to reinforce a falling edge of the clock signal.

20. 17. The method of claim 16, wherein the corrective element is a clock buffer and the dynamic signal is provided by a clock management system including at least one of a phase-locked loop and a delay-locked loop.

21. 15. The method of claim 14, wherein the corrective element is a decoupling capacitor.

22. 15. The method of claim 14, wherein the corrective element is a buffer for strengthening the output signal.

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