Selective penetration during lithography process flow in EUV chemically amplified resist (CAR)

Abstract

[0003] Embodiments disclosed herein include a method for patterning a substrate. In one embodiment, the method includes disposing a photoresist layer on a substrate and exposing the photoresist layer to form exposed and unexposed regions in the photoresist layer. In one embodiment, the method further includes treating either the exposed or unexposed regions using a sequential infiltration synthesis (SIS) process to form treatment regions, and developing the photoresist layer to remove portions of the photoresist layer other than the treatment regions.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 18 / 407,776, filed January 9, 2024, which claims the benefit of U.S. Provisional Application No. 63 / 444,852, filed February 10, 2023, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present disclosure relate to the field of semiconductor processing, and more particularly to sequential infiltration synthesis (SIS) for extreme ultraviolet (EUV) resist development. [Background technology]

[0003] Lithography has been used for decades in the semiconductor industry to create 2D and 3D patterns for microelectronic devices. The lithography process involves spin-on deposition of a film (photoresist), irradiating (exposing) the film with a selected pattern using an energy source, and dissolving it in a solvent to remove (etch) either the exposed (positive tone) or unexposed (negative tone) areas of the film. A bake is then performed to remove any remaining solvent.

[0004] Photoresist is a radiation-sensitive material that, when irradiated, undergoes a chemical change in the exposed portions of the film, allowing for a change in solubility between the exposed and unexposed areas. This change in solubility is used to remove (etch) either the exposed or unexposed areas of the photoresist. This develops the photoresist, allowing the pattern to be transferred by etching into the underlying thin film or substrate. After the pattern is transferred, the remaining photoresist is removed, and this process can be repeated multiple times to create the 2D and 3D structures used in microelectronic devices.

[0005] Several properties are important in lithography processes. These properties include sensitivity, resolution, low line edge roughness (LER), etch resistance, and the ability to form thinner layers. The higher the sensitivity, the less energy is required to change the solubility of the deposited film. This can improve the efficiency of the lithography process. Resolution and LER determine how narrow features can be achieved in the lithography process. Pattern transfer to form deep structures requires materials with higher etch resistance. Materials with higher etch resistance also allow for thinner films. Thinner films improve the efficiency of the lithography process. Summary of the Invention

[0006]

[0003] Embodiments disclosed herein include a method for patterning a substrate. In one embodiment, the method includes disposing a photoresist layer on a substrate and exposing the photoresist layer to form exposed and unexposed regions in the photoresist layer. In one embodiment, the method further includes treating either the exposed or unexposed regions using a sequential infiltration synthesis (SIS) process to form treatment regions, and developing the photoresist layer to remove either portions of the treatment regions or portions of the photoresist layer other than the treatment regions.

[0007] Embodiments disclosed herein may also include a method of treating a substrate with a photoresist layer. In one embodiment, the method includes exposing the photoresist layer to extreme ultraviolet (EUV) radiation to form exposed and unexposed regions, the exposed region being adjacent to and contacting the exposed region. In one embodiment, the method further includes treating the photoresist layer with a sequential infiltration synthesis (SIS) process to form treatment regions, the treatment regions being in either the exposed or unexposed regions, and developing the photoresist layer to leave the treatment regions. In one embodiment, the method further includes etching the substrate using the treatment regions as a mask.

[0008]

[0010] Embodiments disclosed herein may also include a method of processing a substrate using a photoresist layer. In one embodiment, the method includes exposing the photoresist layer to extreme ultraviolet (EUV) radiation to form exposed and unexposed regions, and selectively depositing a capping layer over either the exposed or unexposed regions. In one embodiment, the method further includes developing the photoresist layer to leave the capping layer and an underlying region of either the exposed or unexposed regions, and etching the substrate using the capping layer and the underlying region of either the exposed or unexposed regions as a mask. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a cross-sectional view of a substrate having a photoresist layer, according to an embodiment. [Figure 1B] 1A and 1B are cross-sectional views of a substrate during exposure of a photoresist layer, according to an embodiment. [Figure 1C] 1 is a cross-sectional view of a substrate having developed photoresist, according to an embodiment. [Figure 1D]1 is a cross-sectional view of a substrate having processed photoresist, according to an embodiment. [Figure 1E] 1A and 1B are cross-sectional views of a substrate after an etching process, according to an embodiment. [Figure 2A] 1 is a cross-sectional view of a substrate having a photoresist layer, according to an embodiment. [Figure 2B] 1A and 1B are cross-sectional views of a substrate during exposure of a photoresist layer, according to an embodiment. [Figure 2C] 3A and 3B are cross-sectional views of a substrate having exposed regions of a photoresist layer after processing, according to an embodiment. [Figure 2D] 1 is a cross-sectional view of a substrate having a developed photoresist layer, according to an embodiment. [Figure 2E] 1 is a cross-sectional view of a substrate after etching, according to an embodiment. [Figure 3A] 1 is a cross-sectional view of a substrate having a photoresist layer during exposure, according to an embodiment. [Figure 3B] 1 is a cross-sectional view of a substrate after a photoresist layer has been processed, according to an embodiment. [Figure 3C] 1 is a cross-sectional view of a substrate after a photoresist layer has been developed, according to an embodiment. [Figure 3D] 4A and 4B are cross-sectional views of a substrate after the substrate has been etched, according to an embodiment. [Figure 4A] 1 is a cross-sectional view of a substrate having an exposed photoresist layer with a capping layer formed on the exposed regions, according to an embodiment. [Figure 4B] 1 is a cross-sectional view of a substrate after a photoresist layer has been developed, according to an embodiment. [Figure 4C] 4A and 4B are cross-sectional views of a substrate after the substrate has been etched, according to an embodiment. [Figure 5A] 1 is a cross-sectional view of a substrate having an exposed photoresist layer with a capping layer formed on the exposed regions, according to an embodiment. [Figure 5B] 1 is a cross-sectional view of a substrate after a photoresist layer has been developed, according to an embodiment. [Figure 5C]4A and 4B are cross-sectional views of a substrate after the substrate has been etched, according to an embodiment. [Figure 6] FIG. 1 illustrates a plan view of a cluster tool that may be used to process a substrate having exposed photoresist, according to an embodiment. [Figure 7] 1 illustrates a block diagram of an exemplary computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] This specification describes sequential infiltration synthesis (SIS) for extreme ultraviolet (EUV) resist development. The following description sets forth numerous specific details for developing photoresist (such as thermal vapor processes and material regimes) in order to provide a comprehensive understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0011] Specifically, photoresist systems used in extreme ultraviolet (EUV) lithography suffer from inefficiencies. Existing photoresist material systems for EUV lithography require high dosages to provide the solubility switch necessary to render the photoresist material developable. Chemically amplified resists (CARs) contain chemistries that are sensitive to EUV radiation. The chemical amplification concept uses photochemically generated acid as a catalyst. This catalyst initiates a chain reaction of chemical changes within the resist film, providing a gain mechanism to completely convert the exposed regions of the photoresist. The converted regions of the CAR then have etch selectivity over the unexposed regions. In this way, a development process can be used to remove the exposed regions while leaving the unexposed regions intact, or to remove the unexposed regions while leaving the exposed regions intact.

[0012] In another example, organic-inorganic hybrid materials (e.g., metal-oxo material systems) have been proposed as material systems for EUV lithography due to their improved sensitivity to EUV radiation. Such material systems typically contain a metal (e.g., Sn, Hf, Zr, etc.), oxygen, and carbon. Metal-oxo-based organic-inorganic hybrid materials have also been shown to provide low LER, low LWR, and higher resolution, which are necessary properties for forming narrow features.

[0013] In metal-oxo photoresist systems, exposure to EUV radiation causes cross-linking and carbon removal. The difference in carbon percentage between exposed and unexposed areas is used as a solubility switch during development. Specifically, in negative-tone development, unexposed areas with a high carbon content are preferentially etched by the developer. However, it should be understood that in some embodiments, positive-tone development may also be used.

[0014] Thus, there are several approaches to providing highly sensitive EUV photoresists. However, after developing the photoresist, the resulting pattern may not have sufficient etch selectivity to the underlying substrate to provide patterned features with the desired accuracy, resolution, critical dimensions, line edge roughness (LER), line width roughness (LWR), etc. Therefore, a modification process called sequential infiltration synthesis (SIS) can be performed to modify the photoresist. This modification improves the robustness of the photoresist and further protects it from etching chemistries. In some embodiments, the SIS process may include introducing a metal-containing precursor to form a metal oxide material (e.g., alumina) within the photoresist layer. Embodiments may also use a nitrogen-containing gas to form a metal nitride material within the photoresist layer. However, in some embodiments, a non-metal SIS process may also be used. For example, SiCl4 may be provided as a precursor and nitrided with NH3 gas.

[0015] 1A-1E, a series of cross-sectional views are shown illustrating an EUV photolithography patterning process that includes an SIS process. The SIS process illustrated in FIGS. 1A-1E can be considered a conventional process, which describes a process in which the SIS process is performed after the photoresist layer is developed.

[0016] 1A, a cross-sectional view of a substrate 101 is shown. The substrate 101 may be a semiconductor substrate such as silicon. The substrate 101 may also be other materials such as oxides, nitrides, metals, or any other material useful in semiconductor manufacturing processes. The substrate 101 may have a form factor standard for semiconductor processing, such as a wafer (e.g., a 200 mm wafer, a 300 mm wafer, a 450 mm wafer, etc.).

[0017] In some cases, the substrate 101 may be covered by an underlayer 102. The underlayer 102 may be one or more of an anti-reflective coating (ARC), a hard mask layer, or any other layer to enhance patterning. A photoresist layer 110 may be provided on the underlayer 102. The photoresist layer 110 may be a CAR or metal-oxo photoresist system. The photoresist layer 110 may be tailored to absorb and react to EUV radiation. However, DUV radiation may also be used in some cases.

[0018] 1B, a cross-sectional view of substrate 101 during a lithographic exposure process is shown. The lithographic exposure process may include the use of EUV or DUV radiation (indicated by arrows) through a mask 120, reticle, or the like. Openings in mask 120 form exposed regions 115 in photoresist layer 110. Exposed regions 115 may have etch selectivity relative to unexposed regions of photoresist layer 110. The exposure process may be followed by an optional post-exposure bake (PEB) to allow conversion of exposed regions 115 through the entire thickness of photoresist layer 110.

[0019] 1C, a cross-sectional view of substrate 101 is shown after photoresist layer 110 has been developed. Photoresist layer 110 can be developed using a wet or dry etching process. In particular, unexposed areas of photoresist layer 110 may be removed, leaving exposed areas 115. Exposed areas 115 have a pattern that is subsequently transferred to the underlying substrate 101.

[0020] Referring now to FIG. 1D, a cross-sectional view of the substrate 101 after the SIS process is shown. The SIS process can form processed regions 117 in the exposed regions 115. As shown, the processed regions 117 can form a shell around the exposed regions 115. However, in some cases, the exposed regions can be completely converted to processed regions 117. The SIS process can include flowing precursors into a chamber. The precursors penetrate the pores of the exposed regions 115. As shown, both the top surface and sidewalls can be converted to processed regions 117. The top surface 103 of the underlayer 102 can also be exposed and damaged by the SIS process.

[0021] 1E, a cross-sectional view of substrate 101 after an etching process is shown. The etching process may result in features 105 that penetrate through underlying layer 102 and into substrate 101. Feature 105 may be a trench, hole, line, etc. After the etching process, underlying layer 102 and exposed regions 115 of photoresist layer 110 may be removed.

[0022] The process described above with respect to FIGS. 1A-1E is not without its problems. One problem is that the SIS process is performed after the development process. As a result, some damage may occur to the exposed underlayer 102. Damage to the underlayer 102 may adversely affect pattern transfer to the underlying substrate 101. Furthermore, the process described above may be performed by transporting the substrate through multiple different tools (e.g., resist deposition tool, exposure tool, developer tool, SIS tool, etching tool, etc.). This results in significant downtime between processing steps and exposes the substrate 101 to potential damage or particle contamination.

[0023] Accordingly, embodiments disclosed herein include an SIS process that occurs before a photoresist development process, thereby protecting underlying layers during the SIS process. Furthermore, this processing can be performed, at least in part, in a cluster tool. A cluster tool includes multiple different processing chambers that are coupled together through a transfer chamber, thereby eliminating the need to remove the substrate from a vacuum environment between different processing steps.

[0024] In one embodiment, the photoresist patterning process described herein can be performed using either a CAR system or a metal-oxo system. Furthermore, the photoresist material can be sensitive to either EUV or DUV radiation. Also, the SIS process can include a metal-based process or a non-metal-based process.

[0025] Because the SIS process is performed before developing the photoresist, the SIS process may need to be selective between exposed and unexposed regions. For example, a change in the functional group of the photoresist can be used as a switch to selectively perform the SIS process. In one example, EUV or DUV exposure can change the functional group from an ester to a hydroxide.

[0026] 2A-2E, a series of cross-sectional views are shown illustrating a process for patterning a substrate 201 with a photolithography process, according to an embodiment. In one embodiment, the photolithography process can be an EUV or DUV process to expose a photoresist layer, an SIS treatment of the photoresist layer, and a development of the photoresist layer.

[0027] 2A, a cross-sectional view of a substrate 201 is shown, according to an embodiment. The substrate 201 may be a semiconductor substrate, such as silicon. The substrate 201 may also be other materials, such as oxides, nitrides, metals, or any other material useful in semiconductor manufacturing processes. In one embodiment, the substrate 201 may have a form factor standard for semiconductor processing, such as a wafer (e.g., a 200 mm wafer, a 300 mm wafer, a 450 mm wafer, etc.).

[0028] In some embodiments, the substrate 201 may be covered by an underlayer 202. The underlayer 202 may be one or more of an ARC, a hard mask layer, or any other layer to enhance patterning. A photoresist layer 210 may be provided on the underlayer 202. The photoresist layer 210 may be a CAR or metal-oxo photoresist system. The photoresist layer 210 may be tailored to absorb and react to EUV radiation. However, in some embodiments, DUV radiation may also be used.

[0029] 2B, a cross-sectional view of substrate 201 during a lithographic exposure process is shown. The lithographic exposure process may include the use of EUV or DUV radiation (shown by arrows) through a mask 220, reticle, or the like. Openings in mask 220 form exposed regions 215 in photoresist layer 210. Exposed regions 215 may have etch selectivity relative to unexposed regions of photoresist layer 210. After the exposure process, a PEB may be performed in some embodiments to allow conversion of exposed regions 215 through the entire thickness of photoresist layer 210.

[0030] Referring now to FIG. 2C , a cross-sectional view of substrate 201 after SIS processing is shown, according to an embodiment. In one embodiment, the SIS process converts exposed regions 215 into processed regions 217. The processed regions 217 may include a reinforcing structure, such as a metal oxide (e.g., alumina), or a non-metallic reinforcing material. Because the SIS process is performed before developing photoresist 210, the SIS process only has access to the top surface of exposed regions 215. In this manner, the SIS process may be performed such that processed regions 217 diffuse through the entire thickness of exposed regions 215. However, in some embodiments, partial diffusion through the thickness of the exposed regions is possible. In such partial diffusion embodiments, the entire sidewalls of exposed regions 215 may not be converted to processed regions 217, and a dry development process may be required.

[0031] In one embodiment, the SIS process may utilize a switch in the functional group of the exposed regions 215 to selectively process the photoresist layer 210. For example, the unexposed regions 210 may have ester functional groups and the exposed regions 215 may have hydroxide functional groups. The SIS process may preferentially react with the hydroxide functional groups over the ester functional groups.

[0032] In one embodiment, the SIS process can include any type of SIS process. In one embodiment, the SIS process is a non-metal process. In such an embodiment, the SIS process can include a repeated sequence of steps. The sequence can first include exposing the photoresist layer 210 to a precursor containing silicon or boron. The sequence can then continue by infiltrating the precursor into the photoresist layer 210 through pores contained in the photoresist layer 210. In one embodiment, the sequence further includes purging the process area to remove any residue of the precursor-containing gas and exposing the photoresist layer to an oxidizing agent. In one embodiment, the oxidizing agent penetrates the photoresist layer 210 through pores contained in the photoresist layer 210, producing an oxide coating disposed on the interior surface of the photoresist layer. In one embodiment, the oxide coating comprises silicon oxide or boron oxide. The process can continue with purging the process area to remove any residue of the oxidizing agent-containing gas. This sequence can be repeated any number of times to provide a desired level of conversion of the exposed regions to the processed regions.

[0033] In another embodiment, a metal-based SIS process may be used. The metal-based SIS process may include a repeated sequence of pressurized introduction of a methyl-containing material and an oxidizing gas into a processing environment adjacent to the photoresist layer 210. As an example, a methyl-containing material may be used, but embodiments are not limited to this material class. For example, the metal precursor may also include diethylzinc (DEZ), which forms ZnO. A metal-containing precursor (e.g., Al or Zn) is infiltrated into the photoresist layer 210, and excess precursor is removed by purging. An oxidizing gas (e.g., HO) is then used to convert the metal precursor in the photoresist layer 210 to a metal oxide. In one embodiment, the metal oxide may include alumina or any other suitable metal oxide material (e.g., ZnO). Embodiments may also include using a nitrogen-containing gas to form nitrides. For example, to form TiN, TiCl4 may be used as the metal precursor and NH3 may be flowed in as the nitriding gas. Non-metal precursors may also follow a similar SIS process. For example, SiCl4 may be supplied as a precursor and nitrided with NH3 gas. Such a sequence may be repeated any number of times to provide the desired level of conversion of the exposed area to the processed area.

[0034] 2D, a cross-sectional view of substrate 201 after a development process is shown, according to an embodiment. In one embodiment, photoresist layer 210 can be developed by removing unexposed areas, leaving processed areas 217. The development process can be a dry or wet development process.

[0035] 2E, a cross-sectional view of substrate 201 after an etching process is shown, according to an embodiment. In one embodiment, the etching process may be a wet or dry etching process. The etching process may form features 205 in substrate 201. Features 205 may be trenches, holes, lines, etc. After the etching process, remaining portions of underlayer 202 and photoresist layer 210 (e.g., processed region 217) may be removed.

[0036] In one embodiment, the processes illustrated in Figures 2A-2E may be performed in fewer processing tools than those described in Figures 1A-1E. For example, the SIS process, the development process, and the etch process may be performed in a single cluster tool. An example of a suitable cluster tool is described in more detail below. As such, there is less opportunity for damage or particle contamination when using processes such as those described herein. Additionally, metrology tools, etc., may be included in the cluster tool to perform after-develop inspection (ADI) and / or after-etch inspection (AEI).

[0037] 3A-3D, a series of cross-sectional views illustrating a process for etching a substrate according to an additional embodiment are shown. The embodiment shown in Figures 3A-3D is similar to the embodiment shown in Figures 2A-2E, except that the tone of the photoresist development is reversed. That is, before etching the substrate, the unexposed areas are treated with an SIS process and the exposed areas are removed.

[0038] 3A, a cross-sectional view of a substrate 301 during lithographic exposure is shown, according to an embodiment. In one embodiment, the substrate 301 can be a semiconductor, oxide, nitride, metal, or any other material suitable for semiconductor manufacturing. In one embodiment, an underlayer 302 can be provided on the substrate 301, and a photoresist layer 310 can be provided on the underlayer 302. The photoresist layer 310 can be a CAR or metal-oxo resist system. In one embodiment, a mask 320 or reticle can be used to selectively expose portions of the photoresist layer 310 to form exposed regions 315.

[0039] 3B, a cross-sectional view of the substrate 301 after an SIS process is shown, according to an embodiment. In one embodiment, the SIS process may be selective to unexposed areas of the photoresist layer 310. The SIS process may be a metal-based process or a non-metal-based process. The SIS process may be similar to the SIS process described in more detail above. The SIS process may result in the formation of processed regions 317 between the exposed regions 315.

[0040] 3C, a cross-sectional view of substrate 301 after a development process is shown, according to an embodiment. In an embodiment, the development process may remove exposed regions 315. For example, the development process may be performed as a dry development process or a wet development process. If treatment regions 317 only partially penetrate the thickness of photoresist layer 310, a dry development process may be necessary because dry development processes are more anisotropic in nature than wet development processes.

[0041] 3D, a cross-sectional view of substrate 301 after an etching process is shown, according to an embodiment. In one embodiment, the etching process may form features 305 in substrate 301. The features 305 may include trenches, holes, lines, etc. The etching process may be a dry etching process in some embodiments.

[0042] 2A-2E, the processes of Figures 3A-3D may be performed in an exposure tool and a cluster tool. More particularly, the treatment, development, and etch processes may all be performed in a single cluster tool, with or without associated metrology.

[0043] 2A-3D illustrate SIS processing of a photoresist layer. However, embodiments are not limited to such a process flow. For example, a capping layer may be provided over exposed or unexposed regions of the photoresist to enhance etch selectivity with the underlying substrate. The embodiments shown in FIGS. 4A-5C provide examples of such embodiments.

[0044] 4A, a cross-sectional view of a substrate 401 is shown, according to an embodiment. In one embodiment, the substrate 401 may be similar to any of the substrates described in more detail above. In one embodiment, the substrate 401 may have an underlayer 402 and a photoresist layer 410 provided thereon. The photoresist layer 410 may be a CAR or metal oxo resist.

[0045] In one embodiment, the photoresist layer 410 may be exposed to include exposed and unexposed regions 415. The exposure process may be similar to any of the exposure processes described in more detail above. In one embodiment, a capping layer 430 may be formed over the exposed regions 415. The capping layer 430 may be a hard mask material such as an oxide, a nitride, or the like. The capping layer 430 may be selectively formed over the exposed regions 415 using any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or self-assembled monolayer (SAM) deposition. The deposition process may also be performed in a cluster tool.

[0046] 4B, a cross-sectional view of substrate 401 after a development process is shown, according to an embodiment. In one embodiment, the development process may remove unexposed areas of photoresist layer 410. The development process may be a dry development process in some embodiments. However, in some cases, a wet process may also be used.

[0047] 4C, a cross-sectional view of substrate 401 after an etching process is shown, according to an embodiment. In one embodiment, the etching process results in the formation of features 405 (e.g., trenches, holes, lines, etc.) in substrate 401. After etching, remaining portions of underlayer 402 and photoresist layer 410 may be removed.

[0048] 4A-4C may all be performed in a single cluster tool. For example, the cluster tool may include a deposition chamber for depositing capping layer 430, a dry develop chamber for developing photoresist layer 410, and an etch chamber for etching substrate 401.

[0049] 5A-5C, a series of cross-sectional views illustrating a process for etching a substrate 501 according to an additional embodiment are shown. The embodiment shown in Figures 5A-5C is substantially similar to the embodiment described in Figures 4A-4C, except that the tone of the photoresist is reversed, i.e., the unexposed areas remain after the development process.

[0050] 5A, a cross-sectional view of a substrate 501 is shown, according to an embodiment. In one embodiment, the substrate 501 may be similar to any of the substrates described in more detail above. In one embodiment, the substrate 501 may have an underlayer 502 and a photoresist layer 510 disposed thereon. The photoresist layer 510 may be a CAR or metal oxo resist.

[0051] In one embodiment, the photoresist layer 510 may be exposed to include exposed regions 515 and unexposed regions 510. The exposure process may be similar to any of the exposure processes described in more detail above. In one embodiment, a capping layer 530 may be formed on the unexposed regions 510. The capping layer 530 may be a hard mask material, such as an oxide, a nitride, or the like. The capping layer 530 may be selectively formed on the unexposed regions 510 using any suitable deposition process, such as ALD, CVD, or SAM deposition. The deposition process may also be performed in a cluster tool.

[0052] 5B, a cross-sectional view of substrate 501 after a development process is shown, according to an embodiment. In one embodiment, the development process may remove exposed areas 515 of photoresist layer 510. The development process may be a dry development process in some embodiments. However, in some cases, a wet process may also be used.

[0053] 5C, a cross-sectional view of substrate 501 after an etching process is shown, according to an embodiment. In one embodiment, the etching process results in the formation of features 505 (e.g., trenches, holes, lines, etc.) in substrate 501. After etching, remaining portions of underlayer 502 and photoresist layer 510 may be removed.

[0054] 5A-5C may all be performed in a single cluster tool. For example, the cluster tool may include a deposition chamber for depositing capping layer 530, a dry develop chamber for developing photoresist layer 510, and an etch chamber for etching substrate 501.

[0055] Referring now to FIG. 6 , a plan view of a cluster tool 600 is shown, according to an embodiment. In one embodiment, the cluster tool 600 may include a front-end equipment module (EFEM) 621. The EFEM 621 may receive a front-opening unified pod (FOUP), cassette, or the like, as an entry point for substrates into the cluster tool 600. Substrates processed in the cluster tool 600 may include wafers (e.g., silicon wafers or other semiconductor wafers) of any standard form factor (e.g., 200 mm, 300 mm, 450 mm, etc.). In one embodiment, the EFEM 621 may be coupled to the rest of the cluster tool 600 through a load lock 622. The load lock 622 may isolate atmospheric conditions within the EFEM from vacuum conditions in the rest of the cluster tool 600. However, in some embodiments, the EFEM may also be held at a sub-atmospheric pressure (e.g., a higher pressure than the other side of the load lock 622).

[0056] In one embodiment, a metrology tool 625 may be provided after the load lock 622. The metrology tool 625 may be a scatterometry tool or any other metrology tool useful for ADI or AEI applications. In one embodiment, the metrology tool 625 may be communicatively coupled to a transfer chamber 627. The transfer chamber 627 may include a robotic arm, a track, or any suitable architecture for transporting substrates between the metrology tool 625 and the rest of the cluster tool 600.

[0057] In one embodiment, the transfer chamber 627 may be coupled to one or more developer chambers 610 and one or more etch chambers 612. For example, the cluster tool 600 may be equipped with six developer chambers 610 and four etch chambers 612. The cluster tool 600 may also be equipped with one or more deposition chambers 615. The chambers 610, 612, and 615 may be located on two sides of the transfer chamber 627 to optimize space savings. In one embodiment, the developer chamber 610 may be a dry developer chamber. A plasma source may be used in combination with the developer chamber 610 to develop the resist layer without the use of wet chemistries. Furthermore, the etch chamber 612 may be a dry etch chamber 612 that uses plasma to etch the substrate through the resist layer. The deposition chamber 615 may be a dry deposition chamber (e.g., ALD, CVD, etc.) used to deposit a photoresist layer and / or a capping layer.

[0058] In one embodiment, a substrate enters the EFEM, passes through load lock 622 and metrology tool 625, and is sent to one of the development chambers 610. After development, the substrate is sent to metrology tool 625 for ADI. After ADI, the substrate may be sent through transfer chamber 627 to one of the etching chambers 612, where the substrate may be etched through the developed resist layer. The substrate may then be returned to metrology tool 625 for AEI. Thus, the steps of resist development, capping layer deposition, ADI, substrate etch, and AEI may be performed within a single cluster tool 600 without having to leave the vacuum environment.

[0059] FIG. 7 illustrates a schematic diagram of a machine in the exemplary form of a computer system 700 within which a set of instructions for causing the machine to perform any one or more of the methodologies described herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate as a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Furthermore, while only a single machine is illustrated, the term "machine" is intended to include any collection of machines (e.g., computers) that individually or jointly execute a set of instructions (or sets) to perform any one or more of the methodologies described herein.

[0060] The exemplary computer system 700 includes a processor 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and a secondary memory 718 (e.g., a data storage device, etc.), which communicate with each other via a bus 730.

[0061] Processor 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, processor 702 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processor 702 is configured to execute processing logic 726 for performing the operations described herein.

[0062] Computer system 700 may further include a network interface device 708. Computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generation device 716 (e.g., a speaker).

[0063] The secondary memory 718 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 732 having stored thereon one or more sets of instructions (e.g., software 722) that embody any one or more of the methods or functions described herein. The software 722 may also reside, completely or at least partially, within the main memory 704 and / or the processor 702 during execution by the computer system 700. The main memory 704 and the processor 702 also constitute machine-readable storage media. The software 722 may further be transmitted or received over the network 720 via the network interface device 708.

[0064] While the exemplary embodiment depicts machine-accessible storage medium 732 as a single medium, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium capable of storing or encoding a set of instructions that are executable by a machine and cause the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0065] According to one embodiment of the present disclosure, a machine-accessible storage medium has stored thereon instructions for causing a data processing system to execute a method for exposing a photoresist, performing a SIS process on the photoresist, developing the photoresist, and etching an underlying substrate. The process is performed at least in part in a cluster tool. The cluster tool may include a metrology tool, a development chamber, a deposition chamber, and an etch chamber. In one embodiment, the method disclosed herein may improve etch performance compared to conventional methods.

[0066] Thus, a method is described for processing a substrate using a SIS process where the substrate resides in a cluster tool comprising a metrology tool, a dry develop chamber, a deposition chamber, and an etch chamber.

Claims

1. 1. A method of patterning a substrate, comprising: disposing a photoresist layer on a substrate; exposing the photoresist layer to light to form exposed and unexposed areas in the photoresist layer; treating either the exposed areas or the unexposed areas using a sequential infiltration synthesis (SIS) process to form treated areas; developing the photoresist layer to remove a portion of the processing area or a portion of the photoresist layer outside the processing area; A method comprising:

2. The method of claim 1 , wherein the SIS process is a metal SIS process.

3. The method of claim 1 , wherein the SIS process is a non-metallic SIS process.

4. The method of claim 1 , wherein the treatment region extends through the entire thickness of the photoresist layer.

5. The method of claim 1 , wherein the treatment region extends partially through the thickness of the photoresist layer.

6. The method of claim 4 , wherein developing the photoresist layer is performed using a dry process.

7. Etching the substrate using the processing region as a mask. The method of claim 1 further comprising:

8. The method of claim 1 , wherein the SIS process and the developing are performed in a single cluster tool.

9. 10. The method of claim 1, wherein the photoresist layer is a chemically amplified resist (CAR) or a metal oxo resist.

10. 1. A cluster tool for patterning a substrate with a photoresist layer, comprising: a first chamber; a second chamber coupled to the first chamber; a third chamber coupled to the first chamber and the second chamber; Equipped with exposing the substrate with the photoresist layer to extreme ultraviolet (EUV) radiation to form exposed and unexposed regions; the first chamber is configured to selectively process either the exposed region or the unexposed region using a sequential infiltration synthesis (SIS) process to form a treated region; the second chamber is configured to develop the photoresist layer so as to leave the processing region; The third chamber is configured to etch the substrate using the processing region as a mask.

11. The cluster tool of claim 10 , further comprising a fourth chamber, wherein metrology is performed on the substrate in the fourth chamber after development and / or after etching.

12. The cluster tool of claim 10 , wherein developing the photoresist layer in the second chamber is a thermal dry development process.

13. 11. The cluster tool of claim 10, wherein the photoresist layer comprises a chemically amplified resist (CAR) or a metal oxo resist.

14. 1. A cluster tool for patterning a substrate having a photoresist layer, comprising: a first chamber; a second chamber coupled to the first chamber; a third chamber coupled to the first chamber and the second chamber; Equipped with exposing the photoresist layer to extreme ultraviolet (EUV) radiation to form exposed and unexposed regions; the first chamber is configured to selectively deposit a capping layer over either the exposed areas or the unexposed areas; the second chamber is configured to develop the photoresist layer so as to leave the capping layer and an underlying one of the exposed or unexposed regions; The third chamber is configured to etch the substrate using the capping layer and the underlying one of the exposed regions or the unexposed regions as a mask.

15. a fourth chamber coupled to the first chamber, the second chamber, and the third chamber, the fourth chamber being a metrology chamber configured to perform metrology on the substrate after development and / or after etching; The cluster tool of claim 14 further comprising:

16. The cluster tool of claim 14 , wherein developing the photoresist layer in the second chamber is a thermal dry development process.

17. 15. The cluster tool of claim 14, wherein the photoresist layer comprises a chemically amplified resist (CAR) or a metal oxo resist.

18. The cluster tool of claim 14 , wherein depositing the capping layer is performed using atomic layer deposition, chemical vapor deposition, or a self-assembled monolayer process.

19. The cluster tool of claim 14 , wherein the capping layer is selectively deposited as a result of functional group changes resulting from the EUV exposure.

20. 15. The cluster tool of claim 14, wherein the first chamber, the second chamber, and the third chamber are coupled together by a transfer chamber, and the first chamber, the second chamber, and the third chamber are on the same side of a load lock within the cluster tool.

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