System and method for bonding transparent conductive substrates

Abstract

The element has a substrate and a surface layer on the substrate. The surface layer has at least one first layer made of an optically transparent and insulating first material and at least one second layer at least partially embedded in at least one first region. The at least one second region is made of an optically transparent and conductive second material.

Description

Technical Field

[0001] This technical field relates to wafer-to-wafer, die-to-die, and / or die-to-wafer hybrid bonding systems and methods for semiconductor and optoelectronic devices.

Background Art

[0002] Semiconductor elements, such as semiconductor wafers or integrated device dies, can be stacked on top of each other without an adhesive and directly bonded, thereby forming a bonded structure. Non-conductive (e.g., dielectric, semi-conductive (having semiconductor properties)) surfaces can be processed very smoothly to promote direct covalent bonding even at room temperature and without applying pressure beyond the contact relationship. In some hybrid bonded structures, the non-conductive field regions of the elements can be directly bonded to each other, and the corresponding conductive contact structures can also be directly bonded to each other.

[0003] For example, semiconductor elements can be mounted on a carrier, such as a package substrate, an interposer, a reconfigured wafer, or an element. A semiconductor element can be stacked on top of this semiconductor element (e.g., a first integrated device die can be stacked on top of a second integrated device die). Each of these semiconductor elements can have conductive pads for mechanically and electrically bonding the semiconductor elements to each other, and such conductive pads are mechanically and electrically bonded to each other.

Summary of the Invention

[0004] Some specific embodiments described herein provide an element having a substrate and a surface layer provided on the substrate. The surface layer has at least one first region comprising at least one first material which is optically transparent and insulating, and at least one second region which is at least partially embedded in the at least one first region. The at least one second region consists of a second material which is optically transparent and conductive.

[0005] Some specific embodiments described herein provide a method comprising the step of preparing a first element having an optically transparent first substrate and an optically transparent first surface layer including one or more insulating first regions and one or more conductive second regions. The method further comprises the step of preparing a second element having an optically transparent second substrate and an optically transparent second surface layer including one or more insulating third regions and one or more conductive fourth regions. The method further comprises the step of directly bonding the first surface layer and the second surface layer to each other without adhesive, the direct bonding step comprising the step of bringing the first regions and the second regions into contact with each other.

[0006] Some specific embodiments described herein provide an apparatus having a first substrate, a first layer on the first substrate, a second substrate, and a second layer on the second substrate. The first layer has at least one first region made of an optically transparent and insulating first material, and at least one second region at least partially embedded in the at least one first region. The at least one second region is made of an optically transparent and conductive second material. The second layer is directly bonded to the first layer, and the second layer has at least one third region made of an insulating third material, and at least one fourth region at least partially embedded in the at least one third region. The at least one fourth region is made of a conductive fourth material.

[0007] Some specific embodiments described herein provide an element having a substrate and a hybrid bonding surface layer on the substrate. The hybrid bonding surface layer has at least one first layer made of an optically transparent and electrically conductive first material, and at least two second layers provided covering the at least one first layer. The at least one second layer is made of an optically transparent and conductive metal or polysilicon material.

[0008] Some specific embodiments described herein provide an apparatus having a first substrate, a first plurality of layers on the first substrate, a second substrate, and a second plurality of layers on the second substrate. The first plurality of layers has at least one first layer made of an optically transparent and conductive first material, and at least one second layer laminated to at least one first layer. The at least one second layer is made of an optically transparent and conductive second material, the second material being a metal or polysilicon. The second plurality of layers has at least one third layer made of an optically transparent and conductive third material, and at least one fourth layer laminated to at least one third layer. The at least one fourth layer is made of an optically transparent and conductive fourth material, the fourth material being a metal or polysilicon, and the fourth material being direct-bonded to the second material.

[0009] Some specific embodiments described herein provide a structure having a first device assembly comprising a first backplane substrate including an optically transparent first layer region and a first device substrate. The first device substrate has a first optical device, an optically transparent second layer region in electrical contact with the first optical device, and an optically transparent third layer region in electrical contact with the first optical device. The third region is located on the opposite side of the first device substrate from the second layer region. The second layer region is directly bonded to the first layer region.

[0010] Next, specific examples of implementation will be described with reference to the following drawings, but these examples are provided as illustrations and do not limit the present invention. [Brief explanation of the drawing]

[0011] [Figure 1A] This is a schematic cross-sectional side view of two elements before bonding, according to some specific examples described herein. [Figure 1B] Figure 1A is a schematic cross-sectional side view of the two elements after bonding, according to some specific examples described herein. [Figure 2A] These are schematic cross-sectional views of two exemplary structures that are compatible with some specific concrete examples described herein. [Figure 2B] These are schematic cross-sectional views of two exemplary structures that are compatible with some specific concrete examples described herein. [Figure 3] This is a flowchart illustrating an exemplary method for forming a structure compatible with certain specific concrete examples described herein. [Figure 4A] This is a schematic cross-sectional view taken during the fabrication of the exemplary structure of Figure 2A using the exemplary method of Figure 3, according to some specific examples of embodiments described herein. [Figure 4B] This is a schematic cross-sectional view taken during fabrication using the exemplary method shown in Figure 3 to form the exemplary structure of Figure 2B, according to some specific examples described herein. [Figure 5A] This is a schematic cross-sectional view of an exemplary fabrication sequence for providing a first element, according to some specific embodiment examples described herein. [Figure 5B] This is a schematic cross-sectional view of an exemplary fabrication sequence for providing a first element, according to some specific embodiment examples described herein. [Figure 5C]This is a schematic cross-sectional view of an exemplary fabrication sequence for providing a first element, according to some specific embodiment examples described herein. [Figure 5D] This is a schematic cross-sectional view of an exemplary fabrication sequence for providing a first element, according to some specific embodiment examples described herein. [Figure 6] This is a schematic diagram of an exemplary structure having multiple planar regions, according to some specific examples described herein. [Modes for carrying out the invention]

[0012] The various embodiments disclosed herein relate to direct-bonded structures in which two or more elements can be directly bonded to each other without an intervening adhesive. Figures 1A and 1B are schematic cross-sectional side views of two elements 102 and 104 before and after a bonding process to form a direct hybrid bonded structure 100 without an intervening adhesive, respectively, according to some specific embodiments described herein. As shown in Figures 1A and 1B, the bonded structure 100 preferably consists of a first element 102 and a second element 104 that are directly bonded to each other at a bond interface 118 without an intervening adhesive. The first and second elements 102, 104 may include microelectronic elements (e.g., semiconductor elements, such as integrated device dies, wafers, passive devices, individual active devices, such as power switches, etc.) and / or optical elements or devices (e.g., photodiodes, light-emitting diodes (LEDs), quantum dot light-emitting diodes (QLEDs), lasers, VCSELs, transparency control pixels, liquid crystal pixels, adaptive optics components, waveguides) stacked or bonded together to form a bonded structure 100. For example, one or both of the first and second elements 102, 104 may consist of a thinned substrate or integrated device having a thickness in the range of about 10 μm to 100 μm, about 10 μm to 300 μm, about 30 μm to 300 μm, or about 50 μm to 300 μm. Preferably, the conductive feature portion 106a of the first element 102 (e.g., a contact pad, an exposed end of a via (e.g., a TSV), or a through-substrate electrode) is electrically connected to the corresponding conductive feature portion 106b of the second element 104. In some specific embodiment, the conductive feature portion 106a has an optically transparent conductive material (e.g., indium tin oxide (ITO), indium-doped zinc oxide (Iz), tin oxide (SnO2)) or an optically translucent conductive material (e.g., a metal or polysilicon layer less than 50 nanometers thick).

[0013] Figures 1A and 1B schematically show two elements 102 and 104, but any suitable number of elements can be stacked within the bonded structure 100 according to certain specific embodiments described herein. For example, a third element (not shown) can be stacked on the second element 104, and a fourth element (not shown) can be stacked on the third element. Additionally or alternatively, one or more additional elements (not shown) can be stacked adjacent to each other laterally along the first element 102. In certain specific embodiments, the additional elements stacked laterally may be smaller than the second element (for example, the additional elements stacked laterally may be half the size of the second element).

[0014] In some specific embodiment, elements 102 and 104 are directly bonded to each other without an intervening adhesive. The bonding layer is preferably provided on the front and / or back surfaces of the first and second elements 102 and 104. For example, as schematically shown in Figures 1A and 1B, the first bonding layer 108a of the first element 102 may have a non-conductive field region of the first element 102 comprising a non-conductive material or dielectric (e.g., a dielectric, e.g., silicon oxide, or an undoped semiconductor material, e.g., undoped silicon), and the bonding layer 108b of the second element 104 may have a non-conductive field region of the second element 104 comprising a non-conductive material or dielectric (e.g., a dielectric, e.g., silicon oxide, or an undoped semiconductor material, e.g., undoped silicon). The first and second bonding layers 108a, 108b are preferably provided on the front surfaces 114a, 114b of the semiconductor (e.g., silicon) portions of the device portions 110a, 110b, for example, the first and second elements 102, 104. Active devices (e.g., electrical devices, optical devices) and / or circuit components are preferably patterned within or on the device portions 110a, 110b and / or provided in a different manner, and the active devices and / or circuit components are preferably provided on or near the front surfaces 114a, 114b of the device portions 110a, 110b and / or on or near the back surfaces 116a, 116b opposite to the device portions 110a, 110b.

[0015] The first and second bonding layers 108a and 108b are preferably directly bonded to each other without adhesive (e.g., using dielectric-dielectric bonding techniques). For example, nonconductive bonds or dielectric-dielectric bonds are preferably formed without adhesive using direct bonding techniques disclosed in at least U.S. Patent No. 9,564,414, No. 9,391,143, and No. 10,434,749, which are incorporated herein by reference and whose entire contents are incorporated herein by reference for all purposes. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic despite containing carbon. In some specific concrete examples, the dielectric material does not include polymer materials, such as epoxy, resin, or molding material.

[0016] In certain specific embodiments, the device portions 110a and 110b may have significantly different coefficients of thermal expansion (CTE) that define a heterogeneous structure. The difference in CTE between the device portions 110a and 110b, and especially between the bulk semiconductors (e.g., typically the single-crystal portions) of the device portions 110a and 110b, may be greater than 5 ppm or greater than 10 ppm. For example, the CTE values ​​of certain materials compatible with certain embodiments described herein may be in the range of 2 ppm to 10 ppm, and the difference in CTE between the device portions 110a and 110b may be in the range of 1 ppm to 10 ppm, 2 ppm to 10 ppm, or 5 ppm to 40 ppm. In some specific concrete examples, one of the device parts 110a and 110b may be made of a photoelectron single crystal material including a perovskite material useful for optical piezoelectric or pyroelectric applications, while the other of the device parts 110a and 110b may be made of a more conventional substrate material. For example, one of the device parts 110a and 110b may be made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other of the device parts 110a and 110b may be made of silicon (Si), quartz, fused silica glass, sapphire, or glass. In some other specific embodiment, one of the device parts 110a, 110b is made of a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the device parts 110a, 110b is made of a non-group III-V semiconductor material, such as silicon (Si), or another material with approximately the same CTE, such as quartz, fused silica glass, sapphire, or glass.

[0017] In some specific embodiment, the direct hybrid bond may be formed without an intervening adhesive. For example, the bonding surfaces 112a,112b in the nonconductive field region of the bonding layers 108a,108b may be polished to a high degree of smoothness (e.g., using chemical mechanical polishing (CMP)). The roughness of the polished surfaces 112a,112b may be less than 30 Årms. For example, the roughness of the polished surfaces 112a,112b may be in the range of approximately 0.1 Årms to 15 Årms, 0.5 Årms to 10 Årms, or 1 Årms to 5 Årms. By cleaning the bonding surfaces 112a,112b and exposing them to plasma and / or etching agents, these surfaces 112a,112b can be activated. In some specific embodiments, it is preferable to end-group the surfaces 112a and 112b with chemical species after or during activation (e.g., during the plasma and / or etching process). While not bound by theory, in some specific embodiments, the activation process is often carried out to break the chemical bonds at the bonding surfaces 112a and 112b, and the end-grouping process can introduce additional chemical species to the bonding surfaces 112a and 112b that improve the bonding energy during direct bonding. In some specific embodiments, activation and end-grouping are carried out in the same step (using plasma to activate and end-group the surfaces 112a and 112b). In some specific embodiments, the bonding surfaces 112a and 112b can be end-grouped in a separate process from the activation process to provide additional chemical species that enable direct bonding. In some specific embodiments, the end-grouping chemical species may contain nitrogen. For example, one or both of surfaces 112a and 112b may be exposed to a nitrogen-containing plasma (see, for example, U.S. Patent No. 7,387,944). Furthermore, in some specific embodiments, one or both of the bonding surfaces 112a and 112b may be exposed to fluorine.For example, there may be a region of one or more fluorine peaks at or near the bond interface 118 between the first element 102 and the second element 104. Thus, in the directly bonded structure 100, the bonding interface 118 between two non-conductive materials (e.g., the first and second bonding layers 108a, 108b) can constitute a very smooth interface having a high nitrogen content and / or fluorine peaks at the bond interface 118 (see, e.g., U.S. Patent No. 9,564,414). Additional examples of activation and / or end-capping treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of these U.S. patents is incorporated by reference in its entirety, and the entire description thereof is made part of this specification for all purposes. The roughness of the polished surfaces 112a, 112b may be slightly rougher after the activation process (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or rougher than this as much as possible).

[0018] In certain specific embodiments, the conductive feature portion 106a of the first element 102 may also be directly bonded to the corresponding conductive feature portion 106b of the second element 104. For example, using hybrid bonding techniques, a conductor-conductor direct bond can be provided along a bonding interface 118 that includes a pre-treated, co-direct-bonded non-conductive-non-conductive (dielectric-dielectric) surface as described herein. In certain specific embodiments, conductor-conductor (e.g., conductive feature portion 106a-conductive feature portion 106b) direct bonds and dielectric-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed in at least U.S. Patent No. 9,716,033 and U.S. Patent No. 9,852,988, each of which is incorporated herein by reference and whose entirety is incorporated herein by reference for all purposes. In the direct hybrid bonding embodiment described herein, the conductive feature portion is provided within the non-conductive field region of the first and second bonding layers 108a, 108b, and both the conductive and non-conductive feature portions are pre-treated to enable direct bonding by, for example, the planarization described herein, which is performed by activation and / or termination treatments. Thus, the first and second bonding layers 108a, 108b, pre-treated to enable direct bonding, include both the conductive and non-conductive feature portions.

[0019] For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (e.g., inorganic dielectric surfaces) may be pre-treated as described herein and directly bonded to each other without an intervening adhesive. Conductive contact features (e.g., conductive features 106a, 106b) may be at least partially surrounded by non-conductive (e.g., dielectric) field regions within the first and second bonding layers 108a, 108b and directly bonded to each other without an intervening adhesive. In some particular embodiments, the conductive contact features 106a, 106b may consist of separate pads or traces at least partially embedded in the non-conductive material of the bonding layers 108a, 108b. In some particular embodiments, the conductive contact features consist of the exposed contact surfaces of substrate vias (e.g., through-silicon vias (TSVs)). In some particular embodiments, the conductive features 106a, 106b may each be recessed beneath the outer (e.g., upper) surface (e.g., non-conductive bonding surfaces 112a, 112b) of the non-conductive portions of the first and second bonding layers 108a, 108b. For example, the recess may be less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, or may be in the range from 2 nm to 20 nm, or from 4 nm to 10 nm. In some particular embodiments, prior to direct bonding, the recesses of the opposing elements 102, 104 may be sized such that the total gap between the opposing contact pads is less than 15 nm or less than 10 nm.

[0020] In some specific embodiments, the first and second bonding layers 108a and 108b are often directly bonded to each other at room temperature without a contactor, and then the bonded structure 100 is annealed. During annealing, the conductive feature portions 106a and 106b expand and come into contact with each other, thereby forming a metal-metal direct bond. In some specific embodiments, the materials of the conductive feature portions 106a and 106b mutually diffuse with each other during the annealing process. Beneficially, the Direct Bond Interconnect, i.e., DBI® technology, commercially available from Adeia, Inc. in San Jose, California, can be used to connect high-density conductive feature portions 106a and 106b to each other across the direct bond interface 118 (for example, with small or fine pitches for a regular array). In some specific examples, the pitch of the conductive feature portions 106a, 106b (e.g., conductive traces embedded in the bonding layers 108a, 108b of one of the bonded elements 102, 104) is preferably less than 100 microns or less than 10 microns, and may even be less than 2 microns. For some applications, the ratio of the pitch of the conductive feature portions 106a, 106b to one of the dimensions of the bonding pad (e.g., diameter) is less than 20, less than 10, less than 5, or less than 3, and in some cases preferably less than 2. For other applications, the width of the conductive traces embedded in the bonding layers 108a, 108b of one of the bonded elements 102, 104 is preferably in the range of 0.3 microns to 20 microns (e.g., 0.3 microns to 3 microns). In some specific embodiment, the conductive feature portions 106a, 106b and / or traces consist of copper or copper alloys, gold and gold alloys, nickel and nickel alloys, aluminum and aluminum alloys, however other metals and alloys may be suitable. For example, the conductive feature portions disclosed herein, e.g., conductive feature portions 106a, 106b, may consist of fine-grained metal (e.g., fine-grained copper).

[0021] Thus, in the direct bonding process, the first element 102 can be directly bonded to the second element 104 without an intervening adhesive. In some specific embodiments, the first element 102 consists of a standalone element, for example, a standalone integrated device die. In some other specific embodiments, the first element 102 may consist of a carrier or substrate (e.g., wafer) containing multiple (e.g., tens, hundreds, or more) device regions that form multiple integrated device dies when standalone. Similarly, in some specific embodiments, the second element 104 consists of a standalone element, for example, a standalone integrated device die. In some other specific embodiments, the second element 104 may consist of a carrier or substrate (e.g., wafer). Therefore, some specific embodiments disclosed herein can be used in wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W), or wafer-to-flat panel (W2FP) bonding processes. In a wafer-to-wafer (W2W) process, it is preferable to directly bond two or more wafers to each other (e.g., direct hybrid bonding) and then isolate them using an appropriate isolation process. After isolation, the side edges of the isolated structures (e.g., the side edges of two bonded elements 102 and 104) are preferably located substantially on the same plane, and these side edges preferably include markers representing a common isolation process of the bonded structures (e.g., saw marks if a saw isolation process is used).

[0022] As described herein, the first element 102 and the second element 104 can be directly bonded to each other without adhesive, which differs from the vapor deposition process and consequently results in a structurally different interface compared to vapor deposition. In some specific embodiments, the width of the first element 102 in the bonded structure is approximately the same as the width of the second element 104. In some other specific embodiments, the width of the first element 102 in the bonded structure 100 may differ from the width of the second element 104. Similarly, the width or area of ​​the larger of the first and second elements 102,104 in the bonded structure is preferably at least 10% larger than the width or area of ​​the smaller of the first and second elements 102,104. Thus, the first and second elements 102,104 may consist of non-vapor-deposited elements. Furthermore, unlike vapor-deposited layers, the direct-bonded structure 100 may include defect regions along the bond interface 118 where nanoscale voids (nanovoids) are present. Nanovoids may be formed as a result of activation (e.g., exposure to plasma) of the bonding surfaces 112a,112b. As described herein, the bond interface 118 may contain concentrates of material resulting from the activation and / or final chemical treatment process. For example, in some specific embodiments utilizing nitrogen plasma for activation, a nitrogen peak may occur at the bond interface 118. The nitrogen peak is detectable using a secondary ion mass spectrometer (SIMS). In some specific embodiments, for example, nitrogen-terminated treatment (e.g., exposure of the bonding layer to a nitrogen-containing plasma) can be used to replace the OH groups on the hydrolysis (OH-terminated) surface with NH2, NO, or NO2 molecules, thereby creating a nitrogen-terminated surface. In some specific embodiments utilizing oxygen plasma for activation, an oxygen peak may occur at the bond interface 118. In some specific embodiments, the bond interface 118 may be made of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.As described herein, the direct bond preferably consists of covalent bonds, which are stronger than van der Waals bonds. The bonding layers 108a and 108b may further have polished surfaces that have been planarized to a high degree of smoothness.

[0023] In some specific embodiments, the metal-metal bond between conductive feature portions 106a and 106b is preferably bonded such that metal crystals grow inward across the bond interface 118. In some specific embodiments, the metal is or contains copper, and the copper preferably has crystal grains oriented along the <111> crystal plane to enhance copper diffusion across the bond interface 118. In some specific embodiments, the conductive feature portions 106a and 106b preferably contain a nanotwinned copper crystal structure, which can aid in the coalescence of the conductive feature portions during annealing. The bond interface 118 preferably extends substantially completely to at least a portion of the bonded conductive feature portions 106a and 106b, so that there is substantially no gap between the nonconductive bonding layers 108a and 108b at or near the bonded conductive feature portions 106a and 106b. In some specific embodiments, the barrier layer may be provided beneath and / or surrounding the conductive features 106a, 106b (which may, for example, contain copper). However, in some other specific embodiments, the barrier layer may not be provided beneath the conductive features 106a, 106b, as described, for example, in U.S. Patent No. 11,195,748, which is incorporated herein by reference and whose entirety is part of this specification for all purposes.

[0024] Beneficially, the hybrid bonding techniques described herein enable the realization of extremely fine pitches between adjacent conductive feature portions 106a, 106b and / or small pad sizes. For example, in some specific embodiments, the pitch p between adjacent conductive feature portions 106a (or adjacent conductive feature portions 106b) (e.g., the distance between edges or centers, as shown in Figure 1A) may be in the range of 0.5 to 10 microns, 0.75 to 25 microns, 1 to 25 microns, 1 to 10 microns, or 1 to 5 microns. Furthermore, the larger lateral dimension (e.g., pad diameter) may also be small, for example, in the range of 0.25 to 30 microns, 0.25 to 5 microns, or 0.5 to 5 microns.

[0025] Some specific embodiments disclosed herein relate to optoelectronic devices that include direct bonded contacts made of optically transparent or optically translucent conductive metals (collectively referred to herein as transparent conductors or TCs) instead of metal direct bonded contacts. Examples of optoelectronic devices include optical elements or devices (e.g., photodiodes, light-emitting diodes (LEDs), quantum dot light-emitting diodes (QLEDs), lasers, VCSELs, transparency-controlled pixels, liquid crystal pixels, adaptive optics components, solar cells, waveguides, spatial light modulators, diode lasers, and electrochromic devices) that are stacked or bonded together to form a bonded structure. The TCs on separate substrates are preferably planarized, and the planarized surfaces of the substrates are preferably placed in contact with each other to form a bonded structure, as described herein.

[0026] In some specific embodiment, the optoelectronic devices described in this specification are configured for use in a variety of technical contexts, such optoelectronic devices are area-limited (e.g., displays for visual reality (VR) or augmented reality (AR) applications, multi-junction solar cells) or other designs that have electro-optical elements in a stack of other optical elements, utilizing TC to provide electrical connections between electrical elements without significantly blocking light.

[0027] As used herein, the expression "optically transparent" includes, but is not limited to, optically opaque, optically translucent, and / or having a light transmittance of at least 50% (e.g., at least 60%, at least 75%, at least 88%, or 95% or more) in a given range of optical wavelengths. For example, a given range of optically transparent components (e.g., elements, substrates, layers, devices, feature parts) may be visible wavelengths (e.g., 300 nanometers to 750 nanometers, 400 nanometers to 700 nanometers), ultraviolet wavelengths (e.g., 100 nanometers, 400 nanometers), infrared wavelengths (e.g., 800 nanometers to 1 millimeter), and / or short-wave infrared (SWIR) wavelengths (e.g., 1400 nanometers to 3000 nanometers).

[0028] Figures 2A and 2B schematically show two exemplary structures 200 that are compatible with certain specific embodiments described herein. The structure 200 has at least one first element 210 (e.g., first element 102) including an optically transparent first substrate 212 (e.g., device portion 110a) and an optically transparent first surface layer 214, and at least a second element 220 (e.g., second element 104) including an optically transparent second substrate 222 (e.g., device portion 110b) and an optically transparent second surface layer 224. The first surface layer 214 and the second surface layer 224 are directly bonded to each other without adhesive.

[0029] The first substrate 212 may have at least one first device 216, and the second substrate 222 may have at least one second device 226. For example, as schematically shown in Figure 2A, the first substrate 212 may have a plurality of first devices 216 (e.g., electrical conduits), and the second substrate 222 may have a plurality of second devices 226 (e.g., optoelectronic devices). Figure 2A shows a state in which the first devices 216 of the first substrate 212 have optically transparent electrical conduits, but in certain other embodiment examples, the first devices 216 may have non-optically opaque electrical conduits (e.g., non-optically transparent electrical conduits that do not block the entire optical path through the first device 216). In another embodiment, as schematically shown in Figure 2B, the first substrate 212 has a single first device 216 (e.g., an optoelectronic device, an electro-optical element, a solar cell), and the second substrate 222 has a single second device 226 (e.g., an optoelectronic device, an electrochemical element, a control device).

[0030] In some specific embodiments, the first element 210 has at least one electro-optical (EO) contact 218 (e.g., a broad lateral area contact on the back surface 116a of the corresponding device portion 110a) in electrical and / or optical contact with at least one first device 216, and the second element 220 has at least one electro-optical (EO) contact 228 (e.g., on the back surface 116b of the corresponding device portion 110b) in electrical and / or optical contact with at least one second element 226. The EO contacts 218,228 are preferably configured to send and receive electrical and / or optical signals to and from the first and / or second devices 216,226. Exemplary materials for the EO contacts 218,228 include, but are not limited to, copper or copper alloys, although other metals and alloys, including transparent conductors disclosed herein, may be suitable. The EO contacts 218,228 preferably have an additional conductive layer between the copper and the corresponding first and / or second substrates 212,222.

[0031] In some specific embodiment, the first surface layer 214 has one or more insulating regions 240 and one or more conductive regions 242, and the second surface layer 224 has one or more insulating regions 250 and one or more conductive regions 252. For example, as schematically shown in Figure 2A, the first surface layer 214 may have at least one first insulating region 240 (e.g., bonding layer 108a) and at least one second conductive region 242 (e.g., conductive feature portion 106a), and the second surface layer 224 may have at least one third insulating region 250 (e.g., bonding layer 108b) and at least one fourth conductive region 252 (e.g., conductive feature portion 106b). At least one first region 240 is directly bonded to at least one third region 250, and at least one second region 242 is directly bonded to at least one fourth region 252. At least one second region 242 and at least one fourth region 252 provide a conductive and optically transparent connection between at least one first element 210 and at least one second element 220.

[0032] The first insulating region 240 and the third insulating region 250 are preferably made of an optically transparent dielectric (e.g., an inorganic dielectric), and examples of such dielectrics include semiconductor oxides, semiconductor nitrides, silicon oxide (SiO2), silicon nitride (SiN xExamples include, but are not limited to, Si3N4. At least one conductive second region 242 and at least one conductive fourth region 252 are preferably made of an optically transparent and conductive material, examples of such materials include, but are not limited to, doped metal oxides, undoped metal oxides, aluminum zinc oxide (AZO), indium tin oxide (ITO; In2O3), zinc oxide (ZnO), zinc tin oxide (ZnSnO3; Zn2SnO4), indium-doped zinc oxide (IZO), indium oxide, cadmium tin oxide (Cd2Sn2O4), tin oxide (SnO2), titanium dioxide (TiO2), niobium-doped titanium dioxide (Nb-TiO2), titanium nitride (TiN), and transition metal nitrides containing group IIIB, group IVB, or group VB transition metals. The first and third regions 210 and 250 may consist of the same type of optically transparent dielectric, or they may consist of different types of optically transparent dielectrics (for example, materials having different elemental components and / or different stoichiometric compositions, and direct bonding consists of direct hybrid bonding).

[0033] In some specific embodiment, the first surface layer 214 consists of at least one conductive layer, and the second surface layer 224 consists of at least one conductive layer. The at least one conductive layer of the first and / or second surface layers 214, 224 is preferably made of an optically transparent and conductive material, and examples of such materials include, but are not limited to, doped metal oxides, undoped metal oxides, aluminum zinc oxide (AZO), indium tin oxide (ITO; In2O3), zinc oxide (ZnO), zinc tin oxide (ZnSnO3; Zn2SnO4), indium zinc oxide (IZO), indium oxide, cadmium tin oxide (Cd2Sn2O4), tin oxide (SnO2), titanium dioxide (TiO2), niobium-doped titanium dioxide (Nb-TiO2), titanium nitride (TiN), and transition metal nitrides containing group IIB, group IVB, or group VB transition metals. At least one conductive layer in the first and second regions 214,224 may be made of a dielectric material of the same type of optically transparent and conductive material, or it may be made of a different type of optically transparent and conductive material (for example, materials having different elemental components and / or different stoichiometric compositions, dissimilar alloys, and direct bonding, which consists of direct hybrid bonding).

[0034] In some specific embodiments, the first surface layer 214 consists of a single surface layer and / or the second surface layer 224 consists of a single surface layer, and the two single surface layers are directly bonded to each other. In some other specific embodiments, at least one of the first surface layer 214 and the second surface layer 224 consists of multiple surface layers. For example, as schematically shown in Figure 2B, the first surface layer 214 may have a conductive first layer 260 and a conductive second layer 262 covering the first layer 260, and the second surface layer 224 may have a conductive third layer 270 and a conductive fourth layer 272 covering the third layer 270. The first and third layers 260 and 270 are preferably made of an optically transparent and conductive material. Examples of such materials include doped metal oxides, undoped metal oxides, aluminum zinc oxide (AZO), indium tin oxide (ITO; In2O3), zinc oxide (ZnO), zinc tin oxide (ZnSnO3; Zn2SnO4), indium zinc oxide (IZO), indium oxide, cadmium tin oxide (Cd2Sn2O4), tin oxide (SnO2), titanium dioxide (TiO2), and niobium-doped titanium dioxide (Nb-TiO2). Examples include, but are not limited to, titanium nitride (TiN), tin nitride (Sn3N4), and other metal nitrides (e.g., A3N2, in this case A=Mg, Zn, Sn). The first and third regions 260,270 may consist of the same type of optically transparent and conductive material, or they may consist of different types of optically transparent and conductive materials (e.g., materials having different elemental components and / or different stoichiometric compositions, dissimilar alloys, and direct bonding, or direct hybrid bonding).

[0035] The second and fourth layers 262,272 may consist of a metal or polysilicon layer, which is thin enough (e.g., 50 nanometers or less) to be both optically transparent (e.g., translucent) and conductive. Examples of metals for the metal layer that are compatible with certain specific embodiments described herein include, but are not limited to, metallic elements (e.g., gold, silver, aluminum, copper, iridium, iron, nickel, osmium, palladium, platinum, rhenium, rhodium, ruthenium, zinc) and conductive alloys containing one or more of these metallic elements. Figure 2B schematically shows each of the first and second surface layers 214,224, which consist of two layers, although in certain other embodiments, only one of the first and second surface layers 214,224 consists of two layers, while the other surface layer consists of a single layer. For example, the first surface layer 214 may consist of the first and second layers 260 and 262, and the second surface layer 224 may consist only of the third layer 270. The second and fourth layers 262 and 272 may consist of the same type of metal or polysilicon material, or of different types of metal or polysilicon material (for example, materials having different elemental components and / or different stoichiometric compositions, dissimilar alloys, and direct bonding, or direct hybrid bonding). In some specific embodiment where the roughness of the outer surface of the first layer 260 and / or the third layer 270 is too rough (e.g., not smooth enough) for direct bonding to the first and third layers 260,270, or where direct bonding of the materials of the first and third layers 260,270 to each other is not easy, the second layer 262 and / or the fourth layer 272 can facilitate direct bonding between the first surface layer 214 and the second surface layer 224.

[0036] Figure 3 is a flowchart of an exemplary method 300 for forming a structure 200 (e.g., a structure including a dielectric-dielectric coupling) that is compatible with certain specific embodiments described herein. Figures 4A and 4B schematically show an exemplary method 300 for forming the exemplary structure 200 of Figures 2A and 2B, respectively, according to certain specific embodiments described herein. While the exemplary method 300 is described with reference to the various exemplary structures in Figures 2A, 2B, 4A, and 4B, other structures are also compatible with the exemplary method 300 according to certain specific embodiments described herein.

[0037] In operation block 310, method 300 includes the step of providing a first element 210 having an optically transparent first substrate 212 and an optically transparent first surface layer 214. In operation block 320, method 300 further includes the step of providing a second element 220 having an optically transparent second substrate 222 and an optically transparent second surface layer 224. In operation block 330, method 300 further includes the step of directly bonding the first surface layer 214 and the second surface layer 224 to each other without adhesive. The direct bonding step includes bringing the first surface layer 214 and the second surface layer 224 into contact with each other.

[0038] As schematically shown in Figure 4A, the first surface layer 214 preferably has an insulating first region 240 and a conductive second region 242, and the second surface layer 224 preferably has an insulating third region 250 and a conductive fourth region 252. The second region 242 is at least partially embedded together with the first region 240 (e.g., coplanar), and the fourth region 252 is at least partially embedded together with the third region 250 (e.g., coplanar). The top surface of the second region 242 is preferably recessed relative to the top surface of the first region 240 (e.g., by less than 10 nanometers) and / or the top surface of the fourth region 252 is preferably recessed relative to the top surface of the third region 250 (e.g., by less than 10 nanometers). It is preferable to bring the insulating regions 240 and 250 into contact with each other (for example, after activation) to form a covalent bond at room temperature, and then anneal the structure 200, thereby causing the second region 242 to expand or contract the fourth region 252 (or vice versa), closing the gap corresponding to the recess. Direct hybrid bonding of two surface layers 214,224 to each other without adhesive (for example, using Direct Bond Interconnect, i.e., DBI® technology, commercially available from Adeia, Inc., San Jose, California) may include the steps of bringing a first region 240 and a third region 250 into contact with each other, and bringing a second region 242 and a fourth region 252 into contact with each other (for example, at room temperature) so that the first region 240 and the third region 250 are directly bonded to each other, as well as the second region 242 and the fourth region 252 are directly bonded to each other (for example, forming the structure 200 schematically shown in Figure 2A). The alignment between the second region 242 and the fourth region 252, which are directly bonded to each other, is preferably sufficient to provide substantial electrical contact between the second region 242 and the fourth region 252, if desired (for example, regions 242 and 252 do not need to be perfectly aligned with each other).

[0039] As schematically shown in Figure 4B, the first surface layer 214 may include a conductive first layer 260 and a conductive second layer 262 covering the first layer 260, and the second surface layer 224 may include a conductive third layer 270 and a conductive fourth layer 272 covering the third layer 270. To directly hybrid bond the two surface layers 214,224 to each other without adhesive (using Direct Bond Interconnect, i.e., DBI® technology, commercially available from Adeia, Inc. in San Jose, California), the second layer 262 and the fourth layer 272 may be brought into contact with each other (e.g., at room temperature) so that the second layer 262 and the fourth layer 272 are directly bonded to each other (e.g., forming the structure 200 schematically shown in Figure 2A). In some specific embodiments, the first surface layer 214 includes the first layer 260 and the second layer 262, and the second surface layer 224 includes the third layer 270 and the fourth layer 272; on the other hand, in some other specific embodiments, the first surface layer 214 includes the first layer 260 and the second layer 262, and the second surface layer 224 includes only the third layer 270 (for example, only the first surface layer 214 consists of a metal or polysilicon layer).

[0040] Before bringing the two surfaces 214, 224 into contact with each other, the exemplary method 300 may include a step of cleaning (e.g., rinsing and rotating dry) at least one of the two surface layers 214, 224 (e.g., both of the two surface layers 214, 224) and / or activating (e.g., exposing to plasma and / or a chemical etching agent) at least one of the two surface layers 214, 224 (e.g., both of the two surface layers 214, 224) after cleaning. After the two surface layers 214, 224 have been brought into contact with each other (for example, after the two surface layers 214, 224 have been directly bonded to each other), the exemplary method 300 may include the step of annealing the two surface layers 214, 224 (for example, by heating them to a predetermined temperature above room temperature for a predetermined period of time) (for example, by expanding the second region 242 and / or the fourth region 252 so that the second region 242 and the fourth region 252 come into contact with each other).

[0041] In some specific embodiments, the step of providing a first element 210 and / or a second element 220 comprises the step of fabricating the first element 210 and / or the second element 220. Figures 5A to 5D schematically show an exemplary fabrication sequence for providing a first element 210 according to some specific embodiments described herein. The exemplary fabrication sequence in Figures 5A to 5D is for fabricating the first element 210, starting with a first substrate 212, but the same exemplary fabrication sequence may be used to fabricate the second element 220, starting with a second substrate 222. After the first and second elements 210, 220 have been formed (for example, using the fabrication sequences in Figures 5A to 5D), the method 300 may further include the step of directly bonding the first and second surface layers 214, 224 of the first and second elements 210, 220 to each other.

[0042] The illustrative fabrication sequences in Figures 5A to 5C are preferably used to fabricate the first and second regions 240, 242 of the first surface layer 214 and / or to form the third and fourth regions 250, 252 of the second surface layer 224. In addition, the illustrative fabrication sequence in Figure 5C begins with the first element 210 obtained as a result of the fabrication sequences in Figures 5A to 5B (for example, the first element 210 has a first surface layer 214 comprising an insulating first region 240 and a conductive second region 242, see Figures 2A and 4A for this), but the same illustrative fabrication sequences are preferably used to fabricate a first element 210 having a first surface layer 214 comprising a conductive first region 260 and a conductive second layer 262 covering the first layer 260 (see Figures 2B and 4B for this).

[0043] The example fabrication sequence in Figure 5A includes the step of depositing a conductive and optically transparent first material 410 onto a first substrate 212 (for example, by sputtering or activated chemical vapor deposition to a thickness of the order of microns). After deposition, the first material 410 is preferably planarized (for example, by chemical mechanical planarization (CMP)). The example fabrication sequence in Figure 5A further includes the step of patterning the first material 410 to form a first structure 412 on the first substrate 212 (for example, using photolithography techniques) (for example, patterning ITO using dilute HCl, using HCl vapor in a plasma dry etching process, or using Cl2, BCl3, CH4, or H2 as dry etching agents; these are means for patterning ITO). The fabrication sequence illustrated in Figure 5A involves the steps of depositing an insulating second region 414 between and covering the first structure 412 onto the first substrate 212 (for example, to a thickness of the order of microns), and removing the second material 414 from the first structure 412 (for example, by performing CMP on the second material 414, thereby exposing the underlying first structure 412), so that the second material between the first structures 412 forms a first region 240 and the first structures 412 form a second region 242. This step can also be used to perform planarization for bonding and to create a recess of the second region 242 into the first region 240.

[0044] The example fabrication sequence in Figure 5B includes the steps of depositing an insulating first material 420 onto a first substrate 212 (for example, to a thickness of the order of microns) and patterning the first material 420 (for example, using photolithography techniques) to form a first structure 422 on the first substrate 212. The fabrication sequence illustrated in Figure 5B further includes the steps of depositing a conductive and optically transparent first material 410 on a first substrate 212 between and covering first structures 422 (for example, by sputtering or activated chemical vapor deposition to a thickness of the order of microns), and removing the second material 424 from the first structures 422 (for example, by CMP of the second material 424 to expose the underlying first structures 422, for example, a CMP rate of 50-60 nm / min is preferable), such that the second material 424 between the first structures 422 forms a second region 242 and the first structures 422 form a first region 240. In some specific embodiment, the deposited second material 424 has the surface topography of the underlying first structure 422, while in some other specific embodiment, the deposited second material 424 does not exhibit the surface topography of the underlying first structure 422. As shown in Figures 5A and 5B, the deposition of the conductive and optically transparent material may occur either before or after etching of the dielectric layer (e.g., metal pad etching).

[0045] In some specific embodiments, the outer surface of the second region 242 is recessed relative to the outer surface of the first region 240, while in some other specific embodiments, the outer surface of the first region 240 is recessed relative to the outer surface of the second region 242. The thicknesses of the first and second regions 240,242 can be adjusted to provide a recess between the surfaces of the first region 240 and the second region 242 to take into account the different coefficients of thermal expansion (CTE) of the first material 410 and the second material 414 (e.g., different amounts of thermal expansion in the direction perpendicular to the first and second surface layers 214,224 during annealing of the first and second surface layers 214,224) (e.g., in the range of 2 nanometers to 8 nanometers). For example, the CTE of ITO is 5.8 × 10⁻⁶. -6 / K~9×10 -6 The value is / K, while the CTE of silicon oxide is approximately 0.5 × 10⁻⁶. -6 It is / K. For comparison, the CTE of Cu is approximately 16.7 × 10⁻⁶. -6 The coefficient of heat transfer (CTE) is / K. Compared to the case where Cu is used as the conductive material, the thickness of ITO can be selected to be thicker, and the size of the recess between ITO and the adjacent silicon oxide can be controlled more precisely to account for a smaller CTE difference for ITO / SiO2 compared to Cu / SiO2.

[0046] For example, the outer surface of the second region 242 may be recessed relative to the outer surface of the first region 240, and / or the outer surface of the fourth region 252 may be recessed relative to the outer surface of the third region 250, and by annealing during the direct bonding process, the conductive material of the second region 242 and / or the fourth region 252 can be expanded, so that the second region 242 and the fourth region 252 come into contact with each other and form a desired bond between them. In another embodiment, the outer surface of the first region 240 is preferably recessed relative to the outer surface of the second region 242, and / or the outer surface of the third region 250 is preferably recessed relative to the outer surface of the fourth region 252, and by annealing during the direct bonding process, the insulating material of the first region 240 and / or the third region 250 can be expanded, so that the first region 240 and the third region 250 come into contact with each other and form a desired bond between them.

[0047] The example fabrication sequence in Figure 5C includes the steps of depositing a first photoresist material 430 onto the first and second regions 240, 242 and removing the first photoresist material 430 from the second region 242. The example fabrication sequence in Figure 5C further includes the step of depositing an optically transparent first layer 432 onto the second region 242. For example, a translucent metal layer (e.g., having a thickness of 50 nanometers or less) can be deposited using physical vapor deposition (PVD) or atomic layer deposition (ALD). In another embodiment, an optically transparent polysilicon layer may be deposited (e.g., by physical vapor deposition of silicon). The surface of the deposited layer can maintain the indentation of the second region 242 relative to the surface of the first region 240 and / or maintain the planarity of the second region 242. The example fabrication sequence in Figure 5C further includes the step of removing (e.g., stripping) the first photoresist material 430 from the first region 240, leaving the first layer 432 on the second region 242, so that the second region 240 forms the first layer 260 and the first layer 432 forms the second layer 262 on the first layer 260 (e.g., the portion of the second layer 262 of the second region 242).

[0048] The illustrative fabrication sequence in Figure 5D includes a step beginning with a first substrate 212, which preferably includes a step of planarizing the first substrate 212 so that the conductive region of the outer surface of the first substrate 212 is exposed. The illustrative fabrication sequence in Figure 5D further includes a step of depositing a conductive and optically transparent first material 410 onto the first substrate 212 (e.g., by sputtering or activated chemical vapor deposition to a thickness of the order of microns). The deposition allows for the formation of a stable film while minimizing the formation of nanovoids at the interface with the first substrate 212. After deposition, the first material 410 may be planarized (e.g., by CMP to reduce the roughness of the outer surface of the first material 410) to form a first layer 260. The illustrative fabrication sequence in Figure 5D further includes a step of depositing a thin second layer 262 of metal or polysilicon on the first layer 260 (e.g., having a thickness of less than 50 nanometers). The example fabrication sequence in Figure 5D begins with a first substrate 212 to fabricate a first surface layer 214 comprising a conductive first layer 260 and a conductive second layer 262 covering the first layer 260, but the same example fabrication sequence can be used to fabricate a second surface layer 224 comprising a conductive third layer 270 and a conductive fourth layer 272 covering the third layer 270.

[0049] Figure 6 schematically illustrates an exemplary structure 200 (e.g., a VR / AR display) having multiple flat regions, according to some specific embodiment examples described herein. The exemplary structure 200 in Figure 6 has an LED assembly 500 including an LED backplane 510 (e.g., including an LED array ground plane 516) and an LED plane 520 (e.g., including multiple LEDs 526). The LED backplane 510 and the LED plane 520 are directly bonded to each other at a direct bonding (DB) interface 580 (shown as a dashed line in Figure 6). The LED array ground plane 516 is in electrical contact with the LEDs 526. The exemplary structure 200 in Figure 6 further has a transparent pixel (TP) assembly 600 including a TP backplane 610 (e.g., including a TP array ground plane 616) and a TP plane 620 (e.g., the TP plane 620 has multiple transparent pixels 626 configured to control the transmission of light from the LED assembly 500 through the TP assembly 600). The TP backplane 610 and TP plane 620 are directly bonded to each other at the DB interface 680 (shown as a dashed line in Figure 6). The TP array ground plane 616 is in electrical contact with the transparent pixels 626. The exemplary structure 200 in Figure 6 further has an interposer assembly 700 which is directly bonded to the LED assembly 500 at the DB interface 780a (shown as a dashed line in Figure 6) and to the TP assembly 600 at the DB interface 780b (shown as a dashed line in Figure 6). In some specific embodiment, all of the components schematically shown in Figure 6 are optically transparent or optically translucent. The interposer assembly 700 interfaces with conductive conduits to control the LED 526 of the LED assembly 500 and / or the transparent pixels 626 of the TP assembly 600, and the interposer assembly 700 can also make electrical connections to optically opaque components located outside the figure shown in Figure 6.

[0050] As schematically shown in Figure 6, the LED backplane 510 has a single DB interface 580 with the LED plane 520, and the TP backplane 610 has a single DB interface 680 with the TP plane 620. In addition, the LED plane 520 has two DB interfaces, namely DB interface 580 with the LED backplane 510 and DB interface 780a with the interposer assembly 700, and the TP plane has two DB interfaces, namely DB interface 680 with the TP backplane 610 and DB interface 780b with the interposer assembly 700.

[0051] Each of the LED assemblies 500, TP assemblies 600, and interposer assemblies 700 may include corresponding optically transparent elements, substrates, layers, and devices as described herein with reference to Figures 1A, 1B, 2A, 2B, 4A, and 4B. For example, an LED backplane 510 (e.g., a first element 210) has an LED backplane substrate 512 (e.g., a first substrate 212) equipped with an LED backplane device (e.g., an electrical conduit, a first device 216, an LED array ground plane 516) and an LED backplane layer 514 (e.g., a first surface layer 214) on the LED backplate substrate 512. The LED backplane layer 514 has an optically transparent and conductive region 518 (e.g., a second region 242 equipped with an optically transparent conductive material) and an insulating region 519 (e.g., a first region 240 equipped with an optically transparent insulating material). The LED plane 520 has an LED plane substrate 522 (e.g., a second substrate 222) equipped with LED plane devices (e.g., LED 526, a second device 226), and a first LED plane surface layer 524 (e.g., a second surface layer 214) which includes an optically transparent and conductive region (e.g., a fourth region 252 with an optically transparent conductive material) and an insulating region (e.g., a third region 250 with an optically transparent insulating material). In addition, the LED plane 520 further has a second LED plane surface layer 528 located on the opposite side of the LED plane substrate 522 as seen from the first LED plane surface layer 524. The second LED plane surface layer 528 further has an optically transparent and conductive region and an optically transparent and insulating region.

[0052] In some specific embodiment, the bonded structure (see, for example, Figures 2A, 2B, 4A, and 4B) is preferably covered with a protective layer, preferably mounted on a dicing sheet, and preferably isolated to form an isolated die on a dicing frame (e.g., by layer dicing, laser dicing, reactive ion etching dicing, wet etching, or a combination thereof). The protective layer is preferably removed from the isolated die and the exposed dicing sheet (e.g., by peeling it off) (e.g., using a solvent, reactive ion etching, etc.). The isolated die is preferably cleaned (e.g., by rinsing and drying using high-speed rotation drying or other processes). The cleaned die is preferably configured to allow the following process: for example, the cleaned die is preferably further bonded to a pre-treated surface of another substrate (e.g., having power pads, ground pads, and / or other passive elements configured to supply power to the bonded die).

[0053] While commonly used terminology is used to describe the systems and methods of certain specific embodiments for the sake of ease of understanding, these terms are used herein in accordance with fair interpretation. Although various aspects of this disclosure are described with respect to illustrative examples and embodiments, the disclosed examples and embodiments should not be construed as limiting the invention. Conditional words in the original specification, such as in particular "can" (sometimes translated as "it is preferable"), "could" ("may be possible"), "might" ("might be possible"), or "may" ("may be possible"), unless otherwise specified or understood differently in the context in which they are used, generally mean that a particular embodiment includes certain features, elements, and / or steps, while other embodiments do not include certain features, elements, and / or steps. Thus, such conditional terms generally mean that features, elements, and / or steps are required in any way in one or more embodiments, or that one or more embodiments necessarily include logic for determining, with or without user input or instruction, whether these features, elements, and / or steps are included in or implemented in any suitable embodiment. In particular, “comprises” (sometimes written as “having”) and “comprising” in the original specification should be indicated as referring to an element, component, or step in a non-exclusive manner, indicating that the referenced element, component, or step may exist or be used, or may be combined with other elements, components, or steps not explicitly referenced.

[0054] It should be recognized that the embodiments disclosed herein are not mutually exclusive and can be combined with each other in various configurations. In addition, although the disclosed methods and apparatus are described in the technical context of direct bonding processes, the various embodiments described herein can be introduced into various other suitable devices, methods, and technical contexts.

[0055] The terms relating to degree used herein, such as “approximately,” “about,” “nearly,” and “substantially,” describe values, quantities, or characteristics that are close to the stated values, quantities, or characteristics that still perform the desired function or achieve the given results. For example, “approximately,” “about,” “nearly,” and “substantially” may refer to quantities within ±10%, ±5%, ±2%, ±1%, or ±0.1% of the stated quantity. As another example, the expressions “nearly parallel” and “substantially parallel” refer to values, quantities, or characteristics that deviate by ±10°, ±5°, ±2°, ±1°, or ±0.1° from exactly parallel, and the expressions “nearly perpendicular” and “effectively perpendicular” refer to values, quantities, or characteristics that deviate by ±10°, ±5°, ±2°, ±1°, or ±0.1° from exactly perpendicular. The scope disclosed herein includes any overlap, subrange, and combinations thereof. For example, terms such as "up to a maximum of," "at least," "greater than," "less than," and "between" include the number stated. In the original specification, "a," "an," and "said" include plural unless otherwise explicitly specified. Also, in the descriptions herein, "inside" includes "into" and "on" unless otherwise explicitly specified.

[0056] Although methods and systems have been described herein using elements represented by ordinal numbers as adjectives (e.g., 1st, 2nd, etc.), the ordinal numbers as adjectives are used merely as labels to distinguish one element from another (e.g., one substrate from another substrate or one surface layer from another surface layer), and are not used to indicate the order of these elements or the order in which they are used.

[0057] The disclosures and claims described herein are not limited in scope by any specific examples disclosed herein, for these examples are intended to illustrate certain aspects of the disclosure and not to limit the invention. Any equivalent examples are included within the scope of the disclosure. Indeed, various modifications of the disclosure in form and detail will be apparent to those skilled in the art from the above description, in addition to the embodiments illustrated and described herein. Such modifications also fall within the scope of the invention as described in the claims. The breadth and scope of the disclosure should not be limited by any of the examples disclosed herein and should be determined solely by the claims and their equivalents.

Claims

1. It is an element, circuit board and The substrate has a surface layer, and the surface layer is A first region made of an optically transparent and insulating first material, An element comprising at least one second region at least partially embedded in the at least one first region, wherein the at least one second region is made of an optically transparent and conductive second material.

2. The element according to claim 1, wherein the surface layer is a direct hybrid bonding layer.

3. The element according to claim 1, wherein the first material is a dielectric.

4. The element according to claim 3, wherein the dielectric is selected from the group consisting of semiconductor oxides, semiconductor nitrides, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.

5. The element according to claim 1, wherein the second material is selected from the group consisting of doped metal oxides, undoped metal oxides, aluminum zinc oxide, indium tin oxide, zinc oxide, zinc tin oxide, indium-doped zinc oxide, indium oxide, cadmium tin oxide, tin oxide, titanium dioxide, niobium-doped titanium dioxide, titanium nitride, and transition metal nitrides containing Group IIIB, Group IVB, or Group VB transition metals.

6. It is a method, The steps include: preparing a first element having an optically transparent first substrate and an optically transparent first surface layer including one or more insulating first regions and one or more conductive second regions; The steps include preparing a second element having an optically transparent second substrate and an optically transparent second surface layer including one or more insulating third regions and one or more conductive fourth regions, A method comprising the step of directly bonding a first surface layer and a second surface layer to each other without adhesive, wherein the direct bonding step includes bringing the first region and the second region into contact with each other.

7. The method according to claim 6, wherein the direct bonding step further includes bringing the first region and the third region into contact with each other, and the first region and the third region are directly bonded to each other.

8. The method according to claim 7, wherein the direct bonding step further includes bringing the second region and the fourth region into contact with each other, and the second region and the fourth region are directly bonded to each other.

9. The method according to claim 6, wherein the direct bonding step further includes cleaning at least one of the first and second surface layers before carrying out the step of bringing the first surface layer and the second surface layer into contact with each other.

10. The method according to claim 6, wherein the direct bonding step further includes activating at least one of the first and second surface layers before carrying out the step of bringing the first surface layer and the second surface layer into contact with each other.

11. The method according to claim 6, wherein the direct bonding step further includes annealing the first and second surface layers after the step of bringing the first surface layer and the second surface layer into contact with each other.

12. The step of preparing the first element is, A step of depositing a conductive and optically transparent first material onto a first substrate, The steps include: patterning the first material to form a first structure on the first substrate; The steps include depositing an insulating second material between the first structures and covering the first structures on the first substrate, The method according to claim 6, comprising the step of removing the second material from the first structure such that the second material between the first structures forms a first region and the first structures form a second region.

13. The second substrate and the second surface layer are optically transparent, and the step of preparing the second element is, A step of depositing a conductive and optically transparent third material onto the second substrate, The steps include: patterning the third material to form a second structure on the second substrate; The steps include depositing an insulating fourth material between the second structures and covering the second structures on the second substrate, The method according to claim 12, comprising the step of removing the fourth material from the second structure such that the fourth material between the second structures forms the third region and the second structures form the fourth region.

14. The step of preparing the first element is, A step of depositing an insulating first material onto the first substrate, The steps include: patterning the first material to form a first structure on the first substrate; A step of depositing a conductive and optically transparent second material onto the first substrate between and covering the first structures, The method according to claim 6, comprising the step of removing the second material from the first structure such that the second material between the first structures forms a second region and the first structures form a first region.

15. The second substrate and the second surface layer are optically transparent, and the step of preparing the second element is, The steps include depositing an insulating third material onto the second substrate, The steps include: patterning the third material to form an insulating second structure on the second substrate; A step of depositing a conductive and optically transparent fourth material onto the second substrate between and covering the second structures, The method according to claim 14, comprising the step of removing the fourth material from the second structure such that the fourth material between the second structures forms the fourth region and the second structures form the third region.

16. The step of preparing the first element is, A step of depositing a first photoresist material onto the first and second regions, The steps include removing the first photoresist material from the second region, The steps include depositing a first layer of optically transparent metal or polysilicon onto the second region, The method according to claim 6, comprising the step of removing the first photoresist material from the first region and leaving the first layer on the second region.

17. The second substrate and the second surface layer are optically transparent, and the step of preparing the second element is, The steps include depositing a second photoresist material onto the third and fourth regions, The steps include removing the second photoresist material from the fourth region, The steps include depositing a second layer of optically transparent metal or polysilicon onto the fourth region, The method according to claim 16, comprising the step of removing the second photoresist material from the third region and leaving the second layer on the fourth region.

18. The step of preparing the first element is, A step of depositing a conductive and optically transparent first material onto a first substrate, The steps include: flattening the first material, The process includes the step of depositing a first layer of optically transparent metal or polysilicon onto the planarized first material, The second substrate and the second surface layer are optically transparent, and the step of preparing the second element is, A step of depositing a second material that is conductive and optically transparent onto the second substrate, The steps include: flattening the second material described above, The method according to claim 6, comprising the step of depositing a second layer of optically transparent metal or polysilicon onto the planarized second material.

19. The method according to claim 18, wherein the direct bonding step further includes cleaning at least one of the first and second surface layers before carrying out the step of bringing the first surface layer and the second surface layer into contact with each other.

20. The method according to claim 18, wherein the direct bonding step further includes activating at least one of the first and second surface layers before carrying out the step of bringing the first surface layer and the second surface layer into contact with each other.

21. The method according to claim 18, wherein the direct bonding step further includes annealing the first and second surface layers after the step of bringing the first surface layer and the second surface layer into contact with each other.

22. The method according to claim 6, wherein the step of direct bonding comprises direct hybrid bonding.

23. The method according to claim 6, wherein the first substrate consists of a first photoelectronic element, and the second substrate consists of a second photoelectronic element.

24. The method according to claim 6, wherein the direct bonding step forms a bonded structure, and the method further comprises the steps of covering the bonded structure with a protective layer, separating the bonded structure to form a separate die, removing the protective layer from the separate die, and cleaning the separate die.

25. It is a device, Having a first substrate, The first substrate has a first layer, and the first layer is A first region made of an optically transparent and insulating first material, The present invention comprises at least one second region at least partially embedded in the at least one first region, wherein the at least one second region is made of an optically transparent and conductive second material. Having a second substrate, The second substrate has a second layer, the second layer is directly bonded to the first layer, and the second layer is At least one third region made of an insulating third material, An apparatus having at least one fourth region at least partially embedded in the at least one third region, wherein the at least one fourth region is made of a conductive fourth material.

26. The apparatus according to claim 25, wherein the at least one first region is directly bonded to the at least one third region, and the at least one second region is directly bonded to the at least one fourth region.

27. The apparatus according to claim 26, wherein the first material is the same as the third material.

28. The apparatus according to claim 26, wherein the first material is different from the third material.

29. The apparatus according to claim 26, wherein the second material is the same as the fourth material.

30. The apparatus according to claim 26, wherein the second material is different from the fourth material.

31. The apparatus according to claim 25, wherein the at least one third region and the at least one fourth region are optically transparent.

32. It is an element, circuit board and The substrate has a hybrid bonding surface layer, and the hybrid bonding surface layer is A first layer made of a first material that is optically transparent and electrically conductive, An element comprising at least two second layers provided covering the at least one first layer, wherein the at least one second layer is made of an optically transparent and conductive metal or polysilicon material.

33. The element according to claim 32, wherein the first material is selected from the group consisting of doped metal oxides, undoped metal oxides, aluminum zinc oxide, indium tin oxide, zinc oxide, zinc tin oxide, indium-doped zinc oxide, indium oxide, cadmium tin oxide, tin oxide, titanium dioxide, niobium-doped titanium dioxide, titanium nitride, and transition metal nitrides containing Group IIIB, Group IVB, or Group VB transition metals.

34. The element according to claim 33, wherein the second material is made of at least one metallic material selected from the group consisting of gold, silver, aluminum, copper, iridium, iron, nickel, osmium, palladium, platinum, rhenium, rhodium, ruthenium, and zinc.

35. The element according to claim 34, wherein the at least second layer has a thickness of less than 50 micrometers.

36. It is a device, Having a first substrate, The first substrate has a plurality of first layers, and the plurality of first layers are A first layer made of an optically transparent and conductive first material, The present invention comprises at least one second layer deposited on the at least one first layer, wherein the at least one second layer is made of an optically transparent and conductive second material, and the second material is made of metal or polysilicon. Having a second substrate, The second substrate has a second plurality of layers, and the second plurality of layers are At least one third layer made of an optically transparent and conductive third material, and An apparatus having at least one fourth layer deposited on at least one third layer, wherein the at least one fourth layer is made of an optically transparent and conductive fourth material, the fourth material is made of a metal or polysilicon, and the fourth material is directly bonded to the second material.

37. The apparatus according to claim 36, wherein the first material is the same as the third material.

38. The apparatus according to claim 36, wherein the first material is different from the third material.

39. The apparatus according to claim 36, wherein the second material is the same as the fourth material.

40. The apparatus according to claim 36, wherein the second material is different from the fourth material.

41. The apparatus according to claim 36, wherein the at least one second layer has a thickness of less than 50 nanometers, and the at least one fourth layer has a thickness of less than 50 nanometers.

42. It is a structure, The device comprises a first device assembly, the first device assembly is A first backplane substrate including an optically transparent first layer region, The first device substrate includes, A first optical device and An optically transparent second layer region in electrical contact with the first optical device, A structure having an optically transparent third layer region in electrical contact with the first optical device, wherein the third layer region is located on the opposite side of the first device substrate from the second layer region, and the second layer region is directly bonded to the first layer region.

43. A second device assembly comprising a second optical device and an optically transparent fourth layer region in electrical contact with the second optical device, The device further comprises an interposer assembly located between the first device assembly and the second device assembly, wherein the interposer assembly is An interposer substrate including an electrical conduit, A first set of electrical conduits are in electrical contact with an optically transparent fourth layer region which is directly bonded to the third layer region of the first device assembly, The structure according to claim 42, comprising an optically transparent sixth layer region that is in electrical contact with a second set of electrical conduits and is directly bonded to the fourth layer region of the second device assembly.

44. The second device assembly is A second backplane substrate including an optically transparent seventh layer region, The second device substrate includes, The second optical device and the fourth layer region, The structure according to claim 43, comprising an optically transparent eighth layer region in electrical contact with the second optical device, wherein the eighth layer region is located on the opposite side of the second device substrate as seen from the fourth layer region, and the eighth layer region is directly bonded to the seventh layer region.

45. The structure according to claim 43, wherein the first optical device consists of a light source, and the second optical device consists of pixels.

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