Doped silicon-containing material with improved electrical, mechanical, and etching properties.

Abstract

An exemplary semiconductor processing method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area. The deposition precursor may include a silicon-containing precursor. The method may include supplying a dopant precursor to the processing area of ​​the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating plasma products of the deposition precursor and the dopant precursor. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of approximately -50 MPa or higher.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefits and priority of U.S. Patent Application No. 18 / 192,573, filed March 29, 2023, entitled “DOPED SILICON-CONTAINING MATERIALS WITH INCREASED ELECTRICAL, MECHANICAL, AND ETCH CHARACTERISTICS,” which is incorporated into this application in its entirety by reference.

[0002] Technical field This technology relates to a semiconductor processing method. More specifically, this technology relates to a method for producing doped silicon-containing materials for semiconductor structures. [Background technology]

[0003] Integrated circuits are made possible by processes that manufacture intricately patterned material layers on a substrate surface. Manufacturing patterned materials on a substrate requires controlled methods for depositing and removing the material. As devices become smaller, the aspect ratios of structures and / or material layers can increase, making it difficult to maintain the dimensions of these structures and the properties of these material layers. For example, developing silicon-containing materials that possess desirable electrical and mechanical properties can be a significant challenge. Furthermore, as the number of material layers patterned or removed during processing increases, it becomes increasingly difficult to manufacture materials that can improve removal rate and / or removal selectivity compared to other exposed materials.

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. This technology addresses these and other needs. [Overview of the project]

[0005] An exemplary semiconductor processing method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area. The deposition precursor may include a silicon-containing precursor. The method may include supplying a dopant precursor to the processing area of ​​the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating plasma products of the deposition precursor and the dopant precursor. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of about -50 MPa or higher.

[0006] In some embodiments, the silicon-containing precursor is or may contain tetraethyl orthosilicate (TEOS). The deposition precursor may further contain an oxygen-containing precursor. The oxygen-containing precursor is or may contain nitrous oxide (N2O). The plasma products of the deposition precursor and dopant precursor can be generated at a plasma output of about 2000 W or less. The silicon-containing material has a viscosity of about 5.0 E-0.8 A / cm² at 9 MV / cm². 2 The following leakage currents may be characteristic of silicon-containing materials: 0.001 A / cm². 2 The silicon-containing material may be characterized by a breakdown voltage of approximately 6.0 MV / cm or higher. The silicon-containing material may be characterized by a wet etching rate ratio (WERR) of approximately 2.0 or higher. The method may include annealing the silicon-containing material. Annealing the silicon-containing material may include exposing the silicon-containing material to a temperature of approximately 600°C or higher.

[0007] Embodiments of this technology may encompass a semiconductor processing method. The method may include supplying a silicon-containing precursor and an oxygen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed in the processing area. The method may include supplying a dopant precursor to the processing area of ​​the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating plasma products of the silicon-containing precursor, the oxygen-containing precursor, and the dopant precursor. The method may include depositing a silicon-containing material on a substrate. The silicon-containing material may be characterized by a stress of about -50 MPa or higher. The silicon-containing material may be characterized by a wet etching rate ratio (WERR) of about 2.0 or higher.

[0008] In some embodiments, the dopant precursor may be phosphine (PH3) or contain phosphine. The flow rate of the dopant precursor may be about 500 sccm or less. The silicon-containing material may be characterized by a phosphorus content of about 5 atomic percent or less. The silicon-containing material may be deposited on a polysilicon material. The method may include annealing the silicon-containing material at a temperature of about 600°C or higher for about 5 minutes or more. After annealing, the phosphorus content in the silicon-containing material may decrease by only about 1.0 atomic percent or less.

[0009] Embodiments of this technology may encompass a semiconductor processing method. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed in the processing area. The method may include supplying a dopant precursor to the processing area of ​​the semiconductor processing chamber. The dopant precursor may include a phosphorus-containing precursor. The method may include generating plasma products of the deposition precursor and the dopant precursor. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a phosphorus content of about 3 atomic percent or less. The silicon-containing material may be characterized by a stress of about -50 MPa or higher. The silicon-containing material may be characterized by a wet etching rate ratio (WERR) of about 2.0 or higher.

[0010] In some embodiments, the silicon-containing material may include phosphorus-doped silicon oxide. The silicon-containing material has a viscosity of approximately 1.0E-09A / cm³. 2 The following leakage currents may be characteristic of silicon-containing materials: 0.001 A / cm². 2 It may be characterized by a breakdown voltage of approximately 6.0 MV / cm or higher.

[0011] Such technologies can offer many advantages compared to conventional systems and techniques. For example, embodiments of this technology can produce silicon-containing materials, such as materials containing silicon and oxygen, characterized by an increased wet etching rate ratio (WERR) and compressive stress. Furthermore, this technology can also produce silicon-containing materials with tunable film properties and improved electrical and mechanical properties. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying descriptions and drawings.

[0012] Further understanding of the nature and advantages of the disclosed technology can be gained by referring to the remainder of the specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] A schematic cross-sectional view of an exemplary plasma system according to several embodiments of this technology is shown. [Figure 2] The operation of a semiconductor processing method according to several embodiments of this technology is shown. [Figure 3A] An exemplary schematic cross-sectional structure is shown, which includes material layers and was manufactured according to several embodiments of the present technology. [Figure 3B] An exemplary schematic cross-sectional structure is shown, which includes material layers and was manufactured according to several embodiments of the present technology. [Modes for carrying out the invention]

[0014] Several diagrams are included as schematic representations. These diagrams are for illustrative purposes only, and scale should not be considered unless explicitly stated otherwise. Furthermore, the diagrams are provided as schematic representations to aid understanding and may not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0015] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016] As device size decreases, the thickness and size of many material layers may be reduced to scale the device. As structures within the device are placed closer together and material layers become smaller, silicon-containing materials may not be able to maintain their desired electrical, mechanical, and etching properties. For example, increasing the compressibility of silicon-containing materials may impair the wet etching rate ratio (WERR), which can cause problems during etching operations such as memory hole formation in 3D NAND applications. Furthermore, as material layers become smaller, silicon-containing materials may suffer from a decrease in electrical properties, such as increased leakage current and / or a decrease in breakdown voltage. Moreover, when these silicon-containing materials are incorporated into semiconductor integrated circuits, the process may involve back-end-of-line annealing, which can expose the structure to temperatures exceeding 600°C. Many materials, including silicon-containing materials, can be affected by this annealing, potentially leading to delamination due to poor adhesion.

[0017] This technique overcomes these problems by performing the deposition of a silicon-containing material while supplying a dopant precursor together with the deposition precursor. A dopant precursor such as a phosphorus-containing precursor can provide desirable electrical, mechanical, and etching characteristics to the silicon-containing material. For example, by incorporating a dopant into the silicon-containing material, the trade-off between stress and WERR can be eliminated. Further, by incorporating a dopant into the silicon-containing material, a silicon-containing material characterized by low leakage current and high breakdown voltage can be provided while maintaining film defects at a low level during deposition and / or subsequent processing.

[0018] In the remainder of the disclosure, a particular deposition process utilizing the disclosed technique is identified as normal, and one type of semiconductor processing chamber is described. However, it will be readily understood that the processes described can be implemented in any number of semiconductor processing chambers and in any number of processing operations in which the described films can be incorporated. Thus, the technique should not be considered limited to use only in these particular deposition processes or chambers. In this disclosure, before describing the semiconductor processing method according to the technique, one possible chamber that can be used for implementing the processes according to embodiments of the technique is discussed.

[0019] Figure 1 shows a cross-sectional view of an exemplary processing chamber according to several embodiments of the present technology. The figure may illustrate an outline of a system incorporating one or more aspects of the present technology, and / or a system that may be specifically configured to perform one or more operations according to embodiments of the present technology. Further details of the chamber 100 or the method to be carried out may be described further below. The chamber 100 can be used to form a film layer according to several embodiments of the present technology, but it should be understood that the method can be similarly carried out in any chamber capable of film formation. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and surrounding the substrate support 104 in a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126 that can be conventionally sealed for processing using a slit valve or door. The substrate 103 can be seated on the surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 on which the shaft 144 of the substrate support 104 may be located, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0020] The plasma profile modulator 111 is disposed within the processing chamber 100 and can control the plasma distribution over the entire substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 can include a first electrode 108 that can be disposed adjacent to the chamber body 102, and the chamber body 102 can be separated from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106 or can be a separate sidewall electrode. The first electrode 108 can be an annular or ring-shaped member or can be a ring electrode. The first electrode 108 can be a continuous loop along the periphery of the processing chamber 100 surrounding the processing volume 120 or can be discontinuous at selected positions as required. The first electrode 108 can also be a porous electrode such as a porous ring or mesh electrode or can be a plate electrode such as, for example, a secondary gas distributor.

[0021] One or more isolators 110a, 110b, which can be dielectric materials such as ceramics or metal oxides, for example, aluminum oxide and / or aluminum nitride, contact the first electrode 108 and can electrically and thermally separate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 can define apertures 118 for distributing the processing precursor into the processing volume 120. The gas distributor 112 can be coupled to a first power source 142, for example, an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be coupled to the processing chamber. In some embodiments, the first power source 142 can be an RF power source.

[0022] The gas distributor 112 may be a conductive or non-conductive gas distributor. The gas distributor 112 can also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered by a first power source 142, for example, as shown in Figure 1, or, in some embodiments, the gas distributor 112 may be connected to earth.

[0023] The first electrode 108 can be coupled to a first tuning circuit 128 that can control the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include them. The first tuning circuit 128 may be one or more inductors 132, or may include them. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments shown, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. A second inductor 132B may be positioned between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage sensor or a current sensor and can be coupled to the first electronic controller 134, thereby providing some degree of closed-loop control of the plasma state inside the processing volume 120.

[0024] The second electrode 122 can be connected to the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or bonded to the surface of the substrate support 104. The second electrode 122 can be a plate, a porous plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and can be connected to a second tuning circuit 136 by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms, located on the shaft 144 of the substrate support 104). The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and can be connected to the second electronic controller 140 to provide further control over the plasma state in the processing volume 120.

[0025] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, can be connected to the substrate support 104. The third electrode can be connected to a second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF power, or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature between about 25°C and about 800°C, or higher.

[0026] The lid assembly 106 and substrate support 104 of Figure 1 can be used with any processing chamber for plasma or heat treatment. During operation, the processing chamber 100 can provide real-time control of the plasma state within the processing volume 120. The substrate 103 can be placed on the substrate support 104, and the processing gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the processing chamber 100 through the outlet 152. Power can be coupled with the gas distributor 112 to establish the plasma within the processing volume 120. In some embodiments, the substrate can be subjected to electrical bias using a third electrode 124.

[0027] By supplying energy to the plasma in the processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Next, electronic controllers 134 and 140 can be used to adjust the flow characteristics of the ground path represented by two tuning circuits 128 and 136. Setpoints can be supplied to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and independent control of the uniformity of plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, the electronic sensors can adjust the variable capacitors to maximize the deposition rate and independently minimize thickness non-uniformity.

[0028] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor, as well as the inductances of the first inductor 132A and the second inductor 132B, can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimal air or lateral coverage over the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma increases to its maximum, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, potentially reducing the air coverage of the substrate support. The second electronic controller 140 may have a similar effect, increasing or decreasing the air coverage of the plasma on the substrate support as its capacitance changes.

[0029] Electronic sensors 130 and 138 can be used to tune the respective closed-loop circuits 128 and 136. Depending on the type of sensor used, a current or voltage setpoint can be installed on each sensor, and the sensors may have control software that determines adjustments to the respective electronic controllers 134 and 140 to minimize deviations from the setpoint. As a result, the plasma shape can be selected and dynamically controlled during processing. The above discussion is based on electronic controllers 134 and 140, which may be variable capacitors, but it should be understood that any electronic component with adjustable characteristics can be used to provide adjustable impedance to the tuning circuits 128 and 136.

[0030] Figure 2 shows exemplary operations in processing method 200 according to several embodiments of the present technology. Method 200 can be carried out in various processing chambers, including the processing chamber 100 described above, as well as any other chambers in which operations may be performed. Method 200 may include several optional operations, which may or may not be specifically associated with certain embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formation, but are not critical to the technology or may be carried out by alternative methodologies that would be more readily understood.

[0031] Method 200 may include additional operations before commencing the enumerated operations. For example, additional processing operations may include forming a structure on the semiconductor substrate, which may include both the formation and removal of material. Pre-processing operations may be performed in the chamber in which Method 200 may be carried out, or processing may be carried out in one or more other processing chambers before the substrate is transported to the semiconductor processing chamber in which Method 200 may be carried out. In any case, Method 200 may optionally include delivering the semiconductor substrate to the processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to another chamber that may contain the components described above. The substrate may be placed on a substrate support, which may be a pedestal, such as the substrate support 104, and may be placed in the processing area of ​​a chamber, such as the processing volume 120 described above. Method 200 illustrates the operations schematically shown in Figures 3A-3B, which will be explained in conjunction with the operations of Method 200. Figures 3A-3B show only partial schematic diagrams of an exemplary structure 300, and it should be understood that the substrate 305 may include numerous additional materials and features having various properties and characteristics, as shown in the figures.

[0032] In operation 205, one or more deposition precursors may be supplied to the processing area of ​​the semiconductor processing chamber. As shown in Figure 3A, for example, the material being deposited may be a silicon-containing material 315 used in semiconductor processing. In embodiments, the silicon-containing material 315 may be deposited on another material 310, such as a polysilicon material in 3D NAND applications or a material containing silicon and nitrogen. The deposition precursors may include any number of precursors, including silicon-containing and oxygen-containing precursors, as well as any other deposition precursors useful for forming the silicon-containing material. The deposition precursors may be flowed together or individually. For example, in exemplary embodiments in which a material containing silicon and oxygen can be formed, the silicon-containing and oxygen-containing precursors may be supplied to the processing area of ​​the processing chamber. As will be described later, in some embodiments of the technology, plasma-enhanced deposition can be performed, thereby accelerating the reaction and deposition of the material.

[0033] In embodiments, the silicon-containing precursor may be one or more silanes and disilanes, among other silicon-containing precursors useful in semiconductor processing, or may include them. For example, the silicon-containing precursor may be a precursor containing silicon and oxygen, such as tetraethyl orthosilicate (TEOS), octamethylcyclotetrasiloxane (OMCTS), or any other silicon-containing precursor useful in semiconductor processing. The oxygen-containing precursor may be molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), or any other oxygen-containing precursor useful in semiconductor processing, or may include them.

[0034] The technology may further include supplying a dopant precursor in operation 210. The dopant precursor may be supplied together with other deposition precursors such as a silicon-containing precursor and / or an oxygen-containing precursor. In embodiments, the dopant precursor may be a phosphorus-containing precursor that can promote phosphorus uptake in the deposited silicon-containing material 315. The phosphorus-containing precursor may be one or more of phosphine (PH3), diphosphine (P2H6), triethyl orthophosphate (TEPO), trimethyl phosphate (TMP), triethyl phosphate (TEP), tributyl phosphate (TBP), or any other phosphorus-containing precursor useful in semiconductor processing.

[0035] Depending on the deposition precursor, the flow rate of the dopant precursor can be adjusted to control the uptake of the dopant in the deposited silicon-containing material 315. For example, in the case of phosphorus dopant, even if the flow rate of other deposition precursors exceeds several hundred mg / min or sccm, the dopant precursor can be flowed at a flow rate of approximately 1000 sccm or less, and can be supplied at flow rates of approximately 900 sccm or less, approximately 800 sccm or less, approximately 700 sccm or less, approximately 600 sccm or less, approximately 500 sccm or less, approximately 400 sccm or less, approximately 350 sccm or less, approximately 300 sccm or less, approximately 250 sccm or less, approximately 200 sccm or less, approximately 150 sccm or less, approximately 100 sccm or less, or less.

[0036] In additional embodiments, the carrier gas can be combined with the deposition precursor and / or dopant precursor flowing into the processing area of ​​the semiconductor processing chamber. In embodiments, the carrier gas may be one or more of helium, argon, and molecular nitrogen (N2), among other carrier gases. In embodiments, the carrier gas flow rate may be about 1000 sccm or more, about 1500 sccm or more, about 2000 sccm or more, about 2500 sccm or more, about 3000 sccm or more, about 4000 sccm or more, about 5000 sccm or more, about 6000 sccm or more, or more. In some embodiments, increasing the carrier gas flow rate may be beneficial to the mechanical properties of the film. Furthermore, the presence of the carrier gas can also facilitate plasma generation.

[0037] All supplied precursors can be used in operation 215 to form plasma within the processing area of ​​the semiconductor processing chamber. The plasma is generated within the processing area by supplying RF power to a gas distributor or pedestal, but any other processing chamber capable of generating plasma can be used as well. The plasma can be generated at power levels of approximately 2000 W or less, approximately 1750 W or less, approximately 1500 W or less, approximately 1250 W or less, approximately 1000 W or less, approximately 800 W or less, approximately 600 W or less, approximately 400 W or less, or lower.

[0038] During operation 215 of Method 200, an additional power source, a bias power supply, can be engaged and connected to the pedestal as described above to supply a bias voltage to the plasma generated on the substrate 305. This allows plasma products to be attracted to the substrate 305. The applied bias power can be set relatively low to minimize damage to the structure 300. Thus, in some embodiments, the plasma power supply can supply a plasma output of about 1000W or less to the pedestal, and can supply outputs of about 900W or less, about 800W or less, about 700W or less, about 600W or less, about 500W or less, about 400W or less, or less. Furthermore, by adjusting the applied source power and bias power, densification of the deposited silicon-containing material 315 can occur during Method 200. Although not bound by any particular theory, higher plasma output may increase dopant incorporation because the bond energy between dopants and hydrogen, such as between phosphorus and hydrogen, may be lower than the bond energy between silicon and hydrogen.

[0039] As shown in Figure 3B, in operation 220, the silicon-containing material 315 can be deposited on a substrate 305, such as on a dopant-containing material 310 within the deposited silicon-containing material 315. For example, the silicon-containing material 315 may be phosphorus-doped silicon oxide. In some embodiments, by incorporating a dopant-containing precursor, it is possible to produce a film with reduced leakage current and increased breakdown voltage while controlling stress within the film. The silicon-containing material 315 may be useful in 3D NAND applications, particularly in 3D NAND applications where the number of layers of silicon oxide and polysilicon is increased. Specifically, the increase in the number of layers in 3D NAND requires silicon oxide with a high etching rate to help form straight memory holes during the etching operation. Depending on the structure 300, the thickness of the silicon-containing material 315 may be approximately 30 nm or less, and the thickness of the silicon-containing material 315 may be approximately 28 nm or less, approximately 26 nm or less, approximately 24 nm or less, approximately 22 nm or less, approximately 20 nm or less, approximately 18 nm or less, approximately 16 nm or less, or thinner.

[0040] In some embodiments, since the reaction takes place, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at a temperature of about 250°C or higher, and in some embodiments, it can be maintained at a temperature of about 300°C or higher, about 320°C or higher, about 340°C or higher, about 360°C or higher, about 380°C or higher, about 400°C or higher, about 420°C or higher, about 440°C or higher, about 460°C or higher, about 480°C or higher, about 500°C or higher, about 520°C or higher, about 540°C or higher, about 560°C or higher, about 580°C or higher, about 600°C or higher, about 620°C or higher, about 640°C or higher, or higher. By increasing the temperature, the deposition rate of the material can be decreased. Conversely, by decreasing the temperature, the deposition rate of the material can be increased. Therefore, in some embodiments, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at a temperature of about 700°C or less, and in some embodiments, at a temperature of about 680°C or less, about 660°C or less, about 640°C or less, about 620°C or less, about 600°C or less, about 580°C or less, about 560°C or less, about 540°C or less, about 520°C or less, or lower.

[0041] The semiconductor processing chamber can be maintained at a pressure of approximately 500 mTorr or higher, and in some embodiments, it can be maintained at a pressure of approximately 600 mTorr or higher, approximately 700 mTorr or higher, approximately 800 mTorr or higher, approximately 900 mTorr or higher, approximately 1 Torr or higher, approximately 2 Torr or higher, approximately 3 Torr or higher, approximately 4 Torr or higher, approximately 5 Torr or higher, approximately 6 Torr or higher, approximately 7 Torr or higher, approximately 8 Torr or higher, approximately 9 Torr or higher, approximately 10 Torr or higher, approximately 11 Torr or higher, approximately 12 Torr or higher, approximately 13 Torr or higher, approximately 14 Torr or higher, approximately 15 Torr or higher, or higher. Similarly, in some embodiments, the semiconductor processing chamber can be maintained at a pressure of about 30 Torr or less, and in some embodiments, at a pressure of about 28 Torr or less, about 26 Torr or less, about 24 Torr or less, about 22 Torr or less, about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, or lower. In some cases, the deposition rate increases at higher pressures, while in other cases, the deposition rate decreases at higher pressures.

[0042] The dopant can be included in any amount or concentration, and can be included in the deposited silicon-containing material 315 in amounts of about 5 atomic percent or less, and in some embodiments, it can be included in amounts of about 4.8 atomic percent or less, about 4.6 atomic percent or less, about 4.4 atomic percent or less, about 4.2 atomic percent or less, about 4 atomic percent or less, about 3.8 atomic percent or less, about 3.6 atomic percent or less, about 3.4 atomic percent or less, about 3.2 atomic percent or less, about 3 atomic percent or less, about 2.8 atomic percent or less, about 2.6 atomic percent or less, about 2.4 atomic percent or less, about 2.2 atomic percent or less, about 2 atomic percent or less, about 1.8 atomic percent or less, about 1.6 atomic percent or less, about 1.4 atomic percent or less, about 1.2 atomic percent or less, about 1 atomic percent or less, or lower amounts or concentrations.

[0043] Silicon-containing material 315 can be deposited under high compressive stress. Low-stress materials can be characterized by internal stress levels close to neutral stress (i.e., 0 MPa), while high-stress materials can be characterized by internal stress levels significantly higher than 0 MPa (i.e., high positive (tensile) stress) or significantly lower than 0 MPa (i.e., high negative (compressive) stress). High positive stress can be characterized as tensile stress, causing expansion of adjacent materials and generating outward pushing forces on adjacent substrate features. High negative stress can be characterized as compressive stress, causing contraction of adjacent materials and generating inward tensile forces on adjacent substrate features. In other words, high-stress materials can be characterized by an absolute value of the stress level significantly higher than 0 MPa. Therefore, when a material is characterized by a stress level "greater than -1000 MPa", this refers to the absolute value of the stress level, including levels such as -1500 MPa and -2000 MPa. Similarly, when a material is characterized by a stress level of "less than -1000 MPa," this refers to a stress level close to neutral stress (i.e., 0 MPa), including levels such as -500 MPa and -100 MPa, but not reaching positive values ​​of approximately 1000 MPa or higher.

[0044] The exemplary stress values ​​of silicon-containing material 315 can include values ​​of approximately -50 MPa or higher, where a more negative stress value means the material has greater stress, and a stress value closer to 0 MPa means the material has smaller stress. Additional exemplary stress value ranges may include values ​​of approximately -60 MPa or higher, approximately -70 MPa or higher, approximately -80 MPa or higher, approximately -90 MPa or higher, approximately -100 MPa or higher, approximately -110 MPa or higher, approximately -120 MPa or higher, approximately -130 MPa or higher, approximately -140 MPa or higher, approximately -150 MPa or higher, or higher. By doping silicon-containing material 315, a trade-off between stress and wet etching rate ratio (WERR) can be achieved. More specifically, compared to conventional silicon-containing materials characterized by increased WERR, such as undoped materials containing silicon and oxygen, silicon-containing materials containing phosphorus dopant according to this technology may be characterized by high compressive stress. Furthermore, unlike tensile silicon-containing materials, the compressible silicon-containing materials of this technology can exhibit improved adhesion and reduced delamination.

[0045] Silicon-containing material 315 can be characterized by a WERR of approximately 2.0 or higher, and can also be characterized by a WERR of approximately 2.1 or higher, approximately 2.2 or higher, approximately 2.3 or higher, approximately 2.4 or higher, approximately 2.5 or higher, approximately 2.6 or higher, approximately 2.7 or higher, approximately 2.8 or higher, approximately 2.9 or higher, approximately 3.0 or higher, approximately 3.1 or higher, approximately 3.2 or higher, or greater. The incorporation of dopants may increase the WERR and the compressive stress of silicon-containing material 315. The increase in WERR may be due to the fact that the bond energy between the dopant and oxygen is lower than the bond energy between silicon and oxygen. For example, if the dopant contains phosphorus, the bond energy between phosphorus and oxygen is 335 kJ / mol, while the bond energy between silicon and oxygen is 452 kJ / mol.

[0046] Leakage current and dielectric breakdown can be affected by the atomic concentration within the materials being manufactured. However, by manufacturing the materials according to embodiments of the present technology, the leakage current at 9 MV / cm can be maintained at about 5.0E-8 A / cm 2 or less, about 4.0E-8 A / cm 2 or less, about 3.0E-8 A / cm 2 or less, about 2.8E-8 A / cm 2 or less, about 2.6E-8 A / cm 2 or less, about 2.4E-8 A / cm 2 or less, about 2.2E-8 A / cm 2 or less, about 2.0E-8 A / cm 2 or less, about 1.8E-8 A / cm 2 or less, or can be maintained smaller. Furthermore, the breakdown voltage of the film at 0.001 A / cm can be maintained at about 6.0 MV / cm or higher, about 6.5 MV / cm or higher, about 7.0 MV / cm or higher, about 7.5 MV / cm or higher, about 8.0 MV / cm or higher, about 8.5 MV / cm or higher, about 9.0 MV / cm or higher, about 9.5 MV / cm or higher, about 10.0 MV / cm or higher, about 10.5 MV / cm or higher, about 11.0 MV / cm or higher, about 11.5 MV / cm or higher, about 12.0 MV / cm or higher, about 12.5 MV / cm or higher, about 13.0 MV / cm or higher, about 13.5 MV / cm or higher, about 14.0 MV / cm or higher, or higher.

[0047] ​​In an optional operation 225, method 200 may include annealing the substrate 305. Deposition may be carried out at a first temperature, while thermal annealing may be carried out at a second temperature higher than the first temperature. For example, thermal annealing may be carried out at a temperature of about 480°C or higher, or at a temperature of about 500°C or higher, about 510°C or higher, about 520°C or higher, about 530°C or higher, about 540°C or higher, about 550°C or higher, about 560°C or higher, about 570°C or higher, about 580°C or higher, about 590°C or higher, about 600°C or higher, about 650°C or higher, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, or higher. Thermal annealing can be performed for a time that may be approximately 0.5 minutes or longer, and may be approximately 1 minute or longer, approximately 2 minutes or longer, approximately 3 minutes or longer, approximately 4 minutes or longer, approximately 5 minutes or longer, approximately 6 minutes or longer, approximately 8 minutes or longer, approximately 10 minutes or longer. During annealing in the optional operation 225, the dopant concentration may be maintained in the silicon-containing material 315. The maintenance of the dopant concentration may indicate that the dopant is bound and incorporated within the silicon-containing material 315 and therefore will not migrate during subsequent processing operations. For example, after annealing in the optional operation 225, the phosphorus content in the silicon-containing material may decrease by only about 1.0 atomic% or less, approximately 0.9 atomic% or less, approximately 0.8 atomic% or less, approximately 0.7 atomic% or less, approximately 0.6 atomic% or less, approximately 0.5 atomic% or less, or less atomic%.

[0048] In the preceding description, many details have been given for illustrative purposes to facilitate understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments can be carried out without some of these details, or with further details.

[0049] While several embodiments have been disclosed, it will be apparent to those skilled in the art that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, several well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the Art.

[0050] Where a range of values ​​is presented, it is understood that each intervention value up to the smallest unit of the lower limit between the upper and lower limits of that range is also specifically disclosed, unless the context explicitly indicates otherwise. Any narrow range between any listed value or unlisted intervention value within a listed range and any other listed value or intervention value within that listed range is also included. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range that includes one, neither, or both of the limit values ​​is also included in this technical scope and is subject to any specifically excluded limit values ​​within the specified range. Where one or both limit values ​​are included in the specified range, ranges that exclude one or both of those included limit values ​​are also included.

[0051] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” refer to multiple objects unless otherwise specified in the context. Thus, for example, “a precursor” includes multiple such precursors, and “the material” includes one or more materials and their equivalents known to those skilled in the art.

[0052] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used in this specification and the appended claims, are intended to identify the presence of a described feature, integer, component, or process, but do not exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, Supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area and the deposition precursor includes a silicon-containing precursor. Supplying a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor includes a phosphorus-containing precursor. To generate plasma products of the deposition precursor and the dopant precursor, and The method involves depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of approximately -50 MPa or higher. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the silicon-containing precursor comprises tetraethyl orthosilicate (TEOS).

3. The semiconductor processing method according to claim 1, wherein the deposition precursor further comprises an oxygen-containing precursor.

4. The oxygen-containing precursor is nitrous oxide (N ２ The semiconductor processing method according to claim 3, including O).

5. The semiconductor processing method according to claim 1, wherein the plasma products of the deposition precursor and the dopant precursor are generated with a plasma output of approximately 2000 W or less.

6. The silicon-containing material has an energy of approximately 5.0E-08A / cm at 9MV / cm. ２ The semiconductor processing method according to claim 1, characterized by the following leakage current.

7. The silicon-containing material has a load of 0.001 A / cm². ２ The semiconductor processing method according to claim 1, characterized by a breakdown voltage of approximately 6.0 MV / cm or more.

8. The semiconductor processing method according to claim 1, wherein the silicon-containing material is characterized by a wet etching rate ratio (WERR) of about 2.0 or more.

9. Annealing the silicon-containing material The semiconductor processing method according to claim 1, further comprising:

10. The semiconductor processing method according to claim 1, wherein annealing the silicon-containing material includes exposing the silicon-containing material to a temperature of about 600°C or higher.

11. A semiconductor processing method, Supplying silicon-containing precursors and oxygen-containing precursors to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area. Supplying a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor includes a phosphorus-containing precursor. To generate plasma products of the silicon-containing precursor, the oxygen-containing precursor, and the dopant precursor, and The method involves depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of approximately -50 MPa or higher, and the silicon-containing material is characterized by a wet etching rate ratio (WERR) of approximately 2.0 or higher. A semiconductor processing method, including the following.

12. The dopant precursor is phosphine (PH ３ The semiconductor processing method according to claim 11, including ).

13. The semiconductor processing method according to claim 11, wherein the flow rate of the dopant precursor is about 500 sccm or less.

14. The semiconductor processing method according to claim 11, wherein the silicon-containing material is characterized by a phosphorus content of about 5 atomic percent or less.

15. The semiconductor processing method according to claim 11, wherein the silicon-containing material is deposited on a polysilicon material.

16. Annealing the silicon-containing material at a temperature of approximately 600°C or higher for approximately 5 minutes or more. The semiconductor processing method according to claim 11, further comprising:

17. The semiconductor processing method according to claim 16, wherein, after annealing, the decrease in phosphorus content in the silicon-containing material is about 1.0 atomic percent or less.

18. A semiconductor processing method, Supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed within the processing area. Supplying a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor includes a phosphorus-containing precursor. To generate plasma products of the deposition precursor and the dopant precursor, and The method involves depositing a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a phosphorus content of approximately 3 atomic percent or less, a stress of approximately -50 MPa or higher, and a wet etching rate ratio (WERR) of approximately 2.0 or higher. A semiconductor processing method, including the following.

19. The semiconductor processing method according to claim 18, wherein the silicon-containing material includes phosphorus-doped silicon oxide.

20. The silicon-containing material has a concentration of approximately 1.0E-09A / cm². ２ Characterized by the following leakage currents, The silicon-containing material has a load of 0.001 A / cm². ２ Characterized by a breakdown voltage of approximately 6.0 MV / cm or higher, The semiconductor processing method according to claim 18.

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