Input Circuit

Abstract

To shorten the delay time in an input buffer circuit and suppress the error of the pulse width of an output signal in an input circuit.SOLUTION: An input circuit 1 includes an input buffer circuit 12 whose first node a is an input and second node b is an output, an N type transistor N1 whose source is connected to an input terminal PAD, drain is connected to the first node a, and gate is connected to a power source VDD, and a pullup circuit 21 provided between the first node a and the power source VDD. The pullup circuit 21 makes the power source VDD and the first node a conductive for a predetermined period when the input signal transits from low to high, and does not make the power source VDD and the first node a conductive when the input signal transits from high to low.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an input circuit for use in a semiconductor integrated circuit device. [Background technology]

[0002] When a semiconductor integrated circuit device is connected to another electronic device, a signal having a voltage higher than the power supply voltage of the semiconductor integrated circuit device may be input. In order to protect the internal circuit in such a case, a circuit for lowering the voltage of the input signal is provided in the input circuit of the semiconductor integrated circuit device. For example, in a commonly used input circuit, an N-type transistor for voltage lowering is provided in the front stage of the input buffer circuit, and its gate is connected to the power supply. This reduces the voltage of the input signal to a voltage equivalent to the difference between the power supply voltage and the threshold voltage of the N-type transistor. Therefore, the internal circuit of the semiconductor integrated circuit device can be protected.

[0003] Patent Document 1 discloses an input circuit having an inverter as an input buffer circuit, an N-type transistor for stepping down the voltage provided in front of the inverter, and a P-type transistor connected between the input node of the inverter and a power supply. The gate of this P-type transistor is connected to the output node of the inverter. When the input signal rises and the output signal of the inverter starts to invert from high to low, the P-type transistor turns on and the voltage of the input node of the inverter is boosted to the power supply voltage. This accelerates the inversion of the output signal, making it possible to keep the delay time of the inverter short. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 3092636 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the input circuit disclosed in Patent Document 1 has the following problem. That is, when the input signal starts to fall, the P-type transistor is in an ON state. Therefore, a short circuit occurs between the power supply and the low driving element of the output circuit on the transmitting side until the output signal of the inverter is inverted to high and the P-type transistor is turned off. In this state, the transition of the input signal from high to low becomes gentle, and the inversion of the output signal of the inverter is significantly delayed. Therefore, the delay time of the inverter increases. As a result, a large difference occurs in the delay time of the inverter between the rising and falling edges of the input signal, which causes an error in the pulse width of the output signal of the input circuit.

[0006] An object of the present disclosure is to reduce the delay time in an input buffer circuit in an input circuit and to suppress errors in the pulse width of an output signal. [Means for solving the problem]

[0007] In a first aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply, and a pull-up circuit provided between the first node and the power supply, wherein the pull-up circuit is configured to connect the power supply and the first node for a predetermined period of time when the input signal transitions from low to high, and to not connect the power supply and the first node when the input signal transitions from high to low.

[0008] According to this aspect, the input circuit includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to an input terminal, a drain connected to the first node, and a gate connected to a power supply, and a pull-up circuit provided between the first node and the power supply. When the input signal transitions from low to high, the pull-up circuit makes the power supply and the first node conductive for a predetermined period. Therefore, the voltage of the first node is boosted and the signal inversion of the second node is accelerated, so that the delay time in the input buffer circuit is shortened. On the other hand, when the input signal transitions from high to low, the pull-up circuit does not make the power supply and the first node conductive. Therefore, there is no short circuit between the power supply and the low drive element of the output circuit on the transmitting side, and the input signal transitions quickly from high to low, so that there is no delay in the signal inversion of the second node. Therefore, the difference in delay time in the input buffer circuit between the rising edge and the falling edge of the input signal can be suppressed, so that the error occurring in the pulse width of the output signal can be suppressed.

[0009] In a second aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit that has a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply, and a pull-up circuit provided between the first node and the power supply, the pull-up circuit including first and second P-type transistors connected in series between the power supply and the first node, the first P-type transistor receiving an inverted signal of the signal at the first node at its gate, and the second P-type transistor receiving the signal at the second node at its gate when the input buffer circuit is a buffer that does not invert the logic of a signal, and receiving the inverted signal of the signal at the second node at its gate when the input buffer circuit is an inverter.

[0010] According to this aspect, the input circuit includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit includes first and second P-type transistors connected in series between the power supply and the first node. The first P-type transistor receives an inverted signal of the signal at the first node at its gate. When the input buffer circuit is a buffer that does not invert the logic of a signal, the second P-type transistor receives a signal at the second node at its gate, and when the input buffer circuit is an inverter, the second P-type transistor receives an inverted signal of the signal at the second node at its gate. When the input signal is low, the second P-type transistor is in an on state because it receives a low signal at its gate. When the input signal transitions from low to high, the first P-type transistor turns on when the inverted signal of the signal at the first node falls below a threshold. As a result, the voltage at the first node is boosted and the signal inversion at the second node is accelerated, thereby shortening the delay time in the input buffer circuit. On the other hand, when the input signal is high, the second P-type transistor is in the off state because its gate receives a high signal. Therefore, when the input signal transitions from high to low, there is no short circuit between the power supply and the low driver element of the output circuit on the sending side, and the input signal transitions quickly from high to low, so there is no delay in the signal inversion of the second node. Therefore, the difference in delay time in the input buffer circuit between the rising and falling edges of the input signal can be reduced, thereby reducing errors in the pulse width of the output signal. Effect of the Invention

[0011] According to the present disclosure, in an input circuit, it is possible to reduce the delay time in an input buffer circuit and suppress errors occurring in the pulse width of an output signal. [Brief description of the drawings]

[0012] [Figure 1] Example of circuit configuration of input circuit according to the first embodiment [Diagram 2] Signal waveforms showing the operation of the input circuit in Figure 1 [Diagram 3] Circuit configuration example of input circuit according to the second embodiment [Figure 4] Signal waveforms showing the operation of the input circuit in Figure 3 [Diagram 5] Another example of the circuit configuration of the input circuit according to the second embodiment [Figure 6] Circuit configuration example of input circuit according to the third embodiment [Figure 7] Example of circuit configuration of input circuit according to fourth embodiment [Figure 8] Signal waveforms showing the operation of the input circuit in Figure 7 [Figure 9] Another circuit configuration example of the input circuit according to the fourth embodiment [Figure 10] Another circuit configuration example of the input circuit according to the fourth embodiment [Figure 11] Circuit configuration example of input circuit according to the fifth embodiment [Figure 12] Another circuit configuration example of the input circuit according to the fifth embodiment [Figure 13] Circuit configuration example of input circuit according to the sixth embodiment [Figure 14] (a) is an example of the circuit configuration of the voltage conversion circuit in FIG. 13, and (b) is an example of the input and output voltages of the circuit in (a). [Figure 15] Circuit configuration example of input circuit according to the seventh embodiment DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments will be described with reference to the drawings. In the circuit diagrams shown below, the components related to the present disclosure are illustrated in a simplified manner. For example, components illustrated as being directly connected may be indirectly connected to each other in the actual circuit configuration because other components are disposed between them.

[0014] In the following explanation, "VDD" is used as a symbol to represent both the power supply itself and the power supply voltage. Furthermore, the "high" and "low" of a signal refer to the logic levels of the high and low potential sides of the signal. Furthermore, the "on" and "off" of a transistor refer to whether the transistor is in a conductive or non-conductive state.

[0015] In the following embodiments, it is assumed that the power supply voltage VDD is 1.8 V and the voltage of the input signal is 3.3 V or 1.8 V. The circuit operation will be described for the case where the voltage of the input signal is 3.3 V.

[0016] (First embodiment) Fig. 1 shows the circuit configuration of an input circuit according to a first embodiment. The input circuit 1 shown in Fig. 1 is provided in a semiconductor integrated circuit, and receives an input signal sent from another electronic device to the semiconductor integrated circuit at an input terminal PAD. When the voltage of the input signal is higher than a power supply voltage VDD, the input circuit 1 reduces the voltage of the input signal in order to protect the internal circuitry of the semiconductor integrated circuit.

[0017] The input circuit 1 includes an inverter 11 as an example of an input buffer circuit, an N-type transistor N1 for stepping down provided between an input terminal PAD and the inverter 11, and a pull-up circuit 21. The inverter 11 receives an input from a node a and outputs an output from a node b, inverting the signal at the node a and outputting it to the node b. The N-type transistor N1 has a source connected to the input terminal PAD, a drain connected to the node a, and a gate connected to a power supply VDD.

[0018] The pull-up circuit 21 includes a P-type transistor P1 and a two-input NAND circuit 31. The source of the P-type transistor P1 is connected to a power supply VDD, and the drain is connected to a node a. The two-input NAND circuit 31 receives the signals of the nodes a and b, and has an output node, node c, connected to the gate of the P-type transistor P1. That is, when the signals of the nodes a and b are both high and the signal of the node c is low, the P-type transistor P1 is turned on. Otherwise, the P-type transistor P1 is off.

[0019] The operation of the input circuit 1 in FIG. 1 will be described with reference to the signal waveforms in FIG.

[0020] (1) When a rising signal is input (the input signal transitions from low to high) When the input signal applied to the input terminal PAD is low, the signal at the node a is low and the signal at the node b is high. At this time, the signal at the node c becomes high, and the P-type transistor P1 is off.

[0021] When the input signal transitions from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of node a exceeds the threshold of the NAND circuit 31, the signal of node c goes low, which turns on the P-type transistor P1. When the P-type transistor P1 turns on, the voltage of node a is boosted, and the inversion of the signal of node b is accelerated. Therefore, the delay time in the inverter 11 is shortened (t1).

[0022] Here, by designing the NAND circuit 31 so that its delay time is shorter than that of the inverter 11, the P-type transistor P1 can be turned on earlier than in the example of Patent Document 1.

[0023] When the signal at node b transitions from high to low, the signal at node c goes high and P-type transistor P1 turns off again.

[0024] (2) When a falling signal is input (the input signal transitions from high to low) When the input signal transitions from high to low, the signal at node c remains high and the P-type transistor P1 remains off. Therefore, no short circuit occurs between the power supply VDD and the low driver element of the output circuit on the transmitting side, the input signal transitions quickly from high to low, and the signal waveform does not become sluggish. Therefore, the inversion of the signal at node b is not delayed, and the delay time in the inverter 11 does not increase (t2).

[0025] As a result of the above operation, no error occurs in the pulse width of the signal at node b relative to the pulse width of the input signal applied to input terminal PAD (tH_b=tL_PAD, tL_b=tH_PAD).

[0026] That is, in this embodiment, the pull-up circuit 21 is configured to connect the power supply VDD and node a for a predetermined period of time when the input signal transitions from low to high, and not connect the power supply VDD and node a when the input signal transitions from high to low.

[0027] As described above, according to this embodiment, the input circuit 1 includes an inverter 11 that receives an input from a node a and outputs a node b, an N-type transistor N1 whose source is connected to the input terminal PAD, whose drain is connected to the node a, and whose gate is connected to a power supply VDD, and a pull-up circuit 21 provided between the node a and the power supply VDD. When an input signal transitions from low to high, in the pull-up circuit 21, the output node c of the NAND circuit 31 becomes low for a predetermined period, and the P-type transistor P1 conducts the power supply VDD and the node a. As a result, the voltage of the node a is boosted and the signal inversion of the node b is accelerated, so that the delay time in the inverter 11 is shortened. On the other hand, when an input signal transitions from high to low, in the pull-up circuit 21, the output node c of the NAND circuit 31 does not become low, and the P-type transistor P1 does not conduct the power supply VDD and the node a. As a result, there is no short circuit between the power supply VDD and the low driving element of the output circuit on the transmitting side, and the input signal transitions quickly from high to low, so that there is no delay in the signal inversion of the node b. Therefore, the difference in delay time in inverter 11 between the rising and falling edges of the input signal can be reduced, making it possible to reduce errors occurring in the pulse width of the output signal.

[0028] Note that, as the input buffer circuit, a buffer that does not invert the logic of a signal may be used instead of the inverter 11. In this case, for example, an inverter may be provided between node b and the NAND circuit 31. That is, the signal of node a is provided as a first input to the NAND circuit 31, and when the input buffer circuit is an inverter, the signal of node b is provided as a second input, and when the input buffer circuit is a buffer that does not invert the logic of a signal, an inverted signal of the signal of node b is provided as the second input.

[0029] Second embodiment Fig. 3 shows the circuit configuration of an input circuit according to the second embodiment. The basic configuration of the input circuit 2 shown in Fig. 3 is similar to that of the input circuit 1 shown in Fig. 1. The input circuit 2 includes a buffer 12 that does not invert a signal as an example of an input buffer circuit, and also includes a pull-up circuit 22 that has a different configuration from the pull-up circuit 21 shown in Fig. 1.

[0030] The pull-up circuit 22 includes P-type transistors P1 and P2 connected in series between a power supply VDD and a node a, and an inverter 32. The inverter 32 receives a signal from the node a, and has an output node, node c, connected to the gate of the P-type transistor P1. The P-type transistor P2 receives a signal from a node b, which is the output node of the buffer 12, at its gate.

[0031] The operation of the input circuit 2 in FIG. 3 will be described with reference to the signal waveforms in FIG.

[0032] (1) When a rising signal is input (the input signal transitions from low to high) When the input signal applied to the input terminal PAD is low, the signal at node a is low and the signal at node b is low. At this time, the signal at node c is high, so the P-type transistor P1 is off and the P-type transistor P2 is on.

[0033] When the input signal transitions from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of node a exceeds the threshold of inverter 32, the signal of node c goes low, which turns on P-type transistor P1. Since P-type transistor P2 is on, turning on P-type transistor P1 boosts the voltage of node a, and the inversion of the signal of node b is accelerated. Therefore, the delay time in buffer 12 is shortened (t1).

[0034] Here, by designing the inverter 32 so that the delay time is shorter than that of the buffer 12, the P-type transistor P1 can be turned on earlier than in the example of Patent Document 1.

[0035] When the signal at node b transitions from low to high, P-type transistor P2 turns off.

[0036] (2) When a falling signal is input (the input signal transitions from high to low) When the input signal transitions from high to low, the signal at node b remains high and the P-type transistor P2 remains off. Therefore, no short circuit occurs between the power supply VDD and the low driver element of the output circuit on the transmitting side, the input signal transitions quickly from high to low, and the signal waveform does not become dull. Therefore, the inversion of the signal at node b is not delayed, and the delay time in the buffer 12 does not increase (t2).

[0037] Subsequently, when the voltage at node a drops below the threshold of inverter 32, the signal at node c goes high and P-type transistor P1 turns off again. After that, the signal at node b goes low after a delay time in buffer 12, so P-type transistor P2 turns on again. However, because P-type transistor P1 turns off earlier than P-type transistor P2 turns on, there is no electrical continuity between power supply VDD and node a when a falling signal is input.

[0038] As a result of the above operation, no error occurs in the pulse width of the signal at node b relative to the pulse width of the input signal applied to input terminal PAD (tH_b=tH_PAD, tL_b=tL_PAD).

[0039] In other words, the pull-up circuit 22 is configured to connect the power supply VDD and node a for a predetermined period of time when the input signal transitions from low to high, and not connect the power supply VDD and node a when the input signal transitions from high to low.

[0040] As described above, according to this embodiment, the input circuit 2 includes a buffer 12 having a node a as an input and a node b as an output, an N-type transistor N1 having a source connected to the input terminal PAD, a drain connected to the node a, and a gate connected to a power supply VDD, and a pull-up circuit 22 provided between the node a and the power supply VDD. The pull-up circuit 22 includes P-type transistors P1 and P2 connected in series between the power supply VDD and the node a. The P-type transistor P1 receives an inverted signal of the signal of the node a at its gate, and the P-type transistor P2 receives a signal of the node b at its gate. When the input signal is low, the P-type transistor P1 is in an off state because its gate receives a high signal. When the input signal transitions from low to high, the P-type transistor P1 turns on when the inverted signal of the signal of the node a falls below a threshold. As a result, the voltage of the node a is boosted and the signal inversion of the node b is accelerated, so the delay time in the buffer 12 is shortened. On the other hand, when the input signal is high, the P-type transistor P2 is in an off state because its gate receives a high signal. Therefore, when the input signal transitions from high to low, there is no short circuit between the power supply VDD and the low driver element of the output circuit on the transmitting side, and the input signal transitions quickly from high to low, so there is no delay in signal inversion at the second node. Therefore, the difference in delay time in the buffer 12 between the rising and falling edges of the input signal can be reduced, and therefore errors occurring in the pulse width of the output signal can be reduced.

[0041] Fig. 5 shows another example of the circuit configuration of the input circuit according to this embodiment. As in the input circuit 2A shown in Fig. 5, an inverter 11 may be used as an input buffer circuit. In this case, for example, in the pull-up circuit 22A, an inverter 33 may be provided between node b and the gate of the P-type transistor P2, so that an inverted signal of the signal at node b is provided to the gate of the P-type transistor P2.

[0042] Third embodiment Fig. 6 shows the circuit configuration of an input circuit according to a third embodiment. The basic configuration of the input circuit 3 shown in Fig. 6 is similar to that of the input circuit 2 shown in Fig. 3. The input circuit 3 includes a pull-up circuit 23 having a different configuration from the pull-up circuit 22 shown in Fig. 3.

[0043] The pull-up circuit 23 includes P-type transistors P1 and P2 connected in series between a power supply VDD and a node a, and inverters 32 and 34. The inverter 32 receives a signal from the node a, and has an output node, node c, connected to the gate of the P-type transistor P1. The inverter 34 receives a signal from the node c, and has an output node connected to the gate of the P-type transistor P2.

[0044] That is, in the input circuit 2 shown in FIG. 3, the signal at node b is applied to the gate of the P-type transistor P2, whereas in the input circuit 3 shown in FIG. 6, a signal that is the signal at node a delayed by inverters 32 and 34 is applied to the gate of the P-type transistor P2.

[0045] The operation of the input circuit 3 in Fig. 6 is similar to that of the input circuit 2 in Fig. 3. That is, the pull-up circuit 23 is configured to make the power supply VDD and the node a conductive for a predetermined period when the input signal transitions from low to high, and not to make the power supply VDD and the node a conductive when the input signal transitions from high to low. In addition, in the input circuit 3 in Fig. 6, the control of the P-type transistor P2 is performed independently of the characteristics of the buffer 12, which is an example of an input buffer circuit, and without affecting the characteristics of the buffer 12.

[0046] Therefore, according to this embodiment, as in the second embodiment, the difference in delay time in the buffer 12 between the rising and falling edges of the input signal can be reduced, thereby reducing errors occurring in the pulse width of the output signal.

[0047] (Fourth embodiment) Fig. 7 shows the circuit configuration of an input circuit according to a fourth embodiment. The input circuit 4 shown in Fig. 7 is configured to receive an enable signal EN and to be able to control whether an input signal passes or does not pass in response to the enable signal EN. Here, the input circuit 4 is configured to pass (enable) the input signal when the enable signal EN is "1" (high) and not pass (disable) the input signal when the enable signal EN is "0" (low).

[0048] The input circuit 4 includes a two-input NAND circuit 13 as an input buffer circuit. The two-input NAND circuit 13 receives the signal at node a and an enable signal EN as inputs, and outputs node b. When the enable signal EN is "1", an inverted signal of the signal at node a is output to node b, and when the enable signal EN is "0", node b is fixed high. In other words, when the enable signal EN is "1", the two-input NAND circuit 13 functions as an inverter that passes a signal, and when the enable signal EN is "0", it does not pass a signal.

[0049] The pull-up circuit 24 includes P-type transistors P1 and P2 connected in series between a power supply VDD and a node a, and a NAND circuit 31. The NAND circuit 31 receives the signals at nodes a and b, and has an output node, node c, connected to the gate of the P-type transistor P1. The gate of the P-type transistor P2 is connected to node d, which is the output node of an inverter 41 that receives an enable signal EN as an input. The pull-up circuit 24 has a configuration in which the P-type transistor P2 is added to the pull-up circuit 21 of FIG. 1.

[0050] When the enable signal EN is "1", the two-input NAND circuit 13 functions as an inverter and the P-type transistor P2 turns on, so that the input circuit 4 in FIG. 7 operates in the same manner as the input circuit 1 in FIG. 1 according to the first embodiment.

[0051] Figure 8 shows signal waveforms that indicate operation when the enable signal EN is "0". As shown in Figure 8, when the enable input EN is "0", node b is fixed high. As a result, the signal at node c that is provided to the gate of P-type transistor P1 changes in response to the transition of the input signal. However, since the signal at node d that is provided to the gate of P-type transistor P2 is fixed high, P-type transistor P2 is off. Therefore, no short circuit occurs between the power supply VDD and the low drive element of the output circuit on the transmitting side, and the waveform of the input signal does not become blunted.

[0052] Here, let us suppose that the pull-up circuit 24 has the same configuration as the pull-up circuit 21 in FIG. 1 without adding the P-type transistor P2. In this case, when the signal at node c goes low, a short circuit occurs between the power supply VDD and the low drive element of the output circuit on the transmitting side, and the waveform of the input signal becomes dull. This problem is solved in this embodiment. That is, according to this embodiment, the pass / non-pass of the input signal can be controlled by the enable signal EN, and when the enable signal EN is "0", dulling of the waveform of the input signal can be avoided.

[0053] 9 shows another example of the circuit configuration of the input circuit according to this embodiment. The input circuit 4A shown in FIG. 9 includes a two-input AND circuit 14 as an input buffer circuit. The two-input AND circuit 14 receives the signal at node a and the enable signal EN as inputs, and outputs node b. When the enable signal EN is "1", the signal at node a is output to node b, and when the enable signal EN is "0", node b is fixed low. That is, when the enable signal EN is "1", the two-input AND circuit 14 functions as a buffer that passes a signal, and when the enable signal EN is "0", it does not pass a signal.

[0054] The pull-up circuit 24A includes P-type transistors P1, P2, and P3 connected in series between a power supply VDD and a node a, and an inverter 32. The inverter 32 receives a signal from the node a, and has an output node, node c, connected to the gate of the P-type transistor P1. The P-type transistor P2 receives at its gate a signal from the node b, which is the output of the two-input AND circuit 14. The P-type transistor P3 has a gate connected to a node d, which is the output node of the inverter 41, which receives an enable signal EN as an input. The pull-up circuit 24A has a configuration in which the P-type transistor P3 is added to the pull-up circuit 22 in FIG. 3.

[0055] In the input circuit 4A of FIG. 9, when the enable input EN is "1", the two-input AND circuit 14 functions as a buffer and the P-type transistor P3 is turned on, so that the input circuit 4A operates similarly to the input circuit 2 of FIG. 3 according to the second embodiment. On the other hand, when the enable input EN is "0", the node b is fixed low and the P-type transistor P2 is turned on. However, since the signal at the node d given to the gate of the P-type transistor P3 is fixed high, the P-type transistor P3 is turned off. Therefore, no short circuit occurs between the power supply VDD and the low drive element of the output circuit on the transmitting side, and the waveform of the input signal is not blunted. Therefore, the same effect as the input circuit 4 of FIG. 7 can be obtained.

[0056] Fig. 10 shows another example of the circuit configuration of the input circuit according to this embodiment. The input circuit 4B shown in Fig. 10 includes a two-input NAND circuit 13 as an input buffer circuit. As with the input circuit 4 shown in Fig. 7, the two-input NAND circuit 13 receives the signal at node a and the enable input EN as inputs, and outputs node b.

[0057] The pull-up circuit 24B includes a P-type transistor P1 and a three-input NAND circuit 35. The source of the P-type transistor P1 is connected to a power supply VDD, and the drain is connected to a node a. The three-input NAND circuit 35 receives the signal of the node a, the signal of the node b, and an enable signal EN as inputs, and has an output node c connected to the gate of the P-type transistor P1.

[0058] In the input circuit 4B of FIG. 10, when the enable signal EN is "1", the two-input NAND circuit 13 functions as an inverter and the three-input NAND circuit 35 functions as a two-input NAND circuit, so that it operates similarly to the input circuit 1 of FIG. 1 according to the first embodiment. On the other hand, when the enable signal EN is "0", the node b is fixed to high, but since the input of the three-input NAND circuit 35 includes the enable signal EN, the node c is fixed to high. Therefore, the P-type transistor P1 is off. Therefore, no short circuit occurs between the power supply VDD and the low drive element of the output circuit on the transmitting side, and the waveform of the input signal is not blunted. Therefore, the same effect as the input circuit 4 of FIG. 7 can be obtained.

[0059] 10, only one stage of P-type transistors is arranged between the power supply VDD and node a. This configuration is effective when it is desired to avoid a multi-stage transistor configuration from the viewpoint of area efficiency.

[0060] This embodiment is also applicable when the logic of the enable signal EN is reversed, that is, when the enable signal EN is "0", the input signal is passed (enabled) and when the enable signal EN is "1", the input signal is not passed (disabled). In this case, for example, in the configuration of FIG. 7, the enable signal EN is applied to the gate of the P-type transistor P2, and an inverted signal of the enable signal EN is applied to the two-input NAND circuit 13.

[0061] Fifth embodiment Fig. 11 shows a circuit configuration of an input circuit according to a fifth embodiment. The input circuit 5 shown in Fig. 11 includes an N-type transistor N2 provided between a power supply VDD and a node a, in addition to the configuration of the input circuit 1 shown in Fig. 1 according to the first embodiment. That is, the N-type transistor N2 is provided in parallel with the P-type transistor P1 of the pull-up circuit 21. The drain of the N-type transistor N2 is connected to the power supply VDD, the source is connected to the node a, and the gate is connected to the input terminal PAD.

[0062] The operation of the input circuit 5 in Fig. 11 is the same as that of the input circuit 1 in Fig. 1. However, the N-type transistor N2 turns on when a rising signal with a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal transitions from low to high). This helps boost the voltage at node a.

[0063] Fig. 12 shows another example of the circuit configuration of the input circuit according to the fifth embodiment. The input circuit 5A shown in Fig. 12 includes an N-type transistor N2 provided between the power supply VDD and the node a, in addition to the configuration of the input circuit 4A shown in Fig. 9 according to the fourth embodiment. That is, the N-type transistor N2 is provided in parallel with the P-type transistors P1, P2, and P3 of the pull-up circuit 24A. The drain of the N-type transistor N2 is connected to the power supply VDD, the source is connected to the node a, and the gate is connected to the input terminal PAD.

[0064] The operation of the input circuit 5A in Fig. 12 is the same as that of the input circuit 4A in Fig. 9. However, the N-type transistor N2 turns on when a rising signal with a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal transitions from low to high). This helps boost the voltage at the node a.

[0065] In addition, in the configurations of the other input circuits shown in the first to fourth embodiments described above, an N-type transistor N2 may be added, similarly to the configurations of FIGS.

[0066] Sixth embodiment In response to the recent need for power saving, systems that turn the power supply of semiconductor integrated circuits on and off as needed have become common. However, the input circuit 1 shown in Figure 1 cannot tolerate receiving a high-voltage signal at the input terminal PAD when the power supply is off, i.e., when VDD is 0V. In other words, if the drain-gate withstand voltage of the N-type transistor N1 is 1.8V, when the input terminal PAD receives an input signal of 3.3V when VDD is 0V, the drain-gate voltage of the N-type transistor N1 will be 3.3V, exceeding the withstand voltage.

[0067] Therefore, in this embodiment, an input circuit is provided that can turn off the power, that is, set VDD to 0 V, regardless of the signal received by the input terminal PAD.

[0068] Fig. 13 shows a circuit configuration of an input circuit according to a sixth embodiment. The input circuit 6 shown in Fig. 13 has a basic configuration similar to that of the input circuit 1 shown in Fig. 1. However, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 26 are connected to a node d, not to a power supply VDD. The node d is connected to an input terminal PAD via a voltage conversion circuit 61. When the power supply VDD is on, the voltage conversion circuit 61 outputs the power supply voltage VDD to the node d, and when the power supply VDD is off, the voltage conversion circuit 61 divides the voltage of the input terminal PAD and outputs it to the node d.

[0069] FIG. 14(a) shows an example of the circuit configuration of the voltage conversion circuit 61, and FIG. 14(b) shows the relationship between the input and output voltages of the voltage conversion circuit 61. In the voltage conversion circuit 61, when the power is on (VDD=1.8V), the N-type transistor N61 is turned on, so that the gate voltage of the P-type transistor P63 becomes 0V, and the P-type transistor P63 is turned on. As a result, the voltage VDD is output to the node d regardless of the signal received by the input terminal PAD. On the other hand, when the power is off (VDD=0V), assume that a high (3.3V) is applied to the input terminal PAD. The P-type transistors P61 and P62 are both turned on because the gate voltage is 0V. Therefore, the voltage divided by the resistor R connected in series, that is, 3.3 / 2V, is output to the node d via the transistors P61 and P62. Note that the configuration of the voltage conversion circuit 61 shown in FIG. 14 is merely an example, and is not limited to this.

[0070] The input circuit 6 in Fig. 13 operates as follows: When the power is on (VDD=1.8V), the power supply voltage VDD is output to the node d by the operation of the voltage conversion circuit 61. Therefore, the input circuit 6 in Fig. 13 operates in the same manner as the input circuit 1 in Fig. 1.

[0071] On the other hand, when the power is off (VDD=0V), if a high voltage (3.3V) is applied to the input terminal PAD, the voltage at node d becomes 3.3 / 2V due to the operation of the voltage conversion circuit 61. At this time, the N-type transistor N1 turns on. The voltage at node a drops from the 3.3V voltage at the input terminal PAD due to the pinch-off characteristics of the N-type transistor N1, and does not exceed the voltage at node d. Also, with VDD=0V, the voltage at node c becomes approximately 0V, the P-type transistor P1 turns on, and nodes a and d become conductive. As a result, the voltage at node a becomes 3.3 / 2V.

[0072] In this way, since the gate of N-type transistor N1 is connected to node d and not to the power supply VDD, even if a high signal is applied to the input terminal PAD when the power supply is off, the drain-gate voltage of N-type transistor N1 will not exceed its withstand voltage.

[0073] In addition, since the drain of the P-type transistor P1 is connected to node d, not VDD, no unnecessary current flows in from the input terminal PAD even if a high is applied to the input terminal PAD when the power is off. In other words, if the drain of the P-type transistor P1 is connected to the power supply VDD, and a high is applied to the input terminal PAD when the power is off, a current flows in from the input terminal PAD through the path N-type transistor N1 → node a → P-type transistor P1 → VDD. In this embodiment, this problem is avoided.

[0074] Furthermore, since a stepped-down voltage is applied to node a, the voltage will not exceed the withstand voltage of the transistors located beyond it.

[0075] Therefore, according to this embodiment, the power supply can be turned off in the input circuit 6 without causing degradation or destruction of the transistors and without causing unnecessary inflow current.

[0076] Although the present embodiment has been described above as being applied to the first embodiment, it is also applicable to the other embodiments described above. That is, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 22 or the like may be connected to a node d connected to the input terminal PAD via a voltage conversion circuit 61. In the input circuit 5 shown in FIG. 11 and the input circuit 5A shown in FIG. 12, the drain of the N-type transistor N2 may also be connected to the node d.

[0077] Seventh embodiment Fig. 15 shows the circuit configuration of an input circuit according to the seventh embodiment. The input circuit 7 shown in Fig. 15 has a basic configuration similar to that of the input circuit 6 shown in Fig. 13. However, in the pull-up circuit 27, a P-type transistor P5 and a transfer gate switch SW consisting of a P-type transistor and an N-type transistor connected in parallel are added.

[0078] The P-type transistor P5 is connected between a node c serving as the gate of the P-type transistor P1 and a node a serving as the source. The gate of the P-type transistor P5 is connected to a power supply VDD. The transfer gate switch SW is connected between the node c and the output node of the NAND gate 31. The gate of the N-type transistor constituting the transfer gate switch SW is connected to the power supply VDD, and the gate of the P-type transistor constituting the transfer gate switch SW is connected to the node a.

[0079] The input circuit 7 shown in Fig. 15 operates as follows. When the power is on (VDD = 1.8V), the P-type transistor P5 is turned off, and the transfer gate switch SW is turned on because its N-type transistor is turned on. Therefore, the input circuit 7 in Fig. 15 operates in the same way as the input circuit 6 in Fig. 13.

[0080] On the other hand, when the power is off (VDD=0V), if a high voltage (3.3V) is applied to the input terminal PAD, the P-type transistor P5 turns on, which connects nodes a and c, making the voltages of nodes a and c the same as node d. This turns the P-type transistor P1 off. Also, the transfer gate switch SW turns off the N-type transistor because the gate voltage is 0V, and turns off the P-type transistor because the voltages of its drain (node ​​c) and gate (node ​​a) are equal, so it is also off. As a result, the node c is cut off from the output node of the NAND gate 31, preventing the generation of unnecessary inflow current from the P-type transistor P5 via the NAND gate 31.

[0081] Therefore, according to this embodiment, the power supply can be turned off in the input circuit 7 without causing degradation or destruction of the transistors and without causing unnecessary inflow current.

[0082] Although the present embodiment has been described above as being applied to the circuit configuration of the first embodiment, it can also be applied to the circuit configurations of the other embodiments described above. That is, in the pull-up circuit, a P-type transistor P5 is connected between the gate of any one of the P-type transistors P1, P2, and P3 and the node a, and a transfer gate switch SW is provided between the gate and the node of the previous stage circuit that sends a signal to the P-type transistor P5.

[0083] 3, a P-type transistor P5 may be connected between the gate of the P-type transistor P1 and the node a, and a transfer gate switch SW may be provided between the gate of the P-type transistor P1 and the output node of the inverter 32. Alternatively, a P-type transistor P5 may be connected between the gate of the P-type transistor P2 and the node a, and a transfer gate switch SW may be provided between the gate of the P-type transistor P2 and the input buffer 12.

[0084] The present disclosure is not limited to the configurations shown in the above-described embodiments, and many modifications are possible within the technical concept of the present disclosure by a person having ordinary skill in the art. Furthermore, the components in the multiple embodiments may be combined in any manner without departing from the spirit of the present disclosure. [Industrial Applicability]

[0085] The present disclosure can reduce the delay time in the input buffer circuit in the input circuit and suppress errors that occur in the pulse width of the output signal, which is effective in increasing the speed and improving the performance of LSIs, for example. [Explanation of symbols]

[0086] 1,2,2A,3,4,4A,4B,5,5A,6,7 Input circuit 11 Inverter (input buffer circuit) 12 Buffer (input buffer circuit) 13 2-input NAND circuit (input buffer circuit) 14 2-input AND circuit (input buffer circuit) 21, 22, 22A, 23, 24, 24A, 24B, 26, 27 Pull-up circuit 31 NAND circuit 32, 33, 34 Inverter 61 Voltage conversion circuit N1, N2 N-type transistor P1, P2, P5 P-type transistors PAD input terminal SW Transfer gate switch a. First node b. Second node d. Third node VDD Power supply, power supply voltage

Claims

1. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply; a pull-up circuit provided between the first node and the power supply; The pull-up circuit includes: When the input signal transitions from low to high, the power supply and the first node are electrically connected for a predetermined period, and when the input signal transitions from high to low, the power supply and the first node are not electrically connected; and a NAND circuit having a first input that is a signal at the first node, and a second input that is a signal at the second node when the input buffer circuit is an inverter, and having a second input that is an inverted signal of the signal at the second node when the input buffer circuit is a buffer that does not invert the logic of a signal; a P-type transistor having a source connected to the power supply, a drain connected to the first node, and a gate receiving an output of the NAND circuit; 1. An input circuit comprising:

2. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply; a pull-up circuit provided between the first node and the power supply; The pull-up circuit includes: When the input signal transitions from low to high, the power supply and the first node are electrically connected for a predetermined period, and when the input signal transitions from high to low, the power supply and the first node are not electrically connected; and a first P-type transistor and a second P-type transistor connected in series between the power supply and the first node; the first P-type transistor receives at its gate an inverted signal of the signal at the first node; The second P-type transistor receives at its gate the signal at the second node when the input buffer circuit is a buffer that does not invert the logic of a signal, and receives at its gate an inverted signal of the signal at the second node when the input buffer circuit is an inverter.

1. An input circuit comprising:

3. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply; a pull-up circuit provided between the first node and the power supply; The pull-up circuit includes: When the input signal transitions from low to high, the power supply and the first node are electrically connected for a predetermined period, and when the input signal transitions from high to low, the power supply and the first node are not electrically connected; and a first P-type transistor and a second P-type transistor connected in series between the power supply and the first node; the first P-type transistor receives at its gate an inverted signal of the signal at the first node; The second P-type transistor receives at its gate an inverted signal of the signal received at the gate of the first P-type transistor.

1. An input circuit comprising:

4. An input circuit according to any one of claims 1 to 3, the input buffer circuit receives an enable signal, and when the enable signal is at a first logic level, passes a signal at the first node, but when the enable signal is at a second logic level, does not pass the signal at the first node; The pull-up circuit is configured to prevent electrical continuity between the power supply and the first node when the enable signal is at the second logic level.

1. An input circuit comprising:

5. An input circuit according to any one of claims 1 to 3, a second N-type transistor having a drain connected to the power supply, a source connected to the first node, and a gate connected to the input terminal; 1. An input circuit comprising:

6. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply; a pull-up circuit provided between the first node and the power supply; The pull-up circuit includes: a first P-type transistor and a second P-type transistor connected in series between the power supply and the first node; the first P-type transistor receives at its gate an inverted signal of the signal at the first node; The second P-type transistor receives at its gate the signal at the second node when the input buffer circuit is a buffer that does not invert the logic of a signal, and receives at its gate an inverted signal of the signal at the second node when the input buffer circuit is an inverter.

1. An input circuit comprising:

7. In the input circuit according to claim 6, the input buffer circuit receives an enable signal, and when the enable signal is at a first logic level, passes a signal at the first node, but when the enable signal is at a second logic level, does not pass the signal at the first node; The pull-up circuit includes: a third P-type transistor connected in series with the first and second P-type transistors; The third P-type transistor receives a low signal at its gate when the enable signal is at the first logic level, and receives a high signal at its gate when the enable signal is at the second logic level.

1. An input circuit comprising:

8. In the input circuit according to claim 6, a second N-type transistor having a drain connected to the power supply, a source connected to the first node, and a gate connected to the input terminal; 1. An input circuit comprising:

9. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a third node; a pull-up circuit provided between the first node and the third node; a voltage conversion circuit configured to output a voltage of the power supply to the third node when the power supply is on, and to divide a voltage of the input terminal and output the divided voltage to the third node when the power supply is off, The pull-up circuit includes: When the power supply is on, the third node and the first node are electrically connected for a predetermined period when the input signal transitions from low to high, and the third node and the first node are not electrically connected when the input signal transitions from high to low; and a NAND circuit having a first input that is a signal at the first node, and a second input that is a signal at the second node when the input buffer circuit is an inverter, and having a second input that is an inverted signal of the signal at the second node when the input buffer circuit is a buffer that does not invert the logic of a signal; a first P-type transistor having a source connected to the third node, a drain connected to the first node, and a gate receiving an output of the NAND circuit; a second P-type transistor having a source connected to the gate of the first P-type transistor, a drain connected to the first node, and a gate connected to the power supply; a transfer gate switch including a P-type transistor and an N-type transistor connected in parallel, the transfer gate switch being provided between a gate of the first P-type transistor and an output node of the NAND circuit, the gate of the P-type transistor being connected to the first node, and the gate of the N-type transistor being connected to the power supply.

1. An input circuit comprising:

10. An input circuit for receiving an input signal at an input terminal, an input buffer circuit having a first node as an input and a second node as an output; an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a third node; a pull-up circuit provided between the first node and the third node, a voltage conversion circuit configured to output a voltage of the power supply to the third node when the power supply is on, and to divide a voltage of the input terminal and output the divided voltage to the third node when the power supply is off, The pull-up circuit includes: a first and a second P-type transistor connected in series between the third node and the first node; the first P-type transistor receives at its gate an inverted signal of the signal at the first node; The second P-type transistor receives at its gate the signal at the second node when the input buffer circuit is a buffer that does not invert the logic of a signal, and receives at its gate an inverted signal of the signal at the second node when the input buffer circuit is an inverter.

1. An input circuit comprising:

11. The input circuit of claim 10, The pull-up circuit includes: a third P-type transistor having a source connected to the gate of the first or second P-type transistor, a drain connected to the first node, and a gate connected to the power supply; a transfer gate switch including a P-type transistor and an N-type transistor connected in parallel, the transfer gate switch being provided between a gate of the first or second P-type transistor and a node that sends a signal to the gate, the gate of the P-type transistor being connected to the first node, and the gate of the N-type transistor being connected to the power supply.

1. An input circuit comprising:

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