Data receiving circuit, data receiving system and storage device

Abstract

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, the data receiving circuit including a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal, perform a first comparison on the data signal and the first reference signal, output a first signal pair, and perform a second comparison on the data signal and the second reference signal, output a second signal pair, where the level value of the first reference signal and the level value of the second reference signal are different, and a second amplification module configured to selectively receive the first signal pair or the second signal pair as an input signal pair based on a feedback signal, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal and a second output signal, the feedback signal being obtained based on previously received data. The embodiments of the present disclosure are at least advantageous for improving the receiving performance of the data receiving circuit.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on June 23, 2022, bearing application number 202210726620.8 and entitled "Data Receiving Circuit, Data Receiving System, and Storage Device", the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. [Background technology]

[0003] In memory applications, as the signal transmission speed becomes faster and faster, the impact of channel loss on signal quality becomes greater, and inter-code interference is more likely to occur, and the difference in level between the data signal received by the data receiving circuit in the memory and the reference signal affects the judgment of the data receiving circuit for the data signal, thereby affecting the accuracy of the signal output from the data receiving circuit. At present, an equalization circuit is usually used to compensate the channel, and a continuous time linear equalizer (CTLE) or a decision feedback equalizer (DFE) can be selected as the equalization circuit.

[0004] However, currently adopted equalization circuits have limited adjustment capabilities for data signals, and there is a need to improve the accuracy of the signal output from the data receiving circuit, and therefore there is a need to improve the receiving performance of the data receiving circuit. Summary of the Invention

[0005] SUMMARY OF THE DISCLOSURE The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device that are advantageous in improving at least the receiving performance of the data receiving circuit.

[0006] According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a data receiving circuit, the data receiving circuit including: a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal, perform a first comparison on the data signal and the first reference signal, and output a first signal pair as a result of the first comparison, and perform a second comparison on the data signal and the second reference signal, and output a second signal pair as a result of the second comparison, where a level value of the first reference signal and a level value of the second reference signal are different, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; and a second amplification module configured to selectively receive the first signal pair or the second signal pair as an input signal pair based on a feedback signal, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process, where the feedback signal is obtained based on previously received data.

[0007] In some embodiments, the first amplification module includes a first comparison circuit and a second comparison circuit, the first comparison circuit having a first node and a second node, configured to receive the data signal and the first reference signal, perform the first comparison, and output the first signal and the second signal via the first node and the second node, respectively; and the second comparison circuit having a third node and a fourth node, configured to receive the data signal and the second reference signal, perform the second comparison, and output the third signal and the fourth signal via the third node and the fourth node, respectively.

[0008] In some embodiments, the first comparison circuit includes a first current source and a first comparison unit, the first current source is connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to a sampling clock signal; the first comparison unit is connected to the first node, the second node, and the fifth node and configured to receive the data signal and the first reference signal, perform the first comparison when the first current source supplies a current to the fifth node, and output the first signal and the second signal; the second comparison circuit includes a second current source and a second comparison unit, the second current source is connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the sampling clock signal; and the second comparison unit is connected to the third node, the fourth node, and the sixth node and configured to receive the data signal and the second reference signal, perform the second comparison when the second current source supplies a current to the sixth node, and output the third signal and the fourth signal.

[0009] In some embodiments, a circuit configuration of the first current source is the same as a circuit configuration of the second current source, and a circuit configuration of the first comparison unit is the same as a circuit configuration of the second comparison unit.

[0010] In some embodiments, the first current source includes a first PMOS transistor connected between the power supply node and the fifth node, a gate of the first PMOS transistor receiving the sampling clock signal, and the second current source includes a second PMOS transistor connected between the power supply node and a sixth node, a gate of the second PMOS transistor receiving the sampling clock signal.

[0011] In some embodiments, the first comparison unit includes a third PMOS transistor and a fourth PMOS transistor, the third PMOS transistor is connected between the first node and the fifth node, a gate of the third PMOS transistor receives the data signal, the fourth PMOS transistor is connected between the second node and the fifth node, a gate of the fourth PMOS transistor receives the first reference signal, the second comparison unit includes a fifth PMOS transistor and a sixth PMOS transistor, the fifth PMOS transistor is connected between the third node and the sixth node, a gate of the fifth PMOS transistor receives the data signal, and the sixth PMOS transistor is connected between the fourth node and the sixth node, a gate of the sixth PMOS transistor receives the second reference signal.

[0012] In some embodiments, the first amplification module further includes a first reset unit and a second reset unit, the first reset unit is connected to the first node and the second node and configured to reset the first node and the second node, and the second reset unit is connected to the third node and the fourth node and configured to reset the third node and the fourth node.

[0013] In some embodiments, the first reset unit includes a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected between the first node and a ground terminal, and a gate of the first NMOS transistor receives a first reset signal, the second NMOS transistor is connected between the second node and the ground terminal, and a gate of the second NMOS transistor receives the first reset signal, the second reset unit includes a third NMOS transistor and a fourth NMOS transistor, the third NMOS transistor is connected between the third node and the ground terminal, and a gate of the third NMOS transistor receives the first reset signal, and the fourth NMOS transistor is connected between the fourth node and the ground terminal, and a gate of the fourth NMOS transistor receives the first reset signal.

[0014] In some embodiments, the second amplification module includes a first input unit, a second input unit, and a latch unit, wherein the first input unit is connected to a seventh node and an eighth node and configured to be conductive in response to the feedback signal, thereby receiving the first signal pair and comparing the first signal pair, and providing signals to the seventh node and the eighth node, respectively; the second input unit is connected to the seventh node and the eighth node and configured to be conductive in response to the feedback signal, thereby receiving the second signal pair and comparing the second signal pair, and providing signals to the seventh node and the eighth node, respectively; wherein the first input unit and the second input unit are alternatively conductive based on the feedback signal; and the latch unit is connected to the seventh node and the eighth node and configured to amplify and latch the signal at the seventh node and the signal at the eighth node, and output the first output signal and the second output signal via a first output node and a second output node, respectively.

[0015] In some embodiments, the feedback signal includes differential first and second feedback signals, the first input unit conducting in response to the first feedback signal and the second input unit conducting in response to the second feedback signal.

[0016] In some embodiments, the first input unit includes a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, and an eighth NMOS transistor, a drain of the fifth NMOS transistor is connected to the seventh node, a source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a ground terminal, a gate of the fifth NMOS transistor receives one of the first signal or the first feedback signal, a gate of the sixth NMOS transistor receives the other of the first signal or the first feedback signal, a drain of the seventh NMOS transistor is connected to the eighth node, a source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, a source of the eighth NMOS transistor is connected to the ground terminal, a gate of the seventh NMOS transistor receives one of the second signal or the first feedback signal, and a gate of the eighth NMOS transistor receives the other of the second signal or the first feedback signal.

[0017] In some embodiments, the second input unit includes a ninth NMOS transistor and a tenth NMOS transistor, and an eleventh NMOS transistor and a twelfth NMOS transistor, a drain of the ninth NMOS transistor is connected to the seventh node, a source of the ninth NMOS transistor is connected to a drain of the tenth NMOS transistor, a source of the tenth NMOS transistor is connected to a ground terminal, a gate of the ninth NMOS transistor receives one of the third signal or the second feedback signal, a gate of the tenth NMOS transistor receives the other of the third signal or the second feedback signal, a drain of the eleventh NMOS transistor is connected to the eighth node, a source of the eleventh NMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to the ground terminal, a gate of the eleventh NMOS transistor receives one of the fourth signal or the second feedback signal, and a gate of the twelfth NMOS transistor receives the other of the fourth signal or the second feedback signal.

[0018] In some embodiments, the latch unit includes a thirteenth NMOS transistor and a seventh PMOS transistor, and a fourteenth NMOS transistor and an eighth PMOS transistor, a gate of the thirteenth NMOS transistor and a gate of the seventh PMOS transistor are all connected to the second output node, a source of the thirteenth NMOS transistor is connected to the seventh node, a drain of the thirteenth NMOS transistor and a drain of the seventh PMOS transistor are all connected to the first output node, a source of the seventh PMOS transistor is connected to a power supply node, a gate of the fourteenth NMOS transistor and a gate of the eighth PMOS transistor are all connected to the first output node, a source of the fourteenth NMOS transistor is connected to the eighth node, a drain of the fourteenth NMOS transistor and a drain of the eighth PMOS transistor are all connected to the second output node, and a source of the eighth PMOS transistor is connected to the power supply node.

[0019] In some embodiments, the second amplification module further includes a third reset unit coupled between a power supply node and the output terminal of the latch unit and configured to reset the output terminal of the latch unit.

[0020] In some embodiments, the output terminal of the latch unit includes a first output node and a second output node, the third reset unit includes a ninth PMOS transistor and a tenth PMOS transistor, the ninth PMOS transistor is connected between the first output node and a power supply node, a gate of the ninth PMOS transistor receives a second reset signal, and the tenth PMOS transistor is connected between the second output node and the power supply node, a gate of the tenth PMOS transistor receives the second reset signal.

[0021] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a data receiving system, the data receiving system including a plurality of cascaded data transmission circuits, each of the data transmission circuits including a data receiving circuit as described above and a latch circuit connected to the data receiving circuit, and an output signal of the data transmission circuit of a previous stage is used as the feedback signal of the data transmission circuit of a next stage, and an output signal of the data transmission circuit of a final stage is used as the feedback signal of the data transmission circuit of a first stage.

[0022] In some embodiments, the data receiving circuit receives data in response to a sampling clock signal, and the data receiving system includes four of the data receiving circuits cascaded together, and the phase difference between the sampling clock signals of the data receiving circuits of adjacent stages is 90°.

[0023] In some embodiments, the feedback signal of the data transmission circuit of the next stage is the output signal of the data receiving circuit of the previous stage or the output signal of the latch circuit of the previous stage, and the feedback signal of the data transmission circuit of the first stage is the output signal of the data receiving circuit of the final stage or the output signal of the latch circuit of the final stage.

[0024] According to some embodiments of the present disclosure, yet another aspect of the embodiments of the present disclosure further provides a storage device, the storage device including a plurality of data ports and a plurality of data receiving systems as described above, each of the data receiving systems corresponding to one of the data ports.

[0025] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0026] The first amplification module utilizes the first reference signal and the second reference signal to perform a first comparison and a second comparison on the data signal, respectively, to obtain a first signal pair and a second signal pair, in which the level value of the first reference signal and the level value of the second reference signal are different, and for data signals with different level values, a large difference in level value between the data signal and one of the first reference signal or the second reference signal can be satisfied, which is advantageous to ensure that the difference in level value of at least one of the first signal pair and the second signal pair is large; in this way, when inter-code interference exists in the data signal received by the data receiving circuit, it is advantageous for the second amplification module to receive the one of the first signal pair and the second signal pair with a larger difference in level value based on the feedback signal. It can be understood that based on the difference between the level values ​​of the data signal and the first reference signal and the difference between the level values ​​of the data signal and the second reference signal, the second amplification module can select to receive the one of the first signal pair and the second signal pair with the larger difference in level value based on the feedback signal, so as to ensure that the second amplification module receives a differential signal pair with a larger difference in signal level value, which is advantageous to improve the accuracy of the first output signal and the second output signal output from the second amplification module, that is, the first reference signal and the second reference signal can be used to improve the adjustment ability of the data receiving circuit to the received data signal, and reduce the impact of inter-code interference of the received data signal on the data receiving circuit. [Brief description of the drawings]

[0027] [Figure 1] FIG. 2 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 1 is a functional block diagram of a data receiving system according to an embodiment of the present disclosure. [Diagram 3] 11A to 11C are other two functional block diagrams of a data receiving circuit according to an embodiment of the present disclosure. [Figure 4] 11A to 11C are other two functional block diagrams of a data receiving circuit according to an embodiment of the present disclosure. [Diagram 5]2 is a schematic diagram of a circuit configuration of a first amplification module in a data receiving circuit according to an embodiment of the present disclosure. [Figure 6] 1 is a schematic diagram of a circuit configuration of a second amplification module in a data receiving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] One or more embodiments are illustrated by their corresponding drawings, which are not intended to limit the embodiments, and elements with the same reference numbers in the drawings are shown as similar elements, and unless otherwise specified, the drawings do not constitute a limit on scale, in order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the above briefly introduces the drawings used in the embodiments. Obviously, the drawings described above are only some embodiments of the present disclosure, and based on these drawings, those skilled in the art can also obtain other related drawings without creative efforts.

[0029] As a result of research, it has been found that when the difference between the level value of the data signal received by the data receiving circuit and the level value of the reference signal is small, the data receiving circuit is likely to make an erroneous judgment about the data signal; for example, a data signal that should be high level will be judged to be low level, resulting in an erroneous output signal from the data receiving circuit.

[0030] The embodiments of the present disclosure provide a data receiving circuit, a data receiving system and a storage device, in which the data receiving circuit uses a first reference signal and a second reference signal to perform a first comparison and a second comparison on the data signal respectively to obtain a first signal pair and a second signal pair, in which the level value of the first reference signal and the level value of the second reference signal are different, and for data signals with different level values, a large difference in level value between the data signal and one of the first reference signal or the second reference signal can be satisfied; therefore, when there is inter-code interference in the data signal received by the data receiving circuit, then a second amplification module performs a first comparison and a second comparison on the first signal pair and the second signal pair based on a feedback signal. It is advantageous to receive the one with a larger difference in level values ​​between the first and second signal pairs, thereby realizing the purpose of using the first and second reference signals to improve the adjustment ability of the data receiving circuit to the received data signal and reducing the impact of inter-code interference of the received data signal on the data receiving circuit, and then the second amplifying module selects to receive the one of the first and second signal pairs with a larger difference in level values ​​based on the feedback signal, which is advantageous to ensure that the second amplifying module receives a differential signal pair with a large difference in signal level values, thereby improving the accuracy of the first and second output signals output from the second amplifying module. Therefore, the cooperation of the first and second amplifying modules is advantageous to improve the receiving performance of the data receiving circuit.

[0031] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. However, those skilled in the art can understand that in each embodiment of the present invention, many technical details are shown to help the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on each embodiment below, the technical solution claimed in the present disclosure can be implemented.

[0032] An embodiment of the present disclosure provides a data receiving circuit, and the data receiving circuit provided by the embodiment of the present disclosure will be described in detail below with reference to the drawings. Fig. 1 is a functional block diagram of the data receiving circuit according to the embodiment of the present disclosure, Figs. 3 and 4 are two other functional block diagrams of the data receiving circuit according to the embodiment of the present disclosure, Fig. 5 is a schematic diagram of a circuit configuration of a first amplification module in the data receiving circuit according to the embodiment of the present disclosure, and Fig. 6 is a schematic diagram of a circuit configuration of a second amplification module in the data receiving circuit according to the embodiment of the present disclosure.

[0033] 1 and 3, the data receiving circuit 100 includes a first amplifying module 101 configured to receive a data signal DQ, a first reference signal VR+, and a second reference signal VR-, perform a first comparison on the data signal DQ and the first reference signal VR+, and output a first signal pair as a result of the first comparison, and perform a second comparison on the data signal DQ and the second reference signal VR-, and output a second signal pair as a result of the second comparison, where the level value of the first reference signal VR+ and the level value of the second reference signal VR- are different, and the first signal pair is a first signal pair. a first amplifying module 101 configured to selectively receive the first signal pair or the second signal pair as an input signal pair based on a feedback signal Fb, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal Vout and a second output signal VoutN as a result of the amplification process, where the feedback signal Fb is obtained based on previously received data.

[0034] It can be understood that the level values ​​of the first reference signal VR+ and the second reference signal VR- are different, and for data signals DQ with different level values, a large difference in level values ​​between the data signal and one of the first reference signal VR+ or the second reference signal VR- can be satisfied, and it is advantageous for the first amplification module 101 to amplify the difference in level values; when the difference in level values ​​of at least one of the first and second signal pairs output from the first amplification module 101 becomes large and there is inter-code interference in the data signal DQ received by the data receiving circuit 100, then it is advantageous for the second amplification module 102 to receive the signal pair with a large difference in level values ​​among the first and second signal pairs based on the feedback signal Fb. It can be understood that the data receiving circuit 100 uses the first reference signal VR+ and the second reference signal VR- to improve the adjustment ability of the data receiving circuit 100 to the received data signal DQ, i.e., when inter-code interference exists in the data signal DQ received by the data receiving circuit 100, the second amplifying module 102 will receive a signal pair that is more suitable for the processing of the data signal DQ in the first amplifying module 101 based on the feedback signal Fb, and the signal pair that is more suitable for the data signal DQ is the signal pair between the first signal pair and the second signal pair that has a larger difference in level value, thereby achieving the purpose of reducing the impact of inter-code interference of the received data signal DQ on the data receiving circuit 100.

[0035] Furthermore, since the second amplification module 102 selects to receive the one of the first and second signal pairs with a larger difference in level value based on the feedback signal Fb, it is advantageous to ensure that the second amplification module 102 receives a differential signal pair with a large difference in signal level value, thereby being advantageous to improve the accuracy of the first output signal Vout and the second output signal VoutN output from the second amplification module 102. Therefore, the cooperation of the first amplification module 101 and the second amplification module 102 is advantageous to improve the reception performance of the data receiving circuit 100.

[0036] In some embodiments, when the level value of the first reference signal VR+ is higher than the level value of the second reference signal VR-, the data signal DQ is at a low level, and there is inter-code interference in the data signal DQ received by the data receiving circuit 100, the second amplifying module 102 receives the first signal pair based on the feedback signal Fb, and at this time, the difference in the level values ​​between the data signal DQ and the first reference signal VR+ is greater than the difference in the level values ​​between the data signal DQ and the second reference signal VR-, i.e., the difference in the level values ​​of the signals in the first signal pair is greater than the difference in the level values ​​of the signals in the second signal pair. Therefore, the second amplifying module 102 receiving the first signal pair is advantageous to output the first output signal Vout and the second output signal VoutN that meet the requirements, i.e., to ensure the accuracy of the first output signal Vout and the second output signal VoutN, and thereby to reduce the impact of the inter-code interference of the received data signal DQ on the data receiving circuit 100.

[0037] In addition, when the data signal DQ is at a high level and there is inter-code interference in the data signal DQ received by the data receiving circuit 100, the second amplifying module 102 receives the second signal pair based on the feedback signal Fb, and at this time, the difference in level value between the data signal DQ and the first reference signal VR+ is smaller than the difference in level value between the data signal DQ and the second reference signal VR-, that is, the difference in level value of the signals in the first signal pair is smaller than the difference in level value of the signals in the second signal pair. Therefore, the second amplifying module 102 receiving the second signal pair is advantageous to output the first output signal Vout and the second output signal VoutN that meet the requirements, that is, to ensure the accuracy of the first output signal Vout and the second output signal VoutN, and thereby to reduce the impact of the inter-code interference of the received data signal DQ on the data receiving circuit 100.

[0038] In this way, through cooperation between the first amplification module 101 and the second amplification module 102, when inter-code interference is present in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 receives a signal pair that is more suitable for the processing of the data signal DQ in the first amplification module 101 based on the feedback signal Fb, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output from the second amplification module 102, and thereby reducing the impact of inter-code interference in the received data signal DQ on the data receiving circuit 100.

[0039] In the following, the first amplifying module 101 and the second amplifying module 102 will be described in detail with reference to FIG. 3 and FIG.

[0040] In some embodiments, referring to Figures 3 and 4, the first amplification module 101 includes a first comparison circuit 111 and a second comparison circuit 121, the first comparison circuit 111 having a first node net1 and a second node net2, and configured to receive a data signal DQ and a first reference signal VR+, perform a first comparison, and output a first signal Sn+ and a second signal Sp+ via the first node net1 and the second node net2, respectively; the second comparison circuit 121 having a third node net3 and a fourth node net4, and configured to receive a data signal DQ and a second reference signal VR-, perform a second comparison, and output a third signal Sn- and a fourth signal Sp- via the third node net3 and the fourth node net4, respectively.

[0041] Here, the first comparison circuit 111 performs an amplification process on the voltage difference between the data signal DQ and the first reference signal VR+ to output the first signal Sn+ and the second signal Sp+, i.e., the first signal Sn+ and the second signal Sp+ are influenced by the data signal DQ and the first reference signal VR+, and the second comparison circuit 121 performs an amplification process on the voltage difference between the data signal DQ and the second reference signal VR- to output the third signal Sn- and the fourth signal Sp-, i.e., the third signal Sn- and the fourth signal Sp- are influenced by the data signal DQ and the second reference signal VR-. Therefore, thereafter, when the second amplification module 102 receives a first signal pair based on the feedback signal Fb to output the first output signal Vout and the second output signal VoutN, the first output signal Vout and the second output signal VoutN are influenced by the first signal Sn+ and the second signal Sp+, and when the second amplification module 102 receives a second signal pair based on the feedback signal Fb to output the first output signal Vout and the second output signal VoutN, the first output signal Vout and the second output signal VoutN are influenced by the third signal Sn- and the fourth signal Sp-.

[0042] In this way, whether the data signal DQ received by the first amplification module 101 is at a high level or a low level, one of the difference in level values ​​between the first signal Sn+ and the second signal Sp+ and the difference in level values ​​between the third signal Sn- and the fourth signal Sp- will be larger, and the second amplification module 102 can selectively select the first signal pair and the second signal pair with a larger voltage difference based on the feedback signal Fb, i.e., the data receiving circuit 100 uses the first reference signal VR+ and the second reference signal VR- to improve the adjustment ability of the data receiving circuit 100 for the received data signal DQ, i.e., when inter-code interference exists in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 will receive a signal pair that is more suitable for the processing of the data signal DQ in the first amplification module 101 based on the feedback signal Fb, and further adjust the first output signal Vout and the second output signal VoutN affected by the signal pair.

[0043] In some embodiments, still referring to FIG. 3 and FIG. 4, the first comparison circuit 111 may include a first current source 1111 and a first comparison unit 1112, the first current source 1111 being connected between a power supply node Vcc (see FIG. 5) and a fifth node net5 and configured to supply a current to the fifth node net5 in response to a sampling clock signal clkN, the first comparison unit 1112 being connected to the first node net1, the second node net2, and the fifth node net5, receiving a data signal DQ and a first reference signal VR+, performing a first comparison when the first current source 1111 supplies a current to the fifth node net5, and comparing the first signal Sn+ and the second signal Sn+ to the fifth node net5. The second comparison circuit 121 may include a second current source 1211 and a second comparison unit 1212, wherein the second current source 1211 is connected between a power supply node Vcc and a sixth node net6 and configured to supply a current to the sixth node net6 in response to a sampling clock signal clkN, and the second comparison unit 1212 is connected to the third node net3, the fourth node net4, and the sixth node net6 and configured to receive a data signal DQ and a second reference signal VR-, perform a second comparison when the second current source 1211 supplies a current to the sixth node net6, and output a third signal Sn- and a fourth signal Sp-.

[0044] It can be understood that the first comparison unit 1112 can control the difference between the current supplied to the first node net1 and the current supplied to the second node net2 based on the voltage difference between the data signal DQ and the first reference signal VR+, and output the first signal Sn+ and the second signal Sp+, and the second comparison unit 1212 can control the difference between the current supplied to the third node net3 and the current supplied to the fourth node net4 based on the voltage difference between the data signal DQ and the second reference signal VR-, and output the third signal Sn- and the fourth signal Sp-.

[0045] In some embodiments, the circuit configuration of the first current source 1111 is the same as that of the second current source 1211, and the circuit configuration of the first comparison unit 1112 is the same as that of the second comparison unit 1212. In this way, it is advantageous that the difference between the first signal pair output by the first comparison circuit 111 and the second signal pair output by the second comparison circuit 121 is mainly influenced by the first reference signal VR+ and the second reference signal VR-, and further advantageous that the data receiving circuit 100 reduces the influence of the inter-code interference of the received data signal DQ on the data receiving circuit 100 based on the first reference signal VR+ and the second reference signal VR-, and further improves the accuracy of the first output signal Vout and the second output signal VoutN output from the second amplification module 102.

[0046] In some embodiments, referring to FIG. 5 , the first current source 1111 may include a first PMOS transistor MP1 connected between a power supply node Vcc and a fifth node net5, the gate of the first PMOS transistor MP1 receiving the sampling clock signal clkN, and the second current source 1211 includes a second PMOS transistor MP2 connected between a power supply node Vcc and a sixth node net6, the gate of the second PMOS transistor MP2 receiving the sampling clock signal clkN. When the sampling clock signal clkN is at a low level, the gate of the first PMOS transistor MP1 receives the sampling clock signal clkN and becomes conductive, supplying a current to the fifth node net5, thereby enabling the first comparison unit 1112 to perform a first comparison on the received data signal DQ and the first reference signal VR+; the gate of the second PMOS transistor MP2 receives the sampling clock signal clkN and becomes conductive, supplying a current to the sixth node net6, thereby enabling the second comparison unit 1212 to perform a second comparison on the received data signal DQ and the second reference signal VR-.

[0047] In some embodiments, still referring to FIG. 5 , the first comparison unit 1112 may include a third PMOS transistor MP3 and a fourth PMOS transistor MP4, where the third PMOS transistor MP3 is connected between a first node net1 and a fifth node net5, a gate of the third PMOS transistor MP3 receives a data signal DQ, the fourth PMOS transistor MP4 is connected between a second node net2 and a fifth node net5, a gate of the fourth PMOS transistor MP4 receives a first reference signal VR+, and the second comparison unit 1212 may include a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, where the fifth PMOS transistor MP5 is connected between a third node net3 and a sixth node net6, a gate of the fifth PMOS transistor MP5 receives a data signal DQ, and the sixth PMOS transistor MP6 is connected between a fourth node net4 and a sixth node net6, a gate of the sixth PMOS transistor MP6 receives a second reference signal VR−.

[0048] It should be noted that, for the first comparison unit 1112, the changes in the level values ​​of the data signal DQ and the first reference signal VR+ are not synchronized, so the conduction time of the third PMOS transistor MP3 receiving the data signal DQ is different from the conduction time of the fourth PMOS transistor MP4 receiving the first reference signal VR+, and at the same time, the conduction degree of the third PMOS transistor MP3 is different from the conduction degree of the fourth PMOS transistor MP4. It can be understood that, since the conduction degree of the third PMOS transistor MP3 is different from the conduction degree of the fourth PMOS transistor MP4, the bypass ability of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is also different from that of the fourth PMOS transistor MP4, so that the voltage at the first node net1 is different from the voltage at the second node net2, which is favorable for outputting the first signal Sn+ and the second signal Sp+ as a first signal pair with a large difference in signal level value.

[0049] For the second comparison unit 1212, the changes in the level values ​​of the data signal DQ and the second reference signal VR− are not synchronized, so the conduction time of the fifth PMOS transistor MP5 receiving the data signal DQ is different from the conduction time of the sixth PMOS transistor MP6 receiving the second reference signal VR−, and at the same time, the conduction degree of the fifth PMOS transistor MP5 is different from the conduction degree of the sixth PMOS transistor MP6. It can be understood that, since the conduction degree of the fifth PMOS transistor MP5 is different from the conduction degree of the sixth PMOS transistor MP6, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 have different bypass capabilities for the current at the sixth node net6, so that the voltage at the third node net3 is different from the voltage at the fourth node net4, which is advantageous to output the third signal Sn− and the fourth signal Sp− as a second signal pair with a large difference in signal level value.

[0050] In one example, when the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the conductivity of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4, so that the current at the fifth node net5 flows more through the path in which the third PMOS transistor MP3 is located, and the current at the first node net1 becomes greater than the current at the second node net2. As a result, the level value of the first signal Sn+ output by the first node net1 becomes higher, and the level value of the second signal Sp+ output by the second node net2 becomes lower. When the level value of the data signal DQ is lower than the level value of the second reference signal VR−, the conductivity of the fifth PMOS transistor MP5 is greater than that of the sixth PMOS transistor MP6, so that more current at the sixth node net6 flows through the path in which the fifth PMOS transistor MP5 is located, and the current at the third node net3 becomes higher than the current at the fourth node net4. As a result, the level value of the third signal Sn− output at the third node net3 becomes higher, and the level value of the fourth signal Sp− output at the fourth node net4 becomes lower.

[0051] Similarly, when the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the conductivity of the third PMOS transistor MP3 is lower than the conductivity of the fourth PMOS transistor MP4, the level value of the first signal Sn+ output at the first node net1 is low, and the level value of the second signal Sp+ output at the second node net2 is high; when the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the conductivity of the fifth PMOS transistor MP5 is lower than the conductivity of the sixth PMOS transistor MP6, the level value of the third signal Sn- output at the third node net3 is low, and the level value of the fourth signal Sp- output at the fourth node net4 is high.

[0052] 3 and 4, in some embodiments, the first amplification module 101 may further include a first reset unit 131 and a second reset unit 141, the first reset unit 131 is connected to the first node net1 and the second node net2 and configured to reset the first node net1 and the second node net2, and the second reset unit 141 is connected to the third node net3 and the fourth node net4 and configured to reset the third node net3 and the fourth node net4. In this way, after the data receiving circuit 100 completes the reception of the data signal DQ, the first reference signal VR+ and the second reference signal VR-, and the output of the first output signal Vout and the second output signal VoutN once, the first reset unit 131 can restore the level values ​​at the first node net1 and the second node net2 to their initial values, and the second reset unit 141 can restore the level values ​​at the third node net3 and the fourth node net4 to their initial values, so as to facilitate the next data reception and processing of the subsequent data receiving circuit 100.

[0053] In some embodiments, referring to FIG. 5, the first reset unit 131 may include a first NMOS transistor MN1 and a second NMOS transistor MN2, where the first NMOS transistor MN1 is connected between a first node net1 and a ground terminal, and a gate of the first NMOS transistor MN1 receives a first reset signal WckN; the second NMOS transistor MN2 is connected between a second node net2 and a ground terminal, and a gate of the second NMOS transistor MN2 receives the first reset signal WckN; the second reset unit 141 may include a third NMOS transistor MN3 and a fourth NMOS transistor MN4, where the third NMOS transistor MN3 is connected between a third node net3 and a ground terminal, and a gate of the third NMOS transistor MN3 receives the first reset signal WckN; and the fourth NMOS transistor MN4 is connected between a fourth node net4 and a ground terminal, and a gate of the fourth NMOS transistor MN4 receives the first reset signal WckN.

[0054] In one example, when the sampling clock signal clkN is at a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both conductive, and at this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all turned off, thereby ensuring the normal operation of the data receiving circuit 100. At the same time, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be used as a load of the first comparison unit 1112, thereby increasing the amplification gain of the first comparison unit 1112, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can be used as a load of the second comparison unit 1212, thereby increasing the amplification gain of the second comparison unit 1212. The amplification gain of the comparison unit 1212 can be increased. When the sampling clock signal clkN is at a high level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned off, and no current flows through the first comparison unit 1112 and the second comparison unit 1212. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all conductive, so that the voltage at the first node net1, the voltage at the second node net2, the voltage at the third node net3, and the voltage at the fourth node net4 can be pulled down, and the first node net1, the second node net2, the third node net3, and the fourth node net4 can be reset.

[0055] It should be noted that the first reset signal WckN and the sampling clock signal clkN may be the same clock signal, or may be different clock signals with the same phase but different amplitudes.

[0056] In some embodiments, referring to FIG. 6 , the second amplification module 102 may include a first input unit 112, a second input unit 122, and a latch unit 132, wherein the first input unit 112 is connected to the seventh node net7 and the eighth node net8, and is configured to conduct in response to a feedback signal Fb (see FIG. 1 ), thereby receiving a first signal pair, comparing the first signal pair, and providing signals to the seventh node net7 and the eighth node net8, respectively; the second input unit 122 is connected to the seventh node net7 and the eighth node net8, and is configured to conduct in response to the feedback signal Fb; Thereby, the latch unit 132 is configured to receive a second signal pair, compare the second signal pair, and provide signals to the seventh node net7 and the eighth node net8, respectively, where the first input unit 112 and the second input unit 122 are alternatively conductive based on the feedback signal Fb, and the latch unit 132 is connected to the seventh node net7 and the eighth node net8, and is configured to amplify and latch the signals of the seventh node net7 and the eighth node net8, and output the first output signal Vout and the second output signal VoutN via the first output node net9 and the second output node net10, respectively.

[0057] Here, the first input unit 112 is used to compare the first signal Sn+ with the second signal Sp+ and provide signals to the seventh node net7 and the eighth node net8, the second input unit 122 is used to compare the third signal Sn- with the fourth signal Sp- and provide signals to the seventh node net7 and the eighth node net8, and the latch unit 132 is used to output a high level signal to the first output node net9 and a low level signal to the second output node net10, or output a low level signal to the first output node net9 and a high level signal to the second output node net10 based on the signal of the seventh node net7 and the signal of the eighth node net8.

[0058] In some embodiments, referring to FIG. 6, the feedback signal Fb (see FIG. 1) includes a differential first feedback signal Fb+ and a second feedback signal Fb−, and the first input unit 112 is conductive in response to the first feedback signal Fb+ and the second input unit 122 is conductive in response to the second feedback signal Fb−.

[0059] In one example, when the first feedback signal Fb+ is at a high level and the second feedback signal Fb- is at a low level, the first input unit 112 is turned on in response to the first feedback signal Fb+, and the second input unit 122 is turned off in response to the second feedback signal Fb-, i.e., the first output signal Vout and the second output signal VoutN are obtained based on the first signal Sn+ and the second signal Sp+ received by the first input unit 112; in another example, when the first feedback signal Fb+ is at a low level and the second feedback signal Fb- is at a high level, the first input unit 112 is turned off in response to the first feedback signal Fb+, and the second input unit 122 is turned on in response to the second feedback signal Fb-, i.e., the first output signal Vout and the second output signal VoutN are obtained based on the third signal Sn- and the fourth signal Sp- received by the second input unit 122.

[0060] In some embodiments, still referring to FIG. 6, the first input unit 112 may include a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8, where the drain of the fifth NMOS transistor MN5 is connected to a seventh node net7, the source of the fifth NMOS transistor MN5 is connected to a drain of the sixth NMOS transistor MN6, and the source of the sixth NMOS transistor MN6 is connected to a ground terminal, where the gate of the fifth NMOS transistor MN5 receives one of a first signal Sn+ or a first feedback signal Fb+, and the gate of the fifth NMOS transistor MN5 receives one of a first signal Sn+ or a first feedback signal Fb+. The gate of the sixth NMOS transistor MN6 receives the other of the first signal Sn+ or the first feedback signal Fb+, the drain of the seventh NMOS transistor MN7 is connected to the eighth node net8, the source of the seventh NMOS transistor MN7 is connected to the drain of the eighth NMOS transistor MN8, and the source of the eighth NMOS transistor MN8 is connected to the ground terminal, where the gate of the seventh NMOS transistor MN7 receives one of the second signal Sp+ or the first feedback signal Fb+, and the gate of the eighth NMOS transistor MN8 receives the other of the second signal Sp+ or the first feedback signal Fb+.

[0061] It should be noted that FIG. 6 takes as an example the case where the gate of the fifth NMOS transistor MN5 receives the first feedback signal Fb+, the gate of the sixth NMOS transistor MN6 receives the first signal Sn+, the gate of the seventh NMOS transistor MN7 receives the first feedback signal Fb+, and the gate of the eighth NMOS transistor MN8 receives the second signal Sp+; in actual applications, it is also possible that the gate of the fifth NMOS transistor MN5 receives the first signal Sn+, the gate of the sixth NMOS transistor MN6 receives the first feedback signal Fb+, the gate of the seventh NMOS transistor MN7 receives the second signal Sp+, and the gate of the eighth NMOS transistor MN8 receives the first feedback signal Fb+.

[0062] In one example, when the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the level value of the first signal Sn+ is low and the level value of the second signal Sp+ is high. At this time, when the first input unit 112 is conductive in response to the first feedback signal Fb+, the gate of the sixth NMOS transistor MN6 receives the first signal Sn+ and the gate of the eighth NMOS transistor MN8 receives the second signal Sp+, the conductivity of the eighth NMOS transistor MN8 is greater than the conductivity of the sixth NMOS transistor MN6, so that the voltage at the eighth node net8 is greater than the voltage at the seventh node net7. Therefore, the conductivity of the eighth PMOS transistor MP8 is less than the conductivity of the seventh PMOS transistor MP7, and the latch unit 132 forms a positive feedback amplifier. Furthermore, the first output signal Vout output by the first output node net9 is at a high level, and the second output signal VoutN output by the second output node net10 is at a low level. Similarly, when the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the level value of the first signal Sn+ is high and the level value of the second signal Sp+ is low. At this time, when the first input unit 112 is conductive in response to the first feedback signal Fb+, the first output signal Vout output by the first output node net9 is at a low level and the second output signal VoutN output by the second output node net10 is at a high level.

[0063] In some embodiments, the second input unit 122 may include a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10, and an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12, the drain of the ninth NMOS transistor MN9 is connected to the seventh node net7, the source of the ninth NMOS transistor MN9 is connected to the drain of the tenth NMOS transistor MN10, and the source of the tenth NMOS transistor MN10 is connected to the ground terminal, where the gate of the ninth NMOS transistor MN9 receives one of the third signal Sn− or the second feedback signal Fb−, and the gate of the tenth NMOS transistor MN9 receives one of the third signal Sn− or the second feedback signal Fb−. The gate of the transistor MN10 receives the other of the third signal Sn- or the second feedback signal Fb-, the drain of the eleventh NMOS transistor MN11 is connected to the eighth node net8, the source of the eleventh NMOS transistor MN11 is connected to the drain of the twelfth NMOS transistor MN12, and the source of the twelfth NMOS transistor MN12 is connected to the ground terminal, where the gate of the eleventh NMOS transistor MN11 receives one of the fourth signal Sp- or the second feedback signal Fb-, and the gate of the twelfth NMOS transistor MN12 receives the other of the fourth signal Sp- or the second feedback signal Fb-.

[0064] It should be noted that FIG. 6 takes as an example the case where the gate of the ninth NMOS transistor MN9 receives the second feedback signal Fb-, the gate of the tenth NMOS transistor MN10 receives the third signal Sn-, the gate of the eleventh NMOS transistor MN11 receives the second feedback signal Fb-, and the gate of the twelfth NMOS transistor MN12 receives the fourth signal Sp-; in actual applications, it is also possible that the gate of the ninth NMOS transistor MN9 receives the third signal Sn-, the gate of the tenth NMOS transistor MN10 receives the second feedback signal Fb-, the gate of the eleventh NMOS transistor MN11 receives the fourth signal Sp-, and the gate of the twelfth NMOS transistor MN12 receives the second feedback signal Fb-.

[0065] In one example, when the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the level value of the third signal Sn- is low and the level value of the fourth signal Sp- is high. At this time, when the second input unit 122 is conductive in response to the second feedback signal Fb-, the gate of the tenth NMOS transistor MN10 receives the third signal Sn- and the gate of the twelfth NMOS transistor MN12 receives the fourth signal Sp-, the conductivity of the twelfth NMOS transistor MN12 is higher than the conductivity of the tenth NMOS transistor MN10, so that the voltage at the eighth node net8 is smaller than the voltage at the seventh node net7, and therefore the first output signal Vout output by the first output node net9 is at a high level and the second output signal VoutN output by the second output node net10 is at a low level. Similarly, when the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the level value of the third signal Sn- is high and the level value of the fourth signal Sp- is low. At this time, when the second input unit 122 is conductive in response to the second feedback signal Fb-, the first output signal Vout output by the first output node net9 is at a low level, and the second output signal VoutN output by the second output node net10 is at a high level.

[0066] It should be noted that when multiple data receiving circuits 100 are cascaded, the feedback signal Fb is obtained based on previously received data, which means that the first output signal Vout and the second output signal VoutN output from the data receiving circuit 100 in the previous stage are used as the feedback signal Fb of the data receiving circuit 100 in the next stage, and the first output signal Vout and the second output signal VoutN output from the data receiving circuit 100 in the final stage are used as the feedback signal Fb of the data receiving circuit 100 in the first stage. Specifically, the first output signal Vout output from the first output node net9 of the previous stage data receiving circuit 100 is the first feedback signal Fb+ of the next stage data receiving circuit 100, the second output signal VoutN output from the second output node net10 of the previous stage data receiving circuit 100 is the second feedback signal Fb- of the next stage data receiving circuit 100, the first output signal Vout output from the first output node net9 of the final stage data receiving circuit 100 is the first feedback signal Fb+ of the first stage data receiving circuit 100, and the second output signal VoutN output from the second output node net10 of the final stage data receiving circuit 100 is the second feedback signal Fb- of the first stage data receiving circuit 100.

[0067] It can be understood that when the first output signal Vout outputted at the first output node net9 of the preceding data receiving circuit 100 is at a high level and the second output signal VoutN outputted at the second output node net10 is at a low level, the first feedback signal Fb+ received by the next data receiving circuit 100 is at a high level and the second feedback signal Fb- is at a low level, and the first input unit 112 in the next data receiving circuit 100 is conductive in response to the first feedback signal Fb+ and the second input unit 122 is off in response to the second feedback signal Fb-. On the other hand, when the first output signal Vout outputted from the first output node net9 of the preceding data receiving circuit 100 is at a low level and the second output signal VoutN outputted from the second output node net10 is at a high level, the first feedback signal Fb+ received by the next-stage data receiving circuit 100 is at a low level and the second feedback signal Fb- is at a high level, and the first input unit 112 in the next-stage data receiving circuit 100 is turned off in response to the first feedback signal Fb+, and at this time the second input unit 122 is turned on in response to the second feedback signal Fb-.

[0068] In some embodiments, referring to FIG. 6 , the latch unit 132 may include a thirteenth NMOS transistor MN13 and a seventh PMOS transistor MP7, and a fourteenth NMOS transistor MN14 and an eighth PMOS transistor MP8, where the gate of the thirteenth NMOS transistor MN13 and the gate of the seventh PMOS transistor MP7 are both connected to the second output node net10, the source of the thirteenth NMOS transistor MN13 is connected to the seventh node net7, and the drain of the thirteenth NMOS transistor MN13 and the drain of the seventh PMOS transistor MP7 are both connected to the seventh node net7. the source of the seventh PMOS transistor MP7 is connected to the power supply node Vcc, the gate of the fourteenth NMOS transistor MN14 and the gate of the eighth PMOS transistor MP8 are both connected to the first output node net9, the source of the fourteenth NMOS transistor MN14 is connected to the eighth node net8, the drain of the fourteenth NMOS transistor MN14 and the drain of the eighth PMOS transistor MP8 are both connected to the second output node net10, and the source of the eighth PMOS transistor MP8 is connected to the power supply node Vcc.

[0069] 6, in some embodiments, the second amplification module 102 may further include a third reset unit 142 connected between the power supply node Vcc and the output terminal of the latch unit 132, configured to reset the output terminal of the latch unit 132. In this way, after the data receiving circuit 100 completes receiving the first reference signal VR+ and the second reference signal VR-, and outputting the first output signal Vout and the second output signal VoutN once, the third reset unit 142 can restore the level values ​​at the first output node net9 and the second output node net10 to their initial values, so as to facilitate the next data reception and processing of the subsequent data receiving circuit 100.

[0070] In some embodiments, still referring to FIG. 6, the output terminal of the latch unit 132 may include a first output node net9 and a second output node net10, and the third reset unit 142 may include a ninth PMOS transistor MP9 and a tenth PMOS transistor MP10, where the ninth PMOS transistor MP9 is connected between the first output node net9 and a power supply node Vcc, and the gate of the ninth PMOS transistor MP9 receives the second reset signal clk, and the tenth PMOS transistor MP10 is connected between the second output node net10 and a power supply node Vcc, and the gate of the tenth PMOS transistor MP10 receives the second reset signal clk.

[0071] In one example, the second reset signal clk is an inverted signal of the sampling clock signal clkN. Referring to FIGS. 5 and 6, when the sampling clock signal clkN is at a low level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are all conductive. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all turned off. When the second reset signal clk is at a high level, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are all turned off, thereby ensuring the normal operation of the data receiving circuit 100. When the sampling clock signal clkN is at a high level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are all turned off, and at this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all conductive, the second reset signal clk is at a low level, and the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 also conduct, so that the voltage at the first output node net9 and the voltage at the second output node net10 are pulled down, and the first output node net9 and the second output node net10 can be reset.

[0072] In the following, in conjunction with FIG. 6 and Table 1, a specific operation principle of the data receiving circuit 100 provided according to the embodiment of the present disclosure will be described in detail.

[0073] In one example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout output by the first output node net9 of the previous stage data receiving circuit 100 is the first feedback signal Fb+ of the next stage data receiving circuit 100, the second output signal VoutN output by the second output node net10 of the previous stage data receiving circuit 100 is the second feedback signal Fb- of the next stage data receiving circuit 100, the first output signal Vout output by the first output node net9 of the final stage data receiving circuit 100 is the first feedback signal Fb+ of the first stage data receiving circuit 100, and the second output signal VoutN output by the second output node net10 of the final stage data receiving circuit 100 is the second feedback signal Fb- of the first stage data receiving circuit 100.

[0074] In the following, an example will be described in which the level value of the received first reference signal VR+ is greater than the level value of the second reference signal VR-. In one example, the level value of the first reference signal VR+ may be 0.7V, and the level value of the second reference signal VR- may be 0.3V. When the data signal DQ is at logic level 1, it indicates that the level value of the data signal DQ is greater than the level value of the first reference signal VR+, and when the data signal DQ is at logic level 0, it indicates that the level value of the data signal DQ is less than the level value of the second reference signal VR-.

[0075] Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 of the previous stage is at logic level 1, the first output signal Vout output by the data receiving circuit 100 of the previous stage, i.e., the first feedback signal Fb+ of the data receiving circuit 100 of the next stage, is at a high level, which is represented by logic level 1 in Table 1, and the second output signal VoutN output by the data receiving circuit 100 of the previous stage, i.e., the second feedback signal Fb- of the data receiving circuit 100 of the next stage, is at a low level, which is represented by logic level 0 in Table 1. The gate of the fifth NMOS transistor MN5 and the gate of the seventh NMOS transistor MN7 receive the first feedback signal Fb+ and are turned on, the gate of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11 receive the second feedback signal Fb- and are turned off, the first input unit 112 is used to compare the first signal Sn+ and the second signal Sp+ and provide signals to the seventh node net7 and the eighth node net8, and no current flows through the second input unit 122.

[0076] When the data signal DQ1 received by the data receiving circuit 100 at the previous stage is at logic level 1, the data signal DQ2 received by the data receiving circuit 100 at the next stage falls into one of the following two cases.

[0077] Case 1: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the difference in level value between the data signal DQ2 received by the previous-stage data receiving circuit 100 is large, and large inter-code interference exists. At this time, the first input unit 112 in the next-stage data receiving circuit 100 is conductive, that is, the second amplification module 102 in the next-stage data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+, and the first signal pair output by the first comparison circuit 111 in the next-stage data receiving circuit 100 is received by the second amplification module 102. At this time, in the next-stage data receiving circuit 100, when the data signal DQ2 is at logic level 0 and the voltage difference between the data signal DQ2 and the first reference signal VR+ is greater than the voltage difference between the data signal DQ2 and the second reference signal VR-, the difference in the signal level values ​​in the first signal pair obtained by the processing of the first comparison circuit 111 will be large, and at this time, the second amplification module 102 receiving the first signal pair is advantageous for outputting the first output signal Vout and the second output signal VoutN with higher accuracy, and the purpose of reducing the impact of inter-code interference of the received data signal DQ on the data receiving circuit 100 can be achieved.

[0078] Case 2: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the difference in level value between the data signal DQ2 received by the previous-stage data receiving circuit 100 is small, and the inter-code interference is small or non-existent. At this time, the first input unit 112 in the next-stage data receiving circuit 100 is conductive, and the first signal pair output by the first comparison circuit 111 in the next-stage data receiving circuit 100 is received by the second amplification module 102.

[0079] Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 of the previous stage is at logic level 0 and the data receiving circuit 100 of the previous stage outputs the first output signal Vout, the first feedback signal Fb+ of the data receiving circuit 100 of the next stage is at a low level, which is represented by logic level 0 in Table 1, and the second output signal VoutN output by the data receiving circuit 100 of the previous stage, i.e., the second feedback signal Fb- of the data receiving circuit 100 of the next stage is at a high level, which is represented by logic level 1 in Table 1. At this time, The gate of the fifth NMOS transistor MN5 and the gate of the seventh NMOS transistor MN7 receive the first feedback signal Fb+ and are turned off, the gate of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11 receive the second feedback signal Fb- and are turned on, the second input unit 122 is used to compare the third signal Sn- and the fourth signal Sp- to provide signals to the seventh node net7 and the eighth node net8, and no current flows through the first input unit 112.

[0080] When the data signal DQ1 received by the data receiving circuit 100 at the previous stage is at logic level 0, there are the following two cases for the data signal DQ2 received by the data receiving circuit 100 at the next stage.

[0081] Case 3: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 0, the difference in level value between the data signal DQ2 received by the previous-stage data receiving circuit 100 is small, and the inter-code interference is small or non-existent. At this time, the second input unit 122 in the next-stage data receiving circuit 100 is conductive, and the second signal pair output by the second comparison circuit 121 in the next-stage data receiving circuit 100 is received by the second amplification module 102.

[0082] Case 4: Referring to Table 1, when the data signal DQ2 received by the next-stage data receiving circuit 100 is at logic level 1, the difference in level value between the data signal DQ2 received by the previous-stage data receiving circuit 100 is large, and large inter-code interference exists. At this time, the second input unit 122 in the next-stage data receiving circuit 100 is conductive, and the second amplification module 102 in the next-stage data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-. The second signal pair output by the second comparison circuit 121 in the next-stage data receiving circuit 100 is received by the second amplification module 102. At this time, in the next-stage data receiving circuit 100, when the data signal DQ2 is at logic level 1 and the voltage difference between the data signal DQ2 and the second reference signal VR- is greater than the voltage difference between the data signal DQ2 and the first reference signal VR+, the difference in the signal level values ​​in the second signal pair obtained by processing of the second comparison circuit 121 will be large, and at this time, the second amplifying module 102 receiving the second signal pair is advantageous for outputting the first output signal Vout and the second output signal VoutN with higher accuracy, and the purpose of reducing the impact of inter-code interference of the received data signal DQ on the data receiving circuit 100 can be achieved.

[0083] [Table 1]

[0084] It should be noted that in the above description of the high level and low level, the high level may be equal to or higher than the level of the power supply voltage, and the low level may be equal to or lower than the level of the ground voltage. Moreover, the high level and the low level are relative, and the specific level ranges included in the high level and the low level can be determined according to a specific device. For example, in the case of an NMOS transistor, the high level refers to the level range of the gate voltage that can turn on the NMOS transistor, and the low level refers to the level range of the gate voltage that can turn off the NMOS transistor. In the case of a PMOS transistor, the low level refers to the level range of the gate voltage that can turn on the PMOS transistor, and the high level refers to the level range of the gate voltage that can turn off the PMOS transistor.

[0085] As described above, the first reference signal VR+ and the second reference signal VR- are used to perform a first comparison and a second comparison on the data signal DQ, respectively, to obtain a first signal pair and a second signal pair, in which the level value of the first reference signal VR+ and the level value of the second reference signal VR- are different, and for the data signal DQ with different level values, it can be satisfied that the difference in level value between the data signal DQ and one of the first reference signal VR+ or the second reference signal VR- is large. Therefore, when there is inter-code interference in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 is effective to receive the one of the first signal pair and the second signal pair with the larger difference in level value according to the feedback signal Fb. It is advantageous to use the first reference signal VR+ and the second reference signal VR- to enhance the adjustment ability of the data receiving circuit 100 to the received data signal DQ, thereby realizing the purpose of reducing the impact of inter-code interference of the received data signal DQ on the data receiving circuit 100, and then the second amplifying module 102 selects to receive the first signal pair and the second signal pair with a larger difference in level value based on the feedback signal Fb, so that it is advantageous to ensure that the second amplifying module 102 receives a differential signal pair with a larger difference in signal level value, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output from the second amplifying module 102. Therefore, the cooperation of the first amplifying module 101 and the second amplifying module 102 is advantageous to improve the receiving performance of the data receiving circuit 100.

[0086] Another embodiment of the present disclosure further provides a data receiving system, and the data receiving system provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. Figure 2 is a functional block diagram of a data receiving system according to an embodiment of the present disclosure.

[0087] Referring to FIG. 2, the data receiving system includes a plurality of data transmission circuits 120 connected in cascade, each of which includes a data receiving circuit 100 according to an embodiment of the present disclosure and a latch circuit 110 connected to the data receiving circuit 100, and the output signal of the data transmission circuit 120 of the previous stage is used as the feedback signal Fb of the data transmission circuit 120 of the next stage, and the output signal of the data transmission circuit 120 of the final stage is used as the feedback signal Fb of the data transmission circuit 120 of the first stage.

[0088] Here, the latch circuits 110 are provided in one-to-one correspondence with the data receiving circuits 100, and the latch circuits 110 are used to latch and output signals output from the data receiving circuits 100 corresponding to the latch circuits 110.

[0089] In some embodiments, the data receiving circuit 100 receives data in response to a sampling clock signal clkN (see FIG. 3), and the data receiving system includes four data receiving circuits 100 cascaded together, and the phase difference between the sampling clock signals clkN of the data receiving circuits 100 of adjacent stages is 90°. In this way, the period of the sampling clock signal clkN is twice that of the data signal DQ received at the data port, which is advantageous for saving clock wiring and power.

[0090] It should be noted that FIG. 1 takes as an example a case where the data receiving system includes four cascaded data receiving circuits 100, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages is 90°. In actual applications, the number of cascaded data receiving circuits 100 included in the data receiving system is not limited, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages can be appropriately set based on the number of cascaded data receiving circuits 100.

[0091] In some embodiments, the feedback signal Fb of the next-stage data transmission circuit 120 is the output signal of the previous-stage data receiving circuit 100 or the output signal of the previous-stage latch circuit 110, and the feedback signal Fb of the first-stage data transmission circuit 120 is the output signal of the last-stage data receiving circuit 100 or the output signal of the last-stage latch circuit 110. That is, in one example, the feedback signal Fb of the next-stage data transmission circuit 120 is the output signal of the previous-stage data receiving circuit 100, and in this way, the output of the data receiving circuit 100 is directly transmitted to the next-stage data transmission circuit 120 without having to go through the latch circuit 110, which is advantageous for reducing data transmission delay, and in another example, the feedback signal Fb of the next-stage data transmission circuit 120 is the output signal of the previous-stage latch circuit 110.

[0092] As described above, the data receiving system provided by another embodiment of the present disclosure uses the first reference signal VR+ and the second reference signal VR- to perform a first comparison and a second comparison on the data signal DQ to obtain a first signal pair and a second signal pair, and can satisfy that for the data signal DQ with different level values, the difference in level value between the data signal DQ and one of the first reference signal VR+ or the second reference signal VR- is large. Therefore, when there is inter-code interference in the data signal DQ received by the data receiving circuit 100, the second amplification module 102 then outputs a feedback signal Based on Fb, it is advantageous to receive the first signal pair and the second signal pair which has a larger difference in level value, thereby achieving the purpose of reducing the impact of inter-code interference of the received data signal DQ on the data receiving circuit 100, and it is also advantageous to ensure that the signal received by the second amplification module 102 is a differential signal pair with a large difference in signal level value, thereby being advantageous to improve the accuracy of the first output signal Vout and the second output signal VoutN output from the second amplification module 102, and therefore being advantageous to improve the receiving performance of the data receiving system.

[0093] In yet another embodiment of the present disclosure, a storage device is further provided, the storage device includes a plurality of data ports and a plurality of data receiving systems provided by another embodiment of the present disclosure, each data receiving system corresponds to one data port. In this way, each data port of the storage device can flexibly adjust the data signal DQ received by each data receiving system, and enhance the adjustment ability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device.

[0094] In some embodiments, the storage device may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0095] Those skilled in the art can understand that the above embodiments are specific examples for realizing the present disclosure, and in practical application, various changes in form and details can be made without departing from the spirit and scope of the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data receiving circuit, a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal, perform a first comparison on the data signal and the first reference signal, and output a first signal pair as a result of the first comparison, and perform a second comparison on the data signal and the second reference signal, and output a second signal pair as a result of the second comparison, wherein a level value of the first reference signal and a level value of the second reference signal are different, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal; a second amplification module configured to selectively receive the first signal pair or the second signal pair as an input signal pair based on a feedback signal, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process, wherein if the data receiving circuit is a first data receiving circuit among a plurality of cascaded data receiving circuits, the feedback signal includes the first output signal and the second output signal output by a final data receiving circuit among the plurality of data receiving circuits, and if not, the feedback signal includes the first output signal and the second output signal output by a data receiving circuit preceding the data receiving circuit among the plurality of data receiving circuits.

2. the first amplification module includes a first comparison circuit and a second comparison circuit; the first comparison circuit has a first node and a second node, and is configured to receive the data signal and the first reference signal, perform the first comparison, and output the first signal and the second signal via the first node and the second node, respectively; the second comparison circuit has a third node and a fourth node, and is configured to receive the data signal and the second reference signal to perform the second comparison, and output the third signal and the fourth signal via the third node and the fourth node, respectively; 2. The data receiving circuit according to claim 1.

3. The first comparison circuit includes a first current source and a first comparison unit; the first current source is connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to a sampling clock signal; the first comparison unit is connected to the first node, the second node, and the fifth node, and is configured to receive the data signal and the first reference signal, perform the first comparison when the first current source supplies a current to the fifth node, and output the first signal and the second signal; the second comparison circuit includes a second current source and a second comparison unit; the second current source is connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the sampling clock signal; the second comparison unit is coupled to the third node, the fourth node, and the sixth node, and is configured to receive the data signal and the second reference signal, perform the second comparison when the second current source supplies a current to the sixth node, and output the third signal and the fourth signal; 3. The data receiving circuit according to claim 2.

4. a circuit configuration of the first current source is the same as a circuit configuration of the second current source, and a circuit configuration of the first comparison unit is the same as a circuit configuration of the second comparison unit; 4. The data receiving circuit according to claim 3.

5. The first current source is a first PMOS transistor connected between the power supply node and the fifth node, the gate of the first PMOS transistor receiving the sampling clock signal; The second current source is a second PMOS transistor connected between the power supply node and the sixth node, the gate of the second PMOS transistor receiving the sampling clock signal; 4. The data receiving circuit according to claim 3.

6. the first comparison unit includes a third PMOS transistor and a fourth PMOS transistor; the third PMOS transistor is connected between the first node and the fifth node, a gate of the third PMOS transistor receives the data signal; the fourth PMOS transistor is connected between the second node and the fifth node, a gate of the fourth PMOS transistor receives the first reference signal; the second comparison unit includes a fifth PMOS transistor and a sixth PMOS transistor; the fifth PMOS transistor is connected between the third node and the sixth node, a gate of the fifth PMOS transistor receives the data signal; the sixth PMOS transistor is connected between the fourth node and the sixth node, and a gate of the sixth PMOS transistor receives the second reference signal; 4. The data receiving circuit according to claim 3.

7. The first amplification module further includes a first reset unit and a second reset unit; the first reset unit is connected to the first node and the second node and configured to reset the first node and the second node; the second reset unit is connected to the third node and the fourth node and configured to reset the third node and the fourth node; the first reset unit includes a first NMOS transistor and a second NMOS transistor; the first NMOS transistor is connected between the first node and a ground terminal, and a gate of the first NMOS transistor receives a first reset signal; the second NMOS transistor is connected between the second node and the ground terminal, and a gate of the second NMOS transistor receives the first reset signal; the second reset unit includes a third NMOS transistor and a fourth NMOS transistor; the third NMOS transistor is connected between the third node and the ground terminal, and a gate of the third NMOS transistor receives the first reset signal; the fourth NMOS transistor is connected between the fourth node and the ground terminal, and a gate of the fourth NMOS transistor receives the first reset signal; 4. The data receiving circuit according to claim 3.

8. The second amplification module includes a first input unit, a second input unit, and a latch unit; the first input unit is connected to a seventh node and an eighth node and configured to conduct in response to the feedback signal, thereby receiving the first signal pair, comparing the first signal pair, and providing signals to the seventh node and the eighth node, respectively; the second input unit is connected to the seventh node and the eighth node and configured to conduct in response to the feedback signal, thereby receiving the second signal pair, comparing the second signal pair, and providing signals to the seventh node and the eighth node, respectively; the first input unit and the second input unit are selectively conductive based on the feedback signal; the latch unit is connected to the seventh node and the eighth node, and is configured to amplify and latch a signal at the seventh node and a signal at the eighth node, and output the first output signal and the second output signal via a first output node and a second output node, respectively; the feedback signal includes a differential first feedback signal and a second feedback signal, the first input unit being conductive in response to the first feedback signal, and the second input unit being conductive in response to the second feedback signal; 2. The data receiving circuit according to claim 1.

9. the first input unit includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; a drain of the fifth NMOS transistor is connected to the seventh node, a source of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a ground terminal, a gate of the fifth NMOS transistor receives one of the first signal or the first feedback signal, and a gate of the sixth NMOS transistor receives the other of the first signal or the first feedback signal; a drain of the seventh NMOS transistor is connected to the eighth node, a source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, a source of the eighth NMOS transistor is connected to the ground terminal, a gate of the seventh NMOS transistor receives one of the second signal or the first feedback signal, and a gate of the eighth NMOS transistor receives the other of the second signal or the first feedback signal; 9. The data receiving circuit according to claim 8.

10. the second input unit includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; a drain of the ninth NMOS transistor is connected to the seventh node, a source of the ninth NMOS transistor is connected to a drain of the tenth NMOS transistor, a source of the tenth NMOS transistor is connected to a ground terminal, a gate of the ninth NMOS transistor receives one of the third signal or the second feedback signal, and a gate of the tenth NMOS transistor receives the other of the third signal or the second feedback signal; a drain of the eleventh NMOS transistor is connected to the eighth node, a source of the eleventh NMOS transistor is connected to a drain of the twelfth NMOS transistor, a source of the twelfth NMOS transistor is connected to the ground terminal, a gate of the eleventh NMOS transistor receives one of the fourth signal or the second feedback signal, and a gate of the twelfth NMOS transistor receives the other of the fourth signal or the second feedback signal; 9. The data receiving circuit according to claim 8.

11. the latch unit includes a thirteenth NMOS transistor, a seventh PMOS transistor, a fourteenth NMOS transistor, and an eighth PMOS transistor; a gate of the thirteenth NMOS transistor and a gate of the seventh PMOS transistor are both connected to the second output node, a source of the thirteenth NMOS transistor is connected to the seventh node, a drain of the thirteenth NMOS transistor and a drain of the seventh PMOS transistor are both connected to the first output node, and a source of the seventh PMOS transistor is connected to a power supply node; a gate of the 14th NMOS transistor and a gate of the 8th PMOS transistor are both connected to the first output node, a source of the 14th NMOS transistor is connected to the 8th node, a drain of the 14th NMOS transistor and a drain of the 8th PMOS transistor are both connected to the second output node, and a source of the 8th PMOS transistor is connected to the power supply node.

9. The data receiving circuit according to claim 8.

12. The second amplification module further comprises: a third reset unit connected between a power supply node and the output terminal of the latch unit and configured to reset the output terminal of the latch unit; an output terminal of the latch unit includes a first output node and a second output node; and the third reset unit includes a ninth PMOS transistor and a tenth PMOS transistor; the ninth PMOS transistor is connected between the first output node and a power supply node, and a gate of the ninth PMOS transistor receives a second reset signal; the tenth PMOS transistor is connected between the second output node and the power supply node, and a gate of the tenth PMOS transistor receives the second reset signal; 9. The data receiving circuit according to claim 8.

13. 1. A data receiving system, comprising: A plurality of cascaded data transmission circuits are included, each of the data transmission circuits including the data receiving circuit according to any one of claims 1 to 12 and a latch circuit connected to the data receiving circuit; an output signal of the data transmission circuit of the previous stage is used as the feedback signal of the data transmission circuit of the next stage; A data receiving system, wherein an output signal of the data transmission circuit in a final stage is used as the feedback signal of the data transmission circuit in a first stage.

14. the data receiving circuit receives a data signal in response to a sampling clock signal, the data receiving system includes four of the data receiving circuits connected in cascade, and the phase difference between the sampling clock signals of the data receiving circuits of adjacent stages is 90°; the feedback signal of the data transmission circuit of the next stage is an output signal of the data receiving circuit of the previous stage or an output signal of the latch circuit of the previous stage, and the feedback signal of the data transmission circuit of the first stage is an output signal of the data receiving circuit of the last stage or an output signal of the latch circuit of the last stage; 14. The data receiving system according to claim 13.

15. 1. A storage device comprising: Multiple data ports and 14. A storage device comprising: a plurality of data receiving systems according to claim 13, each of said data receiving systems corresponding to one of said data ports.

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