Semiconductor device and switching power supply device

Abstract

To provide a semiconductor device capable of suppressing generation of GHz-band noise.SOLUTION: A semiconductor device includes: a semiconductor substrate 11 of a first conductivity type; a semiconductor layer 12 of the first conductivity type located on the semiconductor substrate; a first diffusion layer 13 of a second conductivity type located on a surface side in the semiconductor layer of the first conductivity type; and a second diffusion layer 14 of the second conductivity type located in the semiconductor layer of the first conductivity type, being in contact with the first diffusion layer of the second conductivity type in a plan view, arranged so as to surround the first diffusion layer of the second conductivity type, and formed so as to have a withstanding voltage higher than that of the first diffusion layer of the second conductivity type; an insulating layer 15 located on the second diffusion layer of the second conductivity type and on the semiconductor layer outside the second diffusion layer of the second conductivity type in a plan view; and a metal plate 16 located on the first diffusion layer of the second conductivity type, the second diffusion layer of the second conductivity type, and the insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a switching power supply device. [Background technology]

[0002] FIG. 11 is a cross-sectional view showing a mesa diode for voltage clamping in a conventional power clamper. This voltage clamp mesa diode is N ++ The substrate 101 is a silicon substrate 101. ++ An N-type epitaxial layer 102 is formed on a silicon substrate 101. Both ends of the N-type epitaxial layer 102 are tapered. ++ A P ++ An insulating layer 105 such as a glass passivation layer is formed on both ends of the N-type diffusion layer 103 and the N-type epitaxial layer 102, which are tapered. ++ A first metal film 104 made of a laminated film of a Ni layer and an Au layer or a Ni film is formed on the type diffusion layer 103. ++ A second metal film 106 made of a laminated film of a Ni layer and an Au layer or a Ni film is formed under the silicon substrate 101. A technique related to such a voltage clamping mesa diode is described in, for example, Patent Document 1.

[0003] The power clamper is a single element that combines a voltage clamping mesa diode and a high-speed rectifier diode. With conventional power clampers, the generation of noise in the GHz band was not an issue.

[0004] However, the noise regulations of CISPR (Comite International Special des Perturbations Radioélectriques) changed, and it became necessary to suppress the generation of GHz-band noise. It was also confirmed that GHz-band noise was being generated from the mesa-type diode for voltage clamping in the power clamper shown in Figure 11.

[0005] CISPR is a special committee of the International Electrotechnical Commission (IEC) whose purpose is to promote international trade by reaching international agreement on the acceptable limits and measurement methods for unwanted radio waves (interference waves) from various devices that cause radio interference. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-192500 A Summary of the Invention [Problem to be solved by the invention]

[0007] Various aspects of the present invention have an object to provide a semiconductor device capable of suppressing the generation of noise in the GHz band, and a switching power supply device including the semiconductor device. [Means for solving the problem]

[0008] Various aspects of the present invention are described below.

[0009] [1] A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer; a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer; an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view; a metal plate located on the first second conductive type diffusion layer, the second second conductive type diffusion layer, and the insulating layer; A semiconductor device comprising:

[0010] [2] In paragraph [1] above: a second diffusion layer of a second conductive type having an impurity concentration gradient that is gentler than that of the first diffusion layer of a second conductive type;

[0011] [3] In [1] or [2] above, A semiconductor device, characterized in that the second second-conductivity type diffusion layer is deeper than the first second-conductivity type diffusion layer. [4] In paragraph [3] above: A semiconductor device, characterized in that the second second-conductivity-type diffusion layer has a surface concentration higher than that of the first second-conductivity-type diffusion layer. [5] In paragraph [3] above: 2. A semiconductor device comprising: a first diffusion layer of a second conductivity type and a second diffusion layer of a second conductivity type;

[0012] [6] In [1] or [2] above, 2. A semiconductor device comprising: a first diffusion layer of a second conductive type and a second diffusion layer of a second conductive type; [7] In paragraph [3] or [6] above, 2. A semiconductor device comprising: a first diffusion layer of a second conductivity type and a second diffusion layer of a second conductivity type;

[0013] [8] A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer; a buried layer of a first conductivity type, which is located within the semiconductor layer of the first conductivity type, is located below the diffusion layer of the second conductivity type, is in contact with the diffusion layer of the second conductivity type, is located inside the diffusion layer of the second conductivity type in a plan view, and has an impurity concentration higher than that of the semiconductor layer of the first conductivity type; an insulating layer located on an end of the second conductive type diffusion layer outside the first conductive type buried layer and on the semiconductor layer outside the end of the second conductive type diffusion layer in a plan view; a metal plate located on the second conductive type diffusion layer, an end of the second conductive type diffusion layer, and the insulating layer; A semiconductor device comprising:

[0014] [9] In any one of paragraphs [1] to [8] above: The semiconductor device is characterized in that the metal plate has a first metal layer and a second metal layer located on the first metal layer, and the first metal layer is electrically connected to the second metal layer.

[0015]

[10] In any one of paragraphs [1] to [9] above, A semiconductor device having solder located on said metal plate.

[0016]

[11] In paragraph

[10] above: The semiconductor device, characterized in that the solder is located on the metal plate on each of the first second conductive type diffusion layer, the second second conductive type diffusion layer, and the insulating layer.

[0017]

[12] In any one of paragraphs [1] to

[11] above, a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; a shielding film covering a surface of the resin; having The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

[0018]

[13] In any one of paragraphs [1] to

[11] above: a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; having The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[0019]

[14] A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer; a metal plate located on the second conductive type diffusion layer; a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; a shielding film covering a surface of the resin; having The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

[0020]

[15] In paragraph

[12] or

[14] above, The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[0021]

[16] A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer; a metal plate located on the second conductive type diffusion layer; a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; having The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

[0022]

[17] In any one of paragraphs [1] to

[16] above: The semiconductor device, wherein the metal plate has at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer.

[0023]

[18] A switching power supply device comprising a power clamper including the semiconductor device according to any one of [1] to

[17] above. Effect of the Invention

[0024] According to various aspects of the present invention, it is possible to provide a semiconductor device capable of suppressing the generation of noise in the GHz band, and a switching power supply device including the semiconductor device. [Brief description of the drawings]

[0025] [Figure 1] 2. FIG. 2 is a cross-sectional view taken along line 2-2 shown in FIG. [Diagram 2] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 3] This is a modification in which the depth of the second P+ type impurity diffusion layer 14 shown in FIG. 1 is changed. [Figure 4] This is a modification in which the depth of the second P+ type impurity diffusion layer 14 shown in FIG. 1 is changed. [Diagram 5] 2 is a cross-sectional view showing the structure above an N-type epitaxial layer 12 shown in FIG. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8]FIG. 2 is a diagram showing a typical concentration distribution of an impurity introduced for forming a semiconductor device according to one embodiment of the present invention. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view showing a mesa diode for voltage clamping of a conventional power clamper. [Figure 12] FIG. 1 is a cross-sectional view showing a conventional planar diode. [Figure 13] 1 is a circuit diagram illustrating a switching power supply device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram showing a switching power supply device using a DCR snubber of a comparative example. [Figure 15] FIG. 2 is a diagram showing the results of an experiment conducted on the generation of noise in the GHz band (1 GHz to 6 GHz) from a sample of the voltage clamp planar diode shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0027] (First embodiment) <Planar diode for voltage clamping> Fig. 2 is a plan view showing a semiconductor device according to one embodiment of the present invention. Fig. 1 is a cross-sectional view taken along line 2-2 shown in Fig. 2. Reference characters A to F shown in Fig. 1 correspond to reference characters A to F shown in Fig. 2, and the dashed lines shown in Figs. 1 and 2 are intended to make it easier to understand the relationship between the cross-sectional view shown in Fig. 1 and the plan view shown in Fig. 2. However, Fig. 2 is a cross-sectional view of N ++ A first P type silicon substrate 11+ type impurity diffusion layer 13, second P + Only the type impurity diffusion layer 14 and the Al layer 16 are shown, and the other parts are not shown.

[0028] 3 and 4 are diagrams showing the second P shown in FIG. + This is a modified example in which the depth of the first P type impurity diffusion layer 14 is changed. + The second P + Only the type impurity diffusion layers 14a and 14b are shown, and the rest of the configuration is the same as in FIG.

[0029] FIG. 5 shows the N-type epitaxial layer 12 and above shown in FIG. 1, and the rest of the configuration is the same as that shown in FIG. FIG. 8 shows the second P shown in FIGS. + The concentration gradient [0] of the impurity in the first P type impurity diffusion layers 14, 14a, and 14b is + 1 is a diagram for explaining that the impurity concentration gradient of the type impurity diffusion layer 13 is gentler than [0].

[0030] The semiconductor device shown in FIG. 1 is a voltage clamp planar diode. ++ The semiconductor device has a first conductivity type silicon substrate 11 (also called a "first conductivity type semiconductor substrate"). ++ An N-type epitaxial layer 12 (also referred to as a "first conductive type semiconductor layer") is formed on a silicon substrate 11. A first P + In addition, a second P type impurity diffusion layer 13 (also referred to as a "first second conductive type diffusion layer") is formed in the N type epitaxial layer 12. + A second P type impurity diffusion layer 14 (also referred to as a "second second conductivity type diffusion layer") is formed. + The type impurity diffusion layer 14 is a first P + 2, the first P +The second P-type impurity diffusion layer 13 is disposed so as to surround the second P-type impurity diffusion layer 13. During clamping operation, a current flows in a semiconductor region located under a metal plate, which will be described later. + The first P type impurity diffusion layer 14 + The second P + The first P type impurity diffusion layer 14 + The second P type impurity diffusion layer 13 or + The first P + The second P-type impurity diffusion layer 13 is formed so that a breakdown phenomenon (Zener breakdown phenomenon, avalanche breakdown phenomenon, or a mixture of Zener breakdown phenomenon and avalanche breakdown phenomenon) occurs near the contact portion of the second P-type impurity diffusion layer 13. In order to realize this, as detailed typical examples, the relationship between (2) shown in FIG. 8 and (1) shown in FIG. 8, (3) shown in FIG. 8 and (1) shown in FIG. 8, (4) shown in FIG. 8 and (1) shown in FIG. 8, or (5) shown in FIG. 8 and (1) shown in FIG. 8 is used. + The concentration gradient [0] of the impurity in the first P-type impurity diffusion layer 14 is + The impurity concentration gradient is formed more gently [0] than that of the PN junction type impurity diffusion layer 13. The impurity concentration gradient here refers to the absolute value of the rate of change of the impurity concentration which changes as one approaches the PN junction. Note that in FIG. 8, a typical Gaussian type change is assumed, and the impurity concentration simply decreases in the depth direction, but as long as the breakdown phenomenon occurs as described above, any impurity concentration distribution is acceptable, and the example is not limited to that shown in FIG. 8. This is also true for other embodiments of the present invention. + The first P type impurity diffusion layer 14 + The surface concentration may be higher, equal to, or lower than that of the first P type impurity diffusion layer 13. + It is preferable that the impurity diffusion layer 14 is formed so as to diffuse deeper than the type impurity diffusion layer 13 . In addition, the first and second P +Each of the P-type impurity diffusion layers 13 and 14 may be formed, for example, by placing a diffusion source of a P-type impurity on the surface of the N-type epitaxial layer 12 and thermally diffusing the P-type impurity into the N-type epitaxial layer 12, or by ion-implanting the P-type impurity into the N-type epitaxial layer 12 and then thermally diffusing the P-type impurity.

[0031] As shown in FIG. + The planar shape of the second P-type impurity diffusion layer 13 as viewed from above is a quadrangle with arcuate or rounded corners. + The planar shape of the first P type impurity diffusion layer 14 is + The second P + The outline of the planar shape of the first P type impurity diffusion layer 14 is + 1 is an enlarged outline of the planar shape of the type impurity diffusion layer 13.

[0032] As shown in Figure 1, the second P + The first P type impurity diffusion layer 14 + It is preferable that the second P + The first P-type impurity diffusion layer 14a + The second P type impurity diffusion layer 13 may be formed at the same depth as the first P type impurity diffusion layer 13, or may be formed at the same depth as the second P type impurity diffusion layer 13 as shown in FIG. + The first P-type impurity diffusion layer 14b is + 3 (corresponding to (4) in FIG. 8) has a more gentle impurity concentration gradient than the first P+ type impurity diffusion layer 13 (corresponding to (1) in FIG. 8) shown in FIG. 3. Also, the second P+ type impurity diffusion layer 14b (corresponding to (6) in FIG. 8) shown in FIG. 4 has a more gentle impurity concentration gradient than the first P+ type impurity diffusion layer 13 (corresponding to (1) in FIG. 8) shown in FIG. 4. The second P + The depth of the second P type impurity diffusion layer 14 may be deep or shallow, but the effect of suppressing the generation of noise in the 1 to 6 GHz band can be obtained. + The first P type impurity diffusion layer 14 +It is expected that forming the dopant diffusion layer deeper than the type impurity diffusion layer 13 will improve the diode characteristics and also enhance the effect of suppressing the generation of noise in the 1 to 6 GHz band compared to forming the dopant diffusion layer at the same depth or at a shallower depth.

[0033] As shown in Figure 1, the second P + The second P type impurity diffusion layer 14 and + An insulating layer 15 is formed on the N-type epitaxial layer 12 outside the N-type impurity diffusion layer 14. The insulating layer 15 is made of, for example, SiO2, PSG (Phospho-Silicate Glass), or the like. + type impurity diffusion layer 13, second P + An Al layer 16 (also called a "metal plate") is formed on the type impurity diffusion layer 14 and the insulating layer 15. The Al layer 16 is a second P + The insulating layer 14 is formed so as to extend to the outside of the impurity diffusion layer 14 .

[0034] As shown in FIG. 1, the N-type epitaxial layer 12 contains N ++ An impurity diffusion layer 26 is formed. ++ The impurity diffusion layer 26 is a second P + Located outside the second P-type impurity diffusion layer 14 + The insulating layer 15 is formed apart from the second P-type impurity diffusion layer 14. + The N-type impurity diffusion layer 14, the N-type epitaxial layer 12 and the N ++ The insulating layer 15 and the N ++ An Al layer 32 is formed on the impurity diffusion layer 26. ++ Below the mold silicon substrate 11, a Ti / Ni metal layer 28 is formed by laminating a Ti layer and a Ni layer in this order.

[0035] A Ti / Ni metal layer 17 (also referred to as a "second metal layer"), which is formed by laminating a Ti layer and a Ni layer in order, is formed on the Al layer 16 (also referred to as a "first metal layer"), and this Ti / Ni metal layer 17 is electrically connected to the Al layer 16. As described above, the Al layer 16 may be used as a metal plate, but the Al layer 16 and the Ti / Ni metal layer 17 may be collectively referred to as a metal plate 18.

[0036] N ++ A polyimide film 27 is formed on the impurity diffusion layer 26, the insulating layer 15, and the Al layers 16 and 32. Solder 19 is formed on the Ti / Ni metal layer 17. In Fig. 1, the polyimide film 27 is not formed on the Ti / Ni metal layer 17, but the Ti / Ni metal layer 17 may be formed to extend toward the end of the Al layer 16, and the polyimide film 27 may also be formed on the Ti / Ni metal layer 17.

[0037] As described above, by forming the Ti / Ni metal layer 17 so as to extend toward the end of the Al layer 16, it is expected that the noise reduction effect can be increased.

[0038] As shown in Figure 1, mainly the first P + The opening 27a (in other words, mainly the first P + Alternatively, as shown in FIG. 5, an opening 27b of the polyimide film 27 in which the solder 19 is to be formed may be formed so as to be largely expanded toward the end of the Al layer 16, and the solder 19 may be formed in the opening 27b. In other words, the first P + type impurity diffusion layer 13, second P + A Ti / Ni metal layer 17 may be formed on each of the type impurity diffusion layer 14 and the insulating layer 15, and solder 19 may be formed on the Ti / Ni metal layer 17. By forming the solder 19 in this manner so as to be widely spread toward the end of the Al layer 16, it is possible to further increase the effect of suppressing the generation of noise in the 1 to 6 GHz band.

[0039] According to the above-mentioned voltage clamp planar diode, a first P + The first P type impurity diffusion layer 13 is located in the plan view. + The first P + The first P + A second P type impurity diffusion layer 13 has a higher breakdown voltage (for example, a lower impurity concentration). + The second P type impurity diffusion layer 14 is disposed. + The first P + The breakdown phenomenon can be caused in the first P type impurity diffusion layer 13. + By positioning the Al layer 16 as a metal plate on the type impurity diffusion layer 13 and the insulating layer 15, the metal plate exhibits a shielding effect. As a result, it is possible to suppress the generation of noise in the 1 to 6 GHz band from the voltage clamp planar diode, and a noise reduction effect is obtained.

[0040] In addition, in the voltage clamp planar diode shown in Figure 1, the second P + The depth of the first P type impurity diffusion layer 14 is + By making the layer deeper than the first P-type impurity diffusion layer 13, the breakdown phenomenon location is + The area can be made closer to the center than to the end of the type impurity diffusion layer 13. This can further increase the noise reduction effect.

[0041] 1, a Ti / Ni metal layer 17 is formed as a second metal layer on an Al layer 16 as a first metal layer, and the Ti / Ni metal layer 17 is electrically connected to the Al layer 16. Therefore, the Al layer 16 and the Ti / Ni metal layer 17 are combined to form a metal plate 18, which provides a shielding effect. As a result, it is possible to prevent the voltage clamp planar diode from emitting noise in the 1 to 6 GHz band, and a noise reduction effect is obtained.

[0042] Furthermore, solder 19 is formed on the Ti / Ni metal layer 17 of the metal plate 18, and the metal plate 18 is electrically connected to the solder 19. Therefore, the solder 19 and the metal plate 18 act together as a shield, which can suppress the emission of noise in the 1 to 6 GHz band from the voltage clamp planar diode.

[0043] 1 to 5, the impurity diffusion layer is formed by, for example, patterning an oxide film by etching using a photoresist film as a mask, depositing and doping impurities, and then performing a heat treatment. Each layer and polyimide film located on the N-type epitaxial layer 12 can be formed by, for example, a sputtering method, a CVD (Chemical Vapor Deposition) method, a coating method, an etching method, or the like.

[0044] Second embodiment <Planar diode for voltage clamping> Fig. 6 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention, and the cross section is taken along a plane corresponding to Fig. 1. In Fig. 6, the same parts as those in Fig. 1 are denoted by the same reference numerals, and description of the same parts will be omitted.

[0045] As shown in FIG. 6, the N-type epitaxial layer 12 (also called the "first conductive type semiconductor layer") has a P + A P-type impurity diffusion layer 13a (also referred to as a "second conductive type diffusion layer") is formed. + The term "type impurity diffusion layer 13a" also includes the end portion 13b. + An N-type buried layer 31 (also referred to as a "first conductive type buried layer") located in the N-type epitaxial layer 12 is formed below the P-type impurity diffusion layer 13a, and the N-type buried layer 31 has a higher impurity concentration than the N-type epitaxial layer 12. + In a plan view, the + The P-type impurity diffusion layer 13a is disposed inside the P-type impurity diffusion layer 13a. +An end 13b of the N-type impurity diffusion layer 13a is not in contact with the N-type buried layer 31, but is in contact with the N-type epitaxial layer 12, and is a P + The N-type impurity diffusion layer 13 a is disposed so as to surround a portion in contact with the N-type buried layer 31 .

[0046] In plan view, the P + The end 13b of the P-type impurity diffusion layer and + An insulating layer 15 is formed on the N-type epitaxial layer 12 outside the end 13b of the P-type impurity diffusion layer. + type impurity diffusion layer 13a, P + On the end portion 13b of the type impurity diffusion layer and the insulating layer 15, an Al layer 16 (also called a “metal plate”) is formed.

[0047] According to this embodiment, the N-type buried layer 31 is P + The P-type impurity diffusion layer 13a is formed on the inner side of the P + The P-type impurity diffusion layer 13a and the N-type buried layer 31 are in contact with each other. + An end 13b of the N-type impurity diffusion layer 13a contacts the N-type epitaxial layer 12. Since the N-type epitaxial layer 12 has a lower impurity concentration than the N-type buried layer 31, the P + The end 13b of the P-type impurity diffusion layer 13a is in contact with the N-type buried layer 31. + The breakdown voltage is higher than that of the P-type impurity diffusion layer 13a. + The P type impurity diffusion layer 13a is located closer to the center than the end 13b. + The breakdown phenomenon can be caused in the P-type impurity diffusion layer 13a. + By forming an Al layer 16 as a metal plate on the type impurity diffusion layer 13a and the insulating layer 15, the Al layer 16 exhibits a shielding effect. As a result, it is possible to suppress the generation of noise in the 1 to 6 GHz band from the voltage clamp planar diode, thereby obtaining a noise reduction effect.

[0048] (Third embodiment) <Mesa-type diode for voltage clamping> Fig. 7 is a cross-sectional view showing a semiconductor device according to one aspect of the present invention. The semiconductor device shown in Fig. 7 is a voltage clamping mesa diode, and the same parts as those in Fig. 11 are given the same reference numerals and description of the same parts is omitted. The voltage clamping mesa diode shown in Fig. 7 is a conventional voltage clamping mesa diode shown in Fig. 11 with the features of the first embodiment shown in Fig. 1 added.

[0049] The voltage clamp mesa diode shown in Figure 7 is N ++ The semiconductor device has a first conductivity type silicon substrate 101 (also called a "first conductivity type semiconductor substrate"). ++ An N-type epitaxial layer 102 (also called a "first conductive type semiconductor layer") is formed on a silicon substrate 101. A first P ++ In addition, a second P type impurity diffusion layer 13 (also referred to as a "first second conductive type diffusion layer") is formed in the N type epitaxial layer 102. + A second P type impurity diffusion layer 14 (also referred to as a "second second conductivity type diffusion layer") is formed. + The type impurity diffusion layer 14 is a first P + The first P + The second P-type impurity diffusion layer 13 is disposed so as to surround the second P-type impurity diffusion layer 13. During clamping operation, a current flows in a semiconductor region located under a metal plate, which will be described later. + The first P type impurity diffusion layer 14 + The second P + The first P type impurity diffusion layer 14 + The second P type impurity diffusion layer 13 or + The first P +The second P-type impurity diffusion layer 13 is formed so that a breakdown phenomenon (Zener breakdown phenomenon, avalanche breakdown phenomenon, or a mixture of Zener breakdown phenomenon and avalanche breakdown phenomenon) occurs near the contact portion of the second P-type impurity diffusion layer 13. In order to realize this, as detailed typical examples, a relationship between (2) shown in FIG. 3 and (1) shown in FIG. 3, (3) shown in FIG. 3 and (1) shown in FIG. 3, (4) shown in FIG. 3 and (1) shown in FIG. 3, or (5) shown in FIG. 3 and (1) shown in FIG. 3 is formed so that a breakdown phenomenon (Zener breakdown phenomenon, avalanche breakdown phenomenon, or a mixture of Zener breakdown phenomenon and avalanche breakdown phenomenon) occurs near the contact portion of the second P-type impurity diffusion layer 13. + The concentration gradient [0] of the impurity in the first P-type impurity diffusion layer 14 is + The impurity concentration gradient in the second P-type impurity diffusion layer 13 is gentler than that in the first P-type impurity diffusion layer 13. The impurity concentration gradient here refers to the absolute value of the rate of change of the impurity concentration as it approaches the PN junction. Note that in FIG. 3, a typical Gaussian type change is assumed, and the impurity concentration simply decreases in the depth direction, but as long as the breakdown phenomenon occurs as described above, any impurity concentration distribution is acceptable, and is not limited to the example shown in FIG. 3. This also applies to other embodiments of the present invention. + The first P type impurity diffusion layer 14 + The surface concentration may be higher, equal to, or lower than that of the first P type impurity diffusion layer 13. + It is preferable that the impurity diffusion layer 14 is formed so as to diffuse deeper than the type impurity diffusion layer 13 .

[0050] As shown in FIG. + The second P type impurity diffusion layer 14 and + An insulating layer 105 is formed on the N-type epitaxial layer 102 outside the first P-type impurity diffusion layer 14. + type impurity diffusion layer 13, second P + An Al layer 16 (also called a "metal plate") is formed on the type impurity diffusion layer 14 and the insulating layer 15. The Al layer 16 is a second P + The insulating layer 14 is formed so as to extend to the outside of the impurity diffusion layer 14 .

[0051] A Ti / Ni metal layer 17 (also referred to as a "second metal layer") is formed on the Al layer 16 (also referred to as a "first metal layer"), and the Ti / Ni metal layer 17 is electrically connected to the Al layer 16. As described above, the Al layer 16 may be used as a metal plate, but the Al layer 16 and the Ti / Ni metal layer 17 may be collectively referred to as a metal plate 18.

[0052] A polyimide film 27 is formed on the insulating layer 105 and the Al layer 16. Solder 19 is formed on the Ti / Ni metal layer 17.

[0053] In this embodiment, the same effects as in the first embodiment can be obtained.

[0054] (Fourth embodiment) <Mesa-type diode for voltage clamping> Fig. 9 is a cross-sectional view showing a semiconductor device according to one aspect of the present invention, in which the same parts as those in Fig. 7 are given the same reference numerals and the description of the same parts will be omitted. The semiconductor device shown in Fig. 9 is a voltage clamping mesa diode, which is obtained by adding the features of the second embodiment shown in Fig. 6 to the conventional voltage clamping mesa diode shown in Fig. 11.

[0055] As shown in FIG. 9, the N-type epitaxial layer 102 (also called the "first conductive type semiconductor layer") has a P + A P type impurity diffusion layer 13a (also referred to as a "second conductive type diffusion layer") is formed. + An N-type buried layer 31 (also referred to as a "first conductive type buried layer") located in the N-type epitaxial layer 102 is formed under the P-type impurity diffusion layer 13a, and the N-type buried layer 31 has a higher impurity concentration than the N-type epitaxial layer 102. + In a plan view, the + The P-type impurity diffusion layer 13a is disposed inside the P-type impurity diffusion layer 13a. + An end 13b of the N-type impurity diffusion layer 13a is not in contact with the N-type buried layer 31, but is in contact with the N-type epitaxial layer 102, and is a P +The N-type impurity diffusion layer 13 a is disposed so as to surround a portion in contact with the N-type buried layer 31 .

[0056] In plan view, the P + The end 13b of the P-type impurity diffusion layer and + An insulating layer 105 is formed on the N-type epitaxial layer 102 outside the end 13b of the P-type impurity diffusion layer. + type impurity diffusion layer 13a, P + On the end portion 13b of the type impurity diffusion layer and the insulating layer 15, an Al layer 16 (also called a “metal plate”) is formed.

[0057] In this embodiment, the same effects as in the second embodiment can be obtained.

[0058] Fifth embodiment <Resin-encapsulated semiconductor device> FIG. 10 is a cross-sectional view that illustrates a semiconductor device according to one embodiment of the present invention.

[0059] The semiconductor device shown in FIG. ++ A first conductivity type silicon substrate 11 (also referred to as a "first conductivity type semiconductor substrate") and a second conductivity type silicon substrate 12 (also referred to as a "first conductivity type semiconductor substrate") are ++ A metal plate 18 is formed on the silicon substrate 11, a first lead wire 21 is formed on the metal plate 18 and electrically connected to the metal plate 18 by solder 19, and an N ++ The second lead 22 is electrically connected to the silicon substrate 11. The second lead 22 is electrically connected to an electrode 33 by solder 34, the electrode 33 being an N ++ The metal plate 18 is electrically connected to the molded silicon substrate 11. The metal plate 18 is preferably a plate having at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer.

[0060] N shown in Figure 10 ++ The mold silicon substrate 11, the metal plate 18 and the solder 19 can be applied to the semiconductor devices according to the first to fourth embodiments shown in FIGS.

[0061] Furthermore, N shown in FIG. ++ The N-type silicon substrate 11 may be a conventional voltage clamp mesa diode as shown in FIG. ++ A silicon substrate 101 and its N ++ An N-type epitaxial layer 102 is formed on a silicon substrate 101, and a P-type epitaxial layer 103 is formed on the surface side of the N-type epitaxial layer 102. ++ The P diffusion layer 103 and its ++ A voltage clamping mesa diode having a first metal film 104 (also called a "metal plate") formed on the type diffusion layer 103 may be applied.

[0062] In addition, a portion of each of the first lead wire 21 and the second lead wire 22, N ++ The mold silicon substrate 11 and the metal plate 18 are sealed with a resin 23 .

[0063] The surface of the resin 23 is covered with a shielding film 24, and the shielding film 24 is in contact with at least one of the first lead wire 21 and the second lead wire 22. The shielding film 24 is, for example, Shin-Etsu Resin: KMC140-9 or Kaken Tech shielding paste (CR-3911, 3913, 3915, 4000 to 4002).

[0064] Furthermore, the resin 23 is mixed with a material 35 having a higher dielectric constant than the resin 23. In Fig. 10, the material 35 having a higher dielectric constant is shown with three dots, but it is preferable that the material 35 having a higher dielectric constant is mixed with the resin 23 with good uniformity.

[0065] According to this embodiment, by covering the surface of the resin 23 with a shielding film 24 that contacts at least one of the first lead wire 21 and the second lead wire 22, the GHz band noise emitted from the diode can be confined within the resin 23, thereby achieving a noise reduction effect.

[0066] In this embodiment, a part of each of the first lead wire 21 and the second lead wire 22, N ++ The molded silicon substrate 11 and the metal plate 18 are sealed with resin 23, and a material with a high dielectric constant is mixed into this resin 23, so that the material with a high dielectric constant absorbs GHz band noise emitted from the diode, thereby preventing the noise from being emitted outside the resin 23.

[0067] Sixth embodiment <Switching power supply unit> Fig. 13 is a circuit diagram showing a switching power supply device according to one embodiment of the present invention, and Fig. 14 is a circuit diagram showing a switching power supply device using a DCR snubber 61 of a comparative example. The switching power supply device shown in Fig. 13 includes a power clamper 51 including the semiconductor devices according to the first to fifth embodiments. The switching power supply device shown in Fig. 13 is obtained by replacing the DCR snubber 61 shown in Fig. 14 with the power clamper 51, and is mainly used in hard switching flyback power supply circuits and is applied to, for example, standby power supplies for televisions and copiers, indoor unit power supplies for air conditioners, etc. The configurations of FIGS. 13 and 14 will be described below. As shown in FIG. 14, an input voltage V INis applied to the DCR snubber 61. One electrode of the capacitor 54 is electrically connected to one end of the resistor 62 of the DCR snubber 61 and one electrode of the capacitor 63. The other end of the resistor 62 is electrically connected to the other electrode of the capacitor 63 and the cathode of the fast recovery diode 64. The anode of the fast recovery diode 64 is electrically connected to one end of the primary winding of the transformer 56 and one electrode of the switching element 57. The other electrode of the switching element 57 is electrically connected to the other electrode of the capacitor 54. In addition, one electrode of the capacitor 63 is electrically connected to one end of the parasitic inductor 55, and the other end of the parasitic inductor 55 is electrically connected to the other end of the primary winding of the transformer 56. One end of the secondary winding of the transformer 56 is electrically connected to the anode of the diode 58, and the cathode of the diode 58 is electrically connected to one electrode of the capacitor 59. The other electrode of the capacitor 59 is electrically connected to the other end of the secondary winding of the transformer 56, and an output voltage V OUT will be output. The switching power supply device shown in FIG. 13 differs from the switching power supply device shown in FIG. 14 only in the following respects. 13, one electrode of the capacitor 54 is electrically connected to the anode of the Zener diode (avalanche diode) 53 of the power clamper 51 and one end of the parasitic inductor 55. The cathode of the Zener diode 53 is electrically connected to the cathode of the fast recovery diode 52. The anode of the fast recovery diode 52 is electrically connected to one end of the primary winding of the transformer 56 and one electrode of the switching element 57.

[0068] The above first to sixth embodiments can also be implemented in combination with one another. EXAMPLES

[0069] Fig. 15 is a diagram showing the results of an experiment conducted on the generation of noise in the GHz band (1 GHz to 6 GHz) from a sample of the voltage clamp planar diode shown in Fig. 1. Details of the sample are shown in Table 1.

[0070] [Table 1]

[0071] Ip shown in Figure 15 is the peak value of the breakdown current that flows due to the breakdown phenomenon of the diode. This graph plots the Ip value at which GHz-band noise begins to appear. It can be determined that the higher the Ip value, the greater the noise suppression effect.

[0072] The data in the box marked (1) is the second P shown in Figure 1. + The type impurity diffusion layer 14 has a ring structure as shown in FIG. 2, but the outer layer is the second P + The breakdown voltage of the second P + The peak values ​​of the breakdown current of the samples that broke down at the outer corner (ring portion) of the doped impurity diffusion layer 14. From the peak values ​​of the breakdown current of these three samples, it can be seen that the noise suppression effect is improved when the metal plate (Al layer 16) that is the field plate (FP) is longer on the outside in a plan view (see Table 1 and FIG. 15). The FP length is FP60 <FP80である。

[0073] The data in the box (2) are from the first P shown in Figure 1, which is the inner shallow diffusion layer (bulk). + The breakdown occurs in the first P-type impurity diffusion layer 13, but this is the peak value of the breakdown current of the sample without the metal plate (Al layer 16). + It can be seen that the noise generation suppression effect is improved by causing breakdown in the type impurity diffusion layer 13).

[0074] The data in the box (3) are from the first P shown in Figure 1, which is the inner shallow diffusion layer (bulk). +The peak values ​​of the breakdown current of the samples in which breakdown occurs in the type impurity diffusion layer 13 and which have a metal plate (Al layer 16) that is an FP. From the peak values ​​of the breakdown current of these four samples, it can be seen that the noise generation suppression effect is improved when the metal plate (Al layer 16) that is an FP is longer outward in a plan view (see Table 1 and FIG. 15).

[0075] The data in the box (4) is the result of using only the conventional planar diode structure shown in Figure 12, without FP. It is not the subject of comparison with the present invention. In Figure 12, the same parts as in Figure 6 are given the same symbols.

[0076] The data in the box enclosed in (5) is the peak breakdown current value of samples (6-1st_B+FP60, 6-1st_B+FP80) in which an FP (metal plate) is attached to the planar diode shown in Figure 12 of the 6-1st_B sample in (4).

[0077] The data in the box (6) is the outer layer, the second P + The impurity concentration of the type impurity diffusion layer 14 was lowered (secondary prototype), the breakdown voltage of the outer peripheral layer was increased, and the peak value of the breakdown current was the sample with the longest FP. + The breakdown occurred in the impurity diffusion layer13), which had the greatest effect in suppressing noise generation.

[0078] The data in the box (7) is the result of comparing the fast recovery diode (FRD) combined with the voltage clamp planar diode of samples 6-9 in (3) when it is placed in a separate package with the same package. It is not the subject of comparison for this invention.

[0079] Comparison of sample 1-1 in (1) with sample 6-1 in (2) and comparison of the six samples in (2) reveals that the inside (first P + It was confirmed that the noise generation was suppressed by causing breakdown in the impurity diffusion layer13).

[0080] It was confirmed that the longer the field plate is on the outside, the greater the effect of suppressing noise generation is, by comparing sample (1), sample (2) with sample (3), and sample (4) 6-1st_B with sample (5). The present invention has been described above based on the above embodiments and examples, but the present invention is not limited to the above embodiments. It is possible to implement the present invention in various aspects without departing from the spirit of the present invention. The numbers, materials, shapes, positions, sizes, and other aspects of the components described in the above embodiments are merely examples and can be changed without impairing the effects of the present invention. [Explanation of symbols]

[0081] 11 N ++ Silicon substrate (first conductivity type semiconductor substrate) 12 N-type epitaxial layer (first conductivity type semiconductor layer) 13 The First P + Type impurity diffusion layer (first second conductive type diffusion layer) 13a P + Type impurity diffusion layer (second conductive type diffusion layer) 13b P + End of the first conductive type impurity diffusion layer (end of the second conductive type diffusion layer) 14 The Second P + type impurity diffusion layer (second conductive type diffusion layer) 14b The second P + type impurity diffusion layer (second conductive type diffusion layer) 15 Insulating layer 16 Al layer (first metal layer, metal plate) 17 Ti / Ni metal layer (second metal layer) 18 Metal Plate 19 Solder 21 First Lead 22 Second Lead 23 Resin 24 Shielding film 31 N-type buried layer (first conductive type buried layer) 32 Aluminum layer 101 N ++Silicon substrate (first conductivity type semiconductor substrate) 102 N-type epitaxial layer (first conductivity type semiconductor layer) 105 Insulating layer

Claims

1. a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer; a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer; an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view; a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer; Including, the second second-conductivity-type diffusion layer has a depth greater than that of the first second-conductivity-type diffusion layer; a surface concentration of the second second-conductivity type diffusion layer being higher than that of the first second-conductivity type diffusion layer;

2. In claim 1, a second diffusion layer of the second conductivity type having an impurity concentration gradient that is gentler than that of the first diffusion layer of the second conductivity type;

3. A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer; a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer; an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view; a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer; Including, a depth of the second diffusion layer of the second conductivity type is shallower than a depth of the first diffusion layer of the second conductivity type.

4. In claim 3, a surface concentration of the second second-conductivity type diffusion layer being lower than a surface concentration of the first second-conductivity type diffusion layer;

5. A semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a first second conductivity type diffusion layer located on a surface side within the first conductivity type semiconductor layer; a second second-conductivity-type diffusion layer that is located in the first-conductivity-type semiconductor layer, that is in contact with the first second-conductivity-type diffusion layer in a plan view, that is disposed so as to surround the first second-conductivity-type diffusion layer, and that is formed so as to have a higher breakdown voltage than the first second-conductivity-type diffusion layer; an insulating layer located on the second second-conductivity type diffusion layer and on the semiconductor layer outside the second second-conductivity type diffusion layer in a plan view; a metal plate located on the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the insulating layer; Including, the second second-conductivity-type diffusion layer has a depth greater than that of the first second-conductivity-type diffusion layer; a surface concentration of the second second-conductivity type diffusion layer being lower than a surface concentration of the first second-conductivity type diffusion layer;

6. In any one of claims 1 to 5, The semiconductor device is characterized in that the metal plate has a first metal layer and a second metal layer located on the first metal layer, and the first metal layer is electrically connected to the second metal layer.

7. In any one of claims 1 to 6, A semiconductor device having solder located on said metal plate.

8. In claim 1, solder located on the metal plate; The semiconductor device according to claim 1, wherein the solder is located on the metal plate on each of the first second-conductivity type diffusion layer, the second second-conductivity type diffusion layer, and the insulating layer.

9. In any one of claims 1 to 8, a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; a shielding film covering a surface of the resin; having The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

10. In any one of claims 1 to 8, a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; having The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

11. a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer; a metal plate located on the second conductive type diffusion layer; a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; a shielding film covering a surface of the resin; having The semiconductor device according to claim 1, wherein the shielding film is in contact with at least one of the first lead wire and the second lead wire.

12. In claim 9 or 11, The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

13. a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type located on the semiconductor substrate; a second conductive type diffusion layer located on a surface side within the first conductive type semiconductor layer; a metal plate located on the second conductive type diffusion layer; a first lead wire electrically connected to the metal plate; a second lead wire electrically connected to the semiconductor substrate; a resin that seals a portion of each of the first lead wire and the second lead wire, the semiconductor substrate, and the metal plate; having The semiconductor device according to the present invention is characterized in that the resin contains a material having a higher dielectric constant than the resin.

14. In any one of claims 1 to 13, The semiconductor device according to the present invention, wherein the metal plate has at least one metal layer selected from the group consisting of an Al layer, a Ni layer, a Ti layer, an Au layer, and a laminate of a Ni layer and an Al layer.

15. A switching power supply comprising a power clamper including the semiconductor device according to claim 1 .

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