Semiconductor Device

Abstract

To suppress variations in a current flowing through a power MOSFET.SOLUTION: A semiconductor device includes a power MOS chip with a source electrode on the surface, and a control chip mounted on the power MOS chip, and in a region where a control chip of the source electrode is not mounted, a first row bonding pad and a second row bonding pad are formed when viewed from the first outer edge extending in a first direction of the power MOS chip toward the control chip side, and a distance from the second outer edge of the power MOS chip of the first row bonding pad extending in the second direction is longer than the distance from the second outer edge of the second row bonding pad.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a power semiconductor element. [Background technology]

[0002] Power semiconductor elements are used to drive loads such as motors, heaters, and lamps mounted on vehicles and to perform voltage conversion. Power semiconductor elements include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

[0003] From the viewpoint of functional safety, it is desirable for on-board semiconductor devices to be equipped with fault detection and protection functions. Therefore, semiconductor devices using power MOSFETs (or IGBTs) are equipped with a function to detect abnormal states such as overcurrent and overheating of the power MOSFET and to protect the power MOSFET, and a function to output self-diagnosis information to monitor the output state of the power MOSFET.

[0004] The semiconductor chip that mounts the power MOSFET (also called a power MOS chip) and the semiconductor chip that controls the power MOS chip and has protection and self-diagnosis output functions (also called a control chip) are composed of separate semiconductor chips. In recent years, in order to make products smaller and less expensive, products called IPDs (Intelligent Power Devices) that mount the power MOS chip and control chip in a single package have come into use.

[0005] Patent Document 1 discloses a technique for mounting a plurality of power MOS chips and a semiconductor chip mounting a drive circuit and a control circuit for the power MOSFET in one package. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-17620 A Summary of the Invention [Problem to be solved by the invention]

[0007] In Patent Document 1, multiple chips are arranged on a plane, but there are also IPDs with a stack structure in which a control chip is mounted on a power MOS chip. The following will be described with reference to Figs. 7 to 9. Fig. 7 is a plan view of a power MOS chip with a vertical structure. In the case of a power MOS chip with a vertical structure, most of the chip surface is covered with a source electrode 1. A drain electrode is provided on the back surface of the power MOS chip. Fig. 8 is a plan view of an IPD in which a control chip 2 is mounted on a power MOS chip 3 (a view in which the sealing body is made transparent). Fig. 9 is a cross-sectional view taken along line A-A' in Fig. 8. A source pad 4 is provided on the source electrode of the power MOS chip 3, and the lead 5 (source terminal) of the package and the source pad 4 are connected by a bonding wire 6. The drain electrode of the power MOS chip 3 is connected to the drain terminal of the package. When the control chip 2 is mounted on the power MOS chip 3, the area in which the source pad 4 is provided is limited. This is because the source pad 4 must be provided in an area of ​​the source electrode of the power MOS chip 3 that does not overlap with the control chip 2. In this case, there is a problem that the current flow varies depending on the location of the power MOS chip 3. This is because a larger current flows through a transistor formed near the source pad 4, and a smaller current flows through a transistor formed away from the source pad 4.

[0008] Current variation can lead to destruction of the power MOS chip or a decrease in its performance. Areas where a large current flows are more likely to be destroyed, while areas where a small current flows are less likely to contribute to reducing the on-resistance.

[0009] Other objects and novel features will become apparent from the description of this specification and the drawings. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment includes a power MOS chip having a source electrode on its surface, and a control chip mounted on the power MOS chip, and in an area of ​​the source electrode where the control chip is not mounted, a first row of bonding pads and a second row of bonding pads are formed, as viewed from a first outer edge extending in a first direction of the power MOS chip toward the control chip, and the distance of the first row of bonding pads from the second outer edge extending in a second direction of the power MOS chip is longer than the distance of the second row of bonding pads from the second outer edge. Effect of the Invention

[0011] In the semiconductor device according to one embodiment, it is possible to reduce the variation in the current flowing through the power MOSFET. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a plan view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a plan view of the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a plan view of a semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 7 is a plan view of a power MOS chip. [Figure 8] FIG. 8 is a plan view of a conventional semiconductor device. [Figure 9] FIG. 9 is a cross-sectional view of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and duplicated explanations are omitted. In addition, in the drawings, components may be omitted or simplified for convenience of explanation. In addition, at least a part of each embodiment may be combined with each other in any desired manner.

[0014] [Embodiment 1] (Configuration of Semiconductor Device) Fig. 1 is a plan view of an IPD 10 according to embodiment 1. For ease of understanding, Fig. 1 is a perspective view of a sealing body (resin) 14. As shown in Fig. 1, the IPD 10 has a control chip 11 and a power MOS chip 12. The control chip 11 is mounted on the power MOS chip 12.

[0015] The power MOS chip 12 is a vertical power MOSFET (or IGBT) with a source electrode on the front side and a drain electrode on the back side. Bonding pads P1 to P6 are provided on the front side of the power MOS chip 12. The bonding pads P1 to P5 are source pads. The bonding pad P6 is a gate pad. The bonding pads P1 and P2 are connected to a lead (terminal) L1 by bonding wires W1 and W2. The bonding pads P3 and P4 are connected to a lead L2 by bonding wires W3 and W4. The drain electrode on the back side of the power chip MOS 12 is connected to a lead frame 13.

[0016] The control chip 11 has bonding pads P7 to P10. The bonding pad P7 is connected to the bonding pad P5 by a bonding wire W5. The bonding pad P8 is connected to the bonding pad P6 by a bonding wire W6. The bonding pad P9 is connected to the lead L3 by a bonding wire W7. The bonding pad P10 is connected to the lead L4 by a bonding wire W8.

[0017] 2 is a block diagram of the IPD 10. The power MOS chip 12 has a power MOSFET 23, a sense MOSFET 22, and a temperature sensor 24. The sense MOSFET 22 is an element for detecting the current flowing through the power MOSFET 23. These elements are commonly used, so detailed description will be omitted.

[0018] The control chip 11 has a control circuit (Control Circuit) 15, a gate control circuit (Gate Control) 16, a current detection circuit (Current Detector) 17, a voltage detection circuit (Voltage Sense) 18, a current detection circuit (Current Sense) 19, a voltage generation circuit (Voltage Supply) 20, and an ESD protection circuit 21. The control circuit 15 and the gate control circuit 16 generate gate signals for a power MOSFET 23 and a sense MOSFET 22 in response to an input signal (IN) from the outside. The current detection circuit 17 detects a current flowing through the source of the sense MOSFET 22. The voltage detection circuit 18 detects a source voltage (output voltage) of the power MOSFET 23. The control circuit 15 generates a gate signal by referring to the output results of the current detection circuit 17, the voltage detection circuit 18, and the temperature sensor 24. The current detection circuit 19 detects a current flowing through the sense MOSFET 22, and outputs the detection result from an output terminal IS.

[0019] Returning to FIG. 1 for further explanation, the bonding pad P8 is connected to the output of the gate control circuit 16. The gate pad P6 is connected to the gates of the power MOSFET 23 and the sense MOSFET 22. The bonding pad P7 is connected to the input of the current detection circuit 17. The bonding pad P5 is connected to the source of the sense MOSFET 22. The bonding pad P10 is connected to the input of the control circuit 15. The bonding pad P9 is connected to the output of the current detection circuit 19. For simplification, FIG. 1 omits some of the connections between the control chip 11 and the power MOS chip 12.

[0020] Next, the bonding pads P1 to P4, which are a feature of the first embodiment, will be described. As shown in FIG. 1, the bonding pads P1 to P4 are formed in an area of ​​the power MOS chip 12 where the control chip 11 is not mounted. Counting from the outer edge of the power MOS chip 12 along the Y axis toward the control chip 11 side, the bonding pads P1 and P2 are the first row of bonding pads (C1), and the bonding pads P3 and P4 are the second row of bonding pads (C2). Compared with the second row of bonding pads, the first row of bonding pads is formed further inward from the outer edge of the power MOS chip 12 along the X axis. In other words, the distance d1 of the first row of bonding pads from the outer edge along the X axis is longer than the distance d2 of the second row of bonding pads from the outer edge along the X axis.

[0021] Compared with the bonding pads P1 and P2, the bonding pads P3 and P4 inevitably contribute more to the current flowing through the power MOSFET formed under the control chip 11. In other words, the bonding pads P3 and P4 have a larger area of ​​the source electrode. Also, the bonding pads P1 and P2 have a smaller area of ​​the source electrode. This causes the current flowing through the power MOSFET to vary. In the first embodiment, the bonding pads P1 and P2 are formed at positions farther away from the corners of the power MOS chip 12 than in the past, and at positions farther away from the bonding pads P3 and P4, thereby widening the area of ​​the source electrode covered by the bonding pads P1 and P2. By widening the source electrode covered by the bonding pads P1 and P2, the area of ​​the source electrode covered by the bonding pads P3 and P4 becomes narrower. Therefore, it is possible to suppress the variation in the current flowing through the power MOSFET more than in the past.

[0022] In FIG. 1, the bonding pads P1 to P4 are formed in two rows, with two bonding pads per row. However, this is not limited thereto. The bonding pads may be formed in three or more rows, with three or more bonding pads per row. FIG. 3 is a plan view of the case where there are three rows of bonding pads, with three bonding pads per row. In FIG. 3, bonding pads (source pads) P11 to P15, bonding wires W9 to W13, and a lead L5 are added compared to FIG. 1. The bonding pads in the first row are formed on the inner side of the bonding pads in the second row, as in FIG. 1. By increasing the number of bonding pads, it is possible to further suppress the variation in the current flowing through the power MOSFET.

[0023] (effect) As described above, in the IPD 10 of the first embodiment, the bonding pads in the first row are formed further inward than the bonding pads in the second row, which makes it possible to suppress variations in the current flowing through the power MOSFET.

[0024] [Embodiment 2] (Configuration of Semiconductor Device) 4 is a plan view of an IPD 10a according to embodiment 2. The difference from embodiment 1 is that the control chip 11 is mounted near the center of the power MOS chip 12. More precisely, the control chip 11 is mounted near the center of the power MOS chip 12 on the X-axis.

[0025] In Fig. 4, bonding pads (source pads) P16 to P19, bonding wires W14 to W17, and leads L6 and L7 are added compared to Fig. 1. The bonding pads P16 and P17 are connected to the lead L6 by bonding wires W14 and W15. The bonding pads P18 and P19 are connected to the lead L7 by bonding wires W16 and W17.

[0026] The bonding pads P1 to P4 are formed in a first region of the power MOS chip 12 where the control chip 11 is not mounted. The bonding pads P16 to P19 are formed in a second region of the power MOS chip 12 where the control chip 11 is not mounted. The first region is a region between a first outer edge of the power MOS chip 12 along the Y axis and the control chip 11. The second region is a region between a second outer edge of the power MOS chip 12 along the Y axis and the control chip 11.

[0027] As in the first embodiment, counting from the first outer edge of the power MOS chip 12 along the Y axis toward the control chip 11, the bonding pads P1 and P2 are the first row of bonding pads, and the bonding pads P3 and P4 are the second row of bonding pads. Similarly, counting from the second outer edge of the power MOS chip 12 along the Y axis toward the control chip 11, the bonding pads P18 and P19 are the first row (third row overall) of bonding pads (C3), and the bonding pads P16 and P17 are the second row (fourth row overall) of bonding pads (C4). The third row of bonding pads is formed in the same manner as the first row of bonding pads, and the fourth row of bonding pads is formed in the same manner as the second row of bonding pads. That is, compared to the fourth row of bonding pads, the third row of bonding pads is formed further inward from the outer edge of the power MOS chip 12 along the X axis. In other words, the third and fourth rows of bonding pads and the first and second rows of bonding pads are formed symmetrically with respect to the mounting point of the semiconductor chip (control chip 11).

[0028] When the control chip 11 is mounted near the center of the power MOS chip 12, the second embodiment makes it possible to further suppress the variation in the current flowing through the power MOSFET.

[0029] (effect) As described above, the IPD 10a of the second embodiment can provide the same effects as those of the first embodiment.

[0030] [Embodiment 3] (Configuration of Semiconductor Device) 5 is a plan view of an IPD 10b according to the embodiment 3. As in the embodiment 2, a bonding pad (source pad) is also formed on the left side of the control chip 11.

[0031] In Fig. 5, a first row (third row in total) of bonding pads (source pads) P22, bonding wires W18 to W19, and a lead L8 are added to the second region. In the first embodiment, the first row of bonding pads (C1) is composed of two bonding pads P1 and P2, and the second row of bonding pads (C2) is composed of two bonding pads P3 and P4. In Fig. 5, the first row of bonding pads is composed of one rectangular bonding pad P20, and the second row of bonding pads is composed of one rectangular bonding pad P21. And the third row of bonding pads P22 is connected to the lead L8 by bonding wires W18 and W19.

[0032] As in the first embodiment, the first row of bonding pads P20 are formed at a distance d1 from the outer edge along the X-axis of the power MOS chip 12, the second row of bonding pads P21 are formed at a distance d2 from that outer edge (d1>d2), and the third row of bonding pads P22 are formed at a distance d3 from that outer edge, where d1>d3>d2.

[0033] For the same reason as the first row of bonding pads, the third row of bonding pads P22 are formed away from the corners (upper left corner, lower left corner) of the power MOS chip 12, so that the area of ​​the source electrode covered by the bonding pad P22 can be increased. However, the first and second rows of bonding pads are formed on the right side of the control chip 11, but only the bonding pad P22 is formed on the left side of the control chip 11. In other words, both the first and second rows of bonding pads can contribute to the source electrode near the upper right corner and lower right corner of the power MOS chip 12, but only the bonding pad P22 can contribute to the source electrode near the upper left corner and lower left corner of the power MOS chip 12. Therefore, by making d1>d3>d2, the area of ​​the source electrode covered by the bonding pad P22 is increased and the contribution to the source electrode at the corners is increased.

[0034] (effect) As described above, the IPD 10b of the third embodiment can achieve more advantageous effects than those of the first embodiment.

[0035] [Embodiment 4] (Configuration of Semiconductor Device) 6 is a plan view of an IPD 10c according to embodiment 4. The difference from embodiment 1 is that six rows of bonding pads C1 to C6 are formed on the right side of the control chip 11.

[0036] The first row of bonding pads C1 and the second row of bonding pads C2 are the same as those in the first embodiment. The third row of bonding pads C3 is composed of bonding pads (source pads) P23 and P24. The fourth row of bonding pads C4 is composed of bonding pads (source pads) P25 and P26. The fifth row of bonding pads C5 is composed of bonding pads (source pads) P27 and P28. The sixth row of bonding pads C6 is composed of bonding pads (source pads) P29 and P30.

[0037] The bonding pad C3 in the third column is connected to the lead L9 by bonding wires W20 and W21. The bonding pad C4 in the fourth column is connected to the lead L10 by bonding wires W22 and W23. The bonding pad C5 in the fifth column is connected to the lead L11 by bonding wires W24 and W25. The bonding pad C6 in the sixth column is connected to the lead L12 by bonding wires W26 and W27.

[0038] As shown in FIG. 6, the distances d1, d3, d5 from the outer edge along the X-axis of the power MOS chip 12 of the odd-numbered bonding pads C1, C3, C5 gradually decrease (d1 > d3 > d5). Also, the distances d2, d4, d6 from the outer edge along the X-axis of the power MOS chip 12 of the even-numbered bonding pads C2, C4, C6 gradually increase (d2 < d4 < d6). This is because the influence of the corners (upper right corner, lower right corner) of the power MOS chip 12 gradually decreases.

[0039] According to the fourth embodiment, when forming bonding pads of three or more columns, it becomes possible to suppress the variation in the current flowing through the power MOSFET.

[0040] Note that the number of bonding pads may be six or more. Also, the bonding pads in each column (C1 to C6) may be composed of three or more bonding pads, or may be composed of one rectangular bonding pad as in the third embodiment.

[0041] (Effect) As described above, in the IPD10c of the fourth embodiment, it is possible to obtain the effects of the first or more embodiments.

[0042] Note that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0043] 10, 10a, 10b, 10c IPD 11 Control chip 12 Power MOS chip 13 Lead frame 14 Sealing body 15 Control circuit 16 Gate control circuit 17 Current detection circuit 18 Voltage detection circuit 19 Current detection circuit 20 Voltage Generation Circuit 21 ESD protection circuit 22 Sense MOSFET 23 Power MOSFET 24 Temperature Sensor P1~P30 Bonding pads C1 1st row bonding pad C2 2nd row bonding pad C3 3rd row bonding pad C4 4th row bonding pad C5 5th row bonding pad C6 6th row bonding pad W1~W27 Bonding wire L1~L12 leads

Claims

1. a power MOS chip having a source electrode on a surface thereof; A semiconductor device having a control chip mounted on the power MOS chip, In a region of the source electrode where the control chip is not mounted, a first row of bonding pads and a second row of bonding pads are formed as viewed from a first outer edge extending in a first direction of the power MOS chip toward the control chip; a distance from a second outer edge of the power MOS chip to the first row of bonding pads in a second direction is longer than a distance from the second outer edge of the power MOS chip to the second row of bonding pads; Semiconductor device.

2. the power MOS chip has a first bonding pad and a second bonding pad; the control chip has a third bonding pad and a fourth bonding pad; the first bonding pad is connected to the third bonding pad by a first bonding wire; the second bonding pad is connected to the fourth bonding pad by a second bonding wire; The semiconductor device according to claim 1 .

3. the power MOS chip has a first region and a second region in the source electrode where the control chip is not mounted; the first region is a region between the first outer edge and the control chip; the second region is a region between a third outer edge of the power MOS chip extending in the first direction and the control chip, the first row of bonding pads and the second row of bonding pads are formed in the first region; A third row of bonding pads is further formed in the second region. The semiconductor device according to claim 2 .

4. A fourth row of bonding pads is further formed in the second region; the first row of bonding pads, the second row of bonding pads, the third row of bonding pads, and the fourth row of bonding pads are formed symmetrically with respect to a mounting point of the control chip; The semiconductor device according to claim 3 .

5. Each of the first row of bonding pads and the second row of bonding pads is composed of a plurality of bonding pads. The semiconductor device according to claim 2 .

6. each of the first row of bonding pads, the second row of bonding pads, and the third row of bonding pads is formed of a rectangular bonding pad; The semiconductor device according to claim 3 .

7. a distance of the third row of bonding pads from the second outer edge is shorter than a distance of the first row of bonding pads from the second outer edge and longer than a distance of the second row of bonding pads from the second outer edge; The semiconductor device according to claim 3 .

8. In the area where the control chip is not mounted, a plurality of rows of bonding pads are further formed; When viewed from a first outer edge of the power MOS chip toward the control chip, the distance of the bonding pads in odd-numbered rows from the second outer edge gradually decreases, When viewed from a first outer edge of the power MOS chip toward the control chip, the bonding pads in even-numbered rows are spaced apart from the second outer edge in a gradually increasing distance. The semiconductor device according to claim 2 .

9. The semiconductor device is an IPD (Intelligent Power Device). The semiconductor device according to claim 2 .

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