Wiring Board

Abstract

A method for manufacturing a wiring board that can be manufactured with a high yield by improving the yield in the step of peeling off a support is provided. [Solution] This is a method for manufacturing a wiring board in which a bonding process is performed to bond a bonding portion 18a of an FC-BGA wiring board 1 to a bonding portion 18b of an interposer 3, followed by a resin supplying process to fill an underfill 2A between the FC-BGA wiring board 1 and the interposer 3, a resin hardening process to harden the underfill 2A, and a support peeling process to peel a support 5 from the interposer 3, in which the support peeling process is performed first, followed by the resin supplying process, and then the resin hardening process.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] In recent years, with the progress of high speed and high integration of semiconductor devices, there is a demand for narrower pitch of connection terminals with semiconductor elements and finer board wiring for FC-BGA (Flip Chip-Ball Grid Array) wiring boards. On the other hand, there is a demand for connection between FC-BGA wiring boards and motherboards with connection terminals at almost the same pitch as before.

[0003] In order to narrow the pitch of the connection terminals with the semiconductor element and to miniaturize the board wiring, for example, Patent Document 1 below proposes a method of forming wiring on silicon to make a board (silicon interposer) for connecting semiconductor elements, and connecting this to an FC-BGA wiring board. Also, for example, Patent Document 2 below proposes a method of forming fine wiring after planarizing the surface of the FC-BGA wiring board by chemical mechanical polishing (CMP) or the like. Also, for example, Patent Document 3 below proposes a method of forming a board (interposer) with a fine wiring layer on a support, mounting it on an FC-BGA board, and then peeling off the support to form a narrow-pitch wiring board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2002-280490 A [Patent Document 2] JP 2014-225671 A [Patent Document 3] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0005] In the method disclosed in the above Patent Document 1, the silicon interposer is manufactured using a silicon wafer with equipment for semiconductor pre-processing. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from one wafer is small. Furthermore, the manufacturing equipment is expensive, so the interposer is also expensive. In addition, since the silicon wafer is a semiconductor, there is a problem that the transmission characteristics deteriorate.

[0006] The method disclosed in Patent Document 2 does not have the problem of deterioration in transmission characteristics as in Patent Document 1. However, there are problems with yield reduction due to a combination of manufacturing defects in FC-BGA wiring boards and defects during the highly difficult formation of fine wiring, and problems with mounting semiconductor elements due to warping and distortion of FC-BGA wiring boards.

[0007] The method disclosed in Patent Document 3 does not have the problem of deterioration of transmission characteristics as in the method disclosed in Patent Document 1, nor the problem of reduced yield as in the method disclosed in Patent Document 2. However, there is a problem that defects are likely to occur in the step of peeling off the support, which tends to reduce the yield.

[0008] The present invention has been made in consideration of the above problems, and has an object to provide a method for manufacturing a wiring board that can improve the yield in the step of peeling off the support and can manufacture the wiring board with a high yield. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, a method for manufacturing a wiring board according to the present invention is a method for manufacturing a wiring board in which a first wiring board is bonded to a bonding surface of a second wiring board having finer wiring than that of the first wiring board, and a semiconductor element is mounted on a surface of the second wiring board opposite to the bonding surface, the method comprising: a step of forming a first electrode to be bonded to the semiconductor element on a support body via a release layer; a step of forming a multilayer wiring layer on the first electrode, the multilayer wiring layer being formed by laminating a plurality of insulating resin layers and wiring layers; and a step of forming a second electrode to be bonded to the first wiring board on the multilayer wiring layer, thereby manufacturing the second wiring board; and a bonding step of bonding a third electrode of the first wiring board to be bonded to the second wiring board and the second electrode of the second wiring board; After performing the above, a resin supplying process of filling a gap between the first wiring board and the second wiring board with a sealing resin, a resin curing process of curing the sealing resin, and a support peeling process of peeling the support from the second wiring board via the peeling layer are performed, and one of the following is carried out: (1) the support peeling process is performed, and then the resin supplying process is performed, and then the resin curing process is performed; (2) the resin supplying process is performed, and then the support peeling process is performed, and then the resin curing process is performed; or (3) the resin supplying process is performed, and then the resin removal process is performed, and then the sealing resin adhering to the outer peripheral edges of the second wiring board, the peeling layer, and the support is removed, and then the resin curing process is performed, and then the support peeling process is performed. Effect of the Invention

[0010] According to the method for manufacturing a wiring board of the present invention, the yield in the step of peeling off the support is improved, and manufacturing can be performed with high yield. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by using a first embodiment of a method for manufacturing a wiring board according to the present invention. [Diagram 2] 1 is a cross-sectional view showing a schematic structure of an example of an interposer used in a first embodiment of a method for manufacturing a wiring board according to the present invention. [Figure 3A] 3A to 3C are cross-sectional views illustrating a manufacturing procedure for the interposer of FIG. 2. [Figure 3B] 3B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3A. [Figure 3C] 3C is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3B. [Figure 3D] 3D is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3C. [Figure 3E] 3D is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3D. [Figure 3F] 3E is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3E. [Figure 3G] 3F , and FIG. [Figure 3H] 3C is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3G. [Figure 3I] 3H is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3H. [Figure 3J] 3I and FIG. 3F are cross-sectional views illustrating the manufacturing procedure following FIG. 3I. [Figure 3K] 3A to 3J are cross-sectional views illustrating the manufacturing procedure following FIG. 3J. [Figure 3L] 3K is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3K. [Figure 3M] 3B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3L. [Figure 3N] 3B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 3M. [Figure 4A] 3N; FIG. [Figure 4B] 4B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 4A. [Figure 5A] 4C is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 4B. [Figure 5B] 5B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 5A. [Figure 5C] 5C is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 5C. [Figure 6]10 is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by using a second embodiment of a method for manufacturing a wiring board according to the present invention. FIG. [Figure 7A] 4B in a second embodiment of the method for manufacturing a wiring board according to the present invention. FIG. [Figure 7B] 7B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 7A. [Figure 7C] 7B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 7B. [Figure 7D] 7D is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 7C. [Figure 8] 11 is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by using a third embodiment of a method for manufacturing a wiring board according to the present invention. FIG. [Figure 9A] 4B in a third embodiment of the method for manufacturing a wiring board according to the present invention. FIG. [Figure 9B] 9B is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 9A. [Figure 9C] 9C is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 9B. [Figure 9D] 9D is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 9C. [Figure 9E] 9E is a cross-sectional view illustrating a manufacturing procedure subsequent to FIG. 9D. [Figure 10] 13A to 13C are cross-sectional views illustrating a manufacturing procedure of another example 3 in the third embodiment of the method for manufacturing a wiring board according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The embodiment of the method for manufacturing a wiring board according to the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiment described with reference to the drawings. Note that the drawings are appropriately exaggerated for ease of explanation.

[0013] First Embodiment A first embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to FIGS. 1, 2, 3A to 3N, 4A, 4B, and 5A to 5D.

[0014] The wiring board manufactured by the manufacturing method according to this embodiment has a first wiring board bonded to a bonding surface of a second wiring board having finer wiring than the first wiring board, and a semiconductor element mounted on the surface of the second wiring board opposite to the bonding surface.

[0015] 1, a semiconductor package 100 having a semiconductor element 4 mounted thereon has one surface (upper surface in FIG. 1) of an FC-BGA wiring board 1, which is a first wiring board, bonded to one surface (lower surface in FIG. 1) of an interposer 3, which is a second wiring board, by a bonding portion 18 such as a solder bump, a copper post (copper pillar) or a gold bump. The interposer 3 is a thin layer having fine wiring made only of a build-up wiring layer, which is a multi-layer wiring layer formed by laminating a plurality of insulating resin layers and wiring layers.

[0016] An underfill 2A, which is an adhesive insulating sealing resin, is filled in the gap between the FC-BGA wiring board 1 and the interposer 3. A semiconductor element 4 is bonded to the other side of the interposer 3 (the upper side in FIG. 1), i.e., the side opposite to the bonding surface to which the FC-BGA wiring board 1 is connected, by a bonding part 20 made of a copper pillar and its tip, such as solder. An underfill 21 is filled in the gap between the semiconductor element 4 and the interposer 3.

[0017] The underfill 2A is a material used for fixing the FC-BGA wiring board 1 and the interposer 3 and sealing the joint 18. For example, the underfill 2A may be a material obtained by adding silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like as a filler to one of epoxy resin, urethane resin, silicon resin, polyester resin, oxetane resin, and maleimide resin, or a resin in which two or more of these resins are mixed. The underfill 2A can be formed by filling the gap between the FC-BGA wiring board 1 and the interposer 3 with the liquid material and curing it.

[0018] The underfill 21 is an adhesive used to fix the semiconductor chip 4 and the interposer 3 and seal the joint 20, and is made of the same material as the underfill 2A. Note that instead of the underfills 2A and 21, which fill liquid resin by utilizing capillary action after bonding, it is also possible to use an anisotropic conductive film (ACF) or film-like connecting material (NCF), which is a sheet-like film that is placed before bonding and fills spaces during bonding, or a non-conductive paste (NCP), which is a liquid resin that is placed before bonding and fills spaces during bonding.

[0019] The spacing between each of the bonding portions 20 between the interposer 3 and the semiconductor element 4 is generally narrower than the spacing between each of the bonding portions 18 between the interposer 3 and the FC-BGA wiring board 1. For this reason, the other surface side (upper surface side in FIG. 1), i.e., the surface side to which the semiconductor element 4 is bonded, of the interposer 3 requires finer wiring than the one surface side (lower surface side in FIG. 1), i.e., the surface side to which the FC-BGA wiring board 1 is bonded.

[0020] For example, to support the use of current high bandwidth memory (HBM), the wiring width of the interposer 3 must be between 2 μm and 6 μm. To match the characteristic impedance to 50 Ω, if the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wiring will be 2.5 μm. The thickness of one layer, including the wiring, will be 4.5 μm, and if a five-layer interposer 3 is formed with this thickness, the total thickness of the interposer 3 will be about 25 μm.

[0021] As described above, the interposer 3 is thin, with a total thickness of about 25 μm, and it is difficult to bond it to the FC-BGA wiring board 1 in its original state, so it is effective to ensure rigidity by using the support 5. In addition, a flat support 5 is required to form wiring with a width and height of about 2 μm. For the above reasons, as shown in FIG. 2, the interposer 3 is formed on a rigid and flat support 5 via a release layer 6, a protective layer 7, and a seed layer 8. It is also possible to provide layers other than the release layer 6, the protective layer 7, and the seed layer 8 on the support 5.

[0022] A method for manufacturing the interposer 3 according to this embodiment (a second wiring board manufacturing process) will now be described with reference to FIGS. 3A to 3N.

[0023] First, as shown in FIG. 3A, a release layer 6 necessary for peeling off the support 5 in a later step is formed on one surface of the support 5.

[0024] The peeling layer 6 may be made of, for example, a resin that absorbs light such as UV light and generates heat or changes in quality to become peelable, or a resin that foams when heated to become peelable. When a resin that becomes peelable when exposed to light such as UV light is used, the support 5 can be removed from the bonded body of the interposer 3 and the FC-BGA wiring board 1 by irradiating the support 5 with light from the side opposite to the side where the peeling layer 6 is provided.

[0025] In this case, the support 5 must be optically transparent, and may be made of glass, for example. Glass has excellent flatness and is suitable for forming a fine pattern on the interposer 3. In addition, glass has a small coefficient of thermal expansion (CTE) and is not easily distorted, so it is excellent in ensuring pattern arrangement accuracy and flatness.

[0026] When glass is used as the support 5, the thickness of the glass is preferably thicker from the viewpoint of suppressing the occurrence of warping in the manufacturing process, and is preferably 0.7 mm or more, particularly preferably 1.1 mm or more. The CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and from the viewpoint of the CTE of the FC-BGA wiring board 1 and the semiconductor element 4, it is particularly preferably about 9 ppm.

[0027] On the other hand, when a resin that foams when heated is used for the release layer 6, the support 5 can be removed by heating the bond between the interposer 3 and the FC-BGA wiring board 1. In this case, it is also possible to use a material with less distortion, such as metal or ceramics, for the support 5.

[0028] In this embodiment, the peeling layer 6 is made of a resin that absorbs UV light and becomes peelable, and the support 5 is made of glass.

[0029] 3B, a protective layer 7 is formed on the release layer 6. The protective layer 7 is a layer for protecting the interposer 3 when the support 5 is peeled off in a later step. Examples of the protective layer 7 include one type of epoxy resin, acrylic resin, urethane resin, silicone resin, polyester resin, and oxetane resin, or a mixture of two or more types of these resins.

[0030] The resin can be removed after the interposer 3 is peeled off from the support 5. The protective layer 7 can be formed by spin coating, lamination, or the like, as appropriate according to the shape of the resin. In this embodiment, the protective layer 7 is formed by a lamination method using an acrylic resin.

[0031] Next, as shown in FIG. 3C, a seed layer 8 is formed on the protective layer 7 in a vacuum. The seed layer 8 acts as a power supply layer for electrolytic plating in the process of forming wiring. The seed layer 8 may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu 3 N 4 A single Cu alloy or a combination of multiple Cu alloys can be used, and the layer can be formed by, for example, a sputtering method or a CVD method.

[0032] In this embodiment, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer and then a copper layer are formed in sequence by sputtering. The total thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In this embodiment, Ti is 50 nm and Cu is 300 nm.

[0033] Next, as shown in FIG. 3D, a resist pattern 9 is formed, and a conductor layer 10, which is a first electrode, is formed in the openings 9a by electrolytic plating. The conductor layer 10 becomes an electrode for bonding to the semiconductor element 4. Examples of electrolytic plating methods include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. In particular, electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating is preferably 1 μm or more and 30 μm or less from the viewpoint of circuit connection reliability, manufacturing cost, and the like. Thereafter, the resist pattern 9 is removed as shown in FIG. 3E.

[0034] Next, as shown in FIG. 3F, an insulating resin layer 11 is formed. The insulating resin layer 11 is formed so as to embed the conductor layer 10 inside. In this embodiment, the insulating resin layer 11 is formed, for example, by a spin coating method using a photosensitive epoxy resin. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little due to curing after formation, making it excellent for subsequent fine pattern formation.

[0035] In addition to the above, the insulating resin layer 11 can be formed by compressing and curing an insulating resin film with a vacuum laminator. In this case, an insulating film with good flatness can be formed. For example, polyimide can be used as the insulating resin.

[0036] 3G, an opening 11a is formed in the insulating resin layer 11 on the conductor layer 10 by photolithography or the like. Note that it is also possible to subject the opening 11a to a plasma treatment in order to remove residues remaining after development.

[0037] Next, as shown in Fig. 3H, a seed layer 12 is provided on the surface of the insulating resin layer 11 and on the conductor layer 10 in the opening 11a. The seed layer 12 has the same composition and thickness as the above-mentioned seed layer 8, and can be appropriately changed as necessary. In this embodiment, it is formed by a sputtering method so that Ti is 50 nm and Cu is 300 nm.

[0038] Next, as shown in FIG. 3I, a resist pattern 13 is formed on the seed layer 12, and a conductor layer 14, which is a wiring layer, is formed in the openings 13a by electrolytic plating. The conductor layer 14 becomes the wiring layer inside the interposer 3. In this embodiment, copper is used as the conductor layer 14. Thereafter, as shown in FIG. 3J, the resist pattern 13 is removed. Then, unnecessary seed layer 12 is removed by etching.

[0039] 3F to 3J are then repeated a number of times to form a multi-layer wiring layer including a plurality of insulating resin layers 11 and conductor layers 14, as shown in Fig. 3K. The conductor layer 15 located on the outermost surface is used as an electrode for bonding to the FC-BGA wiring board 1.

[0040] Next, as shown in Fig. 3L, an outermost insulating resin layer 16 is provided on the surface of the insulating resin layer 11 and on the conductor layer 15. An opening 16a is formed in the outermost insulating resin layer 16 by exposure to light, development, or the like so as to cover the insulating resin layer 11 while exposing a part of the conductor layer 15. In this embodiment, the outermost insulating resin layer 16 is formed using a photosensitive epoxy resin. Note that the outermost insulating resin layer 16 may be made of the same material as the insulating resin layer 11.

[0041] Next, as shown in FIG. 3M, in order to prevent oxidation of the surface of the conductor layer 15 and improve the wettability of the solder bump, a surface treatment layer 17 is provided on the conductor layer 15 in the opening 16a. In this embodiment, an electroless Ni / Pd / Au plating film is formed as the surface treatment layer 17. It is also possible to form an OSP (Organic Soiderability Preservative / surface treatment with water-soluble preflux) film on the surface treatment layer 17. It is also possible to appropriately select from electroless tin plating, electroless Ni / Au plating, etc. depending on the application.

[0042] Next, as shown in Fig. 3N, a solder material is placed on the surface treatment layer 17, melted, cooled, and fixed to form a joint 18a consisting of a solder bump that joins the FC-BGA wiring board 1 and the interposer 3. In this embodiment, the conductor layer 15, the surface treatment layer 17, and the joint 18a form a second electrode. In this manner, the interposer 3 formed on the support 5 can be obtained.

[0043] Next, the process of bonding the interposer 3 and the FC-BGA wiring board 1 in this embodiment will be described with reference to FIGS. 4A and 4B.

[0044] 4A and 4B, the interposer 3 formed on the support 5 is placed and bonded to the FC-BGA wiring board 1, which has been manufactured with a joint 18b, which is a third electrode, designed to match the joint 18a of the interposer 3, to form the joint 18. Specifically, the interposer 3 is mounted on the FC-BGA wiring board 1 by a mounter, and the joint 18a of the interposer 3 and the joint 18b of the FC-BGA wiring board 1 are melted and bonded to each other by a conveyor-type heating device (reflow), thereby forming the joint 18.

[0045] In addition, when flux is used for soldering, it is preferable to perform a flux cleaning process after the soldering process. In the flux cleaning process, it is preferable to use a direct path cleaning device, but it is also possible to use an ultrasonic cleaning device.

[0046] A method for providing underfill 2A and a method for removing support 5 in this embodiment will be described with reference to FIGS. 5A to 5D.

[0047] First, as shown in Fig. 5A, laser light L, which is UV light, is irradiated onto the peeling layer 6 through the support 5 to peel off the support 5. Specifically, the other surface side (upper surface side in Fig. 5A) of the interposer 3, i.e., the surface opposite to the surface connected to the FC-BGA wiring board 1, is irradiated with laser light F through the support 5 to make the peeling layer 6 formed at the interface with the support 5 into a peelable state, and the support 5 is removed through the peeling layer 6 as shown in Fig. 5B (this is the support peeling step).

[0048] The removal of the support 5 differs depending on the properties of the release layer 6, but when the retention of the release layer 6 is reduced, it can be easily peeled off by pulling the support 5. When the retention of the release layer 6 is strong, it can be peeled off, for example, by adhering a sheet having strong adhesiveness to the support 5 and pulling this sheet.

[0049] Next, as shown in Fig. 5C, underfill 2A is filled between interposer 3 and FC-BGA wiring board 1 (this is the resin supplying step). Underfill 2A is supplied and filled by a dispenser that applies pressure with a syringe and discharges it. Underfill 2A can be applied to a position adjacent to interposer 3 using an underfill application device that uses an air dispense method or a jet dispense method. The applied underfill 2A fills the gap between interposer 3 and FC-BGA wiring board 1 by capillary action.

[0050] Here, if the amount of underfill 2A supplied per unit time is too large, there is a risk of the underfill 2A running over the interposer 3. Therefore, in this embodiment, the supply of underfill 2A to fill the gap between the interposer 3 and the FC-BGA wiring board 1 is divided into multiple supplies at intervals of 3 seconds or more, thereby preventing the underfill 2A from running over the interposer 3.

[0051] The underfill 2A is then cured by heating at a temperature equal to or higher than the curing temperature of the underfill 2A, thereby fixing the interposer 3 and the FC-BGA wiring board 1 together and sealing the joints 18 (this is the resin curing step).

[0052] After the support peeling step, resin supplying step, and resin curing step are completed in this manner, the protective layer 7 is removed and then the seed layer 8 is removed, as shown in FIG. 5D, to obtain the wiring board 22A. In this embodiment, the protective layer 7 made of acrylic resin is removed by an alkaline solvent (1% NaOH, 2.3% TMAH). The seed layer 8 made of titanium and copper from the protective layer 7 side is dissolved and removed by using an alkaline etching agent and an acid etching agent, respectively. In this manner, the wiring board 22A in which the interposer 3 and the FC-BGA wiring board 1 are bonded can be manufactured.

[0053] After this, it is possible to further perform surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. on the conductor layer 10 exposed on the surface in order to prevent oxidation and improve the wettability of the solder bumps.

[0054] In the manufacturing method of wiring board 22A according to this embodiment, a support peeling process is performed, followed by a resin supplying process, and then a resin curing process. This prevents underfill 2A from surrounding the periphery of support 5, and eliminates the underfill 2A from adhering to and holding support 5 as it hardens.

[0055] Therefore, in the manufacturing method of the wiring board 22A according to this embodiment, as described above, by irradiating the peeling layer 6 with laser light L, it is possible to easily peel the support 5 reliably from the protective layer 7.

[0056] Therefore, according to the method for manufacturing wiring board 22A according to this embodiment, the yield in the step of peeling off support 5 can be improved, and wiring board 22A can be manufactured with a high yield.

[0057] Furthermore, by performing flux cleaning before peeling off support 5 from interposer 3, interposer 3 can be cleaned while being protected by support 5.

[0058] Furthermore, since the gap between the FC-BGA wiring board 1 and the interposer 3 is sealed with the underfill 2A, the connection portion 18 can be protected from the alkaline etching agent or acidic etching agent used to remove the protective layer 7 and the seed layer 8, thereby preventing a decrease in connection reliability.

[0059] Second Embodiment A second embodiment of the method for manufacturing a wiring board according to the present invention will be described with reference to Figures 6, 7A to 7D. However, for parts similar to those in the above-mentioned embodiment, the same reference numerals as those used in the description of the above-mentioned embodiment will be used, and descriptions that overlap with those in the above-mentioned embodiment will be omitted.

[0060] 6, wiring board 22B of semiconductor package 100B according to this embodiment is formed so that underfill 2B is located closer to the semiconductor element 4 side (upper side in FIG. 6) than the surface of interposer 3 that is connected to the semiconductor element 4 (upper surface in FIG. 6). Other than that, it has the same structure as wiring board 22A of semiconductor package 100A according to the above-described embodiment.

[0061] The manufacturing method of wiring board 22B according to this embodiment is the same as the manufacturing method of wiring board 22A according to the previously described embodiment up to the bonding process (step of FIG. 4B) of bonding bonding portion 18a of interposer 3 and bonding portion 18b of FC-BGA wiring board 1 to form bonding portion 18.

[0062] Then, as shown in FIG. 7A, underfill 2B is supplied to surround the periphery of interposer 3, seed layer 8, protective layer 7, release layer 6 and support body 5 while sealing the gap between interposer 3 and FC-BGA wiring board 1, and interposer 3 formed on support body 5 and FC-BGA wiring board 1 are temporarily fixed together (this is the resin supplying process).

[0063] Next, as shown in Fig. 7B, laser light L is irradiated to the peeling layer 6 through the support 5. Even when the support 5 is irradiated with the laser light L, the underfill 2B is attached and adhered to the outer periphery of the side surface, so the support 5 does not peel off yet. Next, the underfill 2B is softened by heating, reducing the adhesiveness of the underfill 2B, and the support 5 can be easily peeled off from the underfill 2B (this is the resin adhesiveness reducing step).

[0064] Then, as shown in FIG. 7C, after removing the support 5 (this is the support peeling process), the underfill 2B is hardened by heating it to a temperature equal to or higher than its hardening temperature, thereby fixing the interposer 3 and the FC-BGA wiring board 1 together and sealing the joint 18 (this is the resin hardening process).

[0065] 7D, the protective layer 7 and the seed layer 8 are removed in the same manner as in the above-described embodiment. In this manner, the wiring board 22B in which the interposer 3 and the FC-BGA wiring board 1 are bonded together can be manufactured.

[0066] In the manufacturing method of wiring board 22B according to this embodiment, after the resin supplying step, a resin adhesion reducing step is performed, followed by a support peeling step, and then a resin hardening step is performed. This allows support 5 to be released from adhesion caused by underfill 2B adhering to the periphery of support 5, making it easy to remove support 5.

[0067] Therefore, in the method for manufacturing wiring board 22B according to this embodiment, the yield in the step of peeling off support 5 can be improved, and wiring board 22B can be manufactured with a high yield.

[0068] <Third embodiment> A third embodiment of the method for manufacturing a wiring board according to the present invention will be described with reference to Figures 8, 9A to 9E. However, for parts similar to those in the above-mentioned embodiment, the same reference numerals as those used in the description of the above-mentioned embodiment will be used, and descriptions that overlap with those in the above-mentioned embodiment will be omitted.

[0069] 8, the wiring board 22C of the semiconductor package 100C according to this embodiment is formed so that the underfill 2C is located closer to the FC-BGA wiring board 1 side (lower side in FIG. 8) than the surface (upper surface in FIG. 8) of the interposer 3 that is connected to the semiconductor element 4. Otherwise, the wiring board 22C has the same structure as the wiring boards 22A and 22B of the semiconductor packages 100A and 100B according to the above-described embodiments.

[0070] The manufacturing method of wiring board 22C according to this embodiment is the same as the manufacturing method of wiring boards 22A and 22B according to the previously described embodiments, up to the bonding process (step of FIG. 4B) of bonding bonding portion 18a of interposer 3 to bonding portion 18b of FC-BGA wiring board 1 to form bonding portion 18.

[0071] 9A, underfill 2C is filled between interposer 3 and FC-BGA wiring board 1 (resin supplying process). Next, as shown in Fig. 9B, an underfill removal tool T such as a squeegee is brought into contact with the side surface of interposer 3 (left and right, and front and rear surfaces of the page in Fig. 9B) and slid along the outer periphery of interposer 3 to scrape off and remove underfill 2C adhering to at least the side surface of interposer 3 closer to support body 5 than insulating resin layer 11 (resin removing process).

[0072] That is, since the seed layer 8, the protective layer 7, and the release layer 6 are located closer to the support 5 than the insulating resin layer 11, at least the seed layer 8, the protective layer 7, the release layer 6, and the underfill 2C adhering to the outer periphery of the side surface of the support 5 are removed. In this embodiment, the underfill 2C located on the side surface of the insulating resin layer 11 is not removed, and only the underfill 2C located closer to the support 5 than the insulating resin layer 11 is removed.

[0073] For example, a flat squeegee can be used as the underfill removal jig T, and it is preferable that the end of the squeegee has a tapered shape in the thickness direction, and it can be appropriately selected according to various conditions. In addition, it is preferable to use a material with a relatively low hardness as the underfill removal jig T, and examples of such materials include silicone rubber, urethane, Teflon (registered trademark), other rubbers, plastics, etc.

[0074] Next, the underfill 2C is heated and cured to fix the interposer 3 and the FC-BGA wiring board 1 together and seal the joint 18 (resin curing process). Next, as shown in FIG. 9C, laser light L is irradiated onto the peeling layer 6 through the support 5. Then, as shown in FIG. 9D, the support 5 is peeled off in the same manner as in the previously described embodiment. Next, as shown in FIG. 9E, the protective layer 7 and the seed layer 8 are removed in the same manner as in the previously described embodiment (support peeling process). In this manner, a wiring board 22C in which the interposer 3 and the FC-BGA wiring board 1 are bonded together can be manufactured.

[0075] In the manufacturing method of the wiring board 22C according to this embodiment, after the resin supplying process, a resin removal process is performed to remove the underfill 2C located on the side of the interposer 3, at least the portion closer to the support body 5 than the insulating resin layer 11, and then a resin curing process is performed, followed by a support body peeling process. This makes it possible to control the shape of the underfill 2C after curing, regardless of the shape of the underfill 2C when it is supplied, and therefore prevents the underfill 2C from adhering to the support body 5 as it hardens.

[0076] Therefore, in the manufacturing method of the wiring board 22C of this embodiment, as in the above-mentioned embodiment, the support 5 can be easily and reliably peeled off from the protective layer 7 by irradiating the peeling layer 6 with laser light L.

[0077] Therefore, according to the method for manufacturing wiring board 22C according to this embodiment, similarly to the above-described embodiment, the yield in the step of peeling off support 5 can be improved, and wiring board 22C can be manufactured with a high yield.

[0078] Furthermore, by using a material such as that described above, which has a relatively low hardness, for the underfill removal jig T, the ability of the underfill removal jig T to conform to the shape of the side surface of the interposer 3 can be improved, making it possible to more reliably remove the underfill 2C.

[0079] <Another Example 1 of the Third Embodiment> In the above-described third embodiment, it is also possible to apply a material having a relatively high hardness to the underfill removal jig T. Specifically, for example, any one of Cu, Ti, Sn, Fe, Al, Cr, Ag, Au, Pt, Ni, and Mn, or an alloy of two or more kinds, or a composite of two or more kinds, etc. If such a material having a relatively high hardness is applied to the underfill removal jig T, deformation of the underfill removal jig T when removing the underfill 2C can be suppressed, and the accuracy of the position where the underfill 2C is removed can be improved.

[0080] <Another Example 2 of the Third Embodiment> Furthermore, in the above-described third embodiment, it is also possible to use a syringe needle connected to a suction mechanism as the underfill removal jig T so as to suck and remove the underfill 2C adhering to the outer periphery of the side surface of the interposer 3. When such a syringe needle connected to a suction mechanism is used as the underfill removal jig T, it is possible to prevent the underfill 2C from spreading on the underfill removal jig T during removal and re-adhering to the interposer 3, and it is also possible to prevent the removed underfill 2 from spreading in the width direction on the FC-BGA wiring board 1.

[0081] <Other Example 3 of Third Embodiment> In addition, in the third embodiment described above, it is also possible to carry out a masking forming step before the resin supplying step, carry out a resin removing step, and then carry out a masking removing step before carrying out the resin hardening step.

[0082] Specifically, as shown in FIG. 10, a peelable first masking 23 is formed on a portion of the surface of the FC-BGA wiring substrate 1 facing the interposer 3, and a peelable second masking 24 is formed on the surface of the support 5 opposite the surface on which the interposer 3 is provided.

[0083] The first and second masks 23, 24 may be made of a material that can be patterned and peeled off. For example, a photosensitive dry film resist or a liquid photosensitive resist for forming wiring may be used. In the case of a photosensitive dry film resist, the roll lamination method, the vacuum lamination method, etc. may be used for the first and second masks 23, 24, and in the case of a liquid photosensitive resist, the spin coating method, the slit coating method, the screen printing method, the gravure offset method, etc. may be used.

[0084] The first masking 23 has an opening 23a formed by photolithography for filling with the underfill 2C. The opening 23a of the first masking 23 can be formed over the entire length of the outer periphery of the side surface of the interposer 3, or can be formed only in a part of it. The thickness of the first masking 23 is set to be equal to or less than the thickness of the interposer 3.

[0085] An underfill 2C is filled between the interposer 3 and the FC-BGA wiring board 1 through the opening 23a of the first masking 23, and the underfill 2C adhering to the outer periphery of the side surface of the interposer 3 is removed by the underfill removal tool T in the same manner as described above. It is preferable that the underfill removal tool T has a size (height) that allows it to abut against the first masking 23. After the underfill 2C is cured, the first and second maskings 23, 24 are removed. The first and second maskings 23, 24 are removed with a remover that removes the photosensitive resin.

[0086] In such a manufacturing method, the first masking 23 is formed on a part of the surface of the FC-BGA wiring board 1 facing the interposer 3 before the resin supplying step, and the first masking 23 is removed after the resin removing step and before the resin hardening step, so that the shape of the hardened underfill 2C can be controlled with high precision. That is, for example, as shown in Fig. 10, by making the first masking 23 to have substantially the same thickness as the thickness of the outermost insulating resin layer 16 of the interposer 3, the underfill removing tool T can be arranged to abut against the first masking 23, so that the underfill 2C can be removed from the boundary surface between the insulating resin layer 11 and the outermost insulating resin layer 16, i.e., up to the lowest position of the insulating resin layer 11.

[0087] Furthermore, prior to the resin supplying step, a second masking 24 is formed on the surface of the support 5 opposite the surface on which the interposer 3 is provided, and the second masking 24 is removed after the resin removal step and before the resin hardening step, so that the underfill 2C that has wetted onto the surface of the support 5 opposite the surface on which the interposer 3 is provided can be easily removed.

[0088] The above-described embodiment is merely an example, and other specific details of the structure can be modified as appropriate. [Industrial Applicability]

[0089] The present invention can be used in a semiconductor device having a wiring board equipped with an interposer or the like interposed between a main board and an IC chip. [Explanation of symbols]

[0090] 1. FC-BGA wiring board (first wiring board) 2A, 2B, 2C, 21 Underfill (sealing resin) 3 Interposer (second wiring board) 4. Semiconductor elements 5 Support 6 Release layer 7 Protective layer 8,12 Seed layer 9,13 Resist Pattern 9a,13a opening 10 Conductive layer (first electrode) 11 Insulating resin layer 11a opening 14 Conductor layer (wiring layer) 15 Conductor layer 16 Outermost insulating resin layer 16a opening 17 Surface treatment layer 18,18a,18b,20 joint 22A, 22B, 22C Wiring board 23 First Masking 23a opening 24 Second Masking L Laser light (UV light) T Underfill removal tool

Claims

1. A wiring board in which a first wiring board is formed with finer wiring than a first wiring board and the first wiring board is bonded to a bonding surface of the second wiring board, and a semiconductor element is mounted on a surface of the second wiring board opposite to the bonding surface, a first electrode bonded to the semiconductor element is provided on a surface of the second wiring substrate opposite to the bonding surface; a second electrode bonded to the first wiring board on the bonding surface of the second wiring board; a third electrode bonded to the second electrode is provided on one surface of the first wiring substrate; a sealing resin extending between the first wiring board and the second wiring board and from there, the sealing resin having a portion protruding outside an outer periphery of the second wiring board; the protruding portion of the sealing resin is located at a highest portion in a thickness direction of the second wiring substrate between an upper end and a lower end in the thickness direction of the second wiring substrate, the second wiring board has a multi-layer structure including a conductor layer and an insulator layer; the insulator layer comprises an outermost insulator layer that constitutes an outermost surface of the second wiring board on the side of the first wiring board and is in contact with the sealing resin, and an insulator layer other than the outermost insulator layer, the protruding portion of the sealing resin is located at the highest portion in a thickness direction of the second wiring board at a boundary surface between the outermost insulator layer and an insulator layer other than the outermost insulator layer, Wiring board.

2. The first wiring board is a wiring board for FC-BGA. The wiring board according to claim 1 .

3. The sealing resin contains, as a component, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins. The wiring board according to claim 1 .

4. The sealing resin contains, as a filler, one of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide, or a mixture of two or more of these. The wiring board according to claim 3 .

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