Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method of manufacturing the same capable of suppressing generation of cracks in a Ni plating film.SOLUTION: A silicon carbide semiconductor device has: an electrode formed on a first principal surface of a silicon carbide substrate; a Ni plating film formed on the electrode, containing P; a Pd plating film formed on the Ni plating film; and a Au plating film formed on the Pd plating film. A first P concentration at a first interface with the electrode, of the Ni plating film is higher than a second P concentration at a second interface with the Pd plating film, of the Ni plating film.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] In a silicon carbide semiconductor device, a nickel (Ni) plated film, a palladium (Pd) plated film, and a gold (Au) plated film are formed in this order on an electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-128791 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional silicon carbide semiconductor devices, cracks may occur in the Ni plating film, particularly when the upper surface of the electrode is uneven with large height differences.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing the occurrence of cracks in a Ni plating film, and a method for manufacturing the silicon carbide semiconductor device. [Means for solving the problem]

[0006] The silicon carbide semiconductor device of the present disclosure comprises an electrode formed on a first main surface of a silicon carbide substrate, a Ni plating film containing P formed on the electrode, a Pd plating film formed on the Ni plating film, and an Au plating film formed on the Pd plating film, wherein a first P concentration at a first interface of the Ni plating film with the electrode is higher than a second P concentration at a second interface of the Ni plating film with the Pd plating film. Effect of the Invention

[0007] According to the present disclosure, the occurrence of cracks in a Ni plating film can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a first example of a method for forming a Ni plating film. [Figure 13] FIG. 13 is a cross-sectional view showing a second example of a method for forming a Ni plating film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0011] [1] A silicon carbide semiconductor device according to one embodiment of the present disclosure includes an electrode formed on a first main surface of a silicon carbide substrate, a Ni plating film containing P formed on the electrode, a Pd plating film formed on the Ni plating film, and an Au plating film formed on the Pd plating film, wherein a first P concentration at a first interface of the Ni plating film with the electrode is higher than a second P concentration at a second interface of the Ni plating film with the Pd plating film.

[0012] Since the first P concentration is higher than the second P concentration, the electrode side of the Ni plating film has better coverage, and the Pd plating film has better adhesion. Therefore, the Ni plating film has excellent flatness, and the Pd plating film also has excellent flatness. This makes it possible to suppress the permeation of the plating solution used to form the Au plating film through the Pd plating film, and to suppress the occurrence of cracks in the Ni plating film.

[0013] [2] In [1], the first P concentration may be 12 mass% or more, and the second P concentration may be 4 mass% or less. When the first P concentration is 12 mass% or more, particularly good coverage is obtained, and when the second P concentration is 4 mass% or less, particularly good adhesion with the Pd plating film is obtained.

[0014] [3] In the above [1] or [2], an insulating film is formed on the silicon carbide substrate and has a contact hole formed therein, the electrode is formed on the insulating film and connected to the silicon carbide substrate through the contact hole, and the upper surface of the electrode may have irregularities with a height difference of 0.8 μm to 1.5 μm. Even if the unevenness has a height difference of 0.8 μm to 1.5 μm, the Ni plating film has good coverage and therefore the occurrence of cracks can be suppressed.

[0015] [4] In any of [1] to [3], a third P concentration at a center point between a first point that is the furthest from the first main surface among the points constituting the first interface and an intersection point between a virtual line that passes through the first point and is perpendicular to the first main surface and the second interface may be lower than the first P concentration and higher than the second P concentration. In this case, a rapid change in the P concentration in the Ni plating film can be suppressed.

[0016] [5] In [4], the third P concentration may be higher than 4 mass % and lower than 12 mass %, which makes it easier to suppress a rapid change in the P concentration in the Ni plating film.

[0017] [6] In [4] or [5], the average crystal grain size between the first point and the center point may be smaller than the average crystal grain size between the intersection point and the center point. Depending on the P concentration of the plating solution used to form the Ni plating film, the average crystal grain size between the first point and the center point may be smaller than the average crystal grain size between the intersection point and the center point.

[0018] [7] In any of [1] to [6], the electrodes may contain Al or Cu, which makes it easier to reduce the resistance of the electrodes.

[0019] [8] A method for manufacturing a silicon carbide semiconductor device according to another embodiment of the present disclosure includes forming an electrode on a first main surface of a silicon carbide substrate, forming a P-containing Ni plating film on the electrode, forming a Pd plating film on the Ni plating film, and forming an Au plating film on the Pd plating film, wherein the step of forming the Ni plating film includes forming a first Ni plating film using a first plating solution having a first P concentration, and forming a second Ni plating film on the first Ni plating film using a second plating solution having a second P concentration lower than the first P concentration.

[0020] By forming the first Ni plating film using the first plating solution, good coverage can be obtained. Also, by forming the second Ni plating film using the second plating solution, it is easy to form a Pd plating film with good adhesion on the Ni plating film. Therefore, the permeation of the plating solution used to form the Au plating film through the Pd plating film can be suppressed, and the occurrence of cracks in the Ni plating film can be suppressed.

[0021] [9] In [8], the first P concentration may be 12 mass% or more, and the second P concentration may be 4 mass% or less. When the first P concentration is 12 mass% or more, particularly good coverage is obtained, and when the second P concentration is 4 mass% or less, particularly good adhesion with the Pd plating film is obtained.

[0022]

[10] In the method of [8] or [9], a step of forming a third Ni plating film on the first Ni plating film using a third plating solution having a third P concentration lower than the first P concentration and higher than the second P concentration may be included between the step of forming the first Ni plating film and the step of forming the second Ni plating film, and the second Ni plating film may be formed on the third Ni plating film. In this case, a sudden change in the P concentration in the Ni plating film can be suppressed.

[0023]

[11] In the method of

[10] , the third P concentration may be higher than 4 mass % and lower than 12 mass %, which makes it easier to suppress a rapid change in the P concentration in the Ni plating film.

[0024]

[12] In

[10] or

[11] , the first Ni plating film may have a thickness of 1.5 μm to 2.5 μm, the second Ni plating film may have a thickness of 1.0 μm to 2.0 μm, and the third Ni plating film may have a thickness of 1.0 μm to 2.0 μm. In this case, the generation of cracks in the Ni plating film is particularly easily suppressed.

[0025] [Details of the embodiment of the present disclosure] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Although embodiments of the present disclosure are described in detail below, the present disclosure is not limited thereto. Fig. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment.

[0026] As shown in FIG. 1, a silicon carbide semiconductor device 100 according to the embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

[0027] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type. A semiconductor element is formed on the silicon carbide substrate 10.

[0028] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0029] In this embodiment, a field effect transistor, as an example of a semiconductor element, is formed on a silicon carbide substrate 10. The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, and a contact region .

[0030] The drift region 11 has an n-type by being doped with an n-type impurity such as nitrogen or phosphorus (P). The doping of the n-type impurity into the drift region 11 is preferably performed by doping the impurity during the epitaxial growth of the drift region 11, rather than by ion implantation.

[0031] The body region 12 is provided on the drift region 11. The body region 12 has p-type conductivity by being doped with p-type impurities such as aluminum (Al).

[0032] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 has an n-type conductivity by being doped with an n-type impurity such as nitrogen or phosphorus. The source region 13 constitutes the first main surface 1.

[0033] The contact region 18 has p-type conductivity by being doped with p-type impurities such as aluminum. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and contacts the body region 12.

[0034] A plurality of gate trenches 5 are provided on the first main surface 1. The gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and the plurality of gate trenches 5 are arranged in a second direction. The gate trenches 5 have a bottom surface 4 made of the drift region 11. The gate trenches 5 have a side surface 3 that penetrates the source region 13 and the body region 12 and continues to the bottom surface 4. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The angle of the side surface 3 with respect to a plane including the bottom surface 4 may be 90°.

[0035] A gate insulating film 81 is provided in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0036] A gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5.

[0037] An interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 90 are provided so that the gate trench 5 is located between the contact holes 90 adjacent to each other in the second direction. The contact holes 90 extend in the first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. For example, the depth of the contact hole 90 is 0.8 μm or more and 1.5 μm or less, and may be 1.0 μm or more and 1.3 μm or less. Also, for example, the diameter of the contact hole 90 is 2.0 μm or more and 5.0 μm or less, and may be 2.5 μm or more and 4.5 μm or less.

[0038] A source electrode 60 is provided in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in a contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing nickel silicide (NiSi), for example. The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 is in ohmic junction with the source region 13 and the contact region 18. That is, the source electrode 60 is connected to the silicon carbide substrate 10 through the contact hole 90. The source wiring 62 is made of a material containing aluminum or copper (Cu), for example. The source wiring 62 may be made of a material containing aluminum and copper. The source electrode 60 is electrically insulated from the gate electrode 82 by an interlayer insulating film 83. The source electrode 60 may include a barrier metal film, such as a titanium nitride (TiN) film, between the source wiring 62 and the interlayer insulating film 83. The source electrode 60 is an example of an electrode.

[0039] The upper surface of the source electrode 60 is formed with unevenness reflecting the contact hole 90. The unevenness has a height difference D1 that is approximately the same as the depth of the contact hole 90, and is, for example, 0.8 μm or more and 1.5 μm or less. The unevenness may have a height difference of 1.0 μm or more and 1.3 μm or less. The height difference D1 here refers to the difference in distance from the first main surface 1 between a recess and a protrusion that are adjacent to each other in a cross-sectional view.

[0040] A nickel (Ni) plating film 63 containing phosphorus is formed on the source electrode 60, a palladium (Pd) plating film 64 is formed on the Ni plating film 63, and a gold (Au) plating film 65 is formed on the Pd plating film 64. The thickness of the Ni plating film 63 is preferably 3.0 μm or more and 7.0 μm or less, more preferably 4.0 μm or more and 6.0 μm or less. The thickness of the Pd plating film 64 is preferably 20 nm or more and 40 nm or less, more preferably 25 nm or more and 35 nm or less. The thickness of the Au plating film 65 is preferably 30 nm or more and 70 nm or less, more preferably 40 nm or more and 60 nm or less. The thicknesses of the Ni plating film 63, the Pd plating film 64, and the Au plating film 65 are the thicknesses of the thickest parts of each film. For example, the Ni plating film 63 is the thickness of the part that enters the recess on the upper surface of the source electrode 60.

[0041] The Ni plating film 63 has a first surface 63A in contact with the source electrode 60 and a second surface 63B in contact with the Pd plating film 64. The first P concentration in the first surface 63A is higher than the second P concentration in the second surface 63B. For example, the first P concentration is preferably 12 mass% or more, more preferably 13 mass% or more, and may be 15 mass% or less. The second P concentration is preferably 4 mass% or less, more preferably 3 mass% or less, and may be 2 mass% or more. The P concentration can be measured by, for example, energy dispersive X-ray spectroscopy (EDX). The first surface 63A is an example of a first interface, and the second surface 63B is an example of a second interface.

[0042] Furthermore, a third P concentration at a center point 93 located at the center between a first point 91 that is the farthest from the first main surface 1 among the points constituting the first surface 63A and an intersection 92 between a virtual straight line L1 that passes through the first point 91 and is perpendicular to the first main surface 1 and the second surface 63B may be lower than the first P concentration and higher than the second P concentration. For example, the P concentration of the Ni plating film 63 at the first point 91 is the first concentration, and the P concentration of the Ni plating film 63 at the intersection 92 is the second concentration.

[0043] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic junction with the silicon carbide single crystal substrate 50.

[0044] The acceptor concentration and donor concentration in each of the impurity regions can be measured, for example, by using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

[0045] Next, a method for manufacturing the silicon carbide semiconductor device 100 according to the embodiment will be described. Figures 2 to 11 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.

[0046] First, as shown in Fig. 2, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has an n-type. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of an n-type impurity such as nitrogen. In this manner, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

[0047] Next, as shown in Fig. 3, ions are implanted into the silicon carbide epitaxial layer 40. For example, the body region 12, the source region 13, and the contact region 18 are formed by the ion implantation. The remaining portion of the silicon carbide epitaxial layer 40 functions as the drift region 11. In the ion implantation for forming the body region 12 or the contact region 18, for example, a p-type impurity such as aluminum is ion-implanted. In the ion implantation for forming the source region 13, for example, an n-type impurity such as phosphorus is ion-implanted.

[0048] 4, a plurality of gate trenches 5 are formed in the source region 13, the body region 12, and the drift region 11. The gate trenches 5 can be formed as follows.

[0049] First, a mask (not shown) having an opening is formed on a region where the gate trench 5 is to be formed. Next, using the mask, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. The etching is, for example, reactive ion etching (RIE). By the etching, a recess having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0050] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), sulfur hexafluoride (SF6), or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen (O2) gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of 800°C or more and 900°C or less. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen (N2) gas, argon (Ar) gas, helium (He) gas, or the like can be used as the carrier gas.

[0051] By the thermal etching, a gate trench 5 is formed in the first main surface 1. The gate trench 5 has a bottom surface 4 made of the drift region 11, and a side surface 3 that penetrates the source region 13 and the body region 12 and is continuous to the bottom surface 4. After the thermal etching, the mask is removed from the first main surface 1.

[0052] Next, as shown in FIG. 5, a gate insulating film 81 is formed. For example, the silicon carbide substrate 10 is thermally oxidized to form the gate insulating film 81 in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. As a result, the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is taken into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0053] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0054] 6, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure-chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0055] 7, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0056] Next, as shown in FIG. 8, the interlayer insulating film 83 and the gate insulating film 81 are etched to form a contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, a metal film (not shown) for the contact electrode 61 that contacts the source region 13 and the contact region 18 on the first main surface 1 is formed. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing nickel. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 reacts with silicon contained in the silicon carbide substrate 10 and is silicided. As a result, the contact electrode 61 that makes an ohmic junction with the source region 13 and the contact region 18 is formed. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon.

[0057] Next, as shown in FIG. 9, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the interlayer insulating film 83. The upper surface of the source wiring 62 is formed with unevenness reflecting the contact holes 90. The source wiring 62 is formed by, for example, a sputtering method. The source wiring 62 is made of, for example, a material containing aluminum or copper. The source wiring 62 may be made of a material containing aluminum and copper. In this manner, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0058] Next, as shown in Fig. 10, a Ni plating film 63 containing phosphorus (P) is formed on the source electrode 60. The Ni plating film 63 can be formed by, for example, an electroless plating method. Here, a method for forming the Ni plating film 63 will be described in detail. Fig. 12 is a cross-sectional view showing a first example of a method for forming the Ni plating film 63. Fig. 13 is a cross-sectional view showing a second example of a method for forming the Ni plating film 63.

[0059] 12, a first Ni plating film 101 is formed using a first plating solution having a first P concentration, and then a second Ni plating film 102 is formed on the first Ni plating film 101 using a second plating solution having a second P concentration lower than the first P concentration. Preferably, the first Ni plating film 101 is formed to a thickness such that the entire upper surface of the first Ni plating film 101 is above the upper surface of the source electrode 60.

[0060] The first P concentration is preferably 12 mass % or more, and more preferably 13 mass % or more. By using the first plating solution having such a first P concentration, the first Ni plating film 101 having excellent coverage can be formed. That is, the first Ni plating film 101 can be embedded in the recesses present on the surface of the source electrode 60, while the upper surface of the first Ni plating film 101 has excellent flatness. The first P concentration may be 15 mass % or less.

[0061] The second P concentration is preferably 4 mass% or less, and more preferably 3 mass% or less. By using the second plating solution having such a second P concentration, Ni can be easily replaced with Pd, and a Pd plating film 64 with good adhesion can be easily formed on the Ni plating film 63. The second P concentration may be 2 mass% or more.

[0062] In the second example, as shown in FIG. 13, after the formation of the first Ni plating film 101 and before the formation of the second Ni plating film 102, a third Ni plating film 103 is formed on the first Ni plating film 101 using a third plating solution having a third P concentration. Then, the second Ni plating film 102 is formed on the third Ni plating film 103. The third P concentration is lower than the first P concentration and higher than the second P concentration. Preferably, the first Ni plating film 101 is formed to a thickness such that the entire upper surface of the first Ni plating film 101 is above the upper surface of the source electrode 60. By forming the third Ni plating film 103, a sudden change in the P concentration in the Ni plating film 63 can be suppressed.

[0063] In the second example, the first P concentration is preferably 12 mass% or more, more preferably 13 mass% or more, and may be 15 mass% or less, and the second P concentration is preferably 4 mass% or less, more preferably 3 mass% or less, and may be 2 mass% or more.

[0064] The third P concentration is preferably higher than 4 mass % and lower than 12 mass %, and more preferably higher than 6 mass % and lower than 10 mass %. By using the third plating solution with such a third P concentration, excellent adhesion is ensured between the first Ni plating film 101 and the second Ni plating film 102, and peeling within the Ni plating film 63 is easily suppressed.

[0065] 11, a Pd plating film 64 is formed on the Ni plating film 63, and an Au plating film 65 is formed on the Pd plating film 64. The Pd plating film 64 and the Au plating film 65 can be formed by, for example, an electroless plating method. In addition, a drain electrode 70 is formed in contact with the silicon carbide single crystal substrate 50 on the second main surface 2.

[0066] In this manner, silicon carbide semiconductor device 100 including a field effect transistor can be manufactured.

[0067] In the silicon carbide semiconductor device 100 according to the embodiment, since the Ni plating film 63 includes a portion corresponding to the first Ni plating film 101, excellent flatness can be obtained on the upper surface of the Ni plating film 63 even if steep irregularities are formed on the upper surface of the source electrode 60. Therefore, excellent flatness can also be obtained on the upper surface of the Pd plating film 64.

[0068] During the formation of the Au plating film 65, the plating solution may permeate the Pd plating film 64 and reach the Ni plating film 63. In particular, when the upper surface of the Pd plating film 64 has irregularities, the plating solution is likely to permeate the concaves of the Pd plating film 64 and reach the Ni plating film 63. When the plating solution for the Au plating film 65 reaches the Ni plating film 63, cracks occur in the Ni plating film 63. In contrast, in this embodiment, excellent flatness is obtained on the upper surface of the Ni plating film 63, and excellent flatness is also obtained on the upper surface of the Pd plating film 64. Therefore, the permeation of the plating solution used to form the Au plating film 65 through the Pd plating film 64 can be suppressed, and the occurrence of cracks in the Ni plating film 63 can be suppressed.

[0069] For example, even if the upper surface of the source electrode 60 has irregularities with a height difference D1 of 0.8 μm or more and 1.5 μm or less, the Ni plating film 63 has good coverage and therefore can suppress the occurrence of cracks.

[0070] When the Ni plating film 63 is formed according to the first example, the thickness of the first Ni plating film 101 is preferably 1.5 μm or more and 3.5 μm or less, more preferably 1.7 μm or more and 3.3 μm or less, depending on the depth and diameter of the contact hole 90. The thickness of the second Ni plating film 102 is preferably 1.0 μm or more and 3.0 μm or less, more preferably 1.2 μm or more and 2.8 μm or less. In this case, it is particularly easy to suppress the occurrence of cracks in the Ni plating film 63.

[0071] When the Ni plating film 63 is formed according to the second example, the thickness of the first Ni plating film 101 is preferably 1.5 μm or more and 2.5 μm or less, more preferably 1.7 μm or more and 2.3 μm or less, depending on the depth and diameter of the contact hole 90. The thickness of the third Ni plating film 103 is preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less. The thickness of the second Ni plating film 102 is preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less. In this case, it is particularly easy to suppress the occurrence of cracks in the Ni plating film 63.

[0072] In the first example, in the Ni plating film 63, the boundary between the first Ni plating film 101 and the second Ni plating film 102 may not be clear. Similarly, in the second example, the boundary between the first Ni plating film 101 and the third Ni plating film 103 may not be clear, and the boundary between the third Ni plating film 103 and the second Ni plating film 102 may not be clear.

[0073] Furthermore, the P concentration of the plating solution may be continuously decreased from the early stage of film formation to the later stage of film formation when forming the Ni plating film 63. For example, in the early stage of film formation, the P concentration may be preferably 12 mass % or more, more preferably 13 mass % or more, and in the later stage of film formation, the P concentration may be preferably 4 mass % or less, more preferably 3 mass % or less.

[0074] In silicon carbide semiconductor device 100 manufactured in this manner, the first P concentration in first surface 63A is higher than the second P concentration in second surface 63B. For example, the first P concentration is preferably 12 mass % or more, more preferably 13 mass % or more, and may be 15 mass % or less. The second P concentration is preferably 4 mass % or less, more preferably 3 mass % or less, and may be 2 mass % or more. In this case, particularly good coverage is obtained for Ni plating film 63, and particularly good adhesion is obtained between Ni plating film 63 and Pd plating film 64.

[0075] Furthermore, the third P concentration at a center point 93 located at the center between the first point 91 and the intersection point 92 may be lower than the first P concentration and higher than the second P concentration. In this case, a sudden change in the P concentration in the Ni plating film 63 is suppressed. In particular, when the third P concentration is higher than 4 mass% and lower than 12 mass%, a sudden change in the P concentration in the Ni plating film 63 is easily suppressed.

[0076] The average crystal grain size between the first point 91 and the center point 93 may be smaller than the average crystal grain size between the intersection point 92 and the center point 93. When the above-mentioned first plating solution and second plating solution are used, and when the above-mentioned first plating solution, second plating solution, and third plating solution are used, the average crystal grain size between the first point 91 and the center point 93 may be smaller than the average crystal grain size between the intersection point 92 and the center point 93.

[0077] The source electrode 60 preferably contains aluminum or copper. This is because it is easy to reduce the resistance of the source electrode 60. The source electrode 60 may contain aluminum and copper. The source electrode 60 may further contain silicon.

[0078] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0079] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Area 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Ni plating film 63A 1st page 63B 2nd side 64 Pd plating film 65 Au plating film 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 90 Contact Hole 91 1st point 92 intersection 93 center point 100 Silicon carbide semiconductor device 101 First Ni plating film 102 Second Ni plating film 103 Third Ni plating film L1 Virtual line

Claims

1. an electrode formed on a first main surface of the silicon carbide substrate; a P-containing Ni plating film formed on the electrode; A Pd plating film formed on the Ni plating film; an Au plating film formed on the Pd plating film; having a first P concentration at a first interface of the Ni plating film with the electrode is higher than a second P concentration at a second interface of the Ni plating film with the Pd plating film; an insulating film formed on the silicon carbide substrate and having a contact hole; the electrode is formed on the insulating film and connected to the silicon carbide substrate through the contact hole; The silicon carbide semiconductor device has an upper surface of the electrode having projections and recesses with a height difference of 0.8 μm to 1.5 μm.

2. The first P concentration is 12 mass% or more, The silicon carbide semiconductor device according to claim 1 , wherein the second P concentration is not more than 4 mass %.

3. 3. The silicon carbide semiconductor device according to claim 1, wherein a third P concentration at a center point located at the center between a first point that is the furthest from the first main surface among the points constituting the first interface and an intersection point between a virtual line that passes through the first point and is perpendicular to the first main surface and the second interface is lower than the first P concentration and higher than the second P concentration.

4. The silicon carbide semiconductor device according to claim 3 , wherein the third P concentration is higher than 4 mass % and lower than 12 mass %.

5. 5 . The silicon carbide semiconductor device according to claim 3 , wherein an average crystal grain size between the first point and the center point is smaller than an average crystal grain size between the intersection point and the center point.

6. The silicon carbide semiconductor device according to claim 1 , wherein the electrode contains Al or Cu.

7. forming an electrode on a first main surface of the silicon carbide substrate; forming a P-containing Ni plating film on the electrode; forming a Pd plating film on the Ni plating film; forming an Au plating film on the Pd plating film; having The step of forming the Ni plating film includes: forming a first Ni plating film using a first plating solution having a first P concentration; forming a second Ni plating film on the first Ni plating film using a second plating solution having a second P concentration lower than the first P concentration; having a step of forming a third Ni plating film on the first Ni plating film using a third plating solution having a third P concentration lower than the first P concentration and higher than the second P concentration, between the step of forming the first Ni plating film and the step of forming the second Ni plating film; The second Ni plating film is formed on the third Ni plating film.

8. The first P concentration is 12 mass% or more, The method for manufacturing a silicon carbide semiconductor device according to claim 7 , wherein the second P concentration is not more than 4 mass %.

9. 9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the third P concentration is higher than 4 mass % and lower than 12 mass %.

10. The thickness of the first Ni plating film is 1.5 μm or more and 2.5 μm or less, The thickness of the second Ni plating film is 1.0 μm or more and 2.0 μm or less, 10. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the third Ni plating film has a thickness of not less than 1.0 μm and not more than 2.0 μm.

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