Semiconductor package structure and its chips

Abstract

To provide a semiconductor package structure and its chip.SOLUTION: A semiconductor package structure includes a flexible substrate 110 and a chip 120. The chip 120 includes a first bump group 121 and a second bump group 122. The first bump group 121 includes a plurality of first bumps. The second bump group 122 includes a plurality of second bumps. The first bumps and the second bumps are bonded to the respective leads of the flexible substrate 110. By making the length of each second bump longer than the length of each first bump and increasing the bonding force of the second bump relative to the lead, a problem in which the deviation caused by the lead results in the detachment from the bump or the displacement of the bonding position is prevented.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure that prevents a situation in which a lead is displaced or a position where the lead is bonded to a bump is shifted. [Background technology]

[0002] In a conventional semiconductor package structure, multiple bumps on a chip are bonded to multiple leads on a substrate by a thermocompression process, thereby electrically connecting the chip to the substrate. In response to the trend toward miniaturization, the pitch of the bumps is reduced or multiple bumps are arranged to facilitate electrical connection to the substrate. Summary of the Invention [Problem to be solved by the invention]

[0003] However, in the conventional technology described above, if the substrate is deformed due to the effect of the process temperature, the leads joined to the bumps may shift when the bumps are joined to the leads. For example, the leads for joining intermediate bumps or the leads of bumps adjacent to the short sides of the chip may shift, causing the leads to detach from the bumps or the joining positions to shift.

[0004] Therefore, the inventors believed that the above-mentioned drawbacks could be improved, and after extensive research, they discovered that the above-mentioned object could be achieved by adopting the following configuration, which led to the completion of the present invention.

[0005] The present invention has been made in view of the above circumstances, and aims to solve the above problems, i.e., a main object of the present invention is to provide a semiconductor package structure and a chip thereof, which increase the bonding strength of the bumps to the leads by designing bumps of different lengths, and prevent the leads bonded to the bumps from shifting, causing the leads to come off the bumps, or causing the bonding positions to shift. [Means for solving the problem]

[0006] In order to solve the above problems, the present invention employs the following means. A semiconductor package structure according to one aspect of the present invention includes a flexible substrate and a chip. The flexible substrate has a plurality of first circuit lines and a plurality of second circuit lines, and has at least one second circuit line between adjacent first circuit lines, and a plurality of first leads of the first circuit line and a plurality of second leads of the second circuit line are located in a chip bonding area of ​​the flexible substrate. The chip has a surface, a first bump group, and a second bump group, and a first area and a second area are defined on the surface along a first direction. The first bump group is disposed in the first area and includes a plurality of first inner bumps and a plurality of first outer bumps. The second bump group is disposed in the second area and includes a plurality of second inner bumps and a plurality of second outer bumps. Along a second direction intersecting the first direction, the first outer bumps are closer to a long side of the surface than the first inner bumps, and the second outer bumps are closer to the long side than the second inner bumps. Along the second direction, a third length of each of the second inner bumps is longer than a first length of each of the first inner bumps, and a fourth length of each of the second outer bumps is longer than a second length of each of the first outer bumps. The first inner bumps and the second inner bumps are bonded to the first leads, respectively, and the first outer bumps and the second outer bumps are bonded to the second leads, respectively. A bonding area between each of the second inner bumps and each of the first leads is larger than a bonding area between each of the first inner bumps and each of the first leads, and a bonding area between each of the second outer bumps and each of the second leads is larger than a bonding area between each of the first outer bumps and each of the second leads.

[0007] According to one embodiment of the present invention, there is provided a chip. The chip according to the present invention includes a surface, a first group of bumps, and a second group of bumps. A first area and a second area are defined on the surface along a first direction. The first group of bumps is disposed in the first area and includes a plurality of first inner bumps and a plurality of first outer bumps. The second group of bumps is disposed in the second area and includes a plurality of second inner bumps and a plurality of second outer bumps. Along a second direction intersecting the first direction, the first outer bumps are closer to a long side of the surface than the first inner bumps, and the second outer bumps are closer to the long side than the second inner bumps. Along the second direction, a third length of each of the second inner bumps is longer than a first length of each of the first inner bumps, and a fourth length of each of the second outer bumps is longer than a second length of each of the first outer bumps. Effect of the Invention

[0009] As described above, the present invention has the following advantages. According to the present invention, the length of the bumps in the second bump group is longer than the length of the bumps in the first bump group, so that the bonding force of the second bump group to the leads is increased, preventing problems such as the leads bonded to the second bump group shifting and detaching from the bumps or the bonding position becoming displaced.

[0010] Other objects, configurations and effects of the present invention will become apparent from the following detailed description of the preferred embodiments of the present invention. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a semiconductor package structure according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a partially enlarged view of FIG. [Diagram 3] FIG. 2 is a partially enlarged view of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a semiconductor package structure and its chip will be described through an embodiment of the present invention.

[0013] First, an embodiment of a semiconductor package structure 100 according to the present invention will be described with reference to FIGS.

[0014] The semiconductor package structure 100 according to the present invention includes a flexible substrate 110 and a chip 120, and the flexible substrate 110 has a plurality of first circuit lines 111 and a plurality of second circuit lines 112. In this embodiment, there is at least one second circuit line 112 between adjacent first circuit lines 111. A plurality of first leads 111a of the first circuit line 111 and a plurality of second leads 112a of the second circuit line 112 are located in a chip bonding area 110a of the flexible substrate 110, and the chip 120 is mounted on the chip bonding area 110a and electrically connected to the flexible substrate 110.

[0015] 2, the chip 120 has a surface 120a, a first bump group 121, and at least one second bump group 122, and a first area A and at least one second area B are defined on the surface 120a. Along the first direction X, the second area B is closer to the short side 120b of the surface 120a than the first area A. In this embodiment, the chip 120 has two second bump groups 122, and the first bump group 121 is located between the second bump groups 122.

[0016] 1 and 2, the first bump group 121 is disposed in a first area A and includes a plurality of first inner bumps 121a and a plurality of first outer bumps 121b, and the second bump group 122 is disposed in a second area B and includes a plurality of second inner bumps 122a and a plurality of second outer bumps 122b. The first inner bumps 121a and the second inner bumps 122a are respectively bonded to the first lead 111a, and the first outer bumps 121b and the second outer bumps 122b are respectively bonded to the second lead 112a.

[0017] Along a second direction Y intersecting with the first direction X, the first outer bump 121b is closer to the long side 120c of the surface 120a than the first inner bump 121a, and the second outer bump 122b is closer to the long side 120c than the second inner bump 122a (see FIGS. 1 and 2). Along the first direction X, the second inner bump 122a is closer to the short side 120b than the first inner bump 121a, and the second outer bump 122b is closer to the short side 120b than the first outer bump 121b. In this embodiment, the first direction X is the horizontal axis direction, and the second direction Y is the vertical axis direction. The imaginary line L passes through at least one first inner bump 121a along the first direction X, and along the second direction Y, there is a first distance S1 between the inner end 121b1 of each first outer bump 121b and the imaginary line L, and there is a second distance S2 between the inner end 122b1 of each second outer bump 122b and the imaginary line L, the first distance S1 being longer than the second distance S2.

[0018] Along the second direction Y, the third length H3 of each second inner bump 122a is longer than the first length H1 of each first inner bump 121a, and the fourth length H4 of each second outer bump 122b is longer than the second length H2 of each first outer bump 121b (see FIGS. 1 and 2). In this embodiment, along the first direction X, the first width W1 of each first inner bump 121a is longer than the second width W2 of each first outer bump 121b, and the third width W3 of each second inner bump 122a is longer than the fourth width W4 of each second outer bump 122b.

[0019] 2 and 3, along the second direction Y, each first lead 111a joined to the first inner bump 121a has a first lead length J1, and each first lead 111a joined to the second inner bump 122a has a third lead length J3. The first lead length J1 is the distance from the long side 120c to the inner end 121a1 of the first inner bump 121a, and the third lead length J3 is the distance from the long side 120c to the inner end 122a1 of the second inner bump 122a, and the third lead length J3 is longer than the first lead length J1.

[0020] Along the second direction Y, each second lead 112a joined to the first outer bump 121b has a second lead length J2, and each second lead 112a joined to the second outer bump 122b has a fourth lead length J4 (see FIGS. 2 and 3). The second lead length J2 is the distance from the long side 120c to the inner end 121b1 of the first outer bump 121b, and the fourth lead length J4 is the distance from the long side 120c to the inner end 122b1 of the second outer bump 122b, and the fourth lead length J4 is longer than the second lead length J2.

[0021] As shown in Figures 1 and 2, the second inner bump 122a is longer than the first inner bump 121a and the second outer bump 122b is longer than the first outer bump 121b, so that the bonding area between the second inner bump 122a and the first lead 111a is larger than the bonding area between the first inner bump 121a and the first lead 111a, the bonding area between the second outer bump 122b and the second lead 112a is larger than the bonding area between the first outer bump 121b and the second lead 112a, the bonding strength of the second inner bump 122a to the first lead 111a is stronger than the bonding strength of the first inner bump 121a to the first lead 111a, and the bonding strength of the second outer bump 122b to the second lead 112a is stronger than the bonding strength of the first outer bump 121b to the second lead 112a. When the flexible substrate 110 deforms or warps due to the process temperature, the bumps on the chip 120 are positioned to resist the distortion and stress caused by the deformation or warping, preventing problems such as the first lead 111a or the second lead 112a shifting and detaching from the bump or the bonding position becoming misaligned.

[0022] 1 and 2, in this embodiment, the third length H3 of each second inner bump 122a is not shorter than the second length H2 of each first outer bump 121b. Preferably, the third length H3 is longer than the second length H2, and the bonding area between the second inner bump 122a and the first lead 111a is larger than the bonding area between the first outer bump 121b and the second lead 112a, so that there is a preferable bonding strength between the second inner bump 122a and the first lead 111a. Also, the fourth length H4 of each second outer bump 122b is longer than the first length H1 of each first inner bump 121a, so that the bonding area between the second outer bump 122b and the second lead 112a is larger than the bonding area between the first inner bump 121a and the first lead 111a, so that there is a preferable bonding strength between the second outer bump 122b and the second lead 112a.

[0023] 1 and 2, the chip 120 further has at least one third bump group 123, and at least one third area C is defined on the surface 120a. In this embodiment, the surface 120a has one first area A, two second areas B, and two third areas C, and along the first direction X, the first area A is located between the second areas B, and the second area B is located between the first area A and the third area C. The third area C is closer to the short side 120b than the second area B. By providing the third bump group 123 in the third area C, the bonding strength of the second bump group 122 and the third bump group 123 to the first lead 111a and the second lead 112a is increased. Preferably, along the first direction X, the width D1 of the first area A occupies 40 to 80% of the total width D of the chip 120, the width D2 of each second area B occupies 5 to 15% of the total width D of the chip 120, and the width D3 of each third area C occupies 5 to 15% of the total width D of the chip 120.

[0024] Along the first direction X, the second bump group 122 is located between the first bump group 121 and the third bump group 123 (see FIGS. 1 and 2). The third bump group 123 includes a plurality of third inner bumps 123a and a plurality of third outer bumps 123b, and along the second direction Y, the third outer bumps 123b are closer to the long side 120c than the third inner bumps 123a. Along the first direction X, the second inner bump 122a is located between the third inner bump 123a and the first inner bump 121a, the third inner bump 123a is closer to the short side 120b than the second inner bump 122a, and the second outer bump 122b is located between the third outer bump 123b and the first outer bump 121b, and the third outer bump 123b is closer to the short side 120b than the second outer bump 122b. The third inner bump 123a is joined to the first lead 111a, and the third outer bump 123b is joined to the second lead 112a. In this embodiment, there is a third distance S3 between the inner end 123b1 of each of the third outer bumps 123b and the imaginary line L along the second direction Y, and the second distance S2 is longer than the third distance S3.

[0025] 1 and 2, along the second direction Y, the fifth length H5 of each of the third inner bumps 123a is longer than the third length H3 of each of the second inner bumps 122a, and the sixth length H6 of each of the third outer bumps 123b is longer than the fourth length H4 of each of the second outer bumps 122b. In this embodiment, along the first direction X, the fifth width W5 of each of the third inner bumps 123a is longer than the sixth width W6 of each of the third outer bumps 123b.

[0026] 2 and 3, along the second direction Y, each first lead 111a joined to the third inner bump 123a has a fifth lead length J5, and each second lead 112a joined to the third outer bump 123b has a sixth lead length J6. The fifth lead length J5 is the distance from the long side 120c to the inner end 123a1 of each third inner bump 123a, and the fifth lead length J5 is longer than the third lead length J3. The sixth lead length J6 is the distance from the long side 120c to the inner end 123b1 of each third outer bump 123b, and the sixth lead length J6 is longer than the fourth lead length J4.

[0027] As shown in Figures 1 and 2, the third inner bump 123a is longer than the second inner bump 122a and the third outer bump 123b is longer than the second outer bump 122b, so that the bonding area between the third inner bump 123a and the first lead 111a is larger than the bonding area between the second inner bump 122a and the first lead 111a, and the bonding area between the third outer bump 123b and the second lead 112a is larger than the bonding area between the second outer bump 122b and the second lead 112a, so that the bonding strength of the third inner bump 123a to the first lead 111a is stronger than the bonding strength of the second inner bump 122a to the first lead 111a, and the bonding strength of the third outer bump 123b to the second lead 112a is stronger than the bonding strength of the second outer bump 122b to the second lead 112a. This enables the flexible substrate 110 to resist distortion and stress caused by deformation or warping, and prevents the first lead 111a joined to the third inner bump 123a or the second lead 112a joined to the third outer bump 123b from shifting and detaching from the third inner bump 123a or the third outer bump 123b, and prevents the problem of the joining position being shifted.

[0028] As shown in Figures 1 and 2, preferably, the fifth length H5 of each third inner bump 123a is not shorter than the fourth length H4 of each second outer bump 122b. In this embodiment, since the fifth length H5 is longer than the fourth length H4, the bonding area between the third inner bump 123a and the first lead 111a is larger than the bonding area between the second outer bump 122b and the second lead 112a, and the bonding force of the third inner bump 123a to the first lead 111a is increased. Also, since the sixth length H6 of each third outer bump 123b is longer than the third length H3 of each second inner bump 122a, the bonding area between the third outer bump 123b and the second lead 112a is larger than the bonding area between the second inner bump 122a and the first lead 111a, and the bonding force of the third outer bump 123b to the second lead 112a is increased.

[0029] As described above, the present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0030] 100 Semiconductor package structure 110 Flexible PCB 110a Chip Bonding Area 111 1st circuit line 111a 1st lead 112 2nd circuit line 112a 2nd Lead 120 Chips 120a surface 120b short side 120c long side 121 First Bump Group 121a 1st inner bump 121a1 Inner end 121b First outer bump 121b1 Inner end 122 Second Bump Group 122a 2nd inner bump 122a1 Inner end 122b 2nd outer bump 122b1 Inner end 123 3rd Bump Group 123a 3rd inner bump 123a1 Inner end 123b 3rd outer bump 123b1 Inner end A 1st Area B 2nd Area C. Third Area D width D1 width D2 width D3 Width H1 First length H2 Second length H3 3rd length H4 4th length H5 5th length H6 6th length J1 First lead length J2 2nd lead length J3 3rd lead length J4 4th lead length J5 5th lead length J6 Length of 6th lead L Virtual Line S1 1st distance S2 2nd distance S3 3rd distance W1 1st width W2 Second width W3 3rd width W4 4th width W5 5th width W6 6th width X 1st direction Y Second direction

Claims

1. a flexible substrate (110) having a plurality of first circuit lines (111) and a plurality of second circuit lines (112), with at least one of the second circuit lines between adjacent first circuit lines, and a plurality of first leads (111a) of the first circuit lines and a plurality of second leads (112a) of the second circuit lines being located in a chip bonding area (110a) of the flexible substrate; The semiconductor device has a surface (120a), a first group of bumps (121) and at least one second group of bumps (122), a first area (A) and at least one second area (B) are defined on the surface along a first direction (X), the first group of bumps is disposed in the first area and includes a plurality of first inner bumps (121a) and a plurality of first outer bumps (121b), the second group of bumps is disposed in the second area and includes a plurality of second inner bumps (122a) and a plurality of second outer bumps (122b), and along a second direction (Y) intersecting the first direction, the first outer bumps are closer to a long side (120c) of the surface than the first inner bumps, and the second outer bumps are closer to the long side than the second inner bumps. a third length (H3) of each of the second inner bumps is longer than a first length of each of the first inner bumps, a fourth length (H4) of each of the second outer bumps is longer than a second length (H2) of each of the first outer bumps, the first inner bumps and the second inner bumps are respectively bonded to the first leads, the first outer bumps and the second outer bumps are respectively bonded to the second leads, a bonding area between each of the second inner bumps and each of the first leads is larger than a bonding area between each of the first inner bumps and each of the first leads, and a bonding area between each of the second outer bumps and each of the second leads is larger than a bonding area between each of the first outer bumps and each of the second leads.

2. 2. The semiconductor package structure of claim 1, wherein the third length is greater than or equal to the second length, the fourth length is greater than the first length, and a bonding area between each of the second outer bumps and each of the second leads is greater than a bonding area between each of the first inner bumps and each of the first leads.

3. 3. The semiconductor package structure according to claim 2, wherein a bonding area between each of the second inner bumps and each of the first leads is larger than a bonding area between each of the first outer bumps and each of the second leads.

4. 2. The semiconductor package structure of claim 1, wherein along the second direction, each of the first leads joined to the first inner bump has a first lead length (J1), and each of the first leads joined to the second inner bump has a third lead length (J3), the length of the first lead being the distance from the long side to an inner end of the first inner bump, the length of the third lead being the distance from the long side to an inner end of the second inner bump, and the length of the third lead being longer than the length of the first lead.

5. 5. The semiconductor package structure of claim 4, wherein along the second direction, each of the second leads joined to the first outer bump has a second lead length (J2), and each of the second leads joined to the second outer bump has a fourth lead length (J4), the length of the second lead being the distance from the long side to an inner end of the first outer bump, the length of the fourth lead being the distance from the long side to an inner end of the second outer bump, and the length of the fourth lead being longer than the length of the second lead.

6. 2. The semiconductor package structure of claim 1, wherein along the first direction, the second area is closer to a short side (120b) of the surface than the first area, the second inner bump is closer to the short side than the first inner bump, and the second outer bump is closer to the short side than the first outer bump.

7. 2. The semiconductor package structure of claim 1, wherein a virtual line (L) passes through at least one of the first inner bumps along the first direction, and a first distance (S1) is provided along the second direction from an inner end of each of the first outer bumps to the virtual line, and a second distance (S2) is provided along the second direction from an inner end of each of the second outer bumps to the virtual line, the first distance being longer than the second distance.

8. At least one third area (c) is defined on the surface, and along the first direction, the second area is located between the first area and the third area, and the chip further has at least one third bump group (123), the third bump group being disposed in the third area, and along the first direction, the second bump group is located between the first bump group and the third bump group, the third bump group including a plurality of third inner bumps (123a) and a plurality of third outer bumps (123b), along the second direction, the third outer bumps are closer to the long side than the third inner bumps, along the first direction, the second inner bumps are located between the third inner bump and the first inner bump, and the second outer bumps are arranged adjacent to the long side.

6. The semiconductor package structure of claim 5, wherein a fifth length (H5) of each of the third inner bumps is longer than the third length of each of the second inner bumps, a sixth length (H6) of each of the third outer bumps is longer than the fourth length of each of the second outer bumps, the third inner bumps are bonded to the first lead, the third outer bumps are bonded to the second lead, a bonding area between each of the third inner bumps and each of the first leads is larger than a bonding area between each of the second inner bumps and each of the first leads, and a bonding area between each of the third outer bumps and each of the second leads is larger than a bonding area between each of the second outer bumps and each of the second leads.

9. 9. The semiconductor package structure of claim 8, wherein the fifth length is greater than or equal to the fourth length, the sixth length is greater than the third length, and a bonding area between each of the third outer bumps and each of the second leads is greater than a bonding area between each of the second inner bumps and each of the first leads.

10. 10. The semiconductor package structure of claim 9, wherein a bonding area between each of the third inner bumps and each of the first leads is greater than a bonding area between each of the second outer bumps and each of the second leads.

11. 9. The semiconductor package structure of claim 8, wherein along the second direction, each of the first leads joined to the third inner bump has a fifth lead length (J5), and each of the second leads joined to the third outer bump has a sixth lead length (J6), the fifth lead length being the distance from the long side to the inner end of the third inner bump, the fifth lead length being longer than the third lead length, the sixth lead length being the distance from the long side to the inner end of the third outer bump, and the sixth lead length being longer than the fourth lead length.

12. 9. The semiconductor package structure of claim 8, wherein a virtual line (L) passes through at least one of the first inner bumps along the first direction, and along the second direction, a first distance (S1) is between an inner end of each of the first outer bumps and the virtual line, a second distance (S2) is between an inner end of each of the second outer bumps and the virtual line, and a third distance (S3) is between an inner end of each of the third outer bumps and the virtual line, the first distance being longer than the second distance and the second distance being longer than the third distance.

13. 9. The semiconductor package structure of claim 8, wherein along the first direction, a width of the first area occupies 40-80% of a total width of the chip, a width of the second area occupies 5-15% of the total width of the chip, and a width of the third area occupies 5-15% of the total width of the chip.

14. a surface (120a) having a first area (A) and at least one second area (B) defined along a first direction (X); a first bump group (121) disposed in the first area and including a plurality of first inner bumps (121a) and a plurality of first outer bumps (121b), the first outer bumps being closer to a long side (120c) of the surface than the first inner bumps along a second direction (Y) intersecting the first direction; and at least one second bump group (122) disposed in the second area and including a plurality of second inner bumps (122a) and a plurality of second outer bumps (122b), the second outer bumps being closer to the long side than the second inner bumps along the second direction, a third length (H3) of each of the second inner bumps being longer than the first length (H1) of each of the first inner bumps along the second direction, and a fourth length (H4) of each of the second outer bumps being longer than the second length (H2) of each of the first outer bumps along the second direction.

15. 15. The tip of claim 14, wherein the third length is greater than or equal to the second length and the fourth length is greater than the first length.

16. The chip of claim 14, wherein a first width (W1) of each of the first inner bumps is greater than a second width (W2) of each of the first outer bumps along the first direction.

17. 15. The chip of claim 14, wherein a virtual line (L) passes through at least one of the first inner bumps along the first direction, and has a first distance (S1) from an inner end of each of the first outer bumps to the virtual line along the second direction, and a second distance (S2) from an inner end of each of the second outer bumps to the virtual line, the first distance being longer than the second distance.

18. The surface further includes at least one third bump group (123), and at least one third area (C) is defined on the surface, the second area is located between the first area and the third area, the third bump group is disposed in the third area, the second bump group is located between the first bump group and the third bump group along the first direction, the third bump group includes a plurality of third inner bumps (123a) and a plurality of third outer bumps (123b), and the third outer bumps are located between the first bump group and the third bump group along the second direction.

15. The chip of claim 14, wherein a side bump is closer to the long side than the third inner bump, the second inner bump is located between the first inner bump and the third inner bump, and the second outer bump is located between the first outer bump and the third outer bump along the first direction, and a fifth length (H5) of each of the third inner bumps is longer than the third length of each of the second inner bumps, and a sixth length (H6) of each of the third outer bumps is longer than the fourth length of each of the second outer bumps along the second direction.

Images