Semiconductor Device

Abstract

To provide a semiconductor device in which production capacity can be improved and destruction of a gate insulation film can be prevented.SOLUTION: There are provided: an n-type drift layer 2; an n-type first current diffusion layer 3 provided on an upper face of the drift layer; a p-type base region 6 provided on an upper face of the first current diffusion layer; a p-type gate bottom region 4b provided in the first current diffusion layer; p-type base bottom embedded regions (4a and 5) which are arranged in the first current diffusion layer while being apart from a gate bottom protection region, and brought into contact to a lower face of the base region; an n-type second current diffusion layer 9 which is brought into contact to a side face of the base bottom embedded region orthogonal to a direction being parallel to an upper face of the first current diffusion layer; and insulated gate type electrode structures (11 and 12) arranged in a trench 10 which penetrates the base region and reaches the gate bottom protection region. An impurity concentration ratio of the gate bottom protection region to the first current diffusion layer is larger than the impurity concentration ratio of the base bottom embedded region to the second current diffusion layer.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a highly reliable trench type semiconductor device. [Background technology]

[0002] Conventionally, silicon (Si) semiconductors have been used in power semiconductor devices that are primarily used in power conversion devices and the like. In recent years, silicon carbide (SiC), a wide-gap semiconductor, has been expected to replace Si as a semiconductor material. Compared to conventional semiconductor elements that use Si as a material, SiC semiconductors have the advantages of being able to reduce the resistance of elements in the on-state to one-hundredth of that of conventional semiconductor elements that use Si as a material, and being usable in higher temperature environments (e.g., 200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of SiC is about three times larger than that of Si, and that the dielectric breakdown field strength is about ten times larger than that of Si.

[0003] As power semiconductor devices, Schottky barrier diodes (SBD), field effect transistors (FET), static induction transistors (SIT), insulated gate bipolar transistors (IGBT), etc. are commercially available. Trench MOSFETs are semiconductor devices with a three-dimensional structure in which a trench is formed in a SiC semiconductor substrate and the sidewall of the trench is used as a channel. Therefore, when comparing elements with the same on-resistance, trench MOSFETs can overwhelmingly reduce the element area compared to planar vertical MOSFETs, and are considered to be a particularly promising semiconductor element structure.

[0004] In conventional trench MOSFETs, a channel is formed vertically along the sidewall of a trench provided in a SiC semiconductor layer, resulting in a structure in which the entire inner wall of the trench is covered with a gate insulating film. Since the dielectric breakdown field strength of SiC is about 10 times greater than that of Si, the SiC semiconductor layer does not undergo dielectric breakdown when a high voltage is applied, and a high electric field is also applied to the gate insulating film provided on the inner wall of the trench. In particular, the electric field is likely to concentrate at the bottom of the trench facing the drain electrode, and dielectric breakdown of the gate insulating film easily occurs. In order to improve the reliability of trench MOSFETs, an electric field relaxation structure is required that relieves the electric field concentration at the bottom of the trench and prevents breakdown of the gate insulating film. As an electric field relaxation structure that relieves the electric field concentration at the bottom of the trench, a p-type current diffusion layer (CSL) is provided inside the n-type current diffusion layer (CSL) provided around the trench. + The bottom buried region of the base of the p-type and the bottom of the trench are + A gate bottom protection region of the mold is selectively provided.

[0005] However, in conventional trench MOSFETs, the breakdown voltage of the pn junction between the base bottom buried region and the gate bottom protection region and the current spreading layer is almost the same. Therefore, the breakdown voltage of the pn junction in the gate bottom protection region may be lower than that of the pn junction in the base bottom buried region. In this case, the breakdown voltage of the MOSFET is determined by the breakdown voltage at the bottom of the trench. When avalanche breakdown occurs at the pn junction at the bottom of the trench, carriers are injected into the gate insulating film inside the trench, causing an electric field to concentrate at the bottom of the trench, resulting in dielectric breakdown of the gate insulating film.

[0006] Patent Document 1 describes that an n-type buried layer is provided between the base region and the drift layer by ion implantation in contact with the bottom surface of the base bottom buried region to protect the gate insulating film at the bottom of the trench. By making the n-type impurity concentration of the buried layer higher than the n-type impurity concentration directly under the gate bottom protection region, the electric field strength applied to the base bottom buried region is higher than that of the gate bottom protection region. As a result, avalanche breakdown is more likely to occur in the base bottom buried region rather than the gate bottom protection region, preventing the avalanche current from flowing into the gate insulating film.

[0007] Patent Document 2 describes that an n-type buried layer is provided by ion implantation in a stripe shape in a direction perpendicular to the longitudinal direction of the trench at a position deeper than the base bottom buried region and the gate bottom protection region. The buried layer has a higher impurity concentration than the n-type drift layer and the n-type current spreading layer (CSL) between the base bottom buried region and the trench. As a result, the buried layer can spread the current, mitigating the electric field concentration at the bottom of the trench and suppressing avalanche breakdown at the bottom of the trench.

[0008] Patent Document 3 describes the provision by ion implantation of an n-type base bottom covering layer that covers the surface and side surfaces of the base bottom buried region, and an n-type gate bottom covering layer that partially covers the gate bottom protection region. The base bottom covering layer and the gate bottom covering layer each have a higher impurity concentration than the current spreading layer, and prevent a high electric field from being applied to the gate insulating film at the bottom of the trench.

[0009] Hexagonal SiC has anisotropy in the dielectric breakdown field, and the dielectric breakdown field in the c-axis direction is high (see Non-Patent Document 1). In Patent Documents 1 to 3, a structure is proposed that reduces the electric field strength in a direction parallel to the c-axis, and the anisotropy of the dielectric breakdown field is not taken into consideration. The dielectric breakdown field is low in the direction perpendicular to the c-axis, in which the gate bottom protection region and the base bottom buried region face each other. That is, when the electric field is concentrated in the direction perpendicular to the c-axis, avalanche breakdown occurs at a lower electric field strength than in the c-axis direction. Since the current diffusion layer between the gate bottom protection region and the base bottom buried region has a uniform impurity concentration, avalanche breakdown occurs in the gate bottom protection region, resulting in dielectric breakdown of the gate insulating film.

[0010] Furthermore, in Patent Documents 1 to 3, ion implantation of n-type impurities is required at a position deeper than the bottom surface of the base bottom buried region or the gate bottom protection region, which lengthens the operating time of the ion implantation device in the ion implantation process and reduces productivity. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Patent No. 6617657 [Patent Document 2] JP 2019-121716 A [Patent Document 3] Patent No. 6759563 [Non-patent literature]

[0012] [Non-Patent Document 1] T. Kimoto and JA Cooper, "Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, Appendix C: Major Physical Properties of Common SiC Polytypes", John Wiley & Sons, September 2014, pp 521-524 Summary of the Invention [Problem to be solved by the invention]

[0013] SUMMARY OF THE PRESENT DISCLOSURE In view of the above problems, an object of the present invention is to provide a semiconductor device capable of improving productivity and preventing breakdown of a gate insulating film. [Means for solving the problem]

[0014] In order to achieve the above object, one aspect of the present invention includes: (a) a first conductivity type drift layer made of a hexagonal semiconductor having a band gap wider than that of silicon; (b) a first conductivity type first current spreading layer provided on an upper surface of the drift layer and having a higher impurity concentration than the drift layer; (c) a second conductivity type base region provided on an upper surface of the first current spreading layer; (d) a second conductivity type gate bottom protection region provided inside the first current spreading layer and having a side surface and a bottom surface in contact with the first current spreading layer; and (e) a gate bottom protection region provided inside the first current spreading layer. The semiconductor device according to the present invention comprises: (a) a base bottom buried region of a second conductivity type spaced apart from the base region and in contact with a lower surface of the base region; (f) a second current spreading layer of a first conductivity type in contact with a side surface of the base bottom buried region and having a side surface facing the gate bottom protection region; and (g) an insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region, wherein an impurity concentration ratio of the gate bottom protection region to the first current spreading layer is greater than an impurity concentration ratio of the base bottom buried region to the second current spreading layer. Effect of the Invention

[0015] According to the present invention, it is possible to provide a semiconductor device which can improve productivity and prevent breakdown of the gate insulating film. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a plan view illustrating a semiconductor wafer used in the manufacture of the semiconductor device according to the first embodiment. [Diagram 2] 2 is a plan view showing a schematic arrangement of trenches in the semiconductor device according to the first embodiment. FIG. [Figure 3A] 3 is a schematic cross-sectional view showing an example of a SiC semiconductor device according to the first embodiment, as viewed from the direction of line AA in FIG. 2. [Figure 3B] 3B is a schematic plan view showing an example of the SiC semiconductor device according to the first embodiment, as viewed from the direction of line CC in FIG. 3A. [Figure 4] 2A to 2C are schematic cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to the first embodiment. [Diagram 5]5 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 4 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 5 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 6 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 7 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 8 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 10 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 9 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 11 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 10 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 12 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 11 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 13 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 12 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] 14 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 13 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 15 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 14 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 16] 4 is a schematic cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. [Figure 17] 4 is a schematic cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. [Figure 18] 4 is a schematic cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. [Figure 19]10 is a schematic cross-sectional view showing an example of a semiconductor device according to a second embodiment. FIG. [Figure 20] 10A to 10C are schematic cross-sectional views illustrating an example of a process of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 21] 21 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 20 in the method for manufacturing the semiconductor device according to the second embodiment. FIG. [Figure 22] 22 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 21 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Diagram 23] 23 is a schematic cross-sectional view for illustrating an example of a step subsequent to FIG. 22 in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 24] 10 is a schematic cross-sectional view showing another example of the semiconductor device according to the second embodiment. FIG. [Diagram 25] FIG. 11 is a schematic plan view showing an example of a semiconductor device according to another embodiment. [Figure 26] 26 is a schematic cross-sectional view taken along line BB in FIG. 25. [Figure 27] FIG. 13 is a schematic plan view showing another example of a semiconductor device according to another embodiment. [Figure 28] 28 is a schematic cross-sectional view taken along line CC in FIG. 27. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0018] In this specification, the source region of a MOS transistor is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

[0019] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is n-type and the opposite second conductivity type is p-type will be described as an example. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + and -. However, even if the same n and n are added to the semiconductor region, it does not mean that the impurity concentration of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

[0020] (First embodiment) <Structure of Semiconductor Device> The semiconductor device according to the first embodiment is fabricated based on a semiconductor substrate 100 made of a hexagonal semiconductor such as SiC with a (0001) plane orientation, as shown in FIG. 1. An orientation flat OF indicating the crystal orientation of the semiconductor substrate 100 is provided on the outer periphery of the semiconductor substrate 100. The semiconductor substrate 100 is sliced ​​along a direction that forms a plane inclined at a constant offset angle (off angle) with respect to a specific crystal orientation, and the position of the orientation flat OF is determined by the crystal orientation. Instead of the orientation flat OF, a notch may be provided on the outer periphery of the semiconductor substrate 100. The Z direction perpendicular to the paper surface of FIG. 1 is <0001> The (c-axis) direction is the <11-20> direction, and the Y direction is the <1-100> direction. One semiconductor chip 103 is illustrated on the surface of the semiconductor substrate 100 illustrated in Fig. 1. The semiconductor chip 103 has a rectangular planar shape and is arranged on the semiconductor substrate 100 in a matrix pattern.

[0021] The semiconductor chip 103 is provided with an active section including an active element and a peripheral section having a breakdown voltage structure. FIG. 2 illustrates a plurality of trenches 10 of a MOSFET with a trench gate structure provided in the active section. Although not shown, the peripheral section may be provided with an electric field relaxation region such as a guard ring or a junction termination structure (JTE), a channel stopper, and the like. As shown in FIG. 2, a plurality of trenches 10 extend in stripes along the <11-20> direction on the upper surface of the semiconductor chip 103. The crystal plane of the sidewall of the trench is the (11-20) a-plane or the (1-100) m-plane.

[0022] 3 is a cross-sectional view of the semiconductor device according to the first embodiment as viewed from the direction of line AA in FIG. 2. As shown in FIG. 3, in the semiconductor device according to the first embodiment, -The top surface of the drift layer 2 of the <0001> The plane is perpendicular to the c-axis direction, i.e., the Z-direction. A base region 6 of a second conductivity type (p-type) is disposed on the upper surface of the drift layer 2. The drift layer 2 and the base region 6 are each composed of an epitaxially grown layer (hereinafter abbreviated as "epitaxial layer") made of SiC. An upper portion of the base region 6 is formed of a p-type epitaxial layer having a higher impurity concentration than the base region 6. + An n-type base contact region 8 is selectively provided on the upper portion of the base region 6. The n-type base contact region 8 is in contact with the base contact region 8 and has a higher impurity concentration than the drift layer 2. + A first main region (source region) 7 of a type is optionally provided.

[0023] For example, the impurity concentration of the drift layer 2 is 2×10 15 cm -3 More than 2×10 16 cm -3 Hereinafter, the impurity concentration of the base region 6 is 1×10 17 cm -3 More than 1×10 18 cm -3 The impurity concentration of the base contact region 8 is 5×10 18 cm -3 5×10 or more 20 cm -3 Hereinafter, the impurity concentration of the source region 7 is 5×10 18 cm -3 5×10 or more 20 cm -3 The following is the result.

[0024] A trench 10 having a width of 1 μm or less is provided from the upper surface of the source region 7 and the base region 6 through the base region 6. The source region 7 and the base region 6 are in contact with the side surface of the trench 10. A gate insulating film 11 is provided on the bottom surface and side surface of the trench 10. A gate electrode 12 is embedded in the trench 10 via the gate insulating film 11 to form an insulated gate electrode structure (11, 12). As the gate insulating film 11, in addition to a silicon dioxide film (SiO2 film), any one of a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, or a composite film obtained by stacking a plurality of these films can be used. As the material for the gate electrode 12a, for example, a polysilicon layer (doped polysilicon layer) doped with impurities such as phosphorus (P) or boron (B) at a high impurity concentration can be used.

[0025] An n-type first current spreading layer (CSL) 3 having a higher impurity concentration than the drift layer 2 is selectively provided on the upper part of the drift layer 2. The bottom of the trench 10 reaches the first current spreading layer 3. The first current spreading layer 3 is not necessarily provided. If the first current spreading layer 3 is not provided, the bottom of the trench 10 reaches the drift layer 2. Inside the first current spreading layer 3, a p + A p-type gate bottom protection region 4b is provided inside the first current spreading layer 3 below the base contact region 8 at the same depth as the gate bottom protection region 4b and spaced apart from the gate bottom protection region 4b. + The first buried region 4a is provided with a p-type GaN layer 100. The first current spreading layer 3 has a p-type GaN layer 100 in contact with the upper surface of the first buried region 4a and the lower surface of the base region 6. + A second buried region 5 having a base bottom portion is provided below the base contact region 8. The first buried region 4a and the second buried region 5 constitute a base bottom buried region (4a, 5). The second buried region 5 is also provided below the base contact region 8.

[0026] As shown in FIG. 3A, a n-type junction layer having a higher impurity concentration than the first current spreading layer 3 is formed so as to contact the side surface of the first buried region 4a of the base bottom buried region (4a, 5). + A second current diffusion layer 9 having a n-type conductivity type is provided. The second current diffusion layer 9 has a side surface 19 facing the gate bottom protection region 4b. Therefore, the direction perpendicular to the side surface 19 of the second current diffusion layer 9 is the Y direction, that is, the direction perpendicular to the c-axis. In this way, by selectively increasing the impurity concentration of the n-type region in the pn junction perpendicular to the c-axis, avalanche breakdown can be generated with a low electric field strength. This makes it possible to limit the avalanche position to the side surface of the first buried region 4a, thereby preventing the breakdown of the gate insulating film at the bottom of the trench 10. In this case, the second current diffusion layer 9 may be provided so as to contact the corner of the bottom of the first buried region 4a in the base bottom buried region (4a, 5).

[0027] 3B is a plan view of the semiconductor device according to the first embodiment as viewed from the CC cross section in FIG. 3A. In the CC cross section, the first buried region 4a (base bottom buried region) and the gate bottom protection region 4b are arranged in a stripe shape, and a second current diffusion layer 9 is selectively provided on the side wall of the first buried region 4a. Here, the p + A connecting portion 44 of a type may be provided. The connecting portion 44 connects the gate bottom protection region 4b to the source electrode 15 via the base bottom buried region (4a, 5), so that the gate insulating film at the bottom of the trench 10 can be reliably protected. In this case, a second current diffusion layer 9 may be provided on the side wall of the connecting portion 44. This can enhance the effect of preventing the breakdown of the gate insulating film at the bottom of the trench 10. The connecting portion 44 may be formed at the depth of the second buried region 5 to connect the bottom of the connecting portion 44 to the upper surface of the gate bottom protection region 4b. In this case, the second current diffusion layer 9 is in a stripe shape along the first buried region 4a. The connecting portion 44 may be provided in both the first buried region 4a and the second buried region 5. Furthermore, the second current diffusion layer 9 may be provided on the side wall of the second buried region 5.

[0028] An interlayer insulating film 13 is disposed on the upper surface of the gate electrode 12. A silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used as the interlayer insulating film 13. However, the interlayer insulating film 13 may be a silicon oxide film (PSG) doped with phosphorus (P), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG) doped with boron (B), a Si3N4 film, or the like. A laminate film of these may also be used.

[0029] A source contact layer 14 is provided so as to be in physical contact with the source region 7 and the base contact region 8 exposed between the interlayer insulating film 13. A first main electrode (source electrode) 15 is provided so as to cover the interlayer insulating film 13 and the source contact layer 14. The first main electrode (source electrode) 15 is electrically connected to the source region 7 and the base contact region 8 via the source contact layer 14. For example, the source contact layer 14 may be made of nickel silicide (NiSi x ) film and source electrode 15 can be composed of an aluminum (Al) film or an aluminum-silicon (Al-Si) film. A barrier metal layer (not shown) may be provided between interlayer insulating film 13 and source contact layer 14 and first main electrode (source electrode) 15. A titanium nitride (TiN) film, titanium (Ti) film, or the like can be used as the barrier metal layer. Source electrode 15 is disposed separately from a gate surface electrode (not shown). Although not shown, a gate electrode pad (not shown) disposed on the upper surface of the field insulating film is electrically connected to gate electrode 12.

[0030] The bottom surface of the drift layer 2 is +A second main region (drain region) 1 of a type is disposed on the bottom surface of the drain region 1. A second main electrode (drain electrode) 16 is disposed on the bottom surface of the drain region 1. As the drain electrode 16, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Ti, nickel (Ni) and Au can be used, and further a metal film of molybdenum (Mo), tungsten (W) or the like may be laminated on the bottom layer. In addition, a drain contact layer may be provided between the drain region 1 and the drain electrode 16. The drain contact layer is, for example, nickel silicide (NiSi x ) membrane.

[0031] The impurity concentration of the first current diffusion layer 3 is 5×10 16 cm -3 5×10 or more 17 cm -3 The impurity concentration of the second current spreading layer 9 is 5×10 17 cm -3 5×10 or more 18 cm -3 The first buried region 4a of the base bottom buried region (4a, 5) and the gate bottom protection region 4b have the same impurity concentration, and the impurity concentration is 1×10 18 cm -3 More than 1×10 19 cm -3 The impurity concentration of the second buried region 5 is 1×10 18 cm -3 More than 1×10 19 cm -3 The impurity concentration of the drain region 1 is 1×10 18 cm -3 More than 1×10 19 cm -3 The following is the result.

[0032] In the semiconductor device according to the first embodiment, the drain region 1 is made of a semiconductor substrate (SiC substrate) made of SiC, and the drift layer 2 is made of an epitaxial layer (SiC layer) made of SiC. The semiconductor region constituting the semiconductor device according to the first embodiment including the drain region 1 and the drift layer 2 is not limited to SiC. In addition to SiC, for example, hexagonal semiconductor materials such as gallium nitride (GaN), lonsdaleite (hexagonal diamond), and aluminum nitride (AlN) having a wider bandgap than that of Si (1.1 eV) can be used. The bandgap at room temperature has been reported to be 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. In the present invention, a semiconductor having a bandgap wider than that of silicon is defined as a wide bandgap semiconductor.

[0033] During operation of the semiconductor device according to the first embodiment, when the source electrode 15 is set to earth potential, a positive voltage is applied to the drain electrode 16, and a positive voltage equal to or greater than a threshold is applied to the gate electrode 12, an inversion layer (channel) is formed on the side surface of the trench 10 in the base region 6, resulting in an ON state. The inversion layer is formed on the surface of the base region 6 exposed on the side surface of the trench 10, which is the interface between the base region 6 and the gate insulating film 11 sandwiched at a position where the base region 6 faces the gate electrode 12. In the ON state, a current flows from the drain electrode 16 to the source electrode 15 via the drain region 1, the drift layer 2, the first current diffusion layer 3, the inversion layer of the base region 6, and the source region 7. On the other hand, when the voltage applied to the gate electrode 12 is less than the threshold, an inversion layer is not formed in the base region 6, resulting in an OFF state, and no current flows from the drain electrode 16 to the source electrode 15.

[0034] In the first embodiment, as shown in FIG. 3, the second current diffusion layer 9 is provided in contact with the side surface of the first buried region 4a of the base bottom buried region (4a, 5) facing the gate bottom protection region 4b. The second current diffusion layer 9 has a higher impurity concentration than the first current diffusion layer 3. The impurity concentration ratio of the gate bottom protection region 4b to the first current diffusion layer 3 is greater than the impurity concentration ratio of the first buried region 4a to the second current diffusion layer 9. Therefore, the electric field is higher on the side surface 19 of the second current diffusion layer 9 in contact with the side surface of the first buried region 4a than on the side surface of the gate bottom protection region 4b facing the gate bottom protection region 4b in the Y direction, and avalanche breakdown is more likely to occur on the side surface 19 of the second current diffusion layer 9. The impurity concentration of each region used here is the net impurity concentration taking into account both p-type impurities and n-type impurities.

[0035] In addition, as described in Non-Patent Document 1, the dielectric breakdown field of hexagonal 4H-SiC is 2.2MVcm in the direction perpendicular to the c-axis. -1 , 2.8MVcm parallel to the c-axis -1 3. The Y direction in FIG. 3 is perpendicular to the c-axis, and the Z direction is parallel to the c-axis. Compared with the bottom surface of the first buried region 4a in contact with the first current spreading layer 3, the side surface 19 of the second current spreading layer 9, which has a higher impurity concentration than the first current spreading layer 3, has a higher electric field. Furthermore, the dielectric breakdown electric field is lower on the side surface 19 of the second current spreading layer 9 perpendicular to the c-axis than on the bottom surface of the first buried region 4a parallel to the c-axis. Therefore, avalanche breakdown is likely to occur on the side surface 19 of the second current spreading layer 9, which has a lower dielectric breakdown electric field. When avalanche breakdown occurs, the avalanche current flows through the path Pa passing through the inside of the first buried region 4a via the side surface 19 of the second current spreading layer 9 shown by the solid line in FIG. 3, rather than the path Pb passing through the bottom surface of the first buried region 4a shown by the dotted line in FIG. 3. In this manner, in the semiconductor device according to the first embodiment, avalanche breakdown occurs on the side surface 19 of the second current spreading layer 9 where the breakdown electric field is low, and the avalanche current flows while avoiding the gate bottom protection region 4b. Therefore, it is possible to prevent the breakdown of the gate insulating film.

[0036] As described later, the second current spreading layer 9 is formed on the side surface of the first buried region 4a by selectively implanting n-type impurity ions in multiple stages from the top surface of the n-ion implanted layer that is the layer below the first current spreading layer 3. In a conventional electric field relaxation structure formed in contact with the bottom surface of the base bottom buried region, it is necessary to implant n-type impurity ions at a position deeper than the bottom surface of the base bottom buried region. In contrast, in the first embodiment, the depth of the multiple ion implantation for forming the second current spreading layer 9 may be as deep as the bottom surface of the first buried region 4a. Therefore, the operating time of the ion implantation device in the process of forming the second current spreading layer 9 can be shortened, and the production capacity can be improved.

[0037] <Method of Manufacturing Semiconductor Device> Next, the method for manufacturing the SiC semiconductor device according to the first embodiment will be described by taking a trench-gate MOSFET as an example, with reference to the process cross-sectional views of Figures 4 to 15. Note that the method for manufacturing the trench-gate MOSFET described below is just an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0038] First, n-type impurities such as nitrogen (N) are added. + A type SiC semiconductor substrate (substrate) 1p is prepared. The substrate 1p has a (0001) surface. As shown in FIG. - A n-type drift layer 2 is epitaxially grown. Next, a photoresist film is applied to the upper surface of the drift layer 2, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted into the drift layer 2 in multiple stages from the upper surface side of the drift layer 2. In this manner, an n-type n ion-implanted layer 3p is formed on the upper part of the drift layer 2.

[0039] An oxide film made of SiO2 is deposited on the upper surface of the n ion-implanted layer 3p by CVD or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography and dry etching or the like. Using the patterned oxide film 40 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the n ion-implanted layer 3p. As a result, as shown in FIG. 5, p-type impurity ions such as aluminum (Al) are implanted in the upper part of the n ion-implanted layer 3p. + The first buried region 4a and p + In this case, when it is desired to make the first buried region 4a and the gate bottom protection region 4b have different impurity concentrations, they may be implanted with ions separately.

[0040] After removing the oxide film 40, a photoresist film is applied to the upper surfaces of the n ion implantation layer 3p, the first buried region 4a and the gate bottom protection region 4b, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 42 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the n ion implantation layer 3p so as to contact the first buried region 4a. As a result, as shown in FIG. 6, n ions having a higher impurity concentration than the n ion implantation layer 3p are formed on the side surface of the first buried region 4a perpendicular to the Y direction. + A second current spreading layer 9 having a silicide layer is selectively formed on the side surface of the first buried region 4a. The second current spreading layer 9 is formed on the side surface of the first buried region 4a so as to extend from the top surface to the bottom surface.

[0041] After removing the photoresist film 42, an n ion implantation layer 3p, a second current diffusion layer 9, a first buried region 4a, and an upper surface of the gate bottom protection region 4b are implanted with an n -A type epitaxial layer is grown. A photoresist film is applied to the upper surface of the epitaxial layer, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper part of the epitaxial layer from the upper surface side of the epitaxial layer. As a result, as shown in FIG. 7, an n-ion implantation layer 5p is formed on the n-ion implantation layer 3p, the second current diffusion layer 9, the first buried region 4a, and the gate bottom protection region 4b. As will be described later, the n-ion implantation layer 3p and the n-ion implantation layer 5p constitute the first current diffusion layer 3, and it is desirable that the impurity concentration of the n-ion implantation layer 5p is higher than that of the n-ion implantation layer 3p.

[0042] Next, an oxide film made of SiO2 is deposited on the upper surface of the n ion implantation layer 5p by CVD or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography and dry etching or the like. Using the patterned oxide film 50 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the n ion implantation layer 5p. As a result, as shown in FIG. 8, p + A second buried region 5 of the type is selectively formed. Then, a base bottom buried region (4a, 5) consisting of the first buried region 4a and the second buried region 5 is formed.

[0043] After removing the oxide film 50, a p-type base region 6p is epitaxially grown on the upper surface of the second buried region 5 and the n-ion implanted layer 5p, as shown in FIG. 9. A photoresist film is applied to the surface of the base region 6p, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are selectively implanted into the base region 6p in multiple stages from the upper surface side of the base region 6p. As a result, n-type impurity ions such as phosphorus (P) are formed in the upper part of the base region 6p, as shown in FIG. + A source region 7p of the type is formed.

[0044] After removing the photoresist film used as a mask for ion implantation, an oxide film made of SiO2 is deposited on the upper surface of the source region 7p by CVD or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography and dry etching or the like. Using the patterned oxide film 80 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages into the source region 7p from the upper surface side of the source region 7p. As a result, p-type impurity ions such as aluminum (Al) are implanted in the upper part of the base region 6p above the n ion implantation layer 5p, as shown in FIG. 11. + A mold base contact region 8 is formed.

[0045] After removing the oxide film 80 used as an ion implantation mask, an oxide film made of SiO2 is deposited on the upper surface of the base contact region 8 and the source region 7p by CVD or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned by photolithography and dry etching techniques. Using the patterned oxide film 82 as an etching mask, a trench 10 is selectively formed by dry etching techniques such as ICP-RIE. As a result, as shown in FIG. 12, the trench 10 penetrates the source region 7, the base region 6, and the first current diffusion layer 3 to reach the gate bottom protection region 4b. An n-type first current diffusion layer 3 consisting of an n ion implantation layer 3p and an n ion implantation layer 5p is formed on the upper surface of the drift layer 2.

[0046] After removing the oxide film 82, a carbon (C) film is formed on the upper surface of the trench 10 by carbon sputtering or the like. Then, a heat treatment is performed to simultaneously activate the implanted n-type impurity ions and p-type impurity ions. After removing the carbon film, a gate insulating film 11p such as a SiO2 film is formed on the bottom and side surfaces of the trench 10 and on the upper surfaces of the source region 7 and the base contact region 8 by thermal oxidation or chemical vapor deposition (CVD) or the like. Next, as shown in FIG. 13, a polysilicon layer (doped polysilicon layer) 12p doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD or the like so as to fill the trench 10.

[0047] Then, a part of the polysilicon layer 12p and a part of the gate insulating film 11p are selectively removed by photolithography and dry etching. As shown in FIG. 14, a pattern of the gate electrode 12 made of the gate insulating film 11 and the polysilicon layer is formed to form an insulated gate electrode structure (11, 12). Next, an insulating film is deposited on the upper surface of the insulated gate electrode structure (11, 12) made of the gate electrode 12 and the gate insulating film 11 by CVD or the like. As the insulating film, boron phosphorus glass (BPSG), NSG, or the like is used. Then, a part of the deposited insulating film is selectively removed by photolithography and dry etching or the like. As a result, a source electrode contact hole is opened in the interlayer insulating film 13 as shown in FIG. 14. Although not shown, a gate contact hole is also opened in the interlayer insulating film 13 at a location different from the source electrode contact hole so that a part of the gate surface electrode connected to the gate electrode 12 is exposed.

[0048] A metal layer such as a Ni film is deposited by sputtering or vapor deposition, and the metal layer is patterned by photolithography and RIE. Then, rapid thermal annealing (RTA), for example, at about 1000°C, is performed to form NiSi x Then, by removing the unreacted Ni film, a source contact layer 14 is formed on the upper surface of the source region 7 and the base contact region 8 as shown in FIG. 15. Next, a barrier metal layer (not shown) such as a Ti film or a TiN film and a metal layer such as an Al film are deposited by a sputtering technique or the like, and the barrier metal layer and the metal layer are patterned by a photolithography technique, an RIE technique or the like. As a result, a laminated structure of the barrier metal layer and the source electrode 15 is formed so as to cover the source contact layer 14 and the interlayer insulating film 13. In addition, the patterns of the source electrode 15 and the gate surface electrode are separated, and the gate surface electrode is electrically connected to the gate electrode 12 via a wiring layer (not shown) provided on the field insulating film (not shown).

[0049] Furthermore, the bottom surface of the substrate 1p is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Thereafter, a drain electrode 16 made of Ti, Ni, Au or the like is formed on the entire bottom surface of the drain region 1 by a sputtering method or a deposition method or the like. In this manner, the trench gate type semiconductor device shown in FIG. 3 is completed.

[0050] In the first embodiment, as shown in FIG. 6, the second current diffusion layer 9 is formed on the side of the first buried region 4a by selectively implanting n-type impurity ions in multiple stages from the upper surface of the n ion implantation layer 3p. In the conventional electric field relaxation structure formed in contact with the bottom surface of the base bottom buried region, it was necessary to implant n-type impurity ions at a position deeper than the bottom surface of the base bottom buried region. In contrast, in the first embodiment, the depth of the multiple ion implantation for forming the second current diffusion layer 9 may be as deep as the bottom surface of the first buried region 4a. Therefore, the operating time of the ion implantation device in the process of forming the second current diffusion layer 9 can be shortened, and the production capacity can be improved. As a result, it is possible to reduce the manufacturing cost of the semiconductor device.

[0051] As described above, the gate bottom protection region 4b and the first buried region 4a of the base bottom buried region (4a, 5) have the same impurity concentration, and the second current diffusion layer 9 has a higher impurity concentration than the first current diffusion layer 3. However, the gate bottom protection region 4b may have a higher impurity concentration than the first buried region 4a. In this case, the first current diffusion layer 3 and the second current diffusion layer 9 may have almost the same impurity concentration. Alternatively, the second current diffusion layer 9 may not be provided, and only the first current diffusion layer 3 may be provided. The impurity concentration ratio of the gate bottom protection region 4b to the first current diffusion layer 3 can be made larger than the impurity concentration ratio of the first buried region 4a to the second current diffusion layer 9 or the first current diffusion layer 3. Therefore, the electric field becomes higher on the side surface of the first buried region 4a than on the side surface of the gate bottom protection region 4b facing the gate bottom protection region 4b in the Y direction, and avalanche breakdown can be easily generated on the side surface of the first buried region 4a. Here, the impurity concentration being the same means that the impurity concentration is the same within the range of manufacturing variations, and includes a difference of about 10%.

[0052] In addition, the second current diffusion layer 9 is provided on the side surface of the first buried region 4a of the base bottom buried region (4a, 5), but is not limited thereto. + The second current spreading layer 9a may be provided so as to connect over the entire side surface of the base bottom buried region (4a, 5), i.e., from the side surface of the first buried region 4a to the side surface of the second buried region 5. In this case, after the step of forming the second buried region 5 shown in FIG. 8, n-type impurity ions such as nitrogen (N) may be selectively implanted in multiple stages into the n ion implanted layer 5p so as to contact the second buried region 5 from the top surface of the n ion implanted layer 5p. Also, as shown in FIG. 17, an n-type current spreading layer 9a having a side surface 19b perpendicular to the Y direction may be formed only on a part of the side surface of the bottom of the first buried region 4a. + Alternatively, a n-type second current diffusion layer 9b may be provided. Although the area of ​​the side surface 19b is reduced, the electric field strength can be increased. Alternatively, as shown in FIG. 18, a n-type second current diffusion layer 9b having a side surface 19c perpendicular to the Y direction may be provided on the entire side surface of the second buried region 5. + In addition, the second current diffusion layer 9c may be provided over the entire surface in the longitudinal direction (X direction) of the trench, or may be provided selectively.

[0053] Second embodiment <Structure of Semiconductor Device> As shown in FIG. 19, the semiconductor device according to the second embodiment has an n-type semiconductor layer having a higher impurity concentration than the first current spreading layer 3 so as to contact the side surface of the first buried region 4a of the base bottom buried region (4a, 5) inside the first current spreading layer 3. + A second current diffusion layer 9d of a n-type impurity type having a higher impurity concentration than the first current diffusion layer 3 is provided on the upper portion of the drift layer 2 so as to contact the bottom surface of the first buried region 4a. +A third current diffusion layer 20 having a lattice structure is provided. The third current diffusion layer 20 is metallurgically connected to the second current diffusion layer 9d. The second current diffusion layer 9d has a side surface 19d facing the gate bottom protection region 4b. The third current diffusion layer 20 has a bottom surface 21a facing the drain region 1. The direction perpendicular to the side surface 19d of the second current diffusion layer 9d is the Y direction perpendicular to the c-axis. The direction perpendicular to the bottom surface 21a of the third current diffusion layer 20 is the Z direction parallel to the c-axis. Other configurations of the semiconductor device according to the second embodiment are similar to those of the first embodiment, so duplicated explanations will be omitted.

[0054] As shown in FIG. 19, the side and bottom of the first buried region 4a are covered with the second and third current spreading layers 9d and 20. Therefore, by adding the third current spreading layer 20, the electric field strength around the first buried region 4a can be increased. The side 19d of the second current spreading layer 9d is a surface perpendicular to the c-axis, and the dielectric breakdown electric field is lower than that of the bottom surface 21a of the third current spreading layer 20, which is a surface parallel to the c-axis. Therefore, the avalanche breakdown occurs on the side of the side 19d of the second current spreading layer 9d, which has a lower dielectric breakdown electric field, and the avalanche current flows through the inside of the first buried region 4a via the side 19d of the second current spreading layer 9d, as in the first embodiment. In the second embodiment, the avalanche current also flows while avoiding the gate bottom protection region 4b, making it possible to prevent dielectric breakdown of the gate insulating film.

[0055] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a SiC semiconductor device according to the second embodiment will be described using the process cross-sectional views of Figures 20 to 23, taking a trench-gate MOSFET as an example. Note that the method for manufacturing a trench-gate MOSFET described below is just an example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0056] First, n-type impurities such as nitrogen (N) are added. + A type SiC semiconductor substrate (substrate) 1p is prepared. The substrate 1p has a (0001) surface. -A n-type drift layer 2 is epitaxially grown. Next, a photoresist film is applied to the upper surface of the drift layer 2, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted into the drift layer 2 in multiple stages from the upper surface side of the drift layer 2. In this manner, an n-type n ion-implanted layer 3p is formed on the upper part of the drift layer 2.

[0057] An oxide film made of SiO2 is deposited on the upper surface of the n ion implantation layer 3p by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. A photoresist film is applied to the patterned oxide film 40 and the upper surface of the n ion implantation layer 3p, and the photoresist film is patterned by photolithography technology or the like. Using the patterned photoresist film 41 as an ion implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages from the upper surface side of the n ion implantation layer 3p, from the interface between the n ion implantation layer 3p and the drift layer 2, into the upper part of the drift layer 2. In this way, n impurity ions are formed in the upper part of the drift layer 2, as shown in FIG. 20. + A third current spreading layer 20 of the same type is formed.

[0058] After removing the photoresist film 41, p-type impurity ions such as aluminum (Al) are implanted into the n ion-implanted layer 3p in multiple stages using the oxide film 40 as a mask for ion implantation. As a result, as shown in FIG. + The first buried region 4a and p + The first buried region 4a is formed so as to contact the upper surface of the third current spreading layer 20.

[0059] After removing the oxide film 40, a photoresist film is applied to the upper surfaces of the n ion implantation layer 3p, the first buried region 4a and the gate bottom protection region 4b, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film 42 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the n ion implantation layer 3p so as to contact the first buried region 4a. As a result, as shown in FIG. 22, n ions are implanted on the side surface of the first buried region 4a perpendicular to the Y direction. + The second current spreading layer 9d is formed on the entire side surface of the first buried region 4a from the top surface to the bottom surface so as to be connected to the third current spreading layer 20.

[0060] After removing the photoresist film 42, an n ion implantation layer 3p, a second current diffusion layer 9, a first buried region 4a, and an upper surface of the gate bottom protection region 4b are implanted with an n - A type epitaxial layer is grown. A photoresist film is applied to the upper surface of the epitaxial layer, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper part of the epitaxial layer from the upper surface side of the epitaxial layer. As a result, as shown in FIG. 23, an n-ion implantation layer 5p is formed on the n-ion implantation layer 3p, the second current diffusion layer 9d, the first buried region 4a, and the gate bottom protection region 4b. Thereafter, the same manufacturing steps as those of the first embodiment shown in FIG. 8 to FIG. 15 are carried out to complete the trench gate type semiconductor device shown in FIG. 19.

[0061] The second current spreading layer 9d is provided on the entire side surface of the first buried region 4a of the base bottom buried region (4a, 5), but may be provided on only a part of the side surface. For example, as shown in FIG. 24, a n-type semiconductor device having a side surface 19f perpendicular to the Y direction only on a part of the side surface of the bottom of the first buried region 4a may be provided. +Alternatively, a second current diffusion layer 9f of a type having a junction hole 19c may be provided. Although the third current diffusion layer 9d is provided on the entire bottom surface of the first buried region 4a, it may be provided partially. In this case, it is possible to make it easier for an avalanche to occur at the boundary portion of the third current diffusion layer 9d. Note that in FIG. 24, the structure above the source region 7 and the base contact region 8 is omitted. The second current diffusion layer 9f is connected to the third current diffusion layer 20. Although the area of ​​the side surface 19f is reduced, the electric field strength can be increased.

[0062] (Other embodiments) As described above, the insulated gate semiconductor device according to the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0063] In the semiconductor device according to the second embodiment, the third current spreading layer 20 is provided, but multiple third current spreading layers may be provided. For example, as shown in Figs. 25 and 26, multiple rectangular third current spreading layers 20a are provided in contact with the bottom surface of the first buried region 4a. The side surface 19g of each of the multiple third current spreading layers 20a is perpendicular to the Y direction. Therefore, an avalanche current can be introduced into the side surface 19g of the third current spreading layer 20.

[0064] 27 and 28, two third current spreading layers 20b extending in a strip shape may be provided in contact with the bottom surface of the first buried region 4a. Each side surface 19h of the third current spreading layer 20b is perpendicular to the Y direction. Therefore, an avalanche current can be introduced into the side surface 19h of the third current spreading layer 20b. Although two third current spreading layers 20b are illustrated in FIG. 27, the number of third current spreading layers 20b may be three or more.

[0065] 25 to 28 may be connected to a second current spreading layer (not shown). Alternatively, only the third current spreading layers 20a and 20b may be provided, and the second current spreading layer may not be provided.

[0066] Thus, the present invention naturally includes various embodiments not described here, such as configurations in which the configurations described in the above embodiments and modifications are applied in any way. For example, the base bottom buried region (4a, 5) may be designed to have a concentration distribution inside, so that an avalanche occurs on the sidewall of the base bottom buried region (4a, 5). Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0067] 1...Drain region (second main region) 1p,100...Semiconductor substrate (substrate) 2. Drift layer 3...First current spreading layer 3p, 5p...n ion-implanted layers 4a…First buried region (4a,5)…Base bottom buried region 4b…Gate bottom protection area 5...Second buried region 6, 6p...base region 7, 7p...Source region (first main region) 8…Base contact region 9…Second current spreading layer 10. Trench 11, 11p...Gate insulating film (11, 12) Insulated gate electrode structure 12, 12a...gate electrode 13...Interlayer insulating film 14…Source contact layer 15...Source electrode (first main electrode) 16...Drain electrode (second main electrode) 19…Side 20...Third current spreading layer 21…Bottom 40, 50, 80, 82...Oxide film 41, 42...Photoresist film 44…Connection

Claims

1. a first conductivity type drift layer made of a hexagonal semiconductor having a band gap wider than that of silicon; a first current diffusion layer of a first conductivity type provided on an upper surface of the drift layer and having a higher impurity concentration than the drift layer; a second conductivity type base region provided on an upper surface of the first current spreading layer; a second conductivity type gate bottom protection region provided within the first current spreading layer and having a side surface and a bottom surface in contact with the first current spreading layer; a second conductivity type base bottom buried region located inside the first current spreading layer and spaced apart from the gate bottom protection region and in contact with a lower surface of the base region; a second current spreading layer of the first conductivity type in contact with a side surface of the base bottom buried region and having a side surface facing the gate bottom protection region; an insulated gate electrode structure provided within a trench that penetrates the base region and reaches the gate bottom protection region; a ratio of an impurity concentration of the gate bottom protection region to the first current spreading layer is greater than a ratio of an impurity concentration of the base bottom buried region to the second current spreading layer.

2. the hexagonal semiconductor is silicon carbide; 2. The semiconductor device according to claim 1, wherein an upper surface of the drift layer is a (0001) surface.

3. the gate bottom protection region and the base bottom buried region have the same impurity concentration; 3. The semiconductor device according to claim 1, wherein the second current spreading layer has a higher impurity concentration than the first current spreading layer.

4. 4. The semiconductor device according to claim 1, wherein the second current spreading layer is provided on the entire side surface of the base bottom buried region.

5. 4. The semiconductor device according to claim 1, wherein the second current spreading layer is in contact with a corner of a bottom of the base bottom buried region.

6. the base bottom buried region includes a first buried region of a second conductivity type provided at the same level as the gate bottom protection region, and a second buried region of the second conductivity type having a lower surface in contact with an upper surface of the first buried region and an upper surface in contact with the lower surface of the base region; 4. The semiconductor device according to claim 1, wherein the second current spreading layer is in contact with a side surface of the first buried region.

7. the base bottom buried region includes a first buried region of a second conductivity type provided at the same level as the gate bottom protection region, and a second buried region of the second conductivity type having a lower surface in contact with an upper surface of the first buried region and an upper surface in contact with the lower surface of the base region; 4. The semiconductor device according to claim 1, wherein the second current spreading layer is in contact with a side surface of the second buried region.

8. 8. The semiconductor device according to claim 1, further comprising a third current spreading layer of the first conductivity type having a higher impurity concentration than the first current spreading layer, the third current spreading layer being in contact with a bottom surface of the base bottom buried region.

9. 9. The semiconductor device according to claim 8, wherein the third current spreading layer is provided in a plurality of layers spaced apart from each other.

10. a second conductivity type connection portion is further provided that connects the gate bottom protection region and the base bottom buried region; 10. The semiconductor device according to claim 1, wherein the second current spreading layer is also provided on a side wall of the connection portion.

11. the first current spreading layer and the second current spreading layer have the same impurity concentration; 3. The semiconductor device according to claim 1, wherein the gate bottom protection region has a higher impurity concentration than the base bottom buried region.

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