Semiconductor Device

Abstract

Provided is a semiconductor device having a high breakdown-voltage characteristic and capable of preventing a breakdown due to a large transient current. The semiconductor device has a super-junction structure comprising a first conductivity-type first column region and a second conductivity-type second column region disposed adjacent to the first column region, and comprises: a second conductivity-type first semiconductor layer disposed over the first column region and the second column region; a first conductivity-type second semiconductor layer disposed over the first semiconductor layer; a first conductivity-type first semiconductor region which is electrically connected to a first electrode, is spaced apart from the first semiconductor layer, and is disposed in an upper-surface portion of the second semiconductor layer; and a second conductivity-type second semiconductor region which is electrically connected to a second electrode, is spaced apart from the first semiconductor region, is disposed in at least the upper-surface portion of the second semiconductor layer, and is electrically connected to the first semiconductor layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present invention relates to a semiconductor device. [Background technology]

[0002] There are power semiconductor devices that are used for high voltage and large current applications. Known power semiconductor devices utilize a conductivity modulation effect that reduces the resistance of a drift layer or a collector layer in an on-state.

[0003] Semiconductor devices utilizing the conductivity modulation effect include, for example, thyristors, insulated gate bipolar transistors (IGBTs), bipolar transistors (BJTs), and the like.

[0004] Among these, thyristors and IGBTs are capable of passing a large current in a large current region, while BJTs are capable of passing a large current in a region below the built-in potential. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] L. Theolier, C. Benboujema, A. Schellmanns, N. Batut, Y. Raingeaud, JB Quoirin, “BJT Application Expansion by Insertion of Superjunction”, 22nd ISPSD, pp 157-160, 2010 Summary of the Invention [Problem to be solved by the invention]

[0006] However, although BJTs have excellent current characteristics at the time of rise, they have the disadvantage that they have a low breakdown voltage between the base and emitter and are easily destroyed when a large current flows transiently, such as when the device is turned off.

[0007] An object of the embodiments of the present invention is to provide a semiconductor device that has high breakdown voltage characteristics and is capable of suppressing breakdown due to a transient large current. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment has a superjunction structure formed by a first column region of a first conductivity type and a second column region of a second conductivity type disposed adjacent to the first column region, and further includes first and second electrodes disposed on one side of the superjunction structure, constituting a transistor and controlling a current flowing through the transistor, and a third electrode disposed on the opposite side of the superjunction structure to the first electrode and the second electrode, constituting the transistor, the first semiconductor layer of the second conductivity type being disposed on the column region of the first electrode; a second semiconductor layer of the first conductivity type being disposed on the first semiconductor layer; a first semiconductor region of the first conductivity type being electrically connected to the first electrode, the first semiconductor region being spaced apart from the first semiconductor layer and disposed in a surface portion of the second semiconductor layer; and a second semiconductor region of the second conductivity type being electrically connected to the second electrode, the second semiconductor region being spaced apart from the first semiconductor region and disposed in at least a surface portion of the second semiconductor layer, and electrically connected to the first semiconductor layer. Effect of the Invention

[0009] According to the present invention, a semiconductor device is obtained which has high breakdown voltage characteristics and is capable of suppressing breakdown due to a transient large current. [Brief description of the drawings]

[0010] [Figure 1]FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a schematic view of a depletion layer when the semiconductor device according to the first embodiment is in an off state. [Diagram 3] FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to a comparative example. [Figure 4] FIG. 4 is a cross-sectional view showing an example of the configuration of the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a diagram illustrating an example of a configuration of a semiconductor device according to the third embodiment. As shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Modification 1 of Embodiment 3. As shown in FIG. [Figure 7] FIG. 7 is a diagram illustrating an example of a configuration of a semiconductor device according to Modification 2 of Embodiment 3. In FIG. [Figure 8] FIG. 8 is a diagram in which current vectors of the semiconductor device according to the first embodiment are plotted. [Figure 9] FIG. 9 is an electron density contour plot and a current line plot of the semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a graph showing the donor impurity concentration, the acceptor impurity concentration, and the electron density of the semiconductor device according to the second example. [Figure 11] FIG. 11 is a graph showing the electrical characteristics of the semiconductor device according to the third example. [Figure 12] FIG. 12 is a graph showing the breakdown voltage characteristics of the semiconductor devices according to Example 4 and the comparative example. [Figure 13] FIG. 13 is a graph showing the dependency of the on-resistance on the transistor pitch in the semiconductor device according to the fifth example. [Figure 14] FIG. 14 is a graph showing the dependency of the on-resistance and the current amplification factor on the distance from the end of the n-source region to the end of the source contact in the semiconductor device according to Example 6. In FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. In addition, the components in the following embodiments include those that a person skilled in the art can easily imagine or are substantially the same.

[0012] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to the drawings.

[0013] (Example of the configuration of a semiconductor device) Fig. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to embodiment 1. As shown in Fig. 1, the semiconductor device 1 of embodiment 1 includes a semiconductor substrate 10 including an n-type semiconductor layer 11, an n-type column region 12, a p-type column region 13, and a p-type channel layer 14, an n-type semiconductor layer 15, a p-type gate region 16, an n-type source region 17, a source electrode 21, a gate electrode 22, and a drain electrode 23. The names of the source electrode 21, the gate electrode 22, the drain electrode 23, and the like are for convenience and do not necessarily specify their functions.

[0014] The semiconductor substrate 10 has an n-type semiconductor layer 11, which is an n-type semiconductor layer, at the bottom layer. On the n-type semiconductor layer 11, n-type column regions 12 as first column regions which are n-type semiconductor regions and p-type column regions 13 as second column regions which are p-type semiconductor regions are alternately arranged adjacent to each other. These n-type column regions 12 and p-type column regions 13 form a superjunction structure. On the n-type column regions 12 and p-type column regions 13, a p-type channel layer 14 as a first semiconductor layer which is a p-type semiconductor layer is arranged.

[0015] On the p-type channel layer 14, an n-type semiconductor layer 15 is disposed as a second semiconductor layer, which is an n-type semiconductor layer formed by, for example, epitaxial growth. In the n-type semiconductor layer 15, a p-type gate region 16 is disposed as a second semiconductor region, which is a p-type diffusion region extending from the surface portion of the n-type semiconductor layer 15 to the p-type channel layer 14. In addition, an n-type source region 17 is disposed as a first semiconductor region, which is an n-type diffusion region, in the surface portion of the n-type semiconductor layer 15 sandwiched between the p-type gate regions 16. The n-type source region 17 is isolated from the p-type channel layer 14 and the p-type gate region 16 by the n-type semiconductor layer 15. In this case, it is preferable that the distance between the n-type source region 17 and the p-type gate region 16 is, for example, 3 μm or more.

[0016] The total amount of impurities in the n-type column region 12 and the total amount of impurities in the p-type column region 13 are set to be approximately the same. The impurity concentration of the n-type semiconductor layer 15 is lower than the impurity concentration of the n-type column region 12, for example, 1×10 15 cm -3 The impurity concentration of the p-type gate region 16 is set to be higher than the impurity concentration of the p-type channel layer 14.

[0017] A gate electrode 22 as a second electrode is disposed on the p-type gate region 16 and is connected to the p-type gate region 16 via a gate contact 22c. A source electrode 21 as a first electrode is disposed so as to cover the entire region and is connected to the n-type source region 17 via a source contact 21c. An insulating layer 31 is disposed between the gate electrode 22 and the source electrode 21, and the gate electrode 22 and the source electrode 21 are insulated from each other. A drain electrode 23 as a third electrode is disposed so as to cover the entire lower surface of the semiconductor substrate 10 on the n-type semiconductor layer 11 side.

[0018] The operation of the semiconductor device 1 configured as above will be described below.

[0019] When the semiconductor device 1 is turned on, a positive voltage is applied to the drain electrode 23 so that the drain side has a positive potential relative to the source side, and a positive voltage is applied to the gate electrode 22. As a result, holes are injected from the p-type gate region 16 to the n-type source region 17.

[0020] Furthermore, holes are injected from the p-type gate region 16 into the p-type channel layer 14. The holes injected into the p-type channel layer 14 flow through the p-type channel layer 14 into the p-type column region 13 and the n-type column region 12. As a result, at least the upper structure of the superjunction structure has a low resistance due to conductivity modulation.

[0021] On the other hand, electrons are injected from the n-type source region 17 into the p-type channel layer 14. The electrons injected into the p-type channel layer 14 flow through the p-type channel layer 14 into the low-resistance p-type column region 13 and n-type column region 12, and finally reach the drain electrode 23. As a result, a current flows between the source electrode 21 and the drain electrode 23.

[0022] When the semiconductor device 1 is in an off state, no gate voltage is applied to the gate electrode 22. In this state, when a positive voltage is applied to the drain electrode 23, a depletion layer spreads from each of the multiple pn junctions between the p-type column region 13 and the n-type column region 12 to both sides of the p-type column region 13 and the n-type column region 12. This allows the superjunction structure to be depleted at a low electric field strength, making it possible to make the semiconductor device 1 withstand high voltages.

[0023] In the semiconductor device 1 of the first embodiment, an n-type semiconductor layer 15 having a low impurity concentration is disposed between the n-type source region 17 and the p-type channel layer 14. The n-type source region 17 and the p-type gate region 16 are also separated by the n-type semiconductor layer 15. As described above, the impurity concentration of the n-type semiconductor layer 15 is set to, for example, 1×10 15 cm -3 By setting the distance between the n-type source region 17 and the p-type gate region 16 to, for example, 3 μm or more, the breakdown voltage between the n-type source region 17 and the p-type gate region 16 becomes, for example, 50 V or more.

[0024] (Transistor pitch) Next, a preferred configuration of the semiconductor device 1 of the first embodiment will be described with reference to FIG.

[0025] In the semiconductor device 1 of the first embodiment, the smaller the pitch W2 of the superjunction structure, the higher the impurity concentration of the n-type column region 12 can be, and therefore the lower the on-resistance can be.

[0026] On the other hand, the pitch W1 of the transistor depends on the width of the n-type source region 17, and there is an optimum value for the width of the n-type source region 17. This is because, when the width of the n-type source region 17 increases, the number of electrons injected from the n-type source region 17 to the p-type channel layer 14 increases, while the moving distance of holes in the n-type source region 17 and the p-type channel layer 14 becomes longer, resulting in an increase in the source resistance and channel resistance.

[0027] Therefore, in the semiconductor device 1, it is preferable to fix the pitch W2 of the superjunction structure, set the width of the n-type source region 17 so as to minimize the on-resistance of the semiconductor device 1, and set the pitch W1 of the transistors based on the width of the n-type source region 17.

[0028] (Channel layer thickness) A preferred configuration of the semiconductor device 1 of embodiment 1 will now be described with reference to Figures 1 and 2. Figure 2 is a diagram illustrating a schematic view of the depletion layer D when the semiconductor device 1 according to embodiment 1 is in an off state.

[0029] In the on-state, the transport efficiency of majority carriers (electrons) injected from the n-type source region 17 into the p-type channel layer 14 approaches 1 as the thickness WP of the p-type channel layer 14 decreases, thereby improving the current driving capability of the semiconductor device 1.

[0030] On the other hand, if the thickness WP of the p-type channel layer 14 is reduced, the p-type channel layer 14 becomes more likely to be fully depleted in the off state.

[0031] Therefore, it is desirable to make the thickness WP of the p-type channel layer 14 as thin as possible and then increase the impurity concentration Ich of the p-type channel layer 14. As a guideline, the thickness WP of the p-type channel layer 14 should be made thinner than the width W3 of the p-type column region 13, for example, and the impurity concentration Ich should be made higher than the impurity concentration Ico of the p-type column region 13, for example.

[0032] As shown in FIG. 2, by configuring as described above, in the off state, the depletion layer D of the superjunction structure is prevented from connecting between the source and drain, and a high breakdown voltage can be maintained.

[0033] (Source area / source contact distance) Next, a preferred configuration of the semiconductor device 1 of the first embodiment will be described with reference to FIG.

[0034] In the semiconductor device 1 of the first embodiment, it is preferable that the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is equal to or greater than a predetermined distance. This can reduce the current caused by minority carriers (holes) injected from the p-type gate region 16 to the n-type source region 17, thereby decreasing the gate current and increasing the current amplification factor of the semiconductor device 1. Here, the current amplification factor of the semiconductor device 1 is the drain current / gate current.

[0035] The value of the current caused by the holes injected from the p-type gate region 16 to the n-type source region 17 depends on the diffusion length of the holes in the n-type source region 17. Therefore, the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is preferably equal to or greater than the diffusion length of the holes in the n-type source region 17, and the distance W4 is more preferably equal to or greater than three times the diffusion length of the holes.

[0036] (Comparative Example) Next, a semiconductor device of a comparative example will be described with reference to FIG. 3, and the effect of the semiconductor device 1 of the first embodiment over the semiconductor device of the comparative example will be described.

[0037] Fig. 3 is a cross-sectional view showing the configuration of a semiconductor device according to a comparative example. As shown in Fig. 3, the semiconductor device of the comparative example is configured as a superjunction bipolar transistor (SJ-BJT) using a superjunction structure in the collector region.

[0038] The semiconductor substrate 50 of the comparative example semiconductor device has, in order from the bottom, an n-type collector layer 51, an n-type buffer layer 52b, an n-type column region 52, a p-type column region 53, and a p-type base layer 56. An n-type emitter region 57 is selectively formed in the surface layer of the p-type base layer 56 on the n-type column region 52. An emitter electrode 61 connected to the n-type emitter region 57 is disposed on the n-type emitter region 57. A base electrode 62 connected to the p-type base layer 56 is disposed on the p-type base layer 56. The emitter electrode 61 and the base electrode 62 are isolated from each other by an insulating layer 71. A collector electrode 63 is disposed on the lower surface of the semiconductor substrate 50 on the side of the n-type collector layer 51.

[0039] In the semiconductor device of the comparative example, in the off state, a depletion layer spreads from each of the multiple pn junctions between the p-type column region 53 and the n-type column region 52 to both sides of the p-type column region 53 and the n-type column region 52, and the superjunction structure between the p-type column region 53 and the n-type column region 52 is depleted at a low electric field strength, thereby achieving a high breakdown voltage. In addition, since a reverse bias is maintained in the superjunction structure in the off state, the depletion layer does not spread much to the p-type base layer 56, and the p-type base layer 56 can be made thinner. As a result, in the on state, the efficiency of injection of electrons from the emitter region to the collector region can be increased.

[0040] When the semiconductor device of the comparative example is turned on, a positive voltage is applied to the base electrode 62. This causes holes to be injected from the p-type base layer 56 to the n-type emitter region 57, and a collector current flows between the collector and the emitter. In the semiconductor device of the comparative example, which is an SJ-BJT, the impurity concentration of the n-type column region 52 can be made higher than the impurity concentration of the collector layer of a conventional high-voltage vertical bipolar transistor. This makes it possible to suppress a decrease in the current amplification factor due to collector resistance in a region of high collector current density.

[0041] Some of the holes from the p-type base layer 56 flow into the p-type column region 53 and the n-type column region 52, and the resistance of the superjunction structure and the n-type buffer layer 52b is reduced by conductivity modulation. Therefore, in the semiconductor device of the comparative example, it is not necessary to apply a voltage equal to or greater than the diffusion potential difference as in, for example, an IGBT, and a collector current flows when a collector voltage is applied.

[0042] As described above, the semiconductor device of the comparative example is configured as an SJ-BJT and has excellent current rise characteristics. However, in the semiconductor device of the comparative example, the high-concentration p-type base layer 56 and the high-concentration n-type emitter region 57 are in contact with each other, and the breakdown voltage between the base and emitter is low, about 10V to 20V. Furthermore, in the semiconductor device of the comparative example, when a large current flows transiently, such as when the device is turned off, the p-type base layer 56 may be destroyed.

[0043] According to the semiconductor device 1 of the first embodiment, the n-type source region 17 is spaced apart from the p-type channel layer 14 and disposed in the surface layer portion of the n-type semiconductor layer 15. The p-type gate region 16 is spaced apart from the n-type source region 17 and reaches the p-type channel layer 14 from the surface layer portion of the n-type semiconductor layer 15. This increases the reverse breakdown voltage between the gate and source, making breakdown less likely to occur.

[0044] According to the semiconductor device 1 of the first embodiment, the p-type gate region 16 is in contact with the p-type channel layer 14. This reduces the resistance of the current path for a large current that is transiently generated at turn-off, and increases the breakdown voltage.

[0045] According to the semiconductor device 1 of the first embodiment, the pitch W2 of the superjunction structure is fixed, and the pitch W1 of the transistors is set based on the width of the n-type source region 17.

[0046] For example, in the semiconductor device of the comparative example, n-type emitter regions 57 are selectively formed on the n-type column regions 52, p-type base layers 56 are formed on the p-type column regions 53, and a base electrode 62 is formed on the p-type base layer 56. That is, in the case of an SJ-BJT like the semiconductor device of the comparative example, the transistor pitch is the same as the superjunction pitch.

[0047] On the other hand, in the semiconductor device 1 of the first embodiment, the width of the n-type source region 17 can be optimized regardless of the pitch W2 of the superjunction structure, so that the on-resistance of the semiconductor device 1 can be suppressed.

[0048] According to the semiconductor device 1 of the first embodiment, the thickness WP of the p-type channel layer 14 is made thinner than the width W3 of the p-type column region 13, and the impurity concentration Ich is made higher than the impurity concentration Ico of the p-type column region 13. As a result, in the on state, the transport efficiency of electrons injected from the n-type source region 17 to the p-type channel layer 14 can be made closer to 1. Also, in the off state, the p-type channel layer 14 is prevented from being completely depleted, and punch-through between the drain and source is prevented, so that a high breakdown voltage can be maintained.

[0049] According to the semiconductor device 1 of the first embodiment, the distance W4 from the end of the n-type source region 17 to the end of the source contact 21c is three times or more the diffusion length of the holes, thereby reducing the number of holes injected from the p-type gate region 16 to the n-type source region 17, thereby increasing the current gain.

[0050] [Embodiment 2] Next, the semiconductor device 2 of the second embodiment will be described with reference to Fig. 4. The semiconductor device 2 of the second embodiment differs from the above-described first embodiment in that the p-type gate region 18 is not in physical contact with the p-type channel layer 14.

[0051] Fig. 4 is a cross-sectional view showing an example of the configuration of a semiconductor device 2 according to embodiment 2. In Fig. 4, the same components as those in embodiment 1 above are denoted by the same reference numerals, and the description thereof will be omitted.

[0052] As shown in FIG. 4, in the semiconductor device 2 of the second embodiment, the p-type gate region 18 does not reach the p-type channel layer 14. However, the p-type gate region 18 and the p-type channel layer 14 are electrostatically connected. A pnp junction structure is formed between the p-type gate region 18 and the p-type channel layer 14. The state in which the p-type gate region 18 and the p-type channel layer 14 are electrostatically connected means a state in which holes can be injected from the p-type gate region 18 to the p-type channel layer 14 even if the n-type semiconductor layer 15 is interposed. In other words, by adjusting the gradient of the impurity concentration in the pnp junction structure between the p-type gate region 18 and the p-type channel layer 14, the semiconductor device 2 can be operated even if the p-type gate region 18 and the p-type channel layer 14 are separated from each other.

[0053] Therefore, the on / off operation and on / off characteristics of the semiconductor device 2 of the second embodiment are equivalent to those of the semiconductor device 1 of the first embodiment described above.

[0054] On the other hand, in the semiconductor device 2, the p-type gate region 18 is not diffused until it reaches the p-type channel layer 14, so that the manufacturing process does not require high-temperature, long-time heat treatment. This suppresses mutual diffusion of impurities between the n-type column region 12 and the p-type column region 13, and maintains the effective amount of impurities in the n-type column region 12. The effective amount of impurities in the n-type column region 12 contributes to the characteristics in the on-state.

[0055] According to the semiconductor device 2 of the second embodiment, the p-type gate region 18 is not in physical contact with the p-type channel layer 14 but is electrically connected thereto. This makes it unnecessary to perform a high-temperature, long-time heat treatment, and makes it possible to suppress a decrease in the performance of the semiconductor device 2.

[0056] [Embodiment 3] Next, the semiconductor device 3 of the third embodiment will be described with reference to Fig. 5. The semiconductor device 3 of the third embodiment differs from the first and second embodiments described above in that it has a p-type buried gate region 19.

[0057] Fig. 5 is a diagram showing an example of the configuration of a semiconductor device 3 according to embodiment 3. Fig. 5(a) is a vertical cross-sectional view of the semiconductor device 3. Fig. 5(b) is a horizontal cross-sectional view of the semiconductor device 3 taken along line AA in Fig. 5(a). In Fig. 5, configurations similar to those of embodiments 1 and 2 described above are given the same reference numerals, and descriptions thereof will be omitted.

[0058] 5(a), the semiconductor device 3 of the third embodiment has a p-type buried gate region 19 as a third semiconductor region that is a p-type diffusion region in the p-type channel layer 14 below the p-type gate region 18. However, the semiconductor device 3 may have a p-type gate region 16 that reaches the p-type buried gate region 19 as in the first embodiment described above.

[0059] The p-type buried gate region 19 is formed, for example, by forming a p-type channel layer 14 in the semiconductor substrate 10, and then further diffusing p-type impurities at a high concentration in a predetermined region. After the formation of the n-type semiconductor layer 15, which is an epitaxial layer, a part of the highly diffused p-type impurities also diffuses into the n-type semiconductor layer 15, forming the p-type buried gate region 19 that is thicker than the p-type channel layer 14.

[0060] The region where the p-type buried gate region 19 is arranged corresponds to the region where the p-type gate region 18 is electrostatically connected to the p-type channel layer 14, and serves as a current path for a large current that is generated transiently at turn-off, for example. The p-type buried gate region 19 having a high concentration of p-type impurities reduces the resistance of this current path.

[0061] 5(b), the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19 of the semiconductor device 3 extend in a direction along the p-type channel layer 14. The direction along the p-type channel layer 14 includes a direction parallel to the p-type channel layer 14 and a direction approximately parallel to the p-type channel layer 14.

[0062] Further, each of the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19 is arranged in a plurality of rows in a direction intersecting with the extending direction. That is, each of the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19 is arranged in a periodic pattern in a direction intersecting with the extending direction. The direction intersecting with the extending direction includes a direction perpendicular to the extending direction and a direction substantially perpendicular to the extending direction.

[0063] The n-type column regions 12 and p-type column regions 13 of the semiconductor device 3 extend in a direction along the extension direction of the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19. The direction along the extension direction includes a direction parallel to the extension direction and a direction approximately parallel to the extension direction. Furthermore, each of the n-type column regions 12 and the p-type column regions 13 is arranged in a direction intersecting with the extension direction. In other words, each of the n-type column regions 12 and the p-type column regions 13 is arranged in a periodic pattern in the direction intersecting with the extension direction.

[0064] In addition, the shaded region in FIG. 5(b) is a region where the p-type buried gate region 19 and the p-type column region 13 overlap in top view.

[0065] According to the semiconductor device 3 of the third embodiment, the p-type buried gate region 19 is disposed in a region of the p-type channel layer 14 that is electrically connected to the p-type gate region 18. This reduces the resistance of the current path of a large current that is transiently generated at the time of turn-off, suppresses the operation of parasitic elements, and increases the breakdown voltage.

[0066] (Variation 1) Next, a semiconductor device according to a first modification of the third embodiment will be described with reference to Fig. 6. The semiconductor device according to the first modification differs from the first to third embodiments described above in the extending direction of the n-type column regions 12a and the p-type column regions 13a.

[0067] Fig. 6 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Modification 1 of Embodiment 3. More specifically, Fig. 6 is a cross-sectional view of the semiconductor device of Modification 1 taken at the same position as line AA in Fig. 5(a).

[0068] As shown in Fig. 6, the n-type column region 12a and the p-type column region 13a of the semiconductor device of the first modification extend in a direction intersecting with the extending direction of the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19. Furthermore, a plurality of n-type column regions 12 and p-type column regions 13 are arranged in a direction intersecting with the extending direction of the n-type source region 17, the p-type gate region 18, and the p-type buried gate region 19. The shaded region in Fig. 6 is a region where the p-type buried gate region 19 and the p-type column region 13a overlap in a top view.

[0069] In the on-state, the region where the p-type buried gate region 19 and the p-type column region 13a overlap serves as a region that blocks the flow of electrons injected from the n-type source region 17 toward the drain side. The region where the p-type buried gate region 19 and the p-type column region 13a overlap in the semiconductor device of Modification 1 is approximately half the region where the p-type buried gate region 19 and the p-type column region 13a overlap in the semiconductor device 3 of the above-described embodiment 3.

[0070] In the semiconductor device of the first modification, the p-type buried gate region 19 extends in a direction along the p-type channel layer 14, and the p-type column region 13a extends in a direction intersecting the extending direction of the p-type buried gate region 19. This makes it possible to reduce the ratio of the overlapping area between the p-type buried gate region 19 and the p-type column region 13a, and to increase the drain current in the on-state.

[0071] (Variation 2) Next, a semiconductor device 4 according to a second modification of the third embodiment will be described with reference to Fig. 7. The semiconductor device 4 according to the second modification differs from the first to third embodiments described above in that the source contacts 21ca are arranged in an island shape.

[0072] Fig. 7 is a diagram showing an example of a configuration of a semiconductor device 4 according to Modification 2 of Embodiment 3. Fig. 7(a) is a vertical cross-sectional view of the semiconductor device 4. Fig. 7(b) is a horizontal cross-sectional view of the semiconductor device 4 taken along line BB in Fig. 7(a).

[0073] As shown in FIG. 7(b), the source contacts 21ca are separated into islands and arranged in a scattered manner in the direction in which the n-type source region 17 extends.

[0074] FIG. 7(a) is a vertical cross-sectional view of the semiconductor device 4 taken along line CC in FIG. 7(b), and is a vertical cross-sectional view at a position where the source contact 21ca is not present.

[0075] According to the semiconductor device 4 of the second modification, the source contacts 21ca are arranged in a scattered manner in the extending direction of the n-type source region 17. This can further increase the effective distance (corresponding to the distance W4 in FIG. 1) from the end of the n-type source region 17 to the end of the source contact 21ca, and can reduce minority carriers injected from the p-type gate region 16 to the n-type source region 17. This can further increase the current amplification factor in the semiconductor device 4.

[0076] The configuration of the semiconductor device 4 of the second modification is useful not only for the semiconductor device 3 of the third embodiment, but also for the semiconductor devices 1 and 2 of the first and second embodiments described above.

[0077] Furthermore, in the above-mentioned embodiments 1 to 3 and their modifications 1 and 2, n-channel type transistors have been described as examples, but these configurations can also be applied to p-channel type transistors in which the conductivity type of each component is inverted.

[0078] [Example] Hereinafter, the embodiments will be described in detail with reference to the drawings.

[0079] Example 1 Fig. 8 is a diagram in which current vectors of the semiconductor device according to Example 1 are plotted, Fig. 8(a) is a diagram in which hole current vectors are plotted, and Fig. 8(b) is a diagram in which electron current vectors are plotted.

[0080] 8 shows an enlarged view of the device simulation results of the semiconductor device of Example 1 in the on-state, assuming that the semiconductor device of Example 1 has the same configuration as the semiconductor device 2 of Embodiment 2, in the vicinity of the n-type source region 17, the p-type gate region 18, and the p-type channel layer 14. In FIG. 8, for convenience, the same reference numerals are used to denote components corresponding to those of the semiconductor device 2 of Embodiment 2.

[0081] In the vector representation of the hole current in Fig. 8(a), the direction of the vector is the direction of hole movement. As shown in Fig. 8(a), in the on-state, holes are injected from the p-type gate region 18 toward the n-type source region 17 and the p-type channel layer 14. The holes injected into the p-type channel layer 14 flow into the p-type column region 13 and the n-type column region 12.

[0082] In the vector representation of the electron current in Fig. 8(b), the direction opposite to the vector is the direction of electron movement. As shown in Fig. 8(b), in the on-state, electrons are injected from the n-type source region 17 toward the p-type channel layer 14. The electrons injected into the p-type channel layer 14 flow into the p-type column region 13 and the n-type column region 12. The electrons then reach the drain electrode 23, and a current flows between the source electrode 21 and the drain electrode 23.

[0083] The simulation results in Figure 8 enable understanding of the behavior of holes and electrons in the n-type source region 17, the p-type gate region 18, and the regions near the p-type channel layer 14, and support the operation of the semiconductor devices 1 to 3 and 4 of the above-mentioned embodiments 1 to 3 and their modifications 1 and 2.

[0084] Example 2 Second Embodiment Next, a semiconductor device according to a second embodiment will be described with reference to FIGS.

[0085] Fig. 9 shows an electron density contour plot and a current line plot of the semiconductor device according to Example 2. In Fig. 9, the electron density contour plot and the current line plot are displayed superimposed on each other. In Fig. 9, a lighter color indicates a higher electron density.

[0086] 9 shows an enlarged view of the device simulation results of the semiconductor device of Example 2 in the on-state, in the vicinity of the n-type column region 12 and the p-type column region 13, assuming that the semiconductor device of Example 2 has the same configuration as the semiconductor device 2 of Embodiment 2. For convenience, in FIG. 9, the same reference numerals are assigned to the components corresponding to those of the semiconductor device 2 of Embodiment 2.

[0087] Fig. 10 is a graph showing the donor impurity concentration, the acceptor impurity concentration, and the electron density of the semiconductor device according to Example 2. Fig. 10(a) is a graph at the depth position indicated by the line DD in Fig. 9, and Fig. 10(b) is a graph at the depth position indicated by the line EE in Fig. 9. The donor impurity concentration, the acceptor impurity concentration, and the electron density shown in Fig. 10 are also based on simulation.

[0088] 9 and 10, the electron density increases in the upper part of the superjunction structure. This is because, as described above, holes are injected from the p-type gate region 16 through the p-type channel layer 14 into the n-type column region 12 and the p-type column region 13, so that a charge neutral condition is maintained. Also, as shown by the current line plot in FIG. 9, the electron current spreads to both the n-type column region 12 and the p-type column region 13.

[0089] As shown in Figures 9 and 10, the electron density is reduced in the lower part of the superjunction structure. The electron density is approximately the same as the donor impurity concentration in the n-type column region 12, and is less than the acceptor impurity concentration in the p-type column region 13. This is because the holes injected into the n-type column region 12 and the p-type column region 13 gradually decrease as they move downward in the superjunction structure. As a result, the conductivity modulation effect is weakened in the lower part of the superjunction structure, and the electron current flows mainly through the n-type column region 12, as shown by the current line plot in Figure 9.

[0090] Thus, in the semiconductor device of Example 2, in the on-state, mainly the upper portion of the superjunction structure has a low resistance due to conductivity modulation.

[0091] Example 3 Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 11. Fig. 11 is a graph showing electrical characteristics of the semiconductor device according to the third embodiment.

[0092] FIG. 11 plots the results of a device simulation of the semiconductor device of Example 3, assuming that the semiconductor device of Example 3 has the same configuration as the semiconductor device 2 of the second embodiment.

[0093] As shown in FIG. 11, the semiconductor device of Example 3 has a steep rise in drain current in the saturation region, and is predicted to have good electrical characteristics.

[0094] Example 4 Next, the semiconductor device of Example 4 will be described with reference to Fig. 12. Fig. 12 is a graph showing the breakdown voltage characteristics of the semiconductor devices according to Example 4 and a comparative example.

[0095] The semiconductor device of Example 4 had the same configuration as the semiconductor device 2 of the embodiment 2. The semiconductor device of the comparative example was the semiconductor device shown in Fig. 3. The breakdown voltage when a reverse bias was applied to the gate electrode and source electrode of these semiconductor devices was simulated.

[0096] As shown in FIG. 12, the withstand voltage of the semiconductor device of the comparative example was less than 20V, whereas the withstand voltage of the semiconductor device of Example 4 was 50V or more.

[0097] Example 5 Next, a semiconductor device according to a fifth embodiment will be described with reference to FIG.

[0098] Fig. 13 is a graph showing the dependency of on-resistance Ron on transistor pitch in the semiconductor device according to Example 5. The horizontal axis of the graph in Fig. 13 indicates the transistor pitch as the number of p-type column regions between the transistors. That is, in the example of the semiconductor device 1 of embodiment 1 shown in Fig. 1, there are two p-type column regions 13 between the transistors, and the transistor pitch is 2.

[0099] 13 plots the device simulation results when the transistor pitch of the semiconductor device of Example 5 is changed, assuming that the semiconductor device of Example 5 has the same configuration as the semiconductor device 2 of the embodiment 2. More specifically, in FIG. 13, the width of the n-type source region is changed, and the transistor pitch is changed accordingly. In addition, the pitch of the superjunction structure is fixed.

[0100] 13, in the semiconductor device of Example 5, as the transistor pitch increases, the on-resistance Ron decreases at first. This is because, as described above, the width of the n-type source region increases, which increases the number of electrons injected from the n-type source region to the p-type channel layer.

[0101] In the semiconductor device of Example 5, the on-resistance Ron, which had decreased once, increases again as the transistor pitch increases. This is because, as described above, the increase in the width of the n-type source region increases the travel distance of holes in the n-type source region and the p-type channel layer, resulting in an increase in the source resistance and channel resistance.

[0102] From the above, it is clear that there is an optimum value for the transistor pitch, and that it is possible to reduce the on-resistance by optimizing the width of the n-type source region.

[0103] Example 6 Next, a semiconductor device of Example 6 will be described with reference to Fig. 14. Fig. 14 is a graph showing the dependency of the on-resistance Ron and the current amplification factor hFE on the distance from the end of the n-type source region to the end of the source contact in the semiconductor device of Example 6.

[0104] FIG. 14 plots the results of device simulation by changing the distance from the end of the n-type source region to the end of the source contact of the semiconductor device of Example 6 (corresponding to distance W4 in FIG. 1), where the semiconductor device of Example 6 has a configuration similar to that of semiconductor device 2 of embodiment 2.

[0105] 14, in the semiconductor device of Example 6, the current amplification factor hFE (=drain current / gate current) increases as the distance from the end of the n-type source region to the end of the source contact increases. This is because the gate current decreases as the distance from the end of the n-type source region to the end of the source contact increases, because the current due to holes injected from the p-type gate region to the n-type source region decreases. On the other hand, changing the distance from the end of the n-type source region to the end of the source contact has little effect on the on-resistance Ron.

[0106] From the above, it is clear that by increasing the distance from the end of the n-type source region to the end of the source contact, it is possible to increase the current gain without increasing the on-resistance.

[0107] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0108] 1~3 Semiconductor device 11 n-type semiconductor layer 12 n-type column region 13 p-type column region 14 p-type channel layer 15 n-type semiconductor layer 16,18 p-type gate region 17 n-type source region 19 p-type buried gate region 21 Source electrode 21c Source Contact 22 Gate electrode 22c Gate Contact 23 Drain electrode 31 Insulating layer

Claims

1. a first column region of a first conductivity type; a second column region of a second conductivity type disposed adjacent to the first column region, forming a superjunction structure; a first electrode and a second electrode disposed on one side of the superjunction structure, the first electrode and the second electrode forming a transistor and controlling a current flowing through the transistor; a third electrode disposed on an opposite side of the superjunction structure from the first electrode and the second electrode and constituting the transistor, a first semiconductor layer of the second conductivity type disposed on the first column region and the second column region; a second semiconductor layer of the first conductivity type disposed on the first semiconductor layer; a first semiconductor region of the first conductivity type that is electrically connected to the first electrode and is spaced apart from the first semiconductor layer and disposed in a surface portion of the second semiconductor layer; a second semiconductor region of the second conductivity type electrically connected to the second electrode, the second semiconductor region being spaced apart from the first semiconductor region and disposed in at least a surface layer portion of the second semiconductor layer, and electrically connected to the first semiconductor layer; Semiconductor device.

2. the second semiconductor region is not in contact with the first semiconductor layer; The semiconductor device according to claim 1 .

3. a third semiconductor region of the second conductivity type is disposed in a region of the first semiconductor layer that is electrically connected to the second semiconductor region; 3. The semiconductor device according to claim 1 or 2.

4. the third semiconductor region extends in a first direction along the first semiconductor layer; the first column region and the second column region are arranged in the first direction and extend in a second direction intersecting the first direction. The semiconductor device according to claim 3 .

5. a contact on the first semiconductor region for connecting the first semiconductor region and the first electrode; the first semiconductor region extends in a third direction along the first semiconductor layer; The contacts are arranged interspersed in the third direction. The semiconductor device according to claim 1 .

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