Transistor Structure

Abstract

To provide a transistor structure capable of preventing destroy of a fin structure in an embodiment.SOLUTION: A transistor structure contains: a substrate 200; an insulation wall (an oxidation spacer 304 and a nitrogen spacer 306); and a gate region (a gate material 504 and a complex cap layer 506). The substrate includes a fin structure. The insulation wall clamps a side wall of the fin structure. The gate region is provided on the fin structure and the insulation wall. The insulation wall prevents destroy of the fin structure.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a transistor structure, and in particular to a transistor structure that provides solid walls that clamp the active area or narrow fin structure, in particular the sidewalls of the fin structure, that allows control of the relative position or distance between the edge of the source / drain and the edge of the gate, that improves the source / drain resistance, and that allows the majority of the source / drain regions to be isolated by insulating material. [Background technology]

[0002] An example of a state-of-the-art field effect transistor (e.g., NMOS (N-type metal oxide semiconductor) transistor) with a FIN structure (FinFET or Tri-gate) is shown in Figure 1. On a three-dimensional (3D) silicon surface with sidewalls insulated from other transistor sidewalls with an insulating material (e.g., oxide, or oxide / nitride, or some high-k dielectric, etc.), the gate structure 10 of the NMOS transistor is formed with some conductive material (such as metal, polysilicon, polycide, etc.) on top of the insulator. The source 11 and drain 12 of the NMOS transistor are formed by implanting a high concentration of n-type (n+) dopants into a p-type substrate (or p-well) using ion implantation plus thermal annealing techniques, thus resulting in two isolated n+ / p junction regions.

[0003] Also, to reduce impact ionization and hot carrier injection, it is common to form lightly doped drains (n-type LDDs) 13 in front of the source 11 and drain 12 by ion implantation plus thermal annealing techniques prior to the heavily doped n+ / p junctions, which often results in the LDDs 13 encroaching into the portion of the 3D active area underneath the gate structure 10 (as shown in FIG. 1 ). Thus, the effective channel length 14 between the LDDs 13 is inevitably shortened.

[0004] Meanwhile, advances in manufacturing process technology continue to advance rapidly by scaling down NMOS transistor geometries in both horizontal and vertical dimensions (e.g., reducing the minimum feature size, called lambda (λ), from 28 nm to 5 nm or 3 nm). However, this scaling of FinFET or Tri-Gate geometries introduces or exacerbates a number of problems: (1) As both horizontal and vertical dimensions are scaled down, it is difficult to perfectly align the LDD junction edge (or source / drain edge) to the edge of the gate structure 10 using only the conventional self-alignment method using gate, spacer, and ion implantation formation. Also, the thermal annealing technique to remove the ion implantation damage must rely on high temperature processing techniques, such as rapid thermal annealing, by using various energy sources and other thermal processes. Thus, one problem caused is the gate-induced drain leakage (GIDL) current, which is difficult to control, despite the fact that the resulting GIDL current should be minimized to reduce the leakage current, and another problem caused is that the length of the effective channel 14 is difficult to control, and therefore the short channel effect (SCE) is hardly minimized. Moreover, it is also difficult to adjust the relative position between the source / drain edge and the edge of the gate structure 10 to control the GIDL; (2) Also, since the ion implantation for forming the LDD 13 (or the n+ / p junction in NMOS, or the p+ / n junction in PMOS (p-type metal oxide semiconductor)) acts like a bombardment to insert ions from above the silicon surface straight down into the substrate, the dopant concentration is unevenly distributed vertically from the top surface, which has a higher doping concentration, to the junction region, which has a lower doping concentration, making it difficult to create a uniform material interface with few defects from the source 11 and drain 12 to the effective channel 14 and substrate body region; (3) Furthermore, when the lateral dimensions are scaled down to 7 nm, 5 nm, or 3 nm, the height (vertical dimension) of the NMOS transistor fin structure (e.g., 60-300 nm, etc.) becomes much larger than the width (horizontal dimension) of the NMOS transistor fin structure (e.g., 3-7 nm, etc.), which results in the fin structure becoming weak or even collapsing during subsequent processes (e.g., source / drain formation, gate formation, etc.).

[0005] Therefore, the present invention provides a transistor structure for solving the above problems 1)-3). Summary of the Invention

[0006] One embodiment of the present invention provides a transistor structure, the transistor structure including a substrate, an insulating wall, and a gate region, the substrate having a fin structure, the insulating wall clamping a sidewall of the fin structure, the gate region overlying the fin structure and the insulating wall, the insulating wall configured to prevent the fin structure from collapsing.

[0007] According to one aspect of the invention, the insulating walls clamp the four side walls of the fin structure.

[0008] According to one aspect of the invention, the transistor structure further includes a shallow trench isolation (STI) layer surrounding the insulating wall.

[0009] According to one aspect of the invention, the transistor structure further includes a sheet channel layer disposed between a sidewall of the fin structure and the insulating wall, the sheet channel layer being formed by a selective epitaxial growth technique.

[0010] According to one aspect of the invention, the gate region includes a gate dielectric layer over the fin structure, a gate conductive layer over the gate dielectric layer, and a cap layer over the gate conductive layer.

[0011] According to one aspect of the invention, the insulating wall is configured to prevent the fin structure from collapsing during formation of the gate dielectric layer, the gate conductive layer, and the cap layer.

[0012] According to one aspect of the invention, the transistor structure further includes a spacer layer on a sidewall of the gate region.

[0013] According to one aspect of the invention, the transistor structure further includes a first conductive region abutting the fin structure, the first conductive region being independent of the substrate.

[0014] According to one aspect of the invention, a first conductive region is formed in a first recess below an initial surface of the substrate.

[0015] According to one aspect of the invention, the insulating wall is configured to prevent the fin structure from collapsing during formation of the first recess and the first conductive region.

[0016] According to one aspect of the invention, a first recess is formed by (1) etching a substrate to form a temporary recess, then forming a thermal oxide layer over the recess, and (2) etching the thermal oxide layer.

[0017] According to one aspect of the present invention, the first recess has a sidewall, and the first conductive region has a lightly doped region abutting the sidewall of the first recess and a heavily doped region abutting the lightly doped region.

[0018] According to one aspect of the invention, the location of the sidewall of the first recess depends on the thickness of the spacer layer on the sidewall of the gate region and the thickness of the thermal oxide layer.

[0019] According to one aspect of the invention, the relative position between the edge of the gate region and the edge of the first conductive region depends on the thickness of the spacer layer on the sidewall of the gate region and the thickness of the thermal oxide layer.

[0020] Another embodiment of the present invention provides a transistor structure. The transistor structure includes a substrate, a gate region, and a first conductive region. The substrate has a fin structure. The gate region overlies the fin structure. The first conductive region abuts the fin structure, and at least three sides of the first conductive region are in contact with a metal.

[0021] Another embodiment of the present invention provides a transistor structure, the transistor structure including a substrate, a gate region, and a first conductive region, the substrate having a fin structure, the gate region overlying the fin structure, the first conductive region abutting the fin structure, and a bottom surface of the gate region being lower than a bottom surface of the first conductive region.

[0022] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 illustrates a FinFET according to the prior art. [Figure 2A] 1 is a flow chart illustrating a method for fabricating a Fin Field Effect Transistor (FinFET) in accordance with one embodiment of the present invention. [Figure 2B] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Figure 2C] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Figure 2D] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Diagram 3] FIG. 2 shows that a pad oxide layer is grown, a pad nitride layer is deposited, and a trench is formed. [Figure 4] FIG. 2 illustrates a semiconductor layer being formed, oxide spacers being deposited on the semiconductor layer, and nitride spacers being deposited on the oxide spacers. [Diagram 5] FIG. 2 is a diagram showing the formation of shallow trench isolation (STI). [Figure 6] FIG. 13 is a diagram showing that a gate area is defined that spans an active region and an isolation region. [Figure 7] FIG. 2 shows that the gate material is formed and a composite cap layer is deposited. [Figure 8] FIG. 13 shows the STI being etched and the pad nitride layer being removed. [Figure 9] FIG. 13 shows that the pad oxide layer is etched away, portions of the STI are etched back, and oxide 2 spacers and nitride 2 spacers are formed. [Figure 10] FIG. 13 shows that some exposed silicon areas are etched away to create shallow trenches for the source and drain. [Figure 11] FIG. 1 shows that an oxide 3 layer is thermally grown. [Figure 12] FIG. 13 shows that the oxide 3 layer is etched away and the source and drain are formed by SEG technique. [Figure 13] FIG. 2 is a diagram showing a cross section of an SCBFET and Y-direction doping concentrations and X-direction doping concentrations corresponding to the cross section of the SCBFET. [Figure 14] FIG. 13 shows the formation of oxide spacers on the p-type wells and nitride spacers on the oxide spacers. [Figure 15] FIG. 2 illustrates a FinFET according to another embodiment of the present invention. [Figure 16A] 16A and 16B are a flow chart illustrating a method for manufacturing a FinFET according to another embodiment of the present invention. [Figure 16B] 16A and 16B are a flow chart illustrating a method for manufacturing a FinFET according to another embodiment of the present invention. [Figure 17] FIG. 2 shows a pad oxide layer being grown, a pad nitride layer being deposited, a trench being formed, and shallow trench isolation (STI) being formed. [Figure 18]FIG. 1 shows that the pad oxide and pad nitride layers are removed. [Figure 19] FIG. 2 shows the formation of a Hi-K dielectric layer. [Figure 20] FIG. 13 shows that the gate area is defined, the Hi-K dielectric layer along the gate area is etched away, a thermal oxide 1 layer is thermally grown, and nitride 1 spacers and oxide 2 spacers are formed. [Figure 21] FIG. 2 shows that an oxide layer is deposited on STI oxide 1 and then etched back to form STI oxide 2. [Figure 22] FIG. 13 shows that some exposed silicon areas are etched away to create shallow trenches for the source and drain. [Diagram 23] FIG. 1 shows that an oxide 3 layer is thermally grown. [Figure 24] FIG. 1 shows that a nitride 3 layer is deposited on the oxide 3B layer and then the nitride 3 layer is etched back to form localized isolation into the silicon substrate (LISS). [Diagram 25] 25, 26, 27, 28 and 29 are diagrams showing the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 26] 25, 26, 27, 28 and 29 are diagrams showing the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 27] 25, 26, 27, 28 and 29 are diagrams showing the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 28] 25, 26, 27, 28 and 29 are diagrams showing the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 29] 25, 26, 27, 28 and 29 are diagrams showing the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 30A] FIG. 2 illustrates a fused semiconductor junction-metal conductor (MSMC) structure formed in accordance with another embodiment of the present invention. [Figure 30B] FIG. 2 illustrates a fused semiconductor junction-metal conductor (MSMC) structure formed in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Please refer to Figures 2A, 2B, 2C, 2D, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13. Figure 2A is a flow chart showing a method for manufacturing a fin field effect transistor (FinFET) according to an embodiment of the present invention, which can reduce the gate-induced drain leakage (GIDL) current and short channel effect (SCE) of the FinFET, and can form a solid wall clamping the active area or narrow fin structure of the FinFET. The detailed steps are as follows:

[0025] Step 10: Start.

[0026] Step 20: Define the active area based on the p-type well 202 and form the fin structure.

[0027] Step 30: A gate of a FinFET is formed on the original horizontal surface (OHS) of the p-type well 202.

[0028] Step 40: Form the source and drain of the FinFET.

[0029] Step 50: Finished.

[0030] See Figures 2B, 3 and 4. Step 20 may include:

[0031] Step 102: Grow a pad oxide layer 204 and deposit a pad nitride layer 206.

[0032] Step 104: Define the active area and remove portions of the silicon material corresponding to the OHS outside the active area to create trenches 210 and form fin structures.

[0033] Step 106: Grow a semiconductor layer 302 (a sheet-channel layer (SCL), which is optional) surrounding the active area, form oxide spacers 304 and nitride spacers 306, and etch back the oxide spacers 304 and nitride spacers 306.

[0034] 2C, 5, 6 and 7. Step 30 may include:

[0035] Step 108: Deposit an oxide layer and remove the excess oxide layer using a chemical mechanical polishing (CMP) technique to form the STI 402.

[0036] Step 110: Define a gate area spanning the active area and the isolation area, etch away the pad oxide layer 204 and the pad nitride layer 206 corresponding to the gate area, and etch back the STI 402 corresponding to the gate area.

[0037] Step 112: Form a gate dielectric material 502, deposit a gate material 504 in the recess 404, and then etch back the gate material 504.

[0038] Step 114: Form a composite cap layer 506, and polish the composite cap layer 506 by a CMP technique.

[0039] See Figure 2D, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12 and Figure 13. Step 40 may include:

[0040] Step 116: Etch back the STI 402 and remove the pad nitride layer 206.

[0041] Step 118: Etch away pad oxide layer 204 and etch back STI 402.

[0042] Step 120 : Form oxide 2 spacers 802 and nitride 2 spacers 804 on the edges of the gate material 504 and the composite cap layer 506 .

[0043] Step 122: Etch away the exposed silicon.

[0044] Step 124: Thermally grow oxide 3 layer 1002.

[0045] Step 126: Etch away portions of the oxide 3 layer 1002, then form n-type lightly doped drains (LDDs) 1102, 1104, then form an n+ doped source 1106 and an n+ doped drain 1108.

[0046] A detailed description of the above-mentioned fabrication method is as follows: Starting with a well-designed doped p-type well 202, the p-type well 202 is provided in a p-type substrate 200 (although in other embodiments of the invention one may start with the p-type substrate 200 rather than starting with the p-type well 202), in one example the p-type well 202 is counted down from its top surface by about 500 nm from OHS, and is a substrate doped to a lower concentration (even including punch-through implant dopant profiles) of 5×10 higher (for example) than is used in state-of-the-art FinFETs. 18 Dopant / cm 3 For example, the p-type substrate 200 has a concentration close to 1×10 16 Dopant / cm 3The actual dopant concentration will be determined by final volume manufacturing optimization. As a result, a p-type substrate voltage (usually grounded, i.e., 0V) can be provided across most of the body of the FinFET, rather than resulting in a largely depleted fin substrate (which behaves like a voltage floating body with little control or stabilization, making it less desirable than a semiconductor transistor with a voltage stabilized body).

[0047] In step 102, a pad oxide layer 204 of a well-designed thickness is grown over the OHS, and a pad nitride layer 206 of a well-designed thickness is deposited on top of the pad oxide layer 204, as shown in FIG. 3(a).

[0048] In step 104, as shown in Fig. 3(a), photolithography masking technology is used to define the active area of ​​FinFET by anisotropic etching technology, which removes the part of silicon material corresponding to OHS outside the active area to create trench 210 (e.g., about 300 nm deep) for later STI (shallow trench isolation) needs, and thus also creates the fin structure of FinFET. Also, Fig. 3(b) is a top view corresponding to Fig. 3(a), and Fig. 3(a) is a cross-sectional view along the X-direction cutting line shown in Fig. 3(b).

[0049] In step 106, as shown in FIG. 4(a), a semiconductor layer 302 is grown using a selective growth method, such as a selective epitaxial growth (SEG) technique, over the exposed silicon surfaces (the two sidewalls of the fin structure and the top surface of the bottom region of the trench 210), which is hereinafter named a sheet channel layer (SCL), and the SCL can be a monolithic p-type doped silicon with a thickness of about 1-2 nm, which should be fully adjusted to the detailed device design. In another example, the sheet channel layer (SCL) is optional. An oxide spacer 304 is deposited on the semiconductor layer 302, a nitride spacer 306 is deposited on the oxide spacer 304, and the oxide spacer 304 and the nitride spacer 306 are etched back using an anisotropic etching technique to make the top surfaces of the oxide spacer 304 and the nitride spacer 306 coincident with the OHS, where the oxide spacer 304 and the nitride spacer 306 are outside the active area of ​​the FinFET. Therefore, the key point here is that the oxide spacer 304 and the nitride spacer 306 form a solid wall that clamps the active area or narrow fin structure, particularly the sidewalls of the fin structure. This solid clamping wall can be a single layer or other composite capping layer to protect the narrow fin structure from collapsing during the formation of the source / drain or gate of the FinFET.

[0050] Another important point here is that the semiconductor layer 302 is used for the channel region of the FinFET, which will be turned into a depletion region until it is fully inverted into a channel conduction region depending on how the gate voltage is applied. Therefore, the doping concentration of the semiconductor layer 302 affects the threshold voltage of the FinFET and forms the main conductive layer with electron carriers under inversion to connect both the n-type source and the n-type drain. Since the SEG layer 302 is formed separately from the bulk body of the FinFET, the most desirable design is to use a doping concentration preferably lower than that of the fin body (e.g., 1×10 2 × 10 3 × 10 4 × 10 5 × 10 6 × 10 7 × 10 8 × 10 9 × 10 10 × 10 15 × 10 25 × 10 35 × 10 45 × 10 5 × 10 65 × 10 15 × 10 25 × 10 35 × 10 45 × 10 ... 16 From 3×10 18 ) in the fins. Furthermore, as feature sizes (i.e., line dimensions) continue to scale down horizontally, the semiconductor layer 302 also enhances the mechanical stability of the fins as they are proportionately made thinner and taller. Taller fins allow for increased device widths (to compensate for reduced carrier mobility due to undesirable channel collisions as the fins become narrower), but may result in physical collapse of some narrow fins. Also, FIG. 4(b) is a top view corresponding to FIG. 4(a), and FIG. 4(a) is a cross-sectional view taken along the X-direction cut line shown in FIG. 4(b).

[0051] In step 108, as shown in FIG. 5(a), a thick oxide layer is deposited to completely fill the trench 210, and the excess oxide layer is removed using CMP techniques to form the STI 402. The top surface of the STI 402 is at a height that coincides with the top surface of the pad nitride layer 206. Again, the STI 402 further surrounds or clamps the active area or narrow fin structure, particularly the sidewalls of the fin structure, to protect the narrow fin structure from collapsing when forming the source / drain or gate of the FinFET. Also, FIG. 5(b) is a top view corresponding to FIG. 5(a), and FIG. 5(a) is a cross-sectional view along the X-direction cut line shown in FIG. 5(b).

[0052] Then, in step 110, as shown in FIG. 6(a), a photolithographic masking technique is used to define a gate area spanning the active area and the STI isolation area, so that the pad oxide layer 204 and the pad nitride layer 206 corresponding to the gate area are removed to create a recess 404. In addition, the STI 402 corresponding to the gate area is also etched down by a certain amount (e.g., 40-80 nm deep) to form a step structure between the etched STI area corresponding to the gate area and the fin surface. The oxide spacer 304 and the nitride spacer 306 corresponding to the gate area may also be removed. Thus, the top of the semiconductor layer 302 is exposed, providing a smooth line edge roughness for the gate of the FinFET. Also, FIG. 6(b) is a top view corresponding to FIG. 6(a), and FIG. 6(a) is a cross-sectional view along the X-direction cutting line shown in FIG. 6(b).

[0053] In step 112, as shown in FIG. 7(a), a gate dielectric material 502 (composite material or oxide) is formed in the recess 404 (also the step structure between the etched STI 402 corresponding to the gate area and the fin surface), and a gate material 504 (e.g., metal such as tungsten 5044 covering TiN 5042) is deposited on the gate dielectric material 502. Then, the gate material 504 is polished by CMP technique to make the top surface of the gate material 504 coincident with the top surface of the remaining pad nitride layer 206, and the gate material 504 is etched back to make the top surface of the gate material 504 lower than the top surface of the remaining pad nitride layer 206. Thus, a tri-gate structure may exist.

[0054] Then, in step 114, a composite cap layer 506 consisting of a nitride 1 layer 5062 and a hard mask oxide layer 5064 is deposited on the top surface of the gate material 504 in the recess 404, as shown in FIG. 7(a). The composite cap layer 506 is used to protect the gate material 504. The composite cap layer 506 is then polished by a CMP technique to make the top surface of the composite cap layer 506 coincident with the top surface of the pad nitride 206. Also, FIG. 7(b) is a top view corresponding to FIG. 7(a), and FIG. 7(a) is a cross-sectional view taken along the X-direction cut line shown in FIG. 7(b).

[0055] In step 116, as shown in Figure 8(a), the STI 402 is etched and the pad nitride layer 206 is removed to make the top surface of the STI 402 flush with the top surface of the pad oxide layer 204. Also, Figure 8(b) is a top view corresponding to Figure 8(a), and Figure 8(a) is a cross-sectional view taken along the X-direction cut line shown in Figure 8(b).

[0056] Similarly, up to step 116, two semiconductor layers 302 (sheet channel layers, SCLs) are formed on the two sidewalls of the fin (these two semiconductor layers 302 are named Qleft and Qright respectively), but the top surface of the fin structure does not have SCLs, and therefore the threshold voltage of the upper MOSFET (Qtop) which has a higher doping concentration can be higher than that of the two sidewalls of the FinFET).

[0057] In step 118, the pad oxide layer 204 is etched away and portions of the STI 402 are etched back, as shown in FIG. 9(a).

[0058] Then, in step 120, an oxide 2 layer is deposited to form oxide 2 spacers 802 and a nitride 2 layer is deposited to form nitride 2 spacers 804 on the edges of the gate material 504 and composite cap layer 506, as shown in Figure 9(a), with Figure 9(b) being a top view corresponding to Figure 9(a) and Figure 9(a) being a cross-sectional view taken along the X-direction cut line shown in Figure 9(b).

[0059] In another example, the STI 402 can be retained and the pad nitride layer 206 can be removed so that the STI 402 still surrounds the fin structure. The pad oxide layer 204 is then etched away and portions of the STI 402 are etched away so that the remaining STI 402 still has a top surface higher than the OHS, as shown in FIG. 9(c). Thus, the fin structure is surrounded by the remaining STI 402 with a top surface higher than the OHS.

[0060] Then, in step 122, as shown in Fig. 10(a), some exposed silicon areas are etched away to create shallow trenches 902 (e.g., about 50 nm deep) for the source and drain of the FinFET. Also, Fig. 10(b) is a top view corresponding to Fig. 10(a), and Fig. 10(a) is a cross-sectional view taken along the cutting line in the X direction shown in Fig. 10(b). Fig. 10(c) shows another example of etching away some exposed silicon areas to create shallow trenches 902 based on the structure of Fig. 9(c).

[0061] In step 124, as shown in FIG. 11(a), a thermal oxidation process called the Oxide 3 process is used to grow an Oxide 3 layer 1002 (including both an Oxide 3V layer 10022 that penetrates the vertical sidewalls of the bulk body of the FinFET (assumed to have a sharp (110) crystal orientation) and an Oxide 3B layer 10024 on the top surface of the bottom of the shallow trench 902). Since two sidewalls of the shallow trench 902 have a vertical composite of Oxide 2 spacer 802 and Nitride 2 spacer 804 and the other sidewall of the shallow trench 902 is in contact with Oxide spacer 304 and Nitride spacer 306, the width of the source / drain of the FinFET is not affected at all by such a thermal oxidation process. Also, the thicknesses of the Oxide 3V layer 10022 and Oxide 3B layer 10024 depicted in FIG. 11 and subsequent figures are shown for illustrative purposes only and their geometries are not proportional to the dimensions of the STI 402 depicted in those figures. For example, the thickness of oxide 3V layer 10022 and oxide 3B layer 10024 may be approximately 20-30 nm, while the vertical height of STI 402 may be approximately 200-250 nm.

[0062] However, it is very important to design the oxidation 3 process so that the thickness of the oxide 3V layer 10022 can be very precisely controlled, both under precisely controlled thermal oxidation temperature, timing and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the oxide 3V layer 10022 thickness being taken away from the thickness of the exposed (110) silicon surface of the FinFET body vertical wall, and the remaining 60% of the oxide 3V layer 10022 thickness being considered as an addition to the outside of the FinFET body vertical wall (such 40% and 60% distribution of the oxide 3V layer 10022 to the oxide 2 spacer 802 / nitride 2 spacer 804 is depicted in FIG. 11 with dashed lines for special clarity, because its importance will be clearly stated in the following text). Also, FIG. 11(b) is a top view corresponding to FIG. 11(a), and FIG. 11(a) is a cross-sectional view along the X-direction cut line shown in FIG. 11(b). FIG. 11(c) shows another example of the oxidation 3 process based on the structure of FIG. 10(c).

[0063] In step 126, as shown in FIG. 12(a), first, the oxide 3 layer 1002 is etched away. Then, using a selective growth method such as a SEG technique, n-type LDDs 1102, 1104 are formed, followed by the formation of an n+ doped source 1106 and an n+ doped drain 1108. Thus, the main part of the FinFET is completed. Also, FIG. 12(b) is a top view corresponding to FIG. 12(a), and FIG. 12(a) is a cross-sectional view taken along the cutting line in the X direction shown in FIG. 12(b). FIG. 12(c) shows another example of a selective growth process based on the structure of FIG. 11(c). Since the fin structure is surrounded by the remaining STI 402 having a top surface higher than the OHS, in the selective growth of the source / drain region, the selectively grown source / drain region is confined by the remaining STI 402, not on the remaining STI 402.

[0064] It is also noted that in one example, the bottom surface of the gate structure (not shown) over the STI regions may be approximately 10-20 nm lower than the bottom surface of the drain / source regions.

[0065] Please refer to FIG. 13. FIG. 13(a) is a cross-sectional view taken along the cutting line in the Y direction shown in FIG. 12(b). As shown in FIG. 13(a), both Qleft and Qright, which are p-type doped silicon channel regions grown by SEG, are clearly visible on the cross-sectional view. As shown in FIG. 13(b), there are Y-direction concentration profiles LYN and LYP of the prior art, and the Y-direction concentration profile LYN corresponds to the dashed line L1 shown in FIG. 13(a). Similarly, as shown in FIG. 13(c), there are X-direction concentration profiles LXN and LXP of the prior art, and the X-direction concentration profile LXN corresponds to the dashed line L2 shown in FIG. 13(a). The doping concentrations of Qleft and Qright (e.g., 1×10 16 From 3×10 18 ) is smaller than that of the FinFET fin body (e.g., 5×10 18 ) is clearly lower than that.

[0066] The main inventive points are described below. Both drain and source of FinFET are formed by SEG technique except that they are doped with n-type dopant with higher concentration than Qleft and Qright, so that seamless contact area is clearly created between drain and channel and between source and channel, respectively. All of channel, drain and source are completed without ion implantation, and high temperature thermal annealing is not required to remove damage caused by hard bombardment of drain and source formation. Also, a solid wall (e.g. oxide spacer 304 and nitride spacer 306 shown in FIG. 4) clamps the active area or narrow fin structure, especially the sidewall of the fin structure. This solid clamp wall can be a single layer or other composite cap layer to protect the narrow fin structure from collapsing during the formation of source / drain or gate of FinFET. Moreover, STI 402 (shown in FIG. 5) further surrounds or clamps the active area or narrow fin structure, especially the sidewall of the fin structure, to protect the narrow fin structure from collapsing during the formation of source / drain or gate of FinFET. Therefore, even if the height of the fin structure (e.g., 60-300 nm) is much larger than the width of the fin structure (e.g., 3-7 nm) of the FinFET, the fin structure protected by the solid wall of the present invention is less vulnerable during subsequent processes (e.g., source / drain formation, gate formation, etc.). As shown in Fig. 9, another advantage of the present invention is that the thickness of the oxide 2 spacer 802 and nitride 2 spacer 804 formed on the edge of the gate region (i.e., gate material 504 and composite cap layer 506) can be controlled, and the thickness of the oxide 3V layer 10022 and oxide 3B layer 10024 formed by the thermal oxidation process (shown in Fig. 11) can also be controlled, so that the edge of the source / drain can be aligned or substantially aligned with the edge of the gate region (as shown in Fig. 12), especially when the source / drain is formed by the SEG technique.Therefore, according to the present invention, the relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled, and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (such as the oxide 3V layer 10022 shown in FIG. 11, but the oxide 3V layer 10022 is removed in FIG. 12). Thus, the effective channel length Leff (shown in FIG. 12) may be controlled so that the Gate Induced Drain Leakage (GIDL) current problem may be improved.

[0067] In another embodiment, the selective epitaxial growth (SEG) technique of growing the monolithic p-type doped silicon thin sheet channel layer (SCL) shown in Figure 4 is not required, but solid walls (such as oxide spacer 304 and nitride spacer 306 shown in Figure 4) are still formed to clamp the active area or narrow fin structure, especially the sidewalls of the fin structure (as shown in Figure 14). Also, Figure 14(b) is a top view corresponding to Figure 14(a), and Figure 14(a) is a cross-sectional view along the X-direction cut line shown in Figure 14(b).

[0068] Then, after FIG. 14, similar processes as in FIG. 5 to FIG. 12 may be performed to form another transistor structure in FIG. 15. Again, even if the height of the fin structure (e.g., 60-300 nm) is much larger than the width of the fin structure (e.g., 3-7 nm), the fin structure of this embodiment protected by the solid wall is less vulnerable during subsequent processes (e.g., source / drain formation, gate formation, etc.). The relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (e.g., oxide 3V layer 10022 shown in FIG. 11). Thus, the effective channel length Leff may be controlled so that the GIDL current problem may be improved. FIG. 15(c) shows another example where the fin structure is surrounded by the remaining STI 402 with a top surface higher than the OHS, and the source / drain region to be selectively grown is not on the remaining STI 402 but is confined by the remaining STI 402.

[0069] Please refer to Figures 16A, 16B, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29. Figures 16A and 16B are flow charts showing a method for manufacturing a FinFET according to another embodiment of the present invention, and the method for manufacturing a FinFET in Figures 16A and 16B can also reduce the gate-induced drain leakage (GIDL) current and short channel effect (SCE) of the FinFET, and can form a solid wall that clamps the active region or narrow fin structure of the FinFET. The detailed steps are as follows.

[0070] Process 1600: Start.

[0071] Step 1602: Grow a pad oxide layer 204 based on the p-type well 202 and deposit a pad nitride layer 206 (shown in FIG. 17).

[0072] Step 1604: The active areas of the FinFETs are defined and portions of the silicon material corresponding to the OHS outside the active areas are removed to create trenches 210 and fin structures (shown in FIG. 17).

[0073] Step 1606: Deposit an oxide 1 layer and remove excess oxide 1 layer using chemical mechanical polishing (CMP) techniques to form STI oxide 1 1702 (shown in FIG. 17).

[0074] Step 1608: Remove the pad oxide layer 204 and the pad nitride layer 206 (shown in FIG. 18).

[0075] Step 1610: Form a Hi-K dielectric layer 1902 on the OHS and on top of the STI oxide 1 1702 (shown in FIG. 19).

[0076] Step 1612: Define a gate area spanning the active and isolation regions, and etch away the Hi-K dielectric layer 1902 outside the gate area.

[0077] Step 1614: A gate region is formed, such as by depositing a gate material 2002 (e.g., tungsten) on the Hi-K dielectric layer 1902, and then a composite cap layer 506 composed of a nitride 1 layer 5062 and a hardmask oxide layer 5064 is formed (shown in FIG. 20).

[0078] Step 1618: Thermally grow Thermal Oxide 1 layer 2003 (optional).

[0079] Step 1620: Depositing a nitride 1 layer on the thermal oxide 1 layer 2003 and then etching the nitride 1 layer to form nitride 1 spacers 2004, and depositing an oxide 2 layer on the nitride 1 spacers and then etching the oxide 2 layer to form oxide 2 spacers 2006 (shown in FIG. 20).

[0080] Step 1622: An oxide layer is deposited on STI oxide 1 1702 and then etched back to form STI oxide 2 2102 and expose the silicon surface (shown in FIG. 21).

[0081] Step 1624: Etch away the exposed silicon to form shallow trenches 2202 for the source and drain of the FinFETs (shown in FIG. 22).

[0082] Step 1626: Thermally grow oxide 3 layer 2300 in trench 2202, oxide 3 layer 2300 being comprised of oxide 3V layer 2302 and oxide 3B layer 2304 (shown in FIG. 23).

[0083] Step 1628: Within the trench 2202, deposit a nitride 3 layer 2402 (optional) on the oxide 3B layer 2304 and then etch back the nitride 3 layer 2402 to form localized isolation into silicon substrate (LISS) (shown in FIG. 24).

[0084] Step 1630: Within trench 2202, deposit TiN 2502, then deposit metal 2504, such as tungsten, over TiN 2502 (as shown in FIG. 25).

[0085] Step 1632: Etch back the TiN 2502 and metal such as tungsten 2504 (shown in FIG. 26).

[0086] Step 1634: Etch down a portion of the oxide 3V layer 2302 to expose the silicon sidewalls 2702 (shown in FIG. 27).

[0087] Step 1636: Using selective epitaxial growth (SEG) techniques, a n-type lightly doped drain (NLDD) 2802 is formed from the silicon sidewall 2702, followed by the formation of an n+ doped source 2804 and an n+ doped drain 2806 (shown in FIG. 28).

[0088] Step 1638: Deposit a metal, such as tungsten (shown in Figure 29).

[0089] Step 1640: Finished.

[0090] Steps 1602-1626 may refer to steps 102-126 described above, and therefore will not be described further for the sake of brevity. Steps 1628-1638 also utilize a merged semiconductor junction and metal conductor (MSMC) structure (disclosed in U.S. Patent Application No. 16 / 991,044, filed Aug. 12, 2020, the corresponding content of which is incorporated herein by reference) to form a source and drain that are directly connected to the p-type well 202 of the FinFET, and therefore will not be described further for the sake of brevity.

[0091] As shown in Fig. 29, again, (1) the fin structure of the embodiment (shown in Figs. 16A, 16B) is protected by a solid wall, and (2) the relative position or distance between the edge of the source / drain and the edge of the gate region is controllable and can depend on the thickness of the oxide 3V layer 2302 (and / or the thickness of the spacer formed on the edge of the gate region). Also, by forming a fused metal-semiconductor junction at the source / drain as shown in Fig. 29, the resistance of the source / drain can be improved. Moreover, most of the source / drain regions are isolated by insulating materials including the bottom structure by the oxide 3B layer 2304 and / or nitride 3 layer 2402, therefore the junction leakage can be significantly reduced.

[0092] In another embodiment, as shown in FIG. 30A, the top surface of the STI region surrounding the fin structure is higher than the top surface of the fin structure, so that the selectively grown source / drain regions are confined by the STI region rather than over the STI region. A metal contact plug can be deposited in the hole between the STI region and the gate region without using a separate contact mask to create such a hole. Also, the top, bottom, and sidewalls of the source (drain) region can be in direct contact with the metal, dramatically reducing the contact resistance of the source / drain region. Furthermore, it is possible that the bottom surface (not shown) of the gate structure on or over the STI region surrounding the fin structure can be about 10-20 nm lower than the bottom surface of the drain / source region. In FIG. 30A, the metal material surrounds or contacts the top, bottom, and one sidewall of the n+ doped drain.

[0093] Furthermore, in another embodiment (as shown in FIG. 30B), the difference between FIG. 30A and FIG. 30B is that the deposited metal such as deposited TiN 2502 and tungsten 2504 in FIG. 25 and FIG. 26 can be omitted, and simply use the top surface of the nitride 3 layer 2402 as a reference to etch down a portion of the oxide 3V layer 2302 to expose the silicon sidewall 2702, and then use selective growth techniques to form the n-type lightly doped drain (NLDD) 2802 and the n+ doped source 2804 and n+ doped drain 2806, followed by depositing a metal such as tungsten (shown in FIG. 30B). In FIG. 30B, a metal plug contacts the top surface and one sidewall of the n+ doped drain.

[0094] In summary, the FinFET provided by the present invention has several advantages which can be described as follows: (1) A solid wall is formed to clamp the active area or the narrow fin structure, especially the sidewall of the fin structure, so that the fin structure protected by the solid wall of the present invention is less vulnerable even if the height of the fin structure (e.g., 60-300 nm) is much larger than the width of the fin structure (e.g., 3-7 nm); (2) the relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (such as, for example, the oxide 3V layer of FIG. 11 or FIG. 23); (3) By forming a metal-semiconductor junction (e.g., FIG. 30A, FIG. 30B, or FIG. 29, etc.) at the source / drain, the resistance of the source / drain may be improved; (4) Most of the source / drain regions are isolated by insulating materials including bottom structures with oxide 3B layer and / or nitride 3B layer (shown in FIG. 29), thus greatly reducing the junction leakage current; (5) The top surface of the STI region surrounding the fin structure can be higher than the top surface of the fin structure, so that the selectively grown source / drain regions are confined by the STI region rather than over the STI region.

[0095] While the invention has been illustrated and described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. a substrate having a fin structure and an initial surface; a shallow trench isolation (STI) layer, the top surface of the STI layer being higher than the initial surface; an insulating wall clamping the side walls of the fin structure, the insulating wall clamping four side walls of the fin structure and a top surface of the insulating wall being flush with the initial surface; a gate region over the fin structure and the insulating wall; having The insulating wall is configured to prevent the fin structure from collapsing. Transistor structure.

2. The transistor structure of claim 1, wherein the shallow trench isolation (STI) layer surrounds the insulating wall.

3. 10. The transistor structure of claim 1, further comprising a sheet channel layer disposed between the sidewall of the fin structure and the insulating wall, the sheet channel layer being an epitaxial semiconductor layer.

4. 2. The transistor structure of claim 1, wherein the gate region comprises a gate dielectric layer over the fin structure, a gate conductive layer over the gate dielectric layer, and a cap layer over the gate conductive layer.

5. 5. The transistor structure of claim 4, wherein the insulating wall is configured to prevent the fin structure from collapsing during formation of the gate dielectric layer, the gate conductive layer, and the cap layer.

6. 2. The transistor structure of claim 1, further comprising a spacer layer on sidewalls of the gate region.

7. 7. The transistor structure of claim 6, further comprising a first conductive region abutting the fin structure, the first conductive region being independent of the substrate, and a bottom surface of the gate region above the shallow trench isolation layer being lower than a bottom surface of the first conductive region.

8. 8. The transistor structure of claim 7, wherein the first conductive region is formed in a first recess below the initial surface of the substrate.

9. 9. The transistor structure of claim 8, wherein the insulating wall is configured to prevent the fin structure from collapsing during formation of the first recess and the first conductive region.

10. The transistor structure of claim 8 , wherein an edge of the first recess is proximate to an edge of the gate region.

11. 9. The transistor structure of claim 8, wherein the first recess has a sidewall, and the first conductive region has a lightly doped region abutting the sidewall of the first recess and a heavily doped region abutting the lightly doped region.

12. 9. The transistor structure of claim 8, wherein the location of the sidewall of the first recess depends on a thickness of the spacer layer on the sidewall of the gate region and a thickness of a thermal oxide layer.

13. 9. The transistor structure of claim 8, wherein a relative position between an edge of the gate region and an edge of the first conductive region depends on a thickness of the spacer layer on the sidewalls of the gate region and a thickness of a thermal oxide layer.

14. The transistor structure further includes a first conductive region in contact with the fin structure; At least two sides of the first conductive region are in contact with a metal region. The transistor structure of claim 1 .

15. 15. The transistor structure of claim 14, wherein a top surface and sidewalls of the first conductive region are in contact with the metal region.

16. 15. The transistor structure of claim 14, wherein a top surface, a bottom surface, and a sidewall of the first conductive region are in contact with the metal region.

17. The transistor structure of claim 14, wherein the shallow trench isolation layer surrounds the fin structure and the first conductive region is bounded by the shallow trench isolation layer.

18. 20. The transistor structure of claim 17, wherein none of the first conductive regions intersect above the shallow trench isolation layer.

19. The transistor structure further includes a first conductive region in contact with the fin structure; a bottom surface of the gate region is lower than a bottom surface of the first conductive region; The transistor structure of claim 1 .

20. The transistor structure of claim 19, wherein the shallow trench isolation layer surrounds the fin structure, and the bottom surface of the gate region above the shallow trench isolation layer is more than 10 nm lower than the bottom surface of the first conductive region.

21. 20. The transistor structure of claim 19, wherein at least two sides of the first conductive region are in contact with a metal region.

22. The transistor structure of claim 19, wherein the shallow trench isolation layer surrounds the fin structure and the first conductive region is bounded by the shallow trench isolation layer.

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