Semiconductor Device

Abstract

To provide a semiconductor device whose characteristics can be improved.SOLUTION: A semiconductor device according to an embodiment includes first to third electrodes, first and second suffocation areas, and a first insulation film. The concentration of Na in a laminated region peaks at the first position. The concentration of Na at the second position is 1 / 100 of the concentration of Na at the first position. A first distance between the first position and the second position along the first direction is 8 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, there are semiconductor devices using nitride semiconductors, and improvements in the characteristics of such semiconductor devices are desired. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-125440 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device capable of improving characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region is made of Al x1 Ga 1-x1 N (0≦x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region between the first partial region and the second partial region, a fourth partial region between the first partial region and the third partial region, and a fifth partial region between the third partial region and the second partial region. A first direction from the first partial region to the first electrode intersects with a second direction from the first electrode to the second electrode. A direction from the second partial region to the second electrode is along the first direction. The second nitride region is Al x2 Ga 1-x2It includes N(0 < x2 ≤ 1, x1 < x2). The second nitride region includes a sixth partial region and a seventh partial region. The direction from the fourth partial region to the sixth partial region is along the first direction. The direction from the fifth partial region to the seventh partial region is along the first direction. The direction from the third partial region to the third electrode is along the first direction. At least a part of the third electrode is between the sixth partial region and the seventh partial region in the second direction. The first insulating film includes a first insulating region. The first insulating region is between the third partial region and the third electrode in the first direction. The third partial region includes a first surface facing the first insulating region. The fourth partial region includes a second surface facing the sixth partial region. The ratio of the distance along the first direction between the position along the first direction of the first surface and the position along the first direction of the second surface to the length along the first direction of the sixth partial region is 2 or more. The stacked region including the third partial region and the first insulating region includes a first position and a second position. In the first direction, the first position is between the second position and the third electrode. The concentration of Na in the stacked region peaks at the first position. The concentration of Na at the second position is 1 / 100 of the concentration of Na at the first position. The first distance along the first direction between the first position and the second position is 8 nm or less.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1(a) and FIG. 1(b) are schematic cross-sectional views illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the characteristics of the semiconductor device. [Figure 3] FIG. 3 is a graph illustrating the SIMS analysis results in the semiconductor device. [Figure 4] FIG. 4 is a graph illustrating the characteristics of the semiconductor device. [Figure 5] FIGS. 5(a) to FIGS. 5(d) are process-sequence schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the embodiment. [Figure 6]6(a) to 6(d) are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) 1A and 1B are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment. 1(a), the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first nitride region 10, a second nitride region 20, and a first insulating film 41. In this example, the semiconductor device 110 further includes a third nitride region 30 and a second insulating film 42.

[0009] The first nitride region 10 is Al x1 Ga 1-x1 The first nitride region 10 includes, for example, GaN. The first nitride region 10 is, for example, a semiconductor region. The first nitride region 10 includes, for example, a crystal.

[0010] The first nitride region 10 includes, for example, first to fifth partial regions 11 to 15. The third partial region 13 is located between the first partial region 11 and the second partial region 12. The fourth partial region 14 is located between the first partial region 11 and the third partial region 13. The fifth partial region 15 is located between the third partial region 13 and the second partial region 12. The first to fifth partial regions 11 to 15 are, for example, continuous with one another.

[0011] The first direction from the first partial region 11 to the first electrode 51 intersects with the second direction from the first electrode 51 to the second electrode 52.

[0012] The second direction is, for example, the X-axis direction. One direction perpendicular to the X-axis direction is defined as the Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is defined as the Y-axis direction.

[0013] The first direction is, for example, the Z-axis direction.

[0014] The direction from the second partial region 12 to the second electrode 52 is along the first direction (for example, the Z-axis direction).

[0015] The second nitride region 20 contains Al x2 Ga 1-x2 N (0 < x2 ≤ 1, x1 < x2). The second nitride region 20 contains AlGaN. For example, the composition ratio x2 of Al is 0.1 or more and 0.3 or less. In one example, the second nitride region 20 contains, for example, Al 0.2 Ga 0.8 N. The second nitride region 20 is, for example, a semiconductor region. The second nitride region 20 contains, for example, crystals.

[0016] The second nitride region 20 contains the sixth partial region 26 and the seventh partial region 27. The direction from the fourth partial region 14 to the sixth partial region 26 is along the first direction (for example, the Z-axis direction). The direction from the fifth partial region 15 to the seventh partial region 27 is along the first direction.

[0017] The direction from the third partial region 13 to the third electrode 53 is along the first direction (for example, the Z-axis direction). At least a part of the third electrode 53 is located between the sixth partial region 26 and the seventh partial region 27 in the second direction (X-axis direction).

[0018] The first insulating film 41 contains a first insulating region 41a. The first insulating region 41a is located between the third partial region 13 and the third electrode 53 in the first direction (Z-axis direction).

[0019] The third nitride region 30 contains Al x3 Ga 1-x3 N (0 < x3 ≦ 1, x1 < x3). For example, the composition ratio x3 of Al in the third nitride region 30 is higher than the composition ratio x2 of Al in the second nitride region 20. In one example, the composition ratio x3 of Al is, for example, 0.8 or more and 1 or less. For example, the third nitride region 30 contains, for example, AlN. The third nitride region 30 is, for example, a semiconductor region. As will be described later, the crystallinity of the third nitride region 30 may vary depending on the location.

[0020] The third nitride region 30 , th includes the first to seventh portions p1 to p7. The first portion p1 is located between the first insulating region 41a and the third partial region 13 in the Z-axis direction. The second portion p2 is located between the third electrode 53 and the fourth partial region 14 in the X-axis direction. The third portion p3 is located between the third electrode 53 and the fifth partial region 15 in the X-axis direction. The fourth portion p4 is located between the third electrode 53 and the sixth partial region 26 in the X-axis direction. The fifth portion p5 is located between the third electrode 53 and the seventh partial region 27 in the X-axis direction.

[0021] The sixth partial region 26 is located between the sixth portion p6 and the fourth partial region 14 in the Z-axis direction. The seventh partial region 27 is located between the seventh portion p7 and the fifth partial region 15 in the Z-axis direction. The first to seventh portions p1 to p7 are, for example, continuous with each other.

[0022] The second insulating film 42 includes a second insulating region 42b and a third insulating region 42c. The sixth partial region 26 is located between the fourth partial region 14 and the second insulating region 42b. The second insulating region 42b is located between the sixth partial region 26 and the sixth portion p6. The seventh partial region 27 is located between the fifth partial region 15 and the third insulating region 42c. The third insulating region 42c is located between the seventh partial region 27 and the seventh portion p7.

[0023] The first insulating film 41 includes fourth to seventh insulating regions 41d to 41g. The fourth insulating region 41d is located between the fourth portion p4 and the third electrode 53. The fifth insulating region 41e is located between the fifth portion p5 and the third electrode 53. The sixth portion p6 is located between the sixth insulating region 41f and the second insulating region 42b. The seventh portion p7 is located between the seventh insulating region 41g and the third insulating region 42c.

[0024] The first insulating film 41 may further include an eighth insulating region 41h and a ninth insulating region 41i. The eighth insulating region 41h is located between the second portion p2 and the third electrode 53 in the X-axis direction. The ninth insulating region 41i is located between the third portion p3 and the third electrode 53 in the X-axis direction. The fourth to ninth insulating regions 41d to 41i are continuous with one another.

[0025] For example, the first insulating film 41 contains silicon and oxygen. For example, the second insulating film 42 contains silicon and nitrogen. For example, the first insulating film 41 does not contain nitrogen. Alternatively, the concentration of nitrogen contained in the first insulating film 41 is lower than the concentration of nitrogen contained in the second insulating film 42. The first insulating film 41 contains, for example, SiO2. The second insulating film 42 contains, for example, SiN.

[0026] For example, the first nitride region 10 and the second nitride region 20 are included in a stacked layer 18. For example, the stacked layer 18 is provided on a substrate 10s. For example, a buffer layer 17 is formed on the substrate 10s. The first nitride region 10 is epitaxially grown on the buffer layer 17. The second nitride region 20 is epitaxially grown on the first nitride region 10. A second insulating film 42 is formed on the second nitride region 20. The stacked layer 18 may include the second insulating film 42. For example, a portion of the stacked layer 18 is removed through an opening in the second insulating film 42 to form a recess (recess or trench). The bottom of the recess is located in the first nitride region 10. A third nitride region 30 is provided on the bottom surface of the recess (part of the first nitride region 10), the side surface of the recess (part of the first nitride region 10 and part of the second nitride region 20), and the surface (e.g., top surface) of the stacked layer 18. For example, at least a portion of the third nitride region 30 is epitaxially grown. The third nitride region 30 is, for example, a regrown layer. After the formation of the third nitride region 30, a first insulating film 41 is formed. For example, first to third electrodes 51 to 53 are formed. In this way, the semiconductor device 110 is obtained.

[0027] The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as, for example, a drain electrode. The third electrode 53 functions as, for example, a gate electrode. The second insulating film 42 functions as, for example, a gate insulating film. The second insulating film 42 functions as, for example, a protective film. For example, the current (drain current) flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53 (for example, gate voltage). The gate voltage is, for example, the potential of the third electrode 53 relative to the potential of the first electrode 51.

[0028] For example, the first nitride region 10 2 For example, a two-dimensional electron gas 10E is generated in a portion on the side of the nitride region 20. The two-dimensional electron gas 10E serves as a carrier region. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0029] In the semiconductor device 110 according to the embodiment, the third electrode 53 and the 3 partial area 1 3 The first portion p1 of the third nitride region 30 is provided between the first nitride region 30 and the second nitride region 30. For example, 3 partial area 1 3 A two-dimensional electron gas 10F is formed in the portion on the side of the first portion p1. This results in, for example, high mobility.

[0030] 1(b), the third partial region 13 includes a first surface 10fa. The first surface 10fa faces the first insulating region 41a. For example, the first surface 10fa faces the first portion p1. The sixth partial region 26 and the seventh partial region 27 include second surfaces 10fb that face the first electrode 51 and the second electrode 52, respectively. The distance along the first direction between a position along the first direction (Z-axis direction) on the first surface 10fa and a position along the first direction on the second surface 10fb is defined as distance t1. The length along the first direction of the sixth partial region 26 is defined as length t2. Length t2 corresponds to the thickness of the sixth partial region 26. Distance t1 corresponds to the recess depth Dr1. The ratio of distance t1 to length t2 (t1 / t2) is defined as ratio R1. When ratio R1 is 1, the first nitride region 10 is not removed. When ratio R1 is 2, the removal depth of the first nitride region 10 is the same as the thickness (length t2) of the second nitride region 20.

[0031] In the embodiment, the recess depth Dr1 is set deeper than a general depth. In the embodiment, the ratio R1 is 2 or more. The ratio R1 may be 3 or more. The ratio R1 may be 3.5 or more. As will be described later, high mobility can be obtained.

[0032] The inventor's experiments have revealed that a high mobility can be obtained by increasing the recess depth Dr1 (increasing the ratio R1). The results of the experiments will be explained below.

[0033] In the experimental sample, the first nitride region 10 is GaN. The second nitride region 20 is Al. 0.2 Ga 0.8The second nitride region 20 has a thickness (length in the Z-axis direction) of 30 nm. The sixth partial region 26 has a thickness (length t2) of 30 nm. The third nitride region 30 has a thickness (for example, the length in the Z-axis direction of the first portion p1) of 3 nm. The second insulating film 42 has a thickness (length in the Z-axis direction) of 10 nm. The first insulating film 41 has a thickness (for example, the length in the Z-axis direction of the first insulating region 41a) of 30 nm. The first to third electrodes 51 to 53 contain TiN.

[0034] A plurality of samples are fabricated in which the recess depth Dr1 and the ratio R1 are changed. The recesses are formed by RIE (Reactive Ion Etching) using a gas containing BCl4. In the experiment, the recess depth Dr1 (ratio R1) is changed by changing the recess formation time. After the recess formation, a heat treatment is performed in an atmosphere containing ammonia gas to remove elements (such as B and Cl) contained in the etching gas. Thereafter, a third nitride region 30 and a first insulating film 41 are formed, and the heat treatment Reason After that, the first to third electrodes 51 to 53 are formed. This results in a semiconductor device sample. In samples with a deep recess depth Dr1 (high ratio R1), the processing time for forming the recess is long. The mobility of these samples is evaluated.

[0035] FIG. 2 is a graph illustrating the characteristics of the semiconductor device. The horizontal axis of Figure 2 is the ratio R1 (nm, depth of recess). The vertical axis of Figure 2 is the mobility μ (cm 2 / Vs, field mobility). In the sample with a ratio R1 of 1.86, the recess depth Dr1 is 56 nm. In the sample with a ratio R1 of 3.5, the recess depth Dr1 is 105 nm. In the sample with a ratio R1 of 4.1, the recess depth Dr1 is 1 In the sample with a ratio R1 of 5.53, the recess depth Dr1 is 166 nm.

[0036] 2, when the ratio R1 is low and the recess is shallow, the mobility μ is low. When the ratio R1 is high, such as 3.5 or more, and the recess is deep, the mobility μ is high.

[0037] The mobility μ is thought to be related to the ease of carrier movement in the carrier region (for example, the two-dimensional electron gas 10E and the two-dimensional electron gas 10F). When forming the recess, impurities are introduced into the bottom of the recess (third partial region 13), which is thought to reduce the crystal quality and lower the mobility μ. Based on this idea, it is natural to think that it is preferable to make the recess shallower in order to suppress the introduction of impurities when the recess is formed.

[0038] However, the experimental results shown in Figure 2 show that a deep recess and a high ratio R1 result in a high mobility μ. Regarding these new findings, the samples are analyzed.

[0039] FIG. 3 is a graph illustrating the results of SIMS analysis of a semiconductor device. FIG. 3 shows the results of SIMS analysis in the stack region rg1 (see FIG. 1(b)) including the third partial region 13 and the first insulating region 41a. The horizontal axis of FIG. 3 represents the position pZ (nm) along the Z-axis direction. The vertical axis represents the Na concentration C(Na) (atoms / cm 3 ) In FIG. 3, the results for samples with ratios R1 of 1.86, 3.5, or 4.1 are shown.

[0040] As can be seen from Figure 3, the peak value of the Na concentration C(Na) is almost the same whether the ratio R1 is 1.86, 3.5, or 4.1. However, the characteristics regarding the decrease in the Na concentration C(Na) differ depending on the ratio R1. When the ratio R1 is 1.86, the Na concentration C(Na) is difficult to decrease. In contrast, when the ratio R1 is 3.5 or 4.1, the Na concentration C(Na) decreases sharply.

[0041] For example, the stack region rg1 including the third partial region 13 and the first insulating region 41a includes a first position pZ1. The Na concentration in this stack region rg1 peaks at the first position pZ1. When the ratio R1 is 1.86, 3.5, or 4.1, the position of the first position pZ1 in the Z-axis direction is substantially the same (position pZ=31 nm).

[0042] The integral value of the Na concentration C(Na) (the area of ​​the shaded area Cs1 in FIG. 3) in the range from the first position pZ1+4 nm to the first position pZ1+14 nm (pZ=35 to 45 nm range) is defined as parameter C1(Na). A small parameter C1(Na) corresponds to a small amount of Na in this region.

[0043] FIG. 4 is a graph illustrating the characteristics of the semiconductor device. The horizontal axis of Figure 4 is the ratio R1. The vertical axis is the parameter C1(Na) (atoms × 10 10 / cm 2 ) As can be seen from Figure 4, when the ratio R1 is 1.86, the parameter C1(Na) is high. In contrast, when the ratio R1 is 3.5 or 4.1, the parameter C1(Na) is significantly low. Thus, it was found that when the ratio R1 is high, the parameter C1(Na) becomes smaller and the amount of Na is significantly reduced.

[0044] For example, when forming a recess, the second nitride region 20 is removed first, and then removal of the first nitride region 10 begins. The Al composition ratio x2 in the second nitride region 20 is higher than the Al composition ratio x1 in the first nitride region 10. A high Al composition ratio results in a low etching rate. The etching rate of the second nitride region 20 (e.g., AlGaN) is lower than the etching rate of the first nitride region 10 (e.g., GaN). For example, a long etching time is required to remove the second nitride region 20. It is believed that damage occurs to the first nitride region 10 (GaN) during this long etching time. Once etching of the second nitride region 20 (e.g., AlGaN) is completed and etching of the first nitride region 10 (GaN) begins, it is believed that the GaN is removed in a state where it is less likely to be damaged.

[0045] When the recess is shallow and the ratio R1 is low, it is thought that the damaged first nitride region 10 (GaN) is likely to remain. On the other hand, when the recess is deep and the ratio R1 is high, it is thought that the damaged first nitride region 10 (GaN) is also removed, and damage to the remaining GaN is suppressed. It is thought that Na is likely to be trapped in the damage described above. It is thought that Na originates, for example, from impurities in the source gas, impurities attached to the device, or impurities contained in the surrounding environment.

[0046] For example, the above-described mechanism is thought to cause the phenomenon illustrated in Figure 4. In this way, when the recess is deep and the ratio R1 is high, damage is suppressed, and the amount of Na at the bottom of the recess is reduced, for example. As a result, as explained with reference to Figure 2, it is thought that a high ratio R1 results in a high mobility μ.

[0047] The embodiment is based on the above-mentioned newly discovered findings. That is, the ratio R1 is increased. Then, the Na concentration is sharply reduced. For example, as shown in FIG. 3, when the ratio R1 is high, the thickness until the Na concentration C(Na) reaches 1 / 100 of its peak value is thinner than when the ratio R1 is low.

[0048] 3, for example, the stack region rg1 (see FIG. 1(b)) including the third partial region 13 and the first insulating region 41a includes a first position pZ1 and a second position pZ2. In the first direction (Z-axis direction), the first position pZ1 is located between the second position pZ2 and the third electrode 53. For example, in the first direction (Z-axis direction), the first position pZ1 is located between the second position pZ2 and the first insulating region 41a.

[0049] The Na concentration in the stacked region rg1 peaks at a first position pZ1. The Na concentration (peak concentration) at the first position pZ1 is defined as a first concentration Cp1. The Na concentration at the second position pZ2 is defined as a second concentration Cp2. The second concentration Cp2 is 1 / 100 of the Na concentration at the first position pZ1 (first concentration Cp1). The second position pZ2 is the position where the Na concentration C(Na) is 1 / 100 of the peak concentration.

[0050] In the embodiment, the first distance d1 along the first direction (Z-axis direction) between the first position pZ1 and the second position pZ2 is 8 nm or less. Thus, in the embodiment, the Na concentration drops sharply. This allows, for example, a high mobility μ to be obtained. According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0051] In the embodiment, the first distance d1 may be 5 nm or less, which allows the amount of Na to be further reduced.

[0052] In the embodiment, the above parameter C1(Na) (see FIG. 4) is 10×10 10 / cm 2 The parameter C1(Na) is preferably 5×10 10 / cm 2 A small amount of Na can provide, for example, a high mobility μ.

[0053] In the embodiment, the third nitride region 30 includes the first portion p1 on the third sub-region 13 (e.g., GaN), as well as side portions of the recess (e.g., second to fifth portions p2 to p5) and portions on the second nitride region 20 (sixth portion p6 and seventh portion p7). These portions are continuous. By providing such a third nitride region 30, for example, good crystallinity can be easily obtained in the first portion p1. This allows, for example, the two-dimensional electron gas 10F to be stably formed. This allows higher mobility to be stably obtained. According to the embodiment, a semiconductor device can be provided that can stably improve its characteristics.

[0054] In the embodiment, a second insulating film 42 is provided. The second insulating film 42 protects the upper surface of the second nitride region 20 when the recess is formed. Deterioration of the second nitride region 20 can be suppressed.

[0055] In the embodiment, the first portion p1 of the third nitride region 30 is provided on the third partial region 13 of the first nitride region 10. This makes it easier to obtain good crystallinity in the first portion p1, for example.

[0056] On the other hand, the sixth portion p6 of the third nitride region 30 is provided on the second insulating region 42b of the second insulating film 42. The seventh portion p7 of the third nitride region 30 is provided on the third insulating region 42c of the second insulating film 42. In this way, the first portion p1 and the sixth portion p6 have different underlayers. The first portion p1 and the seventh portion p7 have different underlayers. Therefore, the crystallinity and the like may be different between these portions.

[0057] For example, the crystallinity of the first portion p1 is higher than that of the sixth portion p6. The crystallinity of the first portion p1 is higher than that of the seventh portion p7. When the crystallinity of the first portion p1 is high, for example, high mobility is easily obtained.

[0058] For example, at least a part of the first portion p1 may include a crystal, at least a part of the sixth portion p6 may be amorphous, and at least a part of the seventh portion p7 may be amorphous.

[0059] The side portion (e.g., the second portion p2) of the third nitride region 30 is formed on a nitride semiconductor. Therefore, the crystallinity of the side portion is relatively high. For example, the crystallinity of the second portion p2 is higher than the crystallinity of the sixth portion p6. For example, the crystallinity of the third portion p3 is higher than the crystallinity of the seventh portion p7.

[0060] The fourth portion p4 is formed on a nitride semiconductor. Therefore, the fourth portion p4 has a relatively high crystallinity. For example, the crystallinity of the fourth portion p4 is higher than that of the sixth portion p6. For example, the crystallinity of the fifth portion p5 is higher than that of the seventh portion p7.

[0061] In the embodiment, the third electrode 53 faces a part of the first nitride region 10 and faces the second nitride region 20 in the X-axis direction. The third electrode 53 is, for example, a recessed gate electrode. For example, the two-dimensional electron gas 10E below the second nitride region 20 is divided by the third electrode 53 and the first insulating film 41 (gate insulating film). This makes it possible to increase the threshold voltage and easily obtain stable normally-off characteristics.

[0062] An example of a method for manufacturing the semiconductor device 110 according to the embodiment will now be described. 5(a) to 5(d) and 6(a) to 6(d) are schematic cross-sectional views in order of the processes, illustrating a method for manufacturing a semiconductor device according to the embodiment. In these figures, the buffer layer 17 is omitted.

[0063] 5(a), a first nitride region 10 is provided on a base body 10s. A second nitride region 20 is provided on the first nitride region 10. The base body 10s is, for example, a silicon substrate.

[0064] 5(b), a second insulating film 42 is provided on the second nitride region 20. A stacked body 18 is obtained.

[0065] As shown in FIG. 5(c), a mask film 45 having predetermined openings is formed on the second insulating film .

[0066] 5(d), the mask film 45 is used as a mask to remove a part of the second insulating film 42. As a result, an opening 42o is formed in the second insulating film 42.

[0067] 6(a), the second insulating film 42 is used as a mask to remove a portion of the stacked body 18. A recess 18r is formed in the stacked body 18. A portion of the first nitride region 10 is exposed at the bottom 18b of the recess 18r.

[0068] In this case, the recess depth Dr1 corresponds to the distance in the Z-axis direction between the top surface and bottom 18b of the second nitride region 20. The recess depth Dr1 is preferably, for example, three times or more the thickness (length t2) of the second nitride region 20.

[0069] 6(b), the third nitride region 30 is formed. The third nitride region 30 is formed on the first nitride region 10 exposed at the bottom 18b of the recess 18r, the side surface 20s of the second nitride region 20, and the upper surface of the second insulating film 42.

[0070] As shown in FIG. 6(c), a first insulating film 41 is formed.

[0071] As shown in FIG. 6(d), first to third electrodes 51 to 53 are formed. A second direction (X-axis direction) from the first electrode 51 to the second electrode 52 intersects with a first direction (Z-axis direction) from the first nitride region 10 to the second nitride region 20. The position of the third electrode 53 in the second direction is between the position of the first electrode 51 in the second direction and the position of the second electrode 52 in the second direction. At least a portion of the third electrode 53 is located in the remaining space of the recess 18r. In the second direction (X-axis direction), 3 faces the first nitride region 10 You can .

[0072] In the above manufacturing method, the third nitride region 30 is formed on the first nitride region 10 exposed at the bottom 18b of the recess 18r, the side surface 20s of the second nitride region 20, and the upper surface of the first insulating film 41. Good crystallinity can be obtained in the first portion p1 (see FIG. 1(a)) of the third nitride region 30. By forming the recess 18r using the second insulating film 42, the damage to the second nitride region 20 is small. By forming the first insulating film 41 so as to cover the third nitride region 30, the third nitride region 30 is protected.

[0073] Thus, in the above manufacturing method, the laminate 18 is prepared. The laminate 18 includes a first nitride region 10 containing Al x1 Ga 1-x1 N (0 ≦ x1 < 1), a second nitride region 20 containing Al x2 Ga 1-x2 N (0 < x2 ≦ 1, x1 < x2), and a second insulating film 42. The second nitride region 20 is provided between the first nitride region 10 and the second insulating film 42.

[0074] A part of the laminate 18 is removed from the side of the second insulating film 42 to form a recess in the laminate 18. Then, a part of the first nitride region 10 is exposed at the bottom of the recess.

[0075] Al x3 Ga 1-x3 A third nitride region 30 containing Al

[0076] After forming the third nitride region 30, the first insulating film 41 is formed. Electrodes (first to third electrodes 51 to 53) are formed. The formation of the electrodes is carried out, for example, after forming the first insulating film 41.

[0077] The embodiment may include the following configuration (for example, technical solution). (Configuration 1) The first electrode, The second electrode, Al x1Ga 1-x1 A first nitride region containing N(0≦x1<1), wherein the first nitride region includes a first partial region, a second partial region, a third partial region between the first partial region and the second partial region, a fourth partial region between the first partial region and the third partial region, and a fifth partial region between the third partial region and the second partial region. A first direction from the first partial region to the first electrode intersects a second direction from the first electrode to the second electrode. A direction from the second partial region to the second electrode is along the first direction. The first nitride region and Al x2 Ga 1-x2 A second nitride region containing N(0<x2≦1, x1<x2), wherein the second nitride region includes a sixth partial region and a seventh partial region. A direction from the fourth partial region to the sixth partial region is along the first direction. A direction from the fifth partial region to the seventh partial region is along the first direction. The second nitride region and A third electrode, wherein a direction from the third partial region to the third electrode is along the first direction, and at least a part of the third electrode is between the sixth partial region and the seventh partial region in the second direction. The third electrode and A first insulating film including a first insulating region, wherein the first insulating region is between the third partial region and the third electrode in the first direction. The first insulating film and Comprising The third partial region includes a first surface facing the first insulating region. The fourth partial region includes a second surface facing the sixth partial region. A ratio of a distance along the first direction between a position along the first direction of the first surface and a position along the first direction of the second surface to a length along the first direction of the sixth partial region is 2 or more. A stacked region including the third partial region and the first insulating region includes a first position and a second position. In the first direction, the first position is between the second position and the third electrode. The concentration of Na in the stacked region peaks at the first position. The concentration of Na at the second position is 1 / 100 of the concentration of Na at the first position, A semiconductor device, wherein a first distance along the first direction between the first position and the second position is 8 nm or less.

[0078] (Configuration 2) The semiconductor device according to Configuration 1, wherein the first distance is 5 nm or less.

[0079] (Configuration 3) The semiconductor device according to Configuration 1 or 2, wherein the ratio is 3 or more.

[0080] (Configuration 4) The semiconductor device according to Configuration 1 or 2, wherein the ratio is 3.5 or more.

[0081] (Configuration 5) Al x3 Ga 1-x3 Further comprising a third nitride region containing N(0 < x3 ≦ 1, x1 < x3), [[ID=三十二]]The third nitride region includes first to seventh portions, the first portion is between the first insulating region and the third partial region, the second portion is between the third electrode and the fourth partial region, the third portion is between the third electrode and the fifth partial region, the fourth portion is between the third electrode and the sixth partial region, the fifth portion is between the third electrode and the seventh partial region, the sixth partial region is between the sixth portion and the fourth partial region, and the seventh partial region is between the seventh portion and the fifth partial region. The semiconductor device according to any one of Configurations 1 to 4.

[0082] <00​​​​​​​​​​​​the first insulating film includes fourth to seventh insulating regions, the fourth insulating region is between the fourth portion and the third electrode; the fifth insulating region is between the fifth portion and the third electrode; the sixth portion is between the sixth insulating region and the second insulating region; 7. The semiconductor device of claim 6, wherein the seventh portion is between the seventh insulating region and the third insulating region.

[0084] (Configuration 8) the first insulating film further includes an eighth insulating region and a ninth insulating region; the eighth insulating region is between the second portion and the third electrode; 8. The semiconductor device of claim 7, wherein the ninth insulating region is between the third portion and the third electrode.

[0085] (Configuration 9) the first insulating film contains silicon and oxygen, 9. The semiconductor device according to any one of configurations 6 to 8, wherein the second insulating film contains silicon and nitrogen.

[0086] (Configuration 10) 10. The semiconductor device according to any one of configurations 6 to 9, wherein the first portion has higher crystallinity than the sixth portion.

[0087] (Configuration 11) At least a portion of the first portion includes a crystal; 11. The semiconductor device according to any one of configurations 6 to 10, wherein at least a part of the sixth portion is amorphous.

[0088] (Configuration 12) 12. The semiconductor device according to any one of configurations 6 to 11, wherein the second portion has higher crystallinity than the sixth portion.

[0089] (Configuration 13) 13. The semiconductor device according to any one of configurations 6 to 12, wherein the fourth portion has higher crystallinity than the sixth portion.

[0090] (Configuration 14) The first insulating film does not contain nitrogen, or 14. The semiconductor device according to any one of configurations 6 to 13, wherein the concentration of nitrogen contained in the first insulating film is lower than the concentration of nitrogen contained in the second insulating film.

[0091] (Configuration 15) 15. The semiconductor device according to any one of configurations 5 to 14, wherein x3 is higher than x2.

[0092] (Configuration 16) The x1 is equal to or greater than 0 and equal to or less than 0.05, x2 is equal to or greater than 0.1 and equal to or less than 0.3, 16. The semiconductor device according to any one of configurations 5 to 15, wherein x3 is 0.8 or more and 1 or less.

[0093] According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0094] In this specification, "vertical" and "parallel" do not only mean strictly vertical and strictly parallel, but also include variations in the manufacturing process, and may mean substantially vertical and substantially parallel.

[0095] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of elements such as nitride regions, electrodes, and insulating films included in a semiconductor device are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0096] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0097] In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0098] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0099] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0100] 10...nitride region, 10E, 10F...two-dimensional electron gas, 10fa...first surface, 10fb...second surface, 10s...substrate, 11-15...first to fifth partial regions, 17...buffer layer, 18...stacked body, 18b...bottom, 18r...recess, 20...second nitride region, 20s...side surface, 26...sixth partial region, 27...seventh partial region, 30...third nitride region, 41...first insulating film, 41a...first insulating region, 41d-41i...fourth to ninth insulating regions, 42...second insulating film, 42b, 42c...second and third insulating regions, 42o...opening, 45...mask film, 51-53...first to third electrodes, μ...mobility, 110...semiconductor device, C(Na)...concentration, C1(Na)...parameter, Cp1, Cp2...first and second concentrations, Cs1...shaded area, Dr1...recess depth, R1...ratio, d1...first distance, p1~p7...first to seventh portions, pZ...position, pZ1, pZ2...first and second positions, rg1...layer area, t1...distance, t2...length

Claims

1. A first electrode; A second electrode; A ｘ１ G １－ｘ１ N (0≦x1<1), the first nitride region including a first partial region, a second partial region, a third partial region between the first partial region and the second partial region, a fourth partial region between the first partial region and the third partial region, and a fifth partial region between the third partial region and the second partial region, a first direction from the first partial region to the first electrode intersects with a second direction from the first electrode to the second electrode, and a direction from the second partial region to the second electrode is along the first direction; A ｘ２ G １－ｘ２ N (0<x2≦1, x1<x2), the second nitride region including a sixth partial region and a seventh partial region, a direction from the fourth partial region to the sixth partial region being along the first direction, and a direction from the fifth partial region to the seventh partial region being along the first direction; a third electrode, the direction from the third partial region to the third electrode being along the first direction, and at least a portion of the third electrode being between the sixth partial region and the seventh partial region in the second direction; a first insulating film including a first insulating region, the first insulating region being between the third partial region and the third electrode in the first direction; a third nitride region comprising AlN; Equipped with the third portion region includes a first surface facing the first insulating region; the sixth partial region and the seventh partial region each include a second surface facing the first electrode and the second electrode, a ratio of a distance along the first direction between a position along the first direction of the first surface and a position along the first direction of the second surface to a length along the first direction of the sixth partial region is equal to or greater than 2; a stacked region including the third partial region and the first insulating region includes a first position and a second position, and in the first direction, the first position is between the second position and the third electrode; The concentration of Na in the stacked region peaks at the first position, the concentration of Na at the second position is 1 / 100 of the concentration of Na at the first position; a first distance along the first direction between the first position and the second position is 8 nm or less; the third nitride region includes first to seventh portions, the first portion being between the first insulating region and the third partial region, the second portion being between the third electrode and the fourth partial region, the third portion being between the third electrode and the fifth partial region, the fourth portion being between the third electrode and the sixth partial region, the fifth portion being between the third electrode and the seventh partial region, the sixth partial region being between the sixth portion and the fourth partial region, and the seventh partial region being between the seventh portion and the fifth partial region; The x1 is 0 or more and 0.05 or less, The x2 is equal to or greater than 0.1 and equal to or less than 0.3, A semiconductor device, wherein a two-dimensional electron gas is formed in a portion of the first nitride region on the second nitride region side, and a two-dimensional electron gas is formed in a portion of the third region on the first portion side.

2. Further comprising a second insulating film including a second insulating region and a third insulating region; the sixth partial region is between the fourth partial region and the second insulating region; 2. The semiconductor device according to claim 1, wherein said seventh partial region is between said fifth partial region and said third insulating region.

3. the first insulating film includes fourth to seventh insulating regions; the fourth insulating region is between the fourth portion and the third electrode; the fifth insulating region is between the fifth portion and the third electrode; the sixth portion is between the sixth insulating region and the second insulating region; 3. The semiconductor device according to claim 2, wherein said seventh portion is between said seventh insulating region and said third insulating region.

4. the first insulating film further includes an eighth insulating region and a ninth insulating region; the eighth insulating region is between the second portion and the third electrode; The semiconductor device according to claim 3 , wherein said ninth insulating region is between said third portion and said third electrode.

5. the first insulating film contains silicon and oxygen; 5. The semiconductor device according to claim 2, wherein said second insulating film contains silicon and nitrogen.

6. 6. The semiconductor device according to claim 2, wherein the first portion has a higher crystallinity than the sixth portion.

7. At least a portion of the first portion includes a crystal; 7. The semiconductor device according to claim 2, wherein at least a part of the sixth portion is amorphous.

8. 8. The semiconductor device according to claim 2, wherein the second portion has a higher crystallinity than the sixth portion.

9. 9. The semiconductor device according to claim 2, wherein the fourth portion has a higher crystallinity than the sixth portion.

10. The first insulating film does not contain nitrogen, or 10. The semiconductor device according to claim 2, wherein a concentration of nitrogen contained in said first insulating film is lower than a concentration of nitrogen contained in said second insulating film.

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