Semiconductor device and method for manufacturing the same

Abstract

This semiconductor device (1) comprises: a Si substrate (101); a reverse-surface electrode (304) provided to the lower side of the Si substrate (101); an SiC layer (102) provided to the upper side of the Si substrate (101); a nitride semiconductor layer (103) provided to the upper side of the SiC layer (102); a source electrode (201) and a drain electrode (202) that are provided to the upper side of the nitride semiconductor layer (103); a gate electrode (203) in contact with the nitride semiconductor layer (103); an intermediate layer (105) provided to an opening (104), at which the SiC layer (102) and the nitride semiconductor layer (103) are opened; a metal layer (106) provided to the upper side of the opening (104) so as to cover the intermediate layer (105); and a conductor (303) provided inside a through-via (301) passing through the intermediate layer (105) and the Si substrate (101), the conductor (303) being electrically connected to the reverse-surface electrode (304) and the metal layer (106). The intermediate layer (105) is a metal nitride layer or a silicon oxide layer.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a nitride semiconductor device using a Group III nitride semiconductor and a method for manufacturing the same. [Background technology]

[0002] Nitride semiconductor devices using Group III nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) have a high breakdown voltage due to the wide band gap of the material. Furthermore, heterostructures such as AlGaN / GaN can be easily formed in semiconductor devices using Group III nitride semiconductors.

[0003] In an AlGaN / GaN heterostructure, a channel of high concentration of electrons (two-dimensional electron gas; 2DEG (Two Dimensions Electron Gas) is formed on the GaN layer side of the AlGaN / GaN interface due to the difference between the piezoelectric polarization caused by the difference in lattice constant between the materials and the spontaneous polarization of AlGaN and GaN. Nitride semiconductor devices that utilize this two-dimensional electron gas channel have relatively high electron saturation velocity and insulation resistance, as well as relatively high thermal conductivity, and are therefore applied to high-frequency power devices.

[0004] In this type of nitride semiconductor device, since the Si substrate is less expensive than the sapphire substrate or the SiC substrate, there is a technique for forming a nitride semiconductor layer made of a group III nitride semiconductor on a Si substrate. However, when a nitride semiconductor layer made of a group III nitride semiconductor is directly formed on a Si substrate, the lattice constant difference between Si and the group III nitride semiconductor is large, so the crystallinity of the group III nitride semiconductor in the nitride semiconductor layer is lower than that when a nitride semiconductor layer made of a group III nitride semiconductor is formed on a SiC substrate. Therefore, in order to reduce the lattice constant difference between Si and the group III nitride semiconductor, a technique has been proposed in which a buffer layer made of 3C-SiC is formed on a Si substrate and then a nitride semiconductor layer made of a group III nitride semiconductor is formed on the 3C-SiC. By using a buffer layer made of 3C-SiC, the nitride semiconductor layer made of a group III nitride semiconductor can be thickly stacked, so that the crystallinity of the group III nitride semiconductor can be made equivalent to that when a nitride semiconductor layer made of a group III nitride semiconductor is formed on a SiC substrate.

[0005] In addition, in high frequency power devices, a technique has been proposed in which a grounded back electrode is formed on the back surface of a substrate, and a metal is embedded in a through via penetrating the substrate to electrically connect the back electrode to a source electrode on the substrate. This configuration strengthens the grounding of the source electrode, thereby suppressing a decrease in gain.

[0006] Here, as conventional nitride semiconductor devices of this type, GaN-based semiconductor devices disclosed in Patent Documents 1 and 2 will be described.

[0007] FIG. 10 is a cross-sectional view of a nitride semiconductor device 1X disclosed in Patent Document 1.

[0008] As shown in FIG. 10, the nitride semiconductor device 1X disclosed in Patent Document 1 includes a dielectric substrate 107X, a SiC layer 102 formed on the dielectric substrate 107X, a nitride semiconductor layer 103 made of a group III nitride semiconductor formed on the SiC layer 102, and a source electrode 201, a drain electrode 202, and a gate electrode 203 formed on the surface of the nitride semiconductor layer 103. In addition, an opening 104 is provided in the drain region 202D in which the drain electrode 202 is provided so as to penetrate the drain electrode 202, the nitride semiconductor layer 103, and the SiC layer 102, and a metal layer 305 is embedded inside the opening 104. In addition, a through via 301 is provided in the dielectric layer 101X in the dielectric substrate 107X, and a conductor 303 is embedded in the through via 301. In addition, a back electrode 304 is provided on the back surface of the dielectric layer 101X. The dielectric layer 101X, the back electrode 304, and the conductor 303 form a dielectric substrate 107X.

[0009] 10, the back electrode 304 and the drain electrode 202 are electrically connected via the conductor 303 embedded in the through via 301 and the metal layer 305 embedded in the opening 104. Specifically, according to the manufacturing method described in Patent Document 1, after removing the Si substrate on the back surface of the SiC layer 102, the SiC layer 102 and the dielectric substrate 107X are bonded so as to connect the metal layer 305 and the conductor 303.

[0010] 11 is a cross-sectional view of a nitride semiconductor device 1Y disclosed in Patent Document 2. As shown in Fig. 11, the nitride semiconductor device 1Y disclosed in Patent Document 2 includes a Si substrate 101 which is an insulating substrate, a nitride semiconductor layer 103 made of a group III nitride semiconductor formed on the Si substrate 101, and a source electrode 201, a drain electrode 202, and a gate electrode 203 formed on the surface of the nitride semiconductor layer 103. A metal layer 305 serving as a stopper layer is provided in a source region 201S in which the source electrode 201 is provided, and a back electrode 304 is provided on the back surface of the Si substrate 101.

[0011] 11, a through via 301 penetrating a Si substrate 101 and a nitride semiconductor layer 103 reaches a metal layer 305, and a back electrode 304 is electrically connected to a source electrode 201 via the metal layer 305. According to the manufacturing method described in Patent Document 2, the through via 301 is formed from the back surface side of the Si substrate 101, a back electrode 304 is formed along the through via 301, and then a conductor 303 is filled in the through via 301. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2013-243275 A [Patent Document 2] JP 2009-033097 A Summary of the Invention [Problem to be solved by the invention]

[0013] However, in the nitride semiconductor device 1X shown in FIG. 10, as described above, the Si substrate on the back surface of the SiC layer 102 is removed, and then the SiC layer 102 and the dielectric substrate 107X are joined by connecting the metal layer 305 and the conductor 303, resulting in a complex manufacturing process and high costs.

[0014] 11, the back electrode 304 and the source electrode 201 are connected by forming a through via 301 from the back surface of the Si substrate 101. Therefore, although the manufacturing process of the nitride semiconductor device 1Y shown in Fig. 11 is not complicated, since there is no SiC layer between the Si substrate 101 and the nitride semiconductor layer 103, the crystallinity of the Group III nitride semiconductor constituting the nitride semiconductor layer 103 decreases due to the difference in lattice constant between Si and the Group III nitride semiconductor.

[0015] Therefore, in the nitride semiconductor device 1Y shown in FIG. 11, it is considered to provide a SiC layer between the Si substrate 101 and the nitride semiconductor layer 103. Specifically, as in the nitride semiconductor device 1Z shown in FIG. 12, a SiC layer 102 is provided between the Si substrate 101 and the nitride semiconductor layer 103, and a through via 301 is provided penetrating the Si substrate 101, the SiC layer 102, and the nitride semiconductor layer 103 with the metal layer 106 as a stopper, and a conductor 303 is embedded inside the through via 301. This allows the back electrode 304 and the source electrode 201 to be electrically connected via the conductor 303 and the metal layer 106. In addition, in the nitride semiconductor device 1Z shown in FIG. 12, a metal diffusion prevention film 302 is provided on the inner surface of the through via 301 so that the conductor 303 and the Si substrate 101 do not come into contact with each other and cause metals to diffuse between them. That is, the metal diffusion prevention film 302 is provided between the Si substrate 101 and the conductor 303.

[0016] 12, since the SiC constituting the SiC layer 102 is hard and chemically stable, a notch 400 is formed in the Si substrate 101 when the through via 301 is formed. Specifically, the through via 301 is formed by dry etching the Si substrate 101 and the SiC layer 102 using a fluorine-based gas or a chlorine-based gas, but since the etching rate of SiC is slower than the etching rate of Si, side etching occurs in the Si substrate 101 near the SiC layer 102 in the Si substrate 101, resulting in the notch 400.

[0017] If a notch 400 occurs in the Si substrate 101, the notch 400 may become a void when the conductor 303 is formed inside the through via 301, or the presence of the notch 400 may reduce the coverage of the metal diffusion prevention film 302, causing contact between the conductor 303 and the Si substrate 101 and causing interdiffusion of metals, resulting in high resistance. As a result, the quality of the nitride semiconductor device 1Z may deteriorate, leading to a decrease in yield.

[0018] The present disclosure has been made in consideration of such problems, and aims to provide a semiconductor device in which a through via can be provided that penetrates a Si substrate and a SiC layer without causing notching, even if a SiC layer is provided between a Si substrate and a nitride semiconductor layer. [Means for solving the problem]

[0019] In order to achieve the above object, one aspect of a semiconductor device according to the present disclosure includes a Si substrate, a back electrode provided below the Si substrate, a SiC layer provided above the Si substrate, a semiconductor layer provided above the SiC layer and made of a Group III nitride semiconductor, a source electrode and a drain electrode provided above the semiconductor layer, a gate electrode in contact with the semiconductor layer, an intermediate layer provided in an opening that opens at least the SiC layer, a metal layer provided above the opening, and a conductor provided inside a through via that penetrates the intermediate layer and the Si substrate and is electrically connected to the back electrode and the metal layer, the metal layer covering the through via, the intermediate layer being provided between the SiC layer and the conductor, and the intermediate layer being a metal nitride layer or a silicon oxide layer.

[0020] Moreover, one aspect of a manufacturing method of a semiconductor device according to the present disclosure includes forming a SiC layer above a Si substrate, forming a semiconductor layer made of a Group III nitride semiconductor above the SiC layer, forming an opening that opens the SiC layer, forming an intermediate layer in the opening, forming a source electrode, a drain electrode and a gate electrode above the semiconductor layer, forming a metal layer above the opening so as to cover at least a portion of the intermediate layer, forming a through via that penetrates the Si substrate and the intermediate layer from a lower surface side of the Si substrate using the metal layer as a stopper, forming a conductor inside the through via, forming a back electrode below the Si substrate, the back electrode and the metal layer being electrically connected via the conductor, the intermediate layer being provided between the SiC layer and the conductor, and the intermediate layer being a metal nitride layer or a silicon oxide layer. Effect of the Invention

[0021] According to the semiconductor device of the present disclosure, even if a SiC layer is provided between a Si substrate and a nitride semiconductor layer, a through via that penetrates the Si substrate and the SiC layer can be provided without causing notching. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line II-II in FIG. [Figure 3A] FIG. 3A is a diagram illustrating a step of forming a SiC layer and a nitride semiconductor layer on a Si substrate in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a view for illustrating a step of forming openings in the SiC layer and the nitride semiconductor layer in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3C] FIG. 3C is a view for illustrating a step of forming an intermediate layer in the opening in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3D] FIG. 3D is a view for illustrating a step of forming a source electrode, a drain electrode, and a gate electrode in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3E] FIG. 3E is a view for illustrating a step of forming a metal layer on the intermediate layer in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3F] FIG. 3F is a view for illustrating a step of forming a through via that penetrates the Si substrate and the intermediate layer in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3G] FIG. 3G is a view for illustrating a step of forming a conductor in the through via in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3H] FIG. 3H is a view for illustrating a step of forming a back electrode on a Si substrate in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a plan view of a semiconductor device according to a modification of the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment taken along line VV of FIG. [Figure 6A] FIG. 6A is a diagram illustrating a step of forming a SiC layer and a nitride semiconductor layer on a Si substrate in a manufacturing method of a semiconductor device according to a modification of the first embodiment. [Figure 6B] FIG. 6B is a view for illustrating a step of forming a source electrode, a drain electrode, and a gate electrode in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6C] FIG. 6C is a view for illustrating a step of forming an opening in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6D] FIG. 6D is a view for illustrating a step of forming an intermediate layer in the opening in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6E] FIG. 6E is a view for illustrating a step of forming a metal layer on the intermediate layer in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6F] FIG. 6F is a view for illustrating a step of forming a through via that penetrates the Si substrate and the intermediate layer in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6G] FIG. 6G is a view for illustrating a step of forming a conductor in a through via in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 6H] FIG. 6H is a view for illustrating a step of forming a back electrode on a Si substrate in the method for manufacturing a semiconductor device according to the modification of the first embodiment. [Figure 7] FIG. 7 is a plan view of a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the line VIII-VIII in FIG. [Figure 9A]FIG. 9A is a diagram for illustrating a step of forming a SiC layer on a Si substrate in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9B] FIG. 9B is a view for illustrating a step of forming an opening in the SiC layer in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9C] FIG. 9C is a view for illustrating a step of forming an intermediate layer and a nitride semiconductor layer in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9D] FIG. 9D is a view for illustrating a step of forming a source electrode, a drain electrode, and a gate electrode in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9E] FIG. 9E is a view for illustrating a step of forming a metal layer on the intermediate layer in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9F] FIG. 9F is a view for illustrating a step of forming a through via that penetrates the Si substrate and the intermediate layer in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9G] FIG. 9G is a view for illustrating a step of forming a conductor in a through via in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 9H] FIG. 9H is a view for illustrating a step of forming a back electrode on a Si substrate in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a nitride semiconductor device disclosed in Patent Document 1. [Figure 11] FIG. 11 is a cross-sectional view of a nitride semiconductor device disclosed in Patent Document 2. [Figure 12] FIG. 12 is a cross-sectional view of a nitride semiconductor device of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, the arrangement and connection of the components, as well as the steps (processes) and the order of the steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept of the present disclosure will be described as optional components.

[0024] In addition, each drawing is a schematic diagram and is not necessarily a precise illustration. In each drawing, the same reference numerals are used for substantially the same configurations, and duplicated explanations are omitted or simplified.

[0025] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of an element, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

[0026] Furthermore, in this specification, the terms "above", "upper", "below", and "lower" in the configuration of a semiconductor device do not refer to the upper direction (vertically upward) and the lower direction (vertically downward) in an absolute spatial sense, but are terms defined by a relative positional relationship based on the stacking order in a stacked structure.

[0027] In this specification and the drawings, the X-axis, Y-axis, and Z-axis indicate the three axes of a three-dimensional orthogonal coordinate system. Specifically, in this specification, the two axes parallel to the main surface of the substrate of the semiconductor device are defined as the X-axis and Y-axis, and the direction perpendicular to this main surface is defined as the Z-axis direction. More specifically, the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order, that is, the so-called gate length direction, is defined as the X-axis direction. In this specification, unless otherwise specified, the term "planar view" refers to the main surface (upper surface) of the substrate of the semiconductor device as viewed from the Z-axis direction.

[0028] In this specification, a group III nitride semiconductor is a semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, when a group III nitride semiconductor is written as AlInGaN, it means that the group III nitride semiconductor contains any of Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN.

[0029] Furthermore, a layer made of a Group III nitride semiconductor and a layer configured of a Group III nitride semiconductor mean that the layer contains substantially only a Group III nitride semiconductor, although the layer may contain other elements as impurities at a rate of 1 at % or less, such as elements that are unavoidable in the manufacturing process.

[0030] (Embodiment 1) First, a semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view of the semiconductor device 1 according to the first embodiment. Fig. 2 is a cross-sectional view of the semiconductor device 1 according to the first embodiment taken along line II-II in Fig. 1. Note that Fig. 1 is hatched for the sake of convenience in order to make the positions of a source electrode 201, a drain electrode 202, and a gate electrode 203 easier to understand.

[0031] The semiconductor device 1 is a nitride semiconductor device formed using a group III nitride semiconductor. In this embodiment, a case will be described in which the semiconductor device 1 is a high electron mobility transistor (HEMT).

[0032] As shown in Figures 1 and 2, the semiconductor device 1 includes a Si substrate (silicon substrate) 101, a SiC layer (silicon carbide layer) 102, a nitride semiconductor layer 103, an intermediate layer 105, a metal layer 106, a source electrode 201, a drain electrode 202, a gate electrode 203, a metal diffusion prevention film 302, a conductor 303, and a back surface electrode 304.

[0033] The Si substrate 101 is, for example, a substrate made of Si with a (111) principal surface. The resistivity of the Si substrate 101 is, for example, 1 kΩ or more and 20 Ω or less, but is not limited thereto. The type of dopant in the Si substrate 101 may be P-type or N-type. The Si substrate 101 may have a combination of resistivities and dopants.

[0034] In the present embodiment, the Si substrate 101 is a substrate made of Si, but is not limited thereto. For example, the Si substrate 101 may be a substrate in which silicon is formed on a substrate made of a sapphire substrate, a GaN substrate, or an AlN substrate.

[0035] The SiC layer 102 is provided above the Si substrate 101. In this embodiment, the SiC layer 102 is provided on a first main surface (front surface) of the Si substrate 101. The SiC layer 102 is, for example, an epitaxial layer made of 3C-SiC. In "3C-SiC", "C" indicates a cubic crystal, and the number "3" indicates the number of regular tetrahedral structure layers included in one period in the stacking direction. The thickness of the SiC layer 102 is, for example, 5 nm or more and 5000 nm or less, but is not limited thereto. In this embodiment, the thickness of the SiC layer 102 is 2000 nm (2 μm).

[0036] The nitride semiconductor layer 103 is provided above the SiC layer 102. In this embodiment, the nitride semiconductor layer 103 is provided directly on the SiC layer 102. The nitride semiconductor layer 103 is a semiconductor layer made of a group III nitride semiconductor. Specifically, the nitride semiconductor layer 103 is a stack of a plurality of semiconductor layers, each of which is made of a group III nitride semiconductor. The nitride semiconductor layer 103 includes an active layer made of a group III nitride semiconductor. The nitride semiconductor layer 103 also includes a two-dimensional electron gas layer that serves as a carrier of the transistor within the layer. The two-dimensional electron gas is generated at the heterointerface of the active layer. The carrier of the transistor may be formed by ion implantation or doping under epitaxial layer formation conditions.

[0037] The thickness of the nitride semiconductor layer 103 is, for example, not limited to, 100 nm or more and 15000 nm or less In the present embodiment, the thickness of the nitride semiconductor layer 103 is 5000 nm (5 μm).

[0038] A source electrode 201 and a drain electrode 202 are provided above the nitride semiconductor layer 103. In this embodiment, the source electrode 201 and the drain electrode 202 are provided at an interval on the surface of the nitride semiconductor layer 103. The source electrode 201 and the drain electrode 202 face each other in the X-axis direction. The source electrode 201 is provided on a source region 201S in the nitride semiconductor layer 103.

[0039] The source electrode 201 and the drain electrode 202 are metal layers made of a metal material. Specifically, the source electrode 201 and the drain electrode 202 are made of a metal element or a metal alloy containing at least one metal selected from the group consisting of Ti, Al, Ni, Au, Ta, W, Pd, and Cu. In this embodiment, the source electrode 201 and the drain electrode 202 are a laminate in which a Ti layer and an Al layer are laminated in this order. Note that the source electrode 201 and the drain electrode 202 may be a single metal layer instead of a laminate of metal layers.

[0040] Furthermore, each of the source electrode 201 and the drain electrode 202 is electrically connected to the two-dimensional electron gas layer. Specifically, the source electrode 201 and the drain electrode 202 are ohmic-connected to the two-dimensional electron gas layer.

[0041] The gate electrode 203 is provided above the nitride semiconductor layer 103. In this embodiment, the gate electrode 203 is provided on the surface of the nitride semiconductor layer 103, similar to the source electrode 201 and the drain electrode 202. That is, the gate electrode 203 is in contact with the nitride semiconductor layer 103. The gate electrode 203 is provided between the source electrode 201 and the drain electrode 202.

[0042] The gate electrode 203 is made of a metal or a metal alloy containing at least one selected from metals such as Ti, TiN, Ta, TaN, W, Ni, Pd, Au, Al, and Cu. In this embodiment, the gate electrode 203 is a laminate in which a Ni layer and an Au layer are laminated in this order. Note that the gate electrode 203 may be a single layer of a metal layer instead of a laminate of metal layers.

[0043] The gate electrode 203 has a function of controlling a current flowing between the source electrode 201 and the drain electrode 202 (between the source and drain) with respect to carriers formed in the nitride semiconductor layer 103 by a voltage or a current applied to the gate electrode 203. The gate electrode 203 may be configured so that the semiconductor device 1 is of a Schottky junction type, or may be configured so that the semiconductor device 1 is of a normally-on structure with a so-called MIS (Metal-Insulator-Semiconductor) structure in which an insulating layer is provided between the gate electrode 203 and the nitride semiconductor layer 103. The semiconductor device 1 may have a normally-off structure in which a P-type nitride semiconductor layer or the like is provided between the gate electrode 203 and the nitride semiconductor layer 103.

[0044] An opening 104 is provided in the SiC layer 102. The opening 104 opens at least the SiC layer 102. In the present embodiment, the opening 104 opens the SiC layer 102 and the nitride semiconductor layer 103. That is, the opening 104 penetrates the SiC layer 102 and the nitride semiconductor layer 103, and exposes a part of the surface of the Si substrate 101.

[0045] The opening 104 is provided in a part of the source region 201S in which the source electrode 201 is formed. The distance between the opening 104 and the end of the source electrode 201 on the gate electrode 203 side is preferably 500 nm or more. This makes it possible to suppress a decrease in the crystallinity of the nitride semiconductor layer 103 between the gate electrode 203 and the source electrode 201.

[0046] In the present embodiment, the opening 104 is provided in a part of the source region 201S, but is not limited thereto. For example, the opening 104 may be provided in a region where the drain electrode 202 or the gate electrode 203 is formed, or may be provided outside the active region where the transistor is formed.

[0047] In addition, the side surface of the SiC layer 102 and the side surface of the nitride semiconductor layer 103 in the opening 104 are flush with each other, but this is not limited thereto. For example, in the opening 104, the side surface of the nitride semiconductor layer 103 may be recessed from the side surface of the SiC layer 102 toward the opposite side to the opening 104 side, or may protrude toward the inside of the opening 104 beyond the side surface of the SiC layer 102. In addition, the opening width of the opening 104 may be constant in the Z-axis direction, or may vary in the Z-axis direction. In this case, the opening width of the opening 104 may be continuously or discontinuously smaller from the upper surface to the lower surface of the opening 104.

[0048] An intermediate layer 105 is provided in the opening 104. The intermediate layer 105 is provided between the Si substrate 101 exposed by the opening 104 and the metal layer 106. Specifically, the intermediate layer 105 is provided between the upper surface of the Si substrate 101 and the lower surface of the metal layer 106 in the opening 104, and between the side surface of the SiC layer 102 (the inner side surface of the opening 104) and the side surface of the conductor 303 in the opening 104. In this embodiment, the intermediate layer 105 is also provided between the side surface of the nitride semiconductor layer 103 and the metal layer 106 in the opening 104. The upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are substantially flush with each other, but this is not limited thereto.

[0049] In top view, the intermediate layer 105 (opening 104) is provided so as to surround the through via 301. That is, the intermediate layer 105 (opening 104) is provided so as to surround the conductor 303 and the metal diffusion prevention film 302 embedded in the through via 301. Therefore, the intermediate layer 105 (opening 104) is provided between the conductor 303 (through via 301) and the SiC layer 102. That is, the intermediate layer 105 is an intermediate layer interposed between the conductor 303 and the SiC layer 102.

[0050] The intermediate layer 105 is a metal nitride layer or a silicon oxide layer. The intermediate layer 105 functions as a buffer layer that alleviates defects caused by the difference in etching rate between SiC and Si when forming the through via 301 penetrating the Si substrate 101 and the SiC layer 102 by etching. For example, when the Si substrate 101 and the SiC layer 102 are etched by dry etching using a fluorine-based gas or a chlorine-based gas, the etching rate for the fluorine-based gas is Si>SiO2>>SiC>GaN, and the etching rate for the chlorine-based gas is Si=GaN>>SiC. For this reason, it is preferable to use a material that has an etching rate faster than that of SiC as the material that constitutes the intermediate layer 105. Specifically, it is preferable to use a material that has an etching rate faster than that of SiC and slower than that of Si as the material that constitutes the intermediate layer 105.

[0051] As an example, the material constituting the intermediate layer 105 is a metal nitride such as GaN, AlN, TiN, TaN, WN, InN, or SiN, or a silicon oxide such as SiO2 or BPSG (SiO2 containing boron (B) and phosphorus (P)). The intermediate layer 105 is a single layer or multiple layers of any one of these materials. In this embodiment, the intermediate layer 105 is a silicon nitride layer (SiN layer).

[0052] Depending on the etching conditions, the relationship between the etching rates of GaN, AlN, TiN, SiN, SiO2 and Si can be GaN=Si, AlN=Si, TiN>Si, SiN>Si, SiO2>Si (equal signs and inequality signs indicate the magnitude relationship of the etching rates). The Vickers hardness of these materials is 15 GPa for GaN, 9.8 to 10.4 GPa for AlN, 10.8 GPa for TiN, 14 GPa for SiN, and 9.7 GPa for SiO2. The Vickers hardness of Si is 9.8 to 10.6 GPa, and the Vickers hardness of SiC is 23 GPa. Therefore, it is preferable that the Vickers hardness of the intermediate layer 105 is equal to or greater than 9.8 GPa, which is the minimum Vickers hardness of the Si substrate 101, and is less than 23 GPa, which is the Vickers hardness of the SiC layer 102.

[0053] In the present embodiment, the intermediate layer 105 is in contact with both the Si substrate 101 and the metal layer 106, but this is not limiting. That is, the intermediate layer 105 and the Si substrate 101 may not be in contact with each other, and the intermediate layer 105 and the metal layer 106 may not be in contact with each other. For example, a layer made of a material other than metal nitride and silicon oxide may be interposed between the Si substrate 101 and the intermediate layer 105. Specifically, a layer made of a material having an etching rate equal to the etching rate of the Si substrate 101 or a material having an etching rate between the etching rate of the Si substrate 101 and the etching rate of the intermediate layer 105 may be interposed between the intermediate layer 105 and the metal layer 106. In addition, a layer made of a material having an etching rate equal to the etching rate of the intermediate layer 105 or a material having an etching rate between the etching rate of the intermediate layer 105 and the etching rate of the metal layer 106 may be interposed between the intermediate layer 105 and the metal layer 106.

[0054] The thickness of the intermediate layer 105 is, for example, 100 nm or more and 15000 nm or less. However, the thickness of the intermediate layer 105 is not limited to this. In the present embodiment, the thickness of the intermediate layer 105 is 500 nm.

[0055] The metal layer 106 is provided above the opening 104. The metal layer 106 also covers at least a part of the intermediate layer 105. In this embodiment, the metal layer 106 is provided so as to cover not only the intermediate layer 105 but also a part of the source electrode 201. The metal layer 106 located above the opening 104 also covers the conductor 303. Specifically, the metal layer 106 covers the top surface of the conductor 303, the bottom surface and side surface of the intermediate layer 105, and a part of the source electrode 201. The metal layer 106 covering the conductor 303 also covers the through via 301. In this embodiment, the metal layer 106 covers the entire through via 301. Specifically, the metal layer 106 is provided so as to protrude from the opening of the through via 301.

[0056] The metal layer 106 functions as an etching stopper layer for stopping the etching of the through via 301 provided in the Si substrate 101. The metal layer 106 is made of, for example, a metal element or a metal alloy containing at least one selected from Cu, Au, Pt, Ni, and Mo. The metal layer 106 may also be made of a metal element or a metal alloy made of a high melting point metal such as W, Ti, or Ta. This can prevent the metal layer 106 from being mixed with the conductor 303. The metal layer 106 may also be made of a metal nitride made of W, Ti, or Ta. In this embodiment, the metal layer 106 is a titanium nitride layer (TiN layer) having a thickness of 300 nm. The metal layer 106 may be either a single layer or a multi-layer.

[0057] The metal layer 106 is electrically connected to the source electrode 201. The metal layer 106 and the source electrode 201 may be electrically connected by direct contact, or may be electrically connected via a conductor such as a wiring layer (not shown). The metal layer 106 may be electrically connected to the drain electrode 202 or the gate electrode 203 instead of the source electrode 201.

[0058] The semiconductor device 1 is provided with a through via 301 that penetrates the intermediate layer 105 and the Si substrate 101. In this embodiment, the through via 301 is provided in the source region 201S. The through via 301 is located inside the opening 104 in a plan view. The through via 301 is a through hole that penetrates the intermediate layer 105 and the Si substrate 101 so as to expose the metal layer 106. Therefore, the upper surface of the through via 301 is the lower surface of the metal layer 106. In this case, the width of the bottom surface of the metal layer 106 is longer than the opening width at the top surface of the through via 301.

[0059] In addition, in a plan view, the through via 301 is surrounded by the intermediate layer 105. In this embodiment, the opening shape of the through via 301 is circular. In this embodiment, the inner diameter (opening width) of the through via 301 monotonically decreases from the lower surface to the upper surface of the through via 301. That is, the opening area of ​​the through via 301 continuously decreases from the lower surface to the upper surface of the through via 301. In this way, the side surface of the through via 301 has a forward tapered shape from the lower surface to the upper surface of the through via 301, so that when the metal diffusion prevention film 302 and the conductor 303 are formed from the back surface of the Si substrate 101, it is possible to prevent voids or cracks from occurring in the metal diffusion prevention film 302 and formation defects from occurring in the conductor 303. That is, a highly reliable through via 301 can be formed in the semiconductor device 1. The inner diameter of the through via 301 may also decrease discontinuously from the lower surface to the upper surface of the through via 301. In addition, in this embodiment, the side surface of the Si substrate 101 and the side surface of the intermediate layer 105 of the through via 301 are flush with each other, but the side surface of the Si substrate 101 and the side surface of the intermediate layer 105 may be discontinuous.

[0060] A metal diffusion prevention film 302 is provided so as to cover the side surface of the through via 301. The metal diffusion prevention film 302 is a thin film layer provided so as to prevent the Si substrate 101 and the conductor 303 from contacting each other and causing metals to diffuse between them. The metal diffusion prevention film 302 is preferably an insulating film made of an insulating material, but may also be a conductive film made of a conductive material. The metal diffusion prevention film 302 is a single layer or multiple layers made of any one material selected from Ti, Ta, TiN, TaN, WN, SiO2, and SiN. In this embodiment, the metal diffusion prevention film 302 is a laminate in which a Ti layer and a TiN layer are laminated in this order. Note that when the metal diffusion prevention film 302 is made of a conductive material, it may cover not only the side surface of the through via 301 but also the top surface of the through via 301.

[0061] A conductor 303 made of a conductive material is provided inside the through via 301. Specifically, the conductor 303 is provided inside the through via 301 whose inner surface is covered with a metal diffusion prevention film 302. The conductor 303 is a buried via formed so as to fill the through via 301.

[0062] In this embodiment, the conductor 303 is a metal layer made of a metal material. The conductor 303 is a single layer or multiple layers of any one selected from Ti, Ta, Cu, Al, Au, Ni, and W. In this embodiment, the conductor 303 is a laminate in which a Ti layer and a Cu layer are laminated in order, or a laminate in which a Ti layer, a TiN layer, a Ti layer, and a Cu layer are laminated in order. The conductor 303 may be filled in the through via 301 so as to completely fill the entire inside of the through via 301, or may be filled in the through via 301 so as to leave a partial cavity.

[0063] The conductor 303 is electrically connected to the rear surface electrode 304 and the metal layer 106. The rear surface electrode 304 and the metal layer 106 are electrically connected via the conductor 303. In the present embodiment, the metal layer 106 and the source electrode 201 are connected, and therefore the source electrode 201 and the rear surface electrode 304 are electrically connected via the metal layer 106 and the conductor 303.

[0064] The back surface electrode 304 is provided below the Si substrate 101. In this embodiment, the back surface electrode 304 is provided on a second main surface (back surface) of the Si substrate 101 opposite to the first main surface (front surface).

[0065] The back surface electrode 304 is an electrode having a solid pattern (a planar (i.e. solid) pattern that is uniformly continuous substantially without gaps) covering the back surface of the Si substrate 101. In this embodiment, the back surface electrode 304 covers the entire back surface of the Si substrate 101.

[0066] The back electrode 304 is made of a metal or a metal alloy containing at least one metal selected from the group consisting of Ti, Al, W, Ta, Cu, Ni, Au, Sn, and Ag. The back electrode 304 may have a single-layer structure or may be a laminate in which a plurality of metal layers are laminated. In this embodiment, the back electrode 304 is a laminate in which a Ti layer, a Ni layer, and a Au layer are laminated in this order. The back electrode 304 and the conductor 303 may be made of the same material.

[0067] The back electrode 304 is electrically grounded. That is, the potential of the back electrode 304 is the ground potential. As described above, the back electrode 304 is electrically connected to the source electrode 201 via the conductor 303 and the metal layer 106. That is, the back electrode 304 and the source electrode 201 are at the same potential. Note that the back electrode 304 may be electrically connected to the drain electrode 202 or the gate electrode 203 instead of being electrically connected to the source electrode 201.

[0068] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to Figures 3A to 3H. Figures 3A to 3H are diagrams for explaining each step of the method for manufacturing the semiconductor device 1 according to the first embodiment.

[0069] First, as shown in FIG. 3A, a SiC layer 102 is formed above a Si substrate 101. Specifically, the SiC layer 102 is formed by epitaxially growing 3C-SiC having a (111) surface and a thickness of 2 μm on the surface of the Si substrate 101. Thereafter, a nitride semiconductor layer 103 made of a group III nitride semiconductor is formed above the SiC layer 102. Specifically, a stack of a plurality of semiconductor layers made of group III nitride semiconductors is epitaxially grown to form the nitride semiconductor layer 103 having a thickness of 5 μm on the surface of the SiC layer 102. Note that a two-dimensional electron gas layer serving as a carrier of a transistor is formed within the nitride semiconductor layer 103.

[0070] Next, as shown in FIG. 3B, an opening 104 is formed to open the SiC layer 102. In this embodiment, the opening 104 opens the SiC layer 102 and the nitride semiconductor layer 103. Specifically, first, a resist (not shown) is applied onto the surface of the nitride semiconductor layer 103, and then the resist is patterned by photolithography and etching to form a resist mask in areas other than the area where the opening 104 is to be formed. Then, the nitride semiconductor layer 103 and the SiC layer 102 are etched and removed by dry etching using the resist mask as a mask, thereby forming the opening 104 penetrating the nitride semiconductor layer 103 and the SiC layer 102 to expose the Si substrate 101. Then, the attached polymer and the resist mask are removed by dry etching.

[0071] Next, as shown in Fig. 3C, intermediate layer 105 is formed in opening 104. Specifically, a silicon nitride layer having a thickness of 500 nm is deposited on nitride semiconductor layer 103 by a CVD (Chemical Vapor Deposition) method so as to cover opening 104, and then the silicon nitride layer other than that in opening 104 is removed by a photolithography method and a dry etching method, thereby leaving only the silicon nitride layer inside opening 104. In this way, intermediate layer 105 made of a silicon nitride layer can be formed so as to cover the inner surface of opening 104.

[0072] 3D, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, a Ti layer and an Al layer patterned with a photoresist are sequentially stacked on the surface of the nitride semiconductor layer 103 by a deposition method, patterned by lift-off, and then alloyed by heat treatment to form the source electrode 201 and the drain electrode 202 that are ohmic-connected to the two-dimensional electron gas in the nitride semiconductor layer 103. At this time, the source electrode 201 is not formed in the region of the source electrode 201 where the through via 301 is formed and around it.

[0073] Thereafter, a Ni layer and an Au layer patterned with a photoresist are sequentially laminated by a deposition method, and patterned by lift-off, followed by forming a gate electrode 203 that makes a Schottky junction with the two-dimensional electron gas in the nitride semiconductor layer 103. In this embodiment, the gate electrode 203 is formed between the source electrode 201 and the drain electrode 202.

[0074] 3E, metal layer 106 is formed above opening 104 so as to cover intermediate layer 105. Specifically, a TiN layer having a thickness of 200 nm is deposited by sputtering, and then lithography and dry etching are used to remove the TiN layer other than source region 201S and a part of the TiN layer on source electrode 201, thereby forming metal layer 106 so as to cover intermediate layer 105 and another part on source electrode 201.

[0075] 3F, a through via 301 is formed penetrating the Si substrate 101 and the intermediate layer 105 from the lower surface side (rear surface side) of the Si substrate 101 using the metal layer 106 as a stopper. Specifically, the through via 301 is formed by removing the Si substrate 101 and the intermediate layer 105 from the lower surface side of the Si substrate 101 using photolithography and etching methods so as to penetrate the Si substrate 101 and the intermediate layer 105. As the etching method, dry etching using a fluorine-based gas or a chlorine-based gas can be used.

[0076] At this time, in this embodiment, since the intermediate layer 105 exists between the SiC layer 102, which is a hard and difficult-to-etch material, and the through via 301, the SiC layer 102 and the through via 301 do not overlap. In other words, the intermediate layer 105 is provided so as to surround the periphery of the through via 301, and when the through via 301 is formed by dry etching, the SiC layer 102 is not etched, and only the Si substrate 101 and the intermediate layer 105 are etched. Therefore, it is possible to suppress the occurrence of notching in the Si substrate 101 when the through via 301 is formed. As a result, the through via 301 that penetrates the Si substrate 101 and the SiC layer 102 can be easily formed.

[0077] The through via 301 may be formed using a Bosch process or a non-Bosch process. The through via 301 may be formed under a plurality of etching conditions, or the intermediate layer 105 may be selectively etched with respect to the Si substrate 101. In this case, the Si substrate 101 may be selectively etched using a fluorine-based gas, and when the intermediate layer 105 is a metal nitride layer, the intermediate layer 105 may be selectively etched using a chlorine-based gas. In this case, the etching conditions may be switched in the middle of the Si substrate 101. The roughness of the side surface of the through via 301 is preferably 300 nm or less.

[0078] Next, as shown in FIG. 3G, a conductor 303 is formed inside the through via 301. In this embodiment, a Ti layer, a TiN layer, a Ti layer, and a Cu layer are deposited in this order by a sputtering method, and then the inside of the through via 301 is filled with a Cu layer by a plating method. Thereafter, the Ti layer, the TiN layer, the Ti layer, and the Cu layer deposited on the back surface of the Si substrate 101 are removed by CMP (Chemical Mechanical Polishing). This allows the conductor 303 consisting of the Ti layer, the TiN layer, the Ti layer, and the Cu layer to be formed only inside the through via 301.

[0079] 3H, a back electrode 304 is formed below the Si substrate 101. Specifically, a Ti layer, a Ni layer, and a Au layer are sequentially deposited on the back surface of the Si substrate 101 by a vapor deposition method, thereby forming the back electrode 304, which is a laminate of the Ti layer, the Ni layer, and the Au layer, on the back surface of the Si substrate 101. As a result, the back electrode 304 and the metal layer 106 are electrically connected via the conductor 303.

[0080] Through a series of steps in this manner, the semiconductor device 1 having the structure shown in FIGS. 1 and 2 can be completed.

[0081] As described above, according to the semiconductor device 1 of the present embodiment, the intermediate layer 105, which is a metal nitride layer or a silicon oxide layer, is provided in the opening 104 that opens the SiC layer .

[0082] With this configuration, even when the through via 301 is formed by etching in a HEMT structure in which the SiC layer 102 made of a hard and difficult-to-etch material is provided between the Si substrate 101 and the nitride semiconductor layer 103, the through via 301 can be formed without simultaneously etching the Si substrate 101 and the SiC layer 102. That is, the intermediate layer 105, which has a faster etching rate than the SiC layer 102 (that is, is harder than the SiC layer 102), is embedded in the SiC layer 102 in advance, and the intermediate layer 105 and the Si substrate 101 are etched simultaneously to form the through via 301. This makes it possible to prevent side etching of the Si substrate 101 due to the difference in etching rate between SiC and Si, as in the nitride semiconductor device 1Z shown in FIG. 12 above. That is, it is possible to prevent notching from occurring.

[0083] In this way, according to the semiconductor device 1 of the present embodiment, the through via 301 penetrating the Si substrate 101 and the SiC layer 102 can be easily provided without notching. Therefore, it is possible to suppress the generation of voids in the conductor 303 inside the through via 301 due to notching, or the occurrence of contact between the conductor 303 and the Si substrate 101 due to a decrease in coverage of the metal diffusion prevention film 302 caused by the presence of notching, which leads to interdiffusion of metals and high resistance. As a result, a highly reliable semiconductor device 1 can be obtained.

[0084] In the semiconductor device 1 according to the present embodiment, the source electrode 201 is electrically connected to the grounded back electrode 304 via the metal layer 106 present in the source region 201S and the conductor 303. This allows the source electrode 201 to be more strongly grounded.

[0085] In the semiconductor device 1 according to the present embodiment, the Vickers hardness of the intermediate layer 105 is preferably equal to or greater than the Vickers hardness of the Si substrate 101, that is, 9.8 GPa, and less than the Vickers hardness of the SiC layer 102, that is, 23 GPa.

[0086] In this way, by setting the hardness of the intermediate layer 105 to a value between the hardness of the Si substrate 101 and the hardness of the SiC layer 102, even in a structure in which the SiC layer 102 is provided between the Si substrate 101 and the nitride semiconductor layer 103, side etching of the Si substrate 101 due to the difference in etching rate between SiC and Si can be effectively suppressed, and the through via 301 can be easily formed. Note that, when a hard layer is provided on the Si substrate 101 regardless of the substrate type of the Si substrate 101, the through via 301 can be easily formed by setting the Vickers hardness of the intermediate layer 105 to a value between the Vickers hardness of the substrate and the hard layer.

[0087] In the semiconductor device 1 of the present embodiment, the inner diameter of the through via 301 monotonically decreases from the lower surface to the upper surface of the through via 301.

[0088] With this configuration, the side surface of the through via 301 has a forward tapered shape from the lower surface to the upper surface of the through via 301, so that the through via 301 having high reliability can be formed.

[0089] In addition, in the semiconductor device 1 of the present embodiment, the upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are substantially flush with each other.

[0090] This configuration can reduce the unevenness of the surface at the wafer level, which is called a global step.

[0091] In the semiconductor device 1 according to the present embodiment, the metal layer 106 includes at least one selected from the group consisting of Cu, Au, Pt, Ni, and Mo. Alternatively, the metal layer 106 may include at least one selected from the group consisting of high-melting-point metals W, Ti, and Ta.

[0092] This configuration makes it possible to suppress the occurrence of mixed crystals between the metal layer 106 and the conductor 303 .

[0093] In the semiconductor device 1 of the present embodiment, the metal layer 106 and the source electrode 201 are electrically connected to each other.

[0094] With this configuration, the conductor 303 in the through via 301 and the source electrode 201 are electrically connected via the metal layer 106. In other words, a source via can be realized.

[0095] In the semiconductor device 1 of the present embodiment, the source electrode 201 is provided on the source region 201S in the nitride semiconductor layer 103, and the through via 301 is provided in the source region 201S.

[0096] This configuration allows the grounding of the source electrode 201 to be strengthened.

[0097] In addition, in the semiconductor device 1 of the present embodiment, the width of the bottom surface of the metal layer 106 is longer than the opening width of the through via 301 at the top surface.

[0098] This configuration makes it possible to prevent the through via 301 from protruding from the metal layer 106 and etching into portions that do not need to be etched when the through via 301 is formed by etching. In other words, it is possible to prevent the through via 301 from stepping off the metal layer 106.

[0099] (Modification of the first embodiment) Next, a modified example of the first embodiment will be described. First, the configuration of a semiconductor device 1A according to a modified example of the first embodiment will be described with reference to Figs. 4 and 5. Fig. 4 is a plan view of the semiconductor device 1A according to a modified example of the first embodiment. Fig. 5 is a cross-sectional view of the semiconductor device 1A according to a modified example of the first embodiment taken along line VV in Fig. 4. Note that, in Fig. 4, hatching is applied for convenience in order to make the positions of the source electrode 201, the drain electrode 202, and the gate electrode 203 easier to understand, as in Fig. 1.

[0100] A semiconductor device 1A according to this modification and the semiconductor device 1 according to the first embodiment are different in the configurations of the opening 104 and the intermediate layer 105.

[0101] Specifically, in the first embodiment, the opening 104 is provided so as to expose the SiC layer 102 and the nitride semiconductor layer 103, but in this modification, the opening 104 is provided so as to expose not only the SiC layer 102 and the nitride semiconductor layer 103 but also the source electrode 201. Therefore, in this modification, the side surface of the SiC layer 102, the side surface of the nitride semiconductor layer 103, and the side surface of the source electrode 201 are flush with each other. Note that in this modification as well, the opening 104 is provided so as to expose the Si substrate 101.

[0102] In addition, in the first embodiment, intermediate layer 105 is provided so as to cover only opening 104 out of opening 104 and source electrode 201, but in this modification, intermediate layer 105 is provided so as to cover both opening 104 and source electrode 201. Specifically, intermediate layer 105 in this modification is provided so as to cover the bottom and side surfaces of opening 104 and a part of source electrode 201.

[0103] In this modification, too, the metal layer 106 located above the opening 104 covers the conductor 303, the intermediate layer 105, and a part of the source electrode 201. In this case, the metal layer 106 also covers the upper part of the intermediate layer 105 that covers the upper part of the source electrode 201.

[0104] Next, a method for manufacturing the semiconductor device 1A according to the modification of the first embodiment will be described with reference to Figures 6A to 6H. Figures 6A to 6H are diagrams for explaining each step of the method for manufacturing the semiconductor device 1A according to the modification of the first embodiment.

[0105] First, as shown in Fig. 6A, a SiC layer 102 is formed above a Si substrate 101, and a nitride semiconductor layer 103 is formed above the SiC layer 102. This step is similar to the step shown in Fig. 3A in the first embodiment.

[0106] 6B, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, first, a Ti layer and an Al layer patterned with a photoresist are sequentially laminated on the surface of the nitride semiconductor layer 103 by a deposition method, patterned by lift-off, and then alloyed by heat treatment to form the source electrode 201 and the drain electrode 202 that are in ohmic contact with the two-dimensional electron gas in the nitride semiconductor layer 103.

[0107] Thereafter, a Ni layer and an Au layer patterned with a photoresist are sequentially laminated by a vapor deposition method, and patterned by lift-off to form a gate electrode 203 that makes a Schottky junction with the two-dimensional electron gas in the nitride semiconductor layer 103. In this modification, the gate electrode 203 is also formed between the source electrode 201 and the drain electrode 202.

[0108] 6C, an opening 104 is formed to expose the SiC layer 102 and the nitride semiconductor layer 103. In this modification, the opening 104 also exposes the source electrode 201 when opening the SiC layer 102 and the nitride semiconductor layer 103. Specifically, the source electrode 201, the nitride semiconductor layer 103, and the SiC layer 102 are etched away using lithography and dry etching to form the opening 104 penetrating the SiC layer 102, the nitride semiconductor layer 103, and the source electrode 201, thereby exposing the Si substrate 101.

[0109] In this manner, in this modification, since the source electrode 201, the nitride semiconductor layer 103, and the SiC layer 102 are removed at the same time, the width of the opening 104 can be easily increased compared to the case where each is removed in a separate process. Therefore, the width of the bottom surface of the metal layer 106 can be easily increased, and the margin for the through via 301 to step over the metal layer 106 can be increased.

[0110] Next, as shown in Fig. 6D, intermediate layer 105 is formed in opening 104. Specifically, a silicon nitride layer having a thickness of 500 nm is deposited by CVD on nitride semiconductor layer 103 so as to cover opening 104, and then photolithography and dry etching are used to remove the silicon nitride layer other than in opening 104 and other than a portion on source electrode 201, thereby leaving only the silicon nitride layer inside opening 104. This allows intermediate layer 105 made of a silicon nitride layer to be formed so as to cover the inner surface of opening 104 and a portion on source electrode 201.

[0111] By forming intermediate layer 105 in this manner, it is possible to suppress the occurrence of a step at the boundary between the surface of nitride semiconductor layer 103 and the surface of intermediate layer 105, as compared to the above-described first embodiment. This makes it possible to suppress the occurrence of voids between nitride semiconductor layer 103 and intermediate layer 105 due to the step.

[0112] Thereafter, as shown in FIG. 6E, a metal layer 106 is formed above the opening 104 so as to cover the intermediate layer 105. Next, as shown in FIG. 6F, a through via 301 is formed penetrating the Si substrate 101 and the intermediate layer 105 from the lower surface side (rear surface side) of the Si substrate 101 using the metal layer 106 as a stopper. Next, as shown in FIG. 6G, a conductor 303 is formed inside the through via 301. Next, as shown in FIG. 6H, a rear surface electrode 304 is formed below the Si substrate 101. Note that the steps shown in FIGS. 6E to 6H can be performed in the same manner as the steps shown in FIGS. 3E to 3H in the first embodiment.

[0113] Through this series of steps, the semiconductor device 1A having the structure shown in FIGS. 4 and 5 can be completed.

[0114] As described above, the semiconductor device 1A according to this modification has the same effects as the semiconductor device 1 according to the first embodiment. For example, in the semiconductor device 1A according to this modification, the intermediate layer 105, which is a metal nitride layer or a silicon oxide layer, is provided in the opening 104 that opens the SiC layer 102. This makes it possible to easily provide the through via 301 that penetrates the Si substrate 101 and the SiC layer 102 without causing notching.

[0115] (Embodiment 2) Next, the semiconductor device 2 according to the second embodiment will be described. First, the configuration of the semiconductor device 2 according to the second embodiment will be described with reference to Figs. 7 and 8. Fig. 7 is a plan view of the semiconductor device 2 according to the second embodiment. Fig. 8 is a cross-sectional view of the semiconductor device 2 according to the second embodiment taken along line VIII-VIII in Fig. 7. Note that, in Fig. 8, similar to Fig. 1, hatching is applied for convenience in order to make the positions of the source electrode 201, the drain electrode 202, and the gate electrode 203 easier to understand.

[0116] The semiconductor device 2 according to the present embodiment and the semiconductor device 1 according to the first embodiment are different in the configurations of the opening 104 and the intermediate layer 105.

[0117] Specifically, in the above-mentioned first embodiment, the opening 104 is provided so as to expose the SiC layer 102 and the nitride semiconductor layer 103, but in the present embodiment, the opening 104 does not expose the nitride semiconductor layer 103, but exposes only the SiC layer 102. Note that, also in the present embodiment, the opening 104 is provided so as to expose the Si substrate 101.

[0118] In the first embodiment, the intermediate layer 105 is formed along the inner surface of the opening 104, but in the present embodiment, the intermediate layer 105 is formed so as to fill the opening 104. Therefore, the upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are flush with each other. In the present embodiment, the intermediate layer 105 is made of a group III nitride semiconductor. That is, in the present embodiment, the intermediate layer 105 and the nitride semiconductor layer 103 are both made of a group III nitride semiconductor. Specifically, the intermediate layer 105 has the same structure as the nitride semiconductor layer 103, and is a laminate of a plurality of semiconductor layers made of group III nitride semiconductors. This allows the intermediate layer 105 and the nitride semiconductor layer 103 to be formed simultaneously in the same process. The two-dimensional electron gas in the nitride semiconductor layer 103 may be inactivated by doping the nitride semiconductor layer 103 with fluorine (F) or boron fluoride (BF2).

[0119] Furthermore, by providing intermediate layer 105 so as to fill opening 104, the global step can be reduced compared to opening 104 in embodiment 1. That is, a wiring layer can be easily formed on source region 201S.

[0120] In this embodiment as well, the metal layer 106 is located above the opening 104 , and covers the conductor 303 , the intermediate layer 105 and a part of the source electrode 201 .

[0121] Next, a method for manufacturing the semiconductor device 2 according to the second embodiment will be described with reference to Figures 9A to 9H. Figures 9A to 9H are diagrams for explaining each step of the method for manufacturing the semiconductor device 2 according to the second embodiment.

[0122] 9A, a SiC layer 102 is formed above a Si substrate 101. Specifically, the SiC layer 102 is formed on the surface of the Si substrate 101 by epitaxially growing 3C-SiC having a (111) surface and a thickness of 2 μm.

[0123] 9B, an opening 104 is formed to open the SiC layer 102. Specifically, the SiC layer 102 is etched away using lithography and dry etching to form the opening 104 penetrating the SiC layer 102 and expose the Si substrate 101.

[0124] Next, as shown in FIG. 9C, the intermediate layer 105 is formed in the opening 104, and the nitride semiconductor layer 103 is formed above the SiC layer 102. Specifically, a stack of a plurality of semiconductor layers made of Group III nitride semiconductors is epitaxially grown on the surface of the SiC layer 102 and on the surface of the Si substrate 101 exposed by the opening 104, to form a nitride semiconductor layer SC having a thickness of 5 μm. At this time, the nitride semiconductor layer SC formed so as to fill the opening 104 has lower crystallinity than the nitride semiconductor layer SC formed on the SiC layer 102. Therefore, the nitride semiconductor layer SC on the SiC layer 102 becomes the nitride semiconductor layer 103 made of a Group III nitride semiconductor having high crystallinity, and the nitride semiconductor layer SC in the opening 104 becomes the intermediate layer 105 made of a Group III nitride semiconductor having low crystallinity and many dislocations. That is, in this embodiment, the nitride semiconductor layer 103 and the intermediate layer 105 are both made of Group III nitride semiconductors, but have different crystallinity. In addition, a two-dimensional electron gas layer that serves as a carrier for a transistor is formed within the nitride semiconductor layer 103 .

[0125] 9D, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, a Ti layer and an Al layer patterned with a photoresist are sequentially laminated by a deposition method on the surface of the nitride semiconductor layer 103, patterned by lift-off, and then alloyed by heat treatment to form the source electrode 201 and the drain electrode 202 that are in ohmic contact with the two-dimensional electron gas in the nitride semiconductor layer 103.

[0126] Thereafter, a Ni layer and an Au layer patterned with a photoresist are sequentially laminated by a deposition method, and patterned by lift-off, and then a gate electrode 203 that forms a Schottky junction with the two-dimensional electron gas in the nitride semiconductor layer 103 is formed. In this embodiment as well, the gate electrode 203 is formed between the source electrode 201 and the drain electrode 202.

[0127] The source electrode 201 may be formed so as to straddle the upper part of the opening 104 in a plan view. In this way, a pit is formed at the boundary between the intermediate layer 105 and the nitride semiconductor layer 103, so that the contact resistance between the source electrode 201 and the two-dimensional electron gas layer can be reduced.

[0128] Thereafter, as shown in FIG. 9E, a metal layer 106 is formed above the opening 104 so as to cover the intermediate layer 105. Next, as shown in FIG. 9F, a through via 301 is formed penetrating the Si substrate 101 and the intermediate layer 105 from the lower surface side (rear surface side) of the Si substrate 101 using the metal layer 106 as a stopper. Next, as shown in FIG. 9G, a conductor 303 is formed inside the through via 301. Next, as shown in FIG. 9H, a rear surface electrode 304 is formed below the Si substrate 101. The steps shown in FIG. 9E to FIG. 9H can be performed in the same manner as the steps shown in FIG. 3E to FIG. 3H in the first embodiment.

[0129] Through this series of steps, the semiconductor device 2 having the structure shown in FIGS. 7 and 8 can be completed.

[0130] As described above, the semiconductor device 2 according to the present embodiment has the same effects as the semiconductor device 1 according to the above-mentioned embodiment 1. For example, also in the semiconductor device 2 according to the present embodiment, the intermediate layer 105, which is a metal nitride layer or a silicon oxide layer, is provided in the opening 104 that opens the SiC layer 102. This makes it possible to easily provide the through via 301 that penetrates the Si substrate 101 and the SiC layer 102 without causing notching.

[0131] In the semiconductor device 2 according to the present embodiment, the intermediate layer 105, like the nitride semiconductor layer 103, is made of a Group III nitride semiconductor.

[0132] This configuration makes it possible to simultaneously form the intermediate layer 105 and the nitride semiconductor layer 103. This makes it possible to manufacture the semiconductor device 2 having the intermediate layer 105 at low cost.

[0133] (Other variations) Although the semiconductor device according to the present disclosure has been described based on the first and second embodiments, the present disclosure is not limited to the first and second embodiments described above.

[0134] For example, the present disclosure also includes forms obtained by applying various modifications conceived by a person skilled in the art to the above-mentioned first and second embodiments, and forms realized by arbitrarily combining the components and functions of the first and second embodiments within the scope of the present disclosure. In addition, the present disclosure also includes any combination of two or more claims among the multiple claims described in the claims at the time of filing of the present application within the scope of technical compatibility. For example, when a dependent claim described in the claims at the time of filing of the present application is made into a multiple claim or multiple multiple claim so as to cite all of the higher claims within the scope of technical compatibility, the present disclosure also includes a combination of all claims included in the multiple claim or multiple multiple claim. [Industrial Applicability]

[0135] The semiconductor device according to the present disclosure is useful for communication devices and inverters that require high speed operation, as well as power switching elements used in power supply circuits and the like. [Explanation of symbols]

[0136] 1, 1A, 2 Semiconductor Device 1X, 1Y, 1Z Nitride Semiconductor Devices 101 Si substrate 101X Dielectric layer 102 SiC layer 103, SC nitride semiconductor layer 104 Opening 105 Middle Class 106 Metal layer 107X Dielectric Substrate 201 Source electrode 201S Source Area 202 Drain electrode 202D Drain region 203 Gate electrode 301 Through Via 302 Metal diffusion prevention film 303 Conductor 304 Back electrode 305 Metal layer 400 Notching

Claims

1. A Si substrate; a back electrode provided below the Si substrate; A SiC layer provided above the Si substrate; a semiconductor layer made of a Group III nitride semiconductor provided above the SiC layer; a source electrode and a drain electrode provided above the semiconductor layer; a gate electrode in contact with the semiconductor layer; an intermediate layer provided at an opening that opens at least the SiC layer; a metal layer disposed above the opening; a conductor provided inside a through via penetrating the intermediate layer and the Si substrate, the conductor being electrically connected to the back surface electrode and the metal layer; the metal layer covers the through via; the intermediate layer is provided between the SiC layer and the conductor; The intermediate layer is a metal nitride layer or a silicon oxide layer. Semiconductor device.

2. The intermediate layer has a Vickers hardness of 9.8 GPa or more and less than 23 GPa. The semiconductor device according to claim 1 .

3. A Si substrate; a back electrode provided below the Si substrate; A SiC layer provided above the Si substrate; a semiconductor layer made of a Group III nitride semiconductor provided above the SiC layer; a source electrode and a drain electrode provided above the semiconductor layer; a gate electrode in contact with the semiconductor layer; an intermediate layer provided at an opening that opens at least the SiC layer; a metal layer disposed above the opening; a conductor provided inside a through via penetrating the intermediate layer and the Si substrate, the conductor being electrically connected to the back surface electrode and the metal layer; the metal layer covers the through via; the intermediate layer is provided between the SiC layer and the conductor; The intermediate layer has a Vickers hardness of 9.8 GPa or more and less than 23 GPa. Semiconductor device.

4. The inner diameter of the through via monotonically decreases from the lower surface to the upper surface of the through via. The semiconductor device according to any one of claims 1 to 3.

5. The intermediate layer is composed of a Group III nitride semiconductor. The semiconductor device according to any one of claims 1 to 3.

6. The upper surface of the intermediate layer and the upper surface of the semiconductor layer are substantially flush with each other. The semiconductor device according to claim 5 .

7. The metal layer includes at least one selected from Cu, Au, Pt, Ni, and Mo. The semiconductor device according to any one of claims 1 to 3.

8. The metal layer includes at least one selected from W, Ti, and Ta. The semiconductor device according to any one of claims 1 to 3.

9. The metal layer and the source electrode are electrically connected. The semiconductor device according to any one of claims 1 to 3.

10. the source electrode is provided on a source region in the semiconductor layer, The through via is provided in the source region. The semiconductor device according to any one of claims 1 to 3.

11. The width of the bottom surface of the metal layer is greater than the opening width of the top surface of the through via. The semiconductor device according to any one of claims 1 to 3.

12. Further, a metal diffusion prevention film is provided to cover a side surface of the through via. The semiconductor device according to any one of claims 1 to 3.

13. forming a SiC layer above a Si substrate; forming a semiconductor layer made of a Group III nitride semiconductor above the SiC layer; forming an opening for opening the SiC layer; forming an intermediate layer in the opening; forming a source electrode, a drain electrode and a gate electrode above the semiconductor layer; forming a metal layer over the opening so as to cover at least a portion of the intermediate layer; forming a through via that penetrates the Si substrate and the intermediate layer from the lower surface side of the Si substrate using the metal layer as a stopper; forming a conductor inside the through via; forming a back electrode below the Si substrate; the back electrode and the metal layer are electrically connected via the conductor; the intermediate layer is provided between the SiC layer and the conductor; The intermediate layer is a metal nitride layer or a silicon oxide layer. A method for manufacturing a semiconductor device.

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