Semiconductor Device

Abstract

To provide a semiconductor device in which the heat radiation characteristic of a transistor can be improved.SOLUTION: On a surface layer part of a substrate formed of semiconductor, an adhesive layer including at least one metal region is disposed in a plan view. On the adhesive layer, a semiconductor element is disposed. The semiconductor element includes a first transistor disposed on a first metal region that is one metal region in the adhesive layer. The first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed thereon, and an emitter layer disposed thereon. On the emitter layer of the first transistor, a first emitter electrode is disposed. On the first emitter electrode, a first conductor projection is disposed. The heat conductivity of the semiconductor material of the surface layer part of the substrate is higher than the heat conductivity of any of the collector layer, the base layer, and the emitter layer of the first transistor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Heterojunction bipolar transistors (HBTs) are used in amplifier circuits for high-frequency signals. To increase the output of the amplifier circuits, it is desirable to improve the heat dissipation characteristics of the HBTs. Patent Document 1 below discloses an HBT with improved heat dissipation characteristics. The HBT disclosed in Patent Document 1 has a base layer and an emitter layer stacked on a collector layer, and a collector electrode is disposed below the collector layer. By joining the collector electrode to a heat dissipation substrate, heat generated in the HBT is conducted to the heat dissipation substrate and dissipated from the heat dissipation substrate to the outside. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-219682 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to further increase the output of an amplifier circuit, there is a demand for further improvement in the heat dissipation characteristics from transistors such as HBTs. An object of the present invention is to provide a semiconductor device capable of improving the heat dissipation characteristics from transistors. [Means for solving the problem]

[0005] According to one aspect of the present invention, A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; On the adhesive layer Device formation layer and It is equipped with The element formation layer is At least one semiconductor element; 、 an interlayer insulating film disposed on the adhesive layer so as to cover the semiconductor element; Including, the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; The element formation layer is a first emitter electrode disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; Including, moreover, a first conductor protrusion disposed on the first emitter electrode and electrically connected to the first emitter electrode, the first conductor protruding in a direction away from the substrate; Get up We are equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; The first metal region is Device formation layer It extends to the outside of moreover, The first metal region Device formation layer The present invention provides a semiconductor device having a collector conductor protrusion connected to a portion extending outwardly of the semiconductor device. Effect of the Invention

[0006] The heat generated in the first transistor is conducted through the first emitter electrode and the first conductor protrusion to the member connected to the first conductor protrusion. Furthermore, the heat generated in the first transistor is conducted to the substrate via the adhesive layer. In this way, the heat generated in the first transistor is conducted in two directions, thereby improving the heat dissipation characteristics from the first transistor. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along dashed line 2-2 of FIG. [Diagram 3] 3A to 3F are schematic cross-sectional views of a semiconductor device at intermediate stages in its manufacture. [Figure 4] 4A to 4C are schematic cross-sectional views of a semiconductor device during its manufacturing process, and FIG. 4D is a schematic cross-sectional view of the completed semiconductor device. [Diagram 5] FIG. 5A is a schematic plan view of a semiconductor device according to a first embodiment, and FIG. 5B is a schematic plan view of a semiconductor device according to a comparative example. [Figure 6] FIG. 6 is a schematic plan view of a semiconductor device according to a modification of the first embodiment. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along dashed line 8-8 in FIG. [Figure 9] FIG. 9 is a cross-sectional view of a semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 11] FIG. 11A is an equivalent circuit diagram showing an example of an electronic circuit using the semiconductor device according to the fourth embodiment, and FIG. 11B is a partial cross-sectional view of a semiconductor device for realizing the electronic circuit shown in FIG. 11A. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to the sixth embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to the seventh embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to the eighth embodiment. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device according to a modification of the eighth embodiment. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device according to another modification of the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [First Example] A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 5B. 1 is a schematic plan view of a semiconductor device according to a first embodiment. An adhesive layer including a first metal region 21A is disposed on a substrate. A first conductive region 40A of an underlying semiconductor layer is disposed so as to substantially overlap with the first metal region 21A. A plurality of semiconductor elements are disposed on the first conductive region 40A. A plurality of first transistors 41 are disposed as the plurality of semiconductor elements.

[0009] Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E. The collector layer 41C and the base layer 41B are substantially overlapped in a plan view. The emitter layer 41E is smaller than the base layer 41B in a plan view and is included in the base layer 41B.

[0010] The first emitter electrode 42E is disposed so as to substantially overlap the emitter layer 41E in plan view. The first emitter electrode 42E has a shape that is long in one direction (left-right direction in FIG. 1) in plan view. The shape of the first emitter electrode 42E in plan view is, for example, rectangular. In plan view, the U-shaped first base electrode 42B is disposed at a distance from each of the two long sides and one short side of the first emitter electrode 42E. In FIG. 1, the first emitter electrode 42E and the first base electrode 42B are hatched. The multiple first transistors 41 are disposed side by side in a width direction perpendicular to the longitudinal direction of the first emitter electrode 42E.

[0011] Fig. 2 is a cross-sectional view taken along dashed line 2-2 in Fig. 1. An adhesive layer 21 is disposed on a substrate 20. The adhesive layer 21 includes at least one first metal region 21A. Fig. 2 shows a cross-section of one first metal region 21A of the adhesive layer 21. The substrate 20 includes a surface layer portion made of a semiconductor. For example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or the like can be used as the substrate 20.

[0012] An underlying semiconductor layer 40 made of a semiconductor is bonded onto the adhesive layer 21. The underlying semiconductor layer 40 includes a first conductive region 40A that is provided with electrical conductivity, and an insulated element isolation region. A cross section of the first conductive region 40A appears in FIG. 2. A plurality of first transistors 41 are disposed on the first conductive region 40A.

[0013] Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E, which are stacked in this order from the substrate 20 side. The first transistors 41 are, for example, heterojunction bipolar transistors. As an example, the first conductive region 40A and the collector layer 41C of the underlying semiconductor layer 40 are formed of n-type GaAs, and the base layer 41B is formed of p-type GaAs. The emitter layer 41E includes, for example, two layers, an n-type InGaP layer and an n-type GaAs layer thereon. These semiconductor layers may be formed of other compound semiconductors, for example, InP, GaN, SiGe, SiC, etc.

[0014] Collector layer 41C is electrically connected to first metal region 21A via first conductive region 40A. First metal region 21A functions as a collector electrode of first transistor 41. Emitter layer 41E is disposed on a partial region of base layer 41B. Alternatively, emitter layer 41E may be disposed on the entire region of base layer 41B, and an emitter mesa may be disposed on a partial region of emitter layer 41E. In this configuration, the region overlapping with the emitter mesa in a plan view substantially functions as the emitter layer.

[0015] A first base electrode 42B is disposed on the base layer 41B, and a first emitter electrode 42E is disposed on the emitter layer 41E. The first base electrode 42B is electrically connected to the base layer 41B, and the first emitter electrode 42E is electrically connected to the emitter layer 41E.

[0016] A first emitter wiring 81E is disposed on the first emitter electrode 42E via an interlayer insulating film 80. The first emitter wiring 81E connects the multiple first emitter electrodes 42E to each other through an opening provided in the interlayer insulating film 80. The collector layers 41C of the multiple first transistors 41 are also connected to each other by the first conductive region 40A and the first metal region 21A. That is, the multiple first transistors 41 are connected in parallel.

[0017] A first emitter pad 82E and a first conductor protrusion 83E are disposed on the first emitter wiring 81E. Solder 84 is placed on the first conductor protrusion 83E. The structure in which the first conductor protrusion 83E is formed of Cu and solder 84 is placed thereon is called a "Cu pillar bump". The first conductor protrusion 83E may have a structure in which solder is not placed on the upper surface, such as an Au bump. A protrusion with such a structure is also called a "pillar". The first conductor protrusion 83E may have a structure in which a conductor pillar is erected on a pad. A conductor protrusion with such a structure is also called a "post". The first conductor protrusion 83E may be a ball bump formed by reflowing solder into a ball shape. In addition to these various structures, various structures including a conductor protruding from a substrate may be used as the conductor protrusion.

[0018] Next, a method for manufacturing a semiconductor device according to a first embodiment will be described with reference to Figures 3A to 4D. Figures 3A to 4C are schematic cross-sectional views of a semiconductor device during its manufacturing process, and Figure 4D is a schematic cross-sectional view of the completed semiconductor device.

[0019] As shown in FIG. 3A, a release layer 201 is epitaxially grown on a mother substrate 200 of a single crystal of a compound semiconductor such as GaAs, and an element formation layer 202 is formed on the release layer 201. In the element formation layer 202, an element structure including the underlying semiconductor layer 40, the multiple first transistors 41, the first emitter electrode 42E, the first base electrode 42B, the interlayer insulating film 80, the first emitter wiring 81E, and the like shown in FIG. 2 is formed. These element structures are formed by a general semiconductor process. In FIG. 3A, the element structures formed in the element formation layer 202 are omitted. At this stage, the element structures corresponding to multiple semiconductor devices are formed in the element formation layer 202, and are not separated into individual semiconductor devices. In addition, the first emitter pad 82E, the first conductor protrusion 83E, and the solder 84 (FIG. 2) are not formed.

[0020] 3B, a resist pattern (not shown) is used as an etching mask to pattern the element formation layer 202 and the release layer 201. At this stage, the element formation layer 202 is separated into individual semiconductor devices.

[0021] Next, as shown in Fig. 3C, a connecting support 204 is attached onto the separated element formation layer 202. As a result, the multiple element formation layers 202 are connected to each other via the connecting support 204. Note that the resist pattern used as an etching mask in the patterning step of Fig. 3B may be left to interpose a resist pattern between the element formation layer 202 and the connecting support 204.

[0022] 3D, the release layer 201 is selectively etched with respect to the mother substrate 200 and the element formation layer 202. As a result, the element formation layer 202 and the connecting support 204 are peeled off from the mother substrate 200. In order to selectively etch the release layer 201, a compound semiconductor having an etching resistance different from that of both the mother substrate 200 and the element formation layer 202 is used as the release layer 201.

[0023] As shown in Fig. 3E, an adhesive layer 21 is formed on the upper surface of substrate 20. Adhesive layer 21 includes a plurality of first metal regions 21A distributed in the surface, and insulating regions 21Z arranged in regions where first metal regions 21A are not arranged. Adhesive layer 21 can be formed by, for example, a damascene process.

[0024] 3F, the element formation layer 202 is bonded to the adhesive layer 21. The element formation layer 202 and the adhesive layer 21 are bonded by van der Waals bonds or hydrogen bonds. Alternatively, the element formation layer 202 may be bonded to the adhesive layer 21 by electrostatic forces, covalent bonds, eutectic alloy bonds, or the like. For example, when the first metal region 21A is made of Au, the element formation layer 202 may be bonded to the adhesive layer 21 by closely adhering the Au film to the Au film and applying pressure thereto.

[0025] Next, as shown in Fig. 4A, the connecting support 204 is peeled off from the element formation layer 202. After the connecting support 204 is peeled off, as shown in Fig. 4B, an interlayer insulating film 86 and a rewiring layer are formed on the adhesive layer 21 and the element formation layer 202. The rewiring layer includes a first emitter pad 82E arranged on a first emitter wiring 81E (Fig. 2), an interconnection wiring 82W that connects a circuit included in the element formation layer 202 and one metal region of the adhesive layer 21, and the like.

[0026] Next, as shown in FIG. 4C, a protective film 87 is formed on the rewiring layer, and a plurality of openings 87A are formed in the protective film 87. Each of the plurality of openings 87A is encompassed by a plurality of first emitter pads 82E in a plan view. A first conductor projection 83E is formed in the opening 87A and on the protective film 87. The first conductor projection 83E projects in a direction away from the substrate 20. Furthermore, solder 84 is placed on the top surface of the first conductor projection 83E, and a reflow process is performed.

[0027] Finally, as shown in Fig. 4D, the substrate 20 is diced. This results in an individualized semiconductor device 28 including the substrate 20, the adhesive layer 21, the element formation layer 202, the first emitter pad 82E, the first conductor protrusion 83E, the interconnection wiring 82W, and the like. With respect to the individualized semiconductor device 28, the substrate 20 is larger than the element formation layer 202 in a plan view. The individualized semiconductor device is flip-chip mounted on a module substrate or the like.

[0028] Next, the excellent effects of the first embodiment will be described. In the first embodiment, heat generated in the first transistor 41 (FIG. 2) is conducted to the substrate 20 through the underlying semiconductor layer 40 and the adhesive layer 21, and is also conducted to the solder 84 through the first emitter electrode 42E, the first emitter wiring 81E, the first emitter pad 82E, and the first conductor protrusion 83E. The heat conducted to the solder 84 is conducted to a module substrate on which the semiconductor device is mounted, etc. The heat conducted to the substrate 20 is diffused within the substrate 20 and then dissipated to the outside. The heat conducted to the module substrate is also dissipated from the module substrate to the outside in the same manner.

[0029] In this way, the heat generated in the first transistor 41 is conducted in both directions, downward (toward the substrate 20) and upward (toward the first conductor protrusion 83E), and dissipated. This improves the heat dissipation characteristics from the first transistor 41 compared to when heat is conducted in one direction. Because the heat dissipation characteristics from the first transistor 41 are improved, it is possible to arrange a plurality of first transistors 41 closely together. This makes it possible to miniaturize the semiconductor device.

[0030] In order to sufficiently diffuse the heat conducted to the substrate 20 into the substrate 20, it is preferable to use a material having a higher thermal conductivity than any of the collector layer 41C, the base layer 41B, and the emitter layer 41E of the first transistor 41 as the semiconductor material of the surface layer of the substrate 20. An example of such a semiconductor material is silicon. In addition, in order to efficiently dissipate heat from the substrate 20 to the outside, it is preferable to configure the substrate 20 to be larger than the underlying semiconductor layer 40 in a plan view.

[0031] Next, further advantageous effects of the first embodiment will be described in comparison with a comparative example with reference to FIGS. 5A and 5B.

[0032] Fig. 5A is a schematic plan view of the semiconductor device according to the first embodiment, and is the same as the schematic plan view shown in Fig. 1. Fig. 5B is a schematic plan view of a semiconductor device according to a comparative example.

[0033] In the semiconductor device according to the comparative example, the adhesive layer 21 (FIG. 2) including the first metal region 21A is not arranged, and the first collector electrode 42C is arranged between two adjacent first transistors 41. The first collector electrode 42C is arranged on the first conductive region 40A of the underlying semiconductor layer 40 (FIG. 2) and is electrically connected to the collector layer 41C (FIG. 2) of the first transistor 41 via the first conductive region 40A. In contrast, in the first embodiment, the first metal region 21A (FIG. 2) of the adhesive layer 21 functions as the collector electrode.

[0034] In the first embodiment, since there is no need to ensure a space for arranging first collector electrode 42C (FIG. 5B) in plan view, the semiconductor device can be made smaller.

[0035] 5B, the distance from the edge of emitter layer 41E to first collector electrode 42C is not equal to the distance from the innermost part of emitter layer 41E to first collector electrode 42C, and the distance varies depending on the position in the plane. In contrast, in the first embodiment, the distance in the thickness direction between emitter layer 41E and first metal region 21A functioning as a collector electrode is constant regardless of the position in the plane. This enables uniform operation in the plane of emitter layer 41E.

[0036] Next, a modification of the first embodiment will be described with reference to FIG. Fig. 6 is a schematic plan view of a semiconductor device according to a modification of the first embodiment. In the first embodiment (Fig. 1), each of the first transistors 41 includes one emitter layer 41E, and one first emitter electrode 42E is arranged for each first transistor 41. In contrast, in the modification shown in Fig. 6, one first transistor 41 includes two emitter layers 41E, and two first emitter electrodes 42E are arranged for each first transistor 41. The two first emitter electrodes 42E are arranged in a direction perpendicular to the longitudinal direction of the first emitter electrode 42E.

[0037] In a plan view, a main portion 42BA of the first base electrode 42B is disposed between two first emitter electrodes 42E. A contact portion 42BB extending in the width direction of the first emitter electrode 42E is provided at one end of the main portion 42BA of the first base electrode 42B. The first base electrode 42B is connected to an upper layer base wiring (not shown) at the contact portion 42BB.

[0038] In this modification, as in the first embodiment, it is possible to improve the heat dissipation characteristics from the first transistor 41, and as an additional effect, it is possible to reduce the size of the semiconductor device.

[0039] Next, another modification of the first embodiment will be described. In the first embodiment, the first conductive region 40A (FIG. 1) is surrounded by an insulated element isolation region, but the element isolation region may not be provided and the entire area of ​​the underlying semiconductor layer 40 (FIG. 2) may be the first conductive region 40A. In the first embodiment, a plurality of first transistors 41 are arranged, but only one first transistor 41 may be arranged. In the first embodiment, as shown in FIG. 2, the underlying semiconductor layer 40 is arranged between the adhesive layer 21 and the first transistor 41, but the underlying semiconductor layer 40 may be omitted. In this case, the collector layer 41C of the first transistor 41 is directly bonded to the first metal region 21A of the adhesive layer 21. In addition, the interlayer insulating film 80 is also directly bonded to the adhesive layer 21.

[0040] [Second Example] Next, a semiconductor device according to a second embodiment will be described with reference to Figures 7 and 8. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 4D will be omitted.

[0041] FIG. 7 is a schematic plan view of a semiconductor device according to the second embodiment. FIG. 8 is a cross-sectional view taken along dashed line 8-8 in FIG. 7. In FIG. 7, the first emitter electrode 42E and the first base electrode 42B are hatched. In the first embodiment (FIGS. 1 and 2), the collector layer 41C and the base layer 41B are separated for each first transistor 41. In contrast, in the second embodiment, the collector layer 41C and the base layer 41B are continuous across a plurality of first transistors 41. In the second embodiment, one emitter layer 41E and the base layer 41B and collector layer 41C directly below it are defined as one first transistor 41.

[0042] A main portion 42BA of one first base electrode 42B is disposed between two adjacent first emitter electrodes 42E. A contact portion 42BB extending in the width direction of the first emitter electrode 42E is provided at one end of the main portion 42BA of the first base electrode 42B. One first base electrode 42B is shared by two first transistors 41 connected to the two first emitter electrodes 42E on both sides thereof. The multiple first base electrodes 42B are connected to a base bias circuit 46 via base ballast resistors 45, respectively.

[0043] Next, the advantageous effects of the second embodiment will be described. In the first embodiment, two first base electrodes 42B are arranged between two mutually adjacent first emitter electrodes 42E. In contrast, in the second embodiment, one first base electrode 42B is arranged between two mutually adjacent first emitter electrodes 42E. This makes it possible to miniaturize the semiconductor device compared to the first embodiment. In addition, when the size and number of first transistors 41 are the same, the area of ​​the collector-base junction interface of the semiconductor device according to the second embodiment is smaller than the total area of ​​the collector-base junction interface of the semiconductor device according to the first embodiment. This provides an excellent effect of reducing the parasitic capacitance between the base and collector.

[0044] Next, a modification of the second embodiment will be described. In the second embodiment, a plurality of first base electrodes 42B arranged between two mutually adjacent first emitter electrodes 42E are separated from each other, and a base ballast resistor 45 is connected to each of the plurality of first base electrodes 42B. When the collector current varies among the plurality of first transistors 41, a specific first transistor 41 having a relatively large collector current may go into thermal runaway. The base ballast resistor 45 has a function of leveling out the variation in the collector current and suppressing thermal runaway. Depending on the operating conditions of the first transistor 41, the first transistor 41 may not easily go into thermal runaway. In such a case, the plurality of first base electrodes 42B may be connected to each other, and one base ballast resistor 45 may be connected to the plurality of first base electrodes 42B.

[0045] [Third Example] Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 9. Below, a description of configurations common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 4D will be omitted.

[0046] 9 is a cross-sectional view of a semiconductor device according to a third embodiment. The semiconductor device according to the first embodiment (FIGS. 1 and 2) includes a plurality of first transistors 41 as semiconductor elements. In contrast, the semiconductor device according to the third embodiment includes a second transistor 51 in addition to the first transistor 41 as a plurality of semiconductor elements arranged on a substrate 20.

[0047] The adhesive layer 21 includes, as a metal region, a second metal region 21B in addition to a first metal region 21A. The first metal region 21A and the second metal region 21B are separated from each other by an insulating region 21Z included in the adhesive layer 21. The underlying semiconductor layer 40 includes, as a conductive region, a second conductive region 40B in addition to a first conductive region 40A. The first conductive region 40A and the second conductive region 40B are separated from each other by an element isolation region 40Z included in the underlying semiconductor layer 40. In a plan view, the first conductive region 40A and the first metal region 21A have a mutually overlapping region. Similarly, the second conductive region 40B and the second metal region 21B also have a mutually overlapping region. Furthermore, at least a portion of the element isolation region 40Z and the insulating region 21Z overlap in a planar view so as to electrically insulate the region consisting of the first conductive region 40A and the first metal region 21A from the region consisting of the second conductive region 40B and the second metal region 21B from each other.

[0048] The second transistor 51 is disposed on the second conductive region 40B. Like the first transistor 41, the second transistor 51 includes a collector layer 51C, a base layer 51B, and an emitter layer 51E. The second metal region 21B functions as a collector electrode of the second transistor 51. A second base electrode 52B is connected to the base layer 51B, and a second emitter electrode 52E is connected to the emitter layer 51E.

[0049] A second emitter wiring 91E, a second emitter pad 92E, and a second conductor protrusion 93E are disposed on the second emitter electrode 52E. Solder 84 is placed on the second conductor protrusion 93E. The second emitter pad 92E is included in the rewiring layer (FIG. 4B) like the first emitter pad 82E. An interlayer insulating film 86 is disposed between the first emitter wiring 81E and the second emitter wiring 91E and the rewiring layer. The first emitter pad 82E and the second emitter pad 92E are covered with a protective film 87 except for the regions connected to the first conductor protrusion 83E and the second conductor protrusion 93E.

[0050] Next, the excellent effects of the third embodiment will be described. In the third embodiment, a first transistor 41 and a second transistor 51 that are electrically isolated from each other are formed on a common substrate 20. This allows two amplifier circuits to be included in one semiconductor device. For example, a two-stage amplifier circuit can be realized by configuring a front-stage amplifier circuit with the second transistor 51 and a rear-stage amplifier circuit with the first transistor 41. Also, in the third embodiment, it is possible to improve heat dissipation characteristics in the same way as in the first embodiment.

[0051] [Fourth Example] Next, a semiconductor device according to a fourth embodiment will be described with reference to Figures 10, 11A, and 11B. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 4D will be omitted.

[0052] 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. In the semiconductor device according to the fourth embodiment, a third transistor 61 and a diode 71 are included in the plurality of semiconductor elements arranged on a substrate 20 in addition to a first transistor 41.

[0053] The adhesive layer 21 includes, as metal regions, a third metal region 21C and a fourth metal region 21D in addition to the first metal region 21A. The first metal region 21A, the third metal region 21C, and the fourth metal region 21D are mutually isolated by an insulating region 21Z. The underlying semiconductor layer 40 includes, as addition to the first conductive region 40A, a third conductive region 40C, and a fourth conductive region 40D. The first conductive region 40A, the third conductive region 40C, and the fourth conductive region 40D are mutually isolated by an element isolation region 40Z. The first metal region 21A, the third metal region 21C, and the fourth metal region 21D at least partially overlap with the first conductive region 40A, the third conductive region 40C, and the fourth conductive region 40D in a plan view. In addition, at least a portion of insulating region 21Z and element isolation region 40Z overlap in a planar view so as to electrically insulate the three regions, namely, the region consisting of the first conductive region 40A and the first metal region 21A, the region consisting of the second conductive region 40B and the second metal region 21B, and the region consisting of the third conductive region 40C and the third metal region 21C, from each other.

[0054] The third transistor 61 is disposed on the third conductive region 40C. The third transistor 61 includes a collector layer 61C, a base layer 61B, and an emitter layer 61E, similar to the first transistor 41. A third base electrode 62B is connected to the base layer 61B, and a third emitter electrode 62E is connected to the emitter layer 61E.

[0055] In plan view, a third collector electrode 62C is disposed inside the third conductive region 40C and the third metal region 21C and outside the third transistor 61. The third collector electrode 62C is electrically connected to the collector layer 61C of the third transistor 61 via the third conductive region 40C and the third metal region 21C. No conductor protrusion is disposed for the third transistor 61. The third collector electrode 62C only needs to be disposed inside the third conductive region 40C in plan view, and does not necessarily have to be disposed inside the third metal region 21C. In addition, when adopting a configuration in which the third metal region 21C and the third conductive region 40C are directly connected to other electronic elements, the third collector electrode 62C may be omitted. For example, the collector layer 61C of the third transistor 61 may be connected to other electronic elements provided on the substrate 20 or other electronic elements provided on the underlying semiconductor layer 40 via the third metal region 21C and the third conductive region 40C.

[0056] The diode 71 is disposed on the fourth conductive region 40D. The diode 71 includes a lower layer 71L of a first conductive type (e.g., n-type) connected to the fourth conductive region 40D, and an upper layer 71U of a second conductive type (e.g., p-type) opposite to the first conductive type disposed thereon. The lower layer 71L is formed by patterning a common semiconductor layer together with the collector layer 41C of the first transistor 41 and the collector layer 61C of the third transistor 61. Similarly, the upper layer 71U is formed by patterning a common semiconductor layer together with the base layer 41B of the first transistor 41 and the base layer 61B of the third transistor 61.

[0057] In plan view, the lower electrode 72L is disposed inside the fourth conductive region 40D and the fourth metal region 21D and outside the diode 71. The lower electrode 72L is electrically connected to the lower layer 71L via the fourth conductive region 40D and the fourth metal region 21D. The lower electrode 72L only needs to be disposed inside the fourth conductive region 40D in plan view, and does not necessarily need to be disposed inside the fourth metal region 21D. The upper electrode 72U is disposed on the upper layer 71U. The upper electrode 72U is electrically connected to the upper layer 71U. In addition, when adopting a configuration in which the fourth metal region 21D and the fourth conductive region 40D are directly connected to other electronic elements, the lower electrode 72L may be omitted. For example, the lower layer 71L of the diode 71 may be connected to other electronic elements provided on the substrate 20 or other electronic elements provided on the underlying semiconductor layer 40 via the fourth metal region 21D and the fourth conductive region 40D.

[0058] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, as in the first embodiment, it is possible to improve the heat dissipation characteristics from the first transistor 41. Furthermore, the semiconductor device according to the fourth embodiment includes a third transistor 61 having a third collector electrode 62C arranged on the underlying semiconductor layer 40, in addition to the first transistor 41 having a first metal region 21A functioning as a collector electrode arranged under the underlying semiconductor layer 40. This provides the excellent effect of increasing the degree of freedom in designing the wiring connected to the collector of the transistor, making it easier to design the circuit.

[0059] Next, an example of an electronic circuit using the semiconductor device according to the fourth embodiment will be described with reference to FIGS. 11A and 11B.

[0060] 11A is an equivalent circuit diagram showing an example of an electronic circuit using the semiconductor device according to the fourth embodiment. A power stage amplifier circuit is formed by a first transistor 41. A power supply voltage is applied to the collector of the first transistor 41 from a power supply terminal Vcc through a choke coil Lc.

[0061] A third transistor 61 is included in the base bias circuit of the first transistor 41. The emitter of the third transistor 61 is connected to the base of the first transistor 41 via a base ballast resistor Rb. The collector and base of the third transistor 61 are connected to a bias power supply port Vbatt and a bias control port Vbias, respectively. A base bias is supplied to the first transistor 41 from the bias power supply port Vbatt through the third transistor 61 and the base ballast resistor Rb in response to a control current applied to the bias control port Vbias.

[0062] A high-frequency signal is input from an input port RFin through an input capacitor Cin to the base of a first transistor 41. The emitter of the first transistor 41 is grounded, and the collector is connected to an output port RFout.

[0063] The collector of the first transistor 41 is grounded via a plurality of serially connected diodes 71. The plurality of diodes 71 are connected with a forward polarity from the collector of the first transistor 41 toward the ground potential, and function as clamp diodes.

[0064] FIG. 11B is a partial cross-sectional view of a semiconductor device for realizing the electronic circuit shown in FIG. 11A. Hereinafter, differences from the structure shown in FIG. 10 will be described. The adhesive layer 21 includes a fifth metal region 21E, and the underlying semiconductor layer 40 includes a fifth conductive region 40E. A pad 76 is disposed on the fifth conductive region 40E. The fifth metal region 21E and the fifth conductive region 40E overlap each other in a plan view. The pad 76 is electrically connected to the fifth metal region 21E via the fifth conductive region 40E.

[0065] In addition to the first emitter wiring 81E, a wiring 75 is disposed on the interlayer insulating film 80. The wiring 75 is connected to the upper electrode 72U and the pad 76 through an opening provided in the interlayer insulating film 80. A multilayer wiring structure 22 is disposed between the substrate 20 and the adhesive layer 21. The multilayer wiring structure 22 includes a wiring 25 and a plurality of vias 26. The upper electrode 72U of the diode 71 is electrically connected to the first metal region 21A functioning as the collector electrode of the first transistor 41 through the wiring 75, the pad 76, the fifth conductive region 40E, the fifth metal region 21E, and the wiring 25 and vias 26 in the multilayer wiring structure 22. The fifth metal region 21E may be extended to the first metal region 21A, bypassing the third transistor 61, in the adhesive layer 21, to connect the upper electrode 72U to the first metal region 21A. When this configuration is adopted, the multilayer wiring structure 22 may be omitted.

[0066] 11B shows an example in which one wiring layer including the first emitter wiring 81E is disposed between the interlayer insulating film 80 and the first emitter pad 82E, but multiple wiring layers may be disposed between the interlayer insulating film 80 and the first emitter pad 82E. The base ballast resistor Rb and the input capacitor Cin are formed on the underlying semiconductor layer 40, for example, before the interlayer insulating film 80 is formed.

[0067] The third collector electrode 62C of the third transistor 61 is connected to a collector conductor protrusion (not shown) arranged on the protective film 87. Bias power is supplied to the collector of the third transistor 61 from the bias power supply port Vbatt (FIG. 11A) of the module substrate via the collector conductor protrusion and the third collector electrode 62C. Since the third collector electrode 62C is arranged on the underlying semiconductor layer 40, the connection structure between the third collector electrode 62C and the collector conductor protrusion for connection to the bias power supply port Vbatt can be simplified compared to the case where the collector electrode of the third transistor 61 is arranged under the underlying semiconductor layer 40.

[0068] Next, a modified example of the fourth embodiment will be described. In the fourth embodiment, the wiring 25 and the via 26 are arranged in the multilayer wiring structure 22, but passive elements made of metal patterns may also be arranged. For example, an inductor may be formed of a spiral or meandering metal pattern. Alternatively, a capacitor may be formed of metal patterns arranged above and below with an interlayer insulating film interposed therebetween.

[0069] [Fifth Example] Next, a semiconductor device according to a fifth embodiment will be described with reference to Fig. 12. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 4D will be omitted.

[0070] 12 is a cross-sectional view of a semiconductor device according to a fifth embodiment. In the fifth embodiment, adhesion layer 21 includes, as a metal region, sixth metal region 21F in addition to first metal region 21A. Underlying semiconductor layer 40 includes, as conductive regions, sixth conductive region 40F and seventh conductive region 40G in addition to first conductive region 40A. Sixth conductive region 40F and seventh conductive region 40G overlap portions of sixth metal region 21F in a plan view, and the two are electrically connected to each other via sixth metal region 21F.

[0071] A diode 71 is disposed on the sixth conductive region 40F. The diode 71 has the same structure as the diode 71 (FIG. 10) of the semiconductor device according to the fourth embodiment. A metal member 77 such as wiring is disposed on the seventh conductive region 40G. The metal member 77 is electrically connected to the sixth metal region 21F through an opening 40K provided in the underlying semiconductor layer 40. The metal member 77 is electrically connected to the diode 71 through the sixth metal region 21F and the sixth conductive region 40F. The opening 40K is formed at the stage shown in FIG. 3A during the manufacturing process. In the state shown in FIG. 3D where the peeling layer 201 has been removed, the metal member 77 in the opening 40K is exposed.

[0072] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, as in the first embodiment, the heat dissipation characteristics from the first transistor 41 can be improved. Furthermore, in the fifth embodiment, the diode 71 and the metal member 77 are connected to each other via the sixth metal region 21F included in the adhesive layer 21. By using the metal region included in the adhesive layer 21 as wiring, the degree of freedom in wiring design can be increased. In addition, since the metal member 77 is connected to the sixth metal region 21F through the opening 40K provided in the underlying semiconductor layer 40, a lower resistance can be achieved compared to a configuration in which the metal member 77 is electrically connected through a conductive region included in the underlying semiconductor layer 40.

[0073] Next, a modification of the fifth embodiment will be described. In the fifth embodiment, the metal member 77 on the underlying semiconductor layer 40 and the diode 71 are connected by the sixth metal region 21F of the adhesive layer 21, but the metal member 77 may be connected to another semiconductor element via the sixth metal region 21F. Also, in the fifth embodiment, the metal member 77 is disposed on the seventh conductive region 40G included in the underlying semiconductor layer 40, but the metal member 77 may be disposed on the element isolation region 40Z. In this case, an opening 40K may be provided in the element isolation region 40Z.

[0074] [Sixth Example] Next, a semiconductor device according to a sixth embodiment will be described with reference to Fig. 13. Below, a description of the configuration common to the semiconductor device according to the fourth embodiment described with reference to Figs. 10 to 11B will be omitted.

[0075] 13 is a cross-sectional view of a semiconductor device according to the sixth embodiment. In the fourth embodiment (FIG. 10), the third conductive region 40C and the fourth conductive region 40D of the underlying semiconductor layer 40 are respectively disposed on the third metal region 21C and the fourth metal region 21D of the adhesive layer 21. In contrast, in the sixth embodiment, the third conductive region 40C and the fourth conductive region 40D of the underlying semiconductor layer 40 are disposed on the insulating region 21Z of the adhesive layer 21.

[0076] In the sixth embodiment, the third collector electrode 62C is connected to the collector layer 61C of the third transistor 61 only through the third conductive region 40C of the underlying semiconductor layer 40. Similarly, the lower electrode 72L is connected to the lower layer 71L of the diode 71 only through the fourth conductive region 40D of the underlying semiconductor layer 40.

[0077] A multilayer wiring structure 22 is disposed between the substrate 20 and the adhesive layer 21. The multilayer wiring structure 22 includes a plurality of wires 25 and a plurality of vias .

[0078] Next, the excellent effects of the sixth embodiment will be described. In the sixth embodiment, as in the first embodiment, it is possible to improve the heat dissipation characteristics from the first transistor 41. Furthermore, in the sixth embodiment, since the insulating region 21Z is provided directly below the third conductive region 40C and the fourth conductive region 40D of the underlying semiconductor layer 40, the wiring 25 of the uppermost wiring layer in the multilayer wiring structure 22 can be arranged in a region overlapping the third conductive region 40C and the fourth conductive region 40D in a plan view. Therefore, an excellent effect is obtained in that the degree of freedom in arranging the wiring 25 in the multilayer wiring structure 22 is increased.

[0079] [Seventh Example] Next, a semiconductor device according to a seventh embodiment will be described with reference to Fig. 14. Below, description of configurations common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 4D will be omitted.

[0080] 14 is a cross-sectional view of a semiconductor device according to the seventh embodiment. In the first embodiment (FIG. 2), the substrate 20 and the adhesive layer 21 are in contact with each other. In contrast, Seventh Example In the example, an insulating layer 23 is disposed between a substrate 20 and an adhesive layer 21. The insulating layer 23 is made of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0081] Next, the excellent effects of the seventh embodiment will be described. In the seventh embodiment, similarly to the first embodiment, it is possible to improve the heat dissipation characteristics from the first transistor 41. Furthermore, in the seventh embodiment, it is possible to improve the insulation between a semiconductor element disposed on the underlying semiconductor layer 40, for example, between the first transistor 41 and the substrate 20.

[0082] [Eighth Example] Next, a semiconductor device according to an eighth embodiment will be described with reference to Fig. 15. Below, a description of the configuration common to the semiconductor device according to the fourth embodiment described with reference to Fig. 10 will be omitted.

[0083] 15 is a cross-sectional view of a semiconductor device according to the eighth embodiment. In the eighth embodiment, a multilayer wiring structure 22 is disposed between a substrate 20 and an adhesive layer 21. The multilayer wiring structure 22 includes a plurality of wires 25 and a plurality of vias 26. A substrate-side transistor 27 is formed in a surface layer portion of the substrate 20. The substrate-side transistor 27 is, for example, a silicon-based MOS transistor or a silicon-based bipolar transistor.

[0084] The first metal region 21A included in the adhesive layer 21 is connected to at least one of the wiring 25 and the via 26 in the multilayer wiring structure 22. Furthermore, the substrate-side transistor 27 is also electrically connected to at least one of the wiring 25 and the via 26 in the multilayer wiring structure 22. For example, one metal region included in the adhesive layer 21 is connected to the substrate-side transistor 27 through the wiring 25 and the via 26 in the multilayer wiring structure 22. Note that a metal region other than the first metal region 21A included in the adhesive layer 21 may be connected to the wiring and the via in the multilayer wiring structure 22.

[0085] Next, the excellent effects of the eighth embodiment will be described. In the eighth embodiment, as in the first embodiment, the heat dissipation characteristics from the first transistor 41 can be improved. Furthermore, in the eighth embodiment, an electronic circuit formed of the substrate-side transistor 27 formed in the surface layer of the substrate 20 and an electronic circuit formed of semiconductor elements such as the first transistor 41 arranged on the underlying semiconductor layer 40 are electrically connected via the multilayer wiring structure 22. Therefore, a compound semiconductor-based semiconductor element and a silicon-based semiconductor element can be connected within the semiconductor device without an intermediate module substrate or the like. This makes it possible to miniaturize a semiconductor module including the semiconductor device.

[0086] Next, a modified example of the eighth embodiment will be described. In the eighth embodiment, the wiring 25 and the via 26 in the multilayer wiring structure 22 are electrically connected to both the substrate-side transistor 27 and the like arranged below the adhesive layer 21 and the first transistor 41 and the like arranged above the adhesive layer 21. As a modified example, it is also possible to adopt a configuration in which the wiring 25 and the via 26 in the multilayer wiring structure 22 are electrically connected to the substrate-side transistor 27 and the like below the adhesive layer 21, but are not electrically connected to the elements above the adhesive layer 21. When adopting this configuration and connecting the substrate-side transistor 27 and the like to the elements above the adhesive layer 21, for example, the two may be electrically connected via a conductor protrusion and a wiring on the module substrate, or the two may be electrically connected via the interconnection wiring 82W (FIG. 4D) without the module substrate. As yet another modified example, it is also possible to adopt a configuration in which the wiring 25 and the via 26 in the multilayer wiring structure 22 are electrically connected to the elements above the adhesive layer 21, but are not electrically connected to the elements on the substrate 20 below the multilayer wiring structure 22.

[0087] In addition, in the eighth embodiment, the first metal region 21A electrically connected to the first transistor 41 is electrically connected to the via 26 and the wiring 25 in the multilayer wiring structure 22, but a configuration may be adopted in which the first metal region 21A is not connected to the via 26 or the wiring 25 in the multilayer wiring structure 22.

[0088] Next, with reference to FIGS. 16 and 17, a modified example in which first metal region 21A is not connected to vias 26 and wiring 25 in multilayer wiring structure 22 will be described.

[0089] 16 is a cross-sectional view of a semiconductor device according to a modified example of the eighth embodiment. The first metal region 21A is not connected to the wiring in the multilayer wiring structure 22. The first metal region 21A and the first conductive region 40A are expanded in the in-plane direction, and a metal pattern 42CC is disposed on the expanded portion of the first conductive region 40A. The metal pattern 42CC is covered with an interlayer insulating film 80. A first collector wiring 81C is disposed on the interlayer insulating film 80. The first collector wiring 81C is connected to the metal pattern 42CC through an opening provided in the interlayer insulating film 80.

[0090] A first collector pad 82C and a collector conductor protrusion 83C are disposed on the first collector wiring 81C. The configurations of the first collector pad 82C and the collector conductor protrusion 83C are the same as those of the first emitter pad 82E and the first conductor protrusion 83E. Solder 84 is placed on the collector conductor protrusion 83. In the modification shown in FIG. 16, the collector of the first transistor 41 is connected to an electronic circuit on the module substrate via the collector conductor protrusion 83C.

[0091] 16, the first conductive region 40A is continuous from the region in which the first transistor 41 is arranged to the region in which the collector conductor protrusion 83C is arranged, but the first conductive region 40A does not necessarily have to be continuous. Even if the first conductive region 40A is not continuous, the collector of the first transistor 41 and the collector conductor protrusion 83C are electrically connected via the first metal region 21A.

[0092] 5A, the metal pattern 42CC may be arranged so as to run parallel to the row of the first transistors 41. By arranging in this manner, the length of the row of the first transistors 41 can be made shorter than that of the comparative example shown in FIG.

[0093] Fig. 17 is a cross-sectional view of a semiconductor device according to another modification of the eighth embodiment. In this modification as well, first metal region 21A is not connected to wiring in multilayer wiring structure 22. In the modification shown in Fig. 16, collector conductor protrusion 83C is disposed inside element formation layer 202 (Fig. 4D) in plan view, but in this modification, collector conductor protrusion 83C is disposed outside element formation layer 202 (Fig. 4D) in plan view.

[0094] The first metal region 21A extends to the outside of the element formation layer 202 (FIG. 4D) in plan view, that is, to the outside of the underlying semiconductor layer 40. An interlayer insulating film 86 is disposed on the adhesive layer 21 on the outside of the underlying semiconductor layer 40. 86 A first collector pad 82C is disposed on the first collector pad 82C. The first collector pad 82C is connected to the first metal region 21A through an opening provided in the interlayer insulating film 86. A protective film 87 is disposed on the first collector pad 82C. A collector conductor projection 83C is disposed on the protective film 87. The collector conductor projection 83C is connected to the first collector pad 82C through an opening provided in the protective film 87. Solder 84 is placed on the collector conductor projection 83C.

[0095] 5A, the first collector pad 82C may be arranged so as to run parallel to the row of the first transistors 41. By arranging in this manner, the length of the row of the first transistors 41 can be made shorter than that in the comparative example shown in FIG.

[0096] As in this modification, the collector conductor protrusion 83C connected to the collector of the first transistor 41 may be disposed in a region where the underlying semiconductor layer 40 is not disposed in plan view.

[0097] 16 and 17, a current path connected in parallel to first metal region 21A may be formed by wiring and vias in multilayer wiring structure 22. This can reduce the electrical resistance between the collector of first transistor 41 and collector conductor protrusion 83C.

[0098] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0099] 20 Substrate 21 Adhesive layer 21A 1st metal area 21B 2nd metal area 21C 3rd metal area 21D 4th metal area 21E 5th metal area 21F 6th metal area 21Z Insulation Area 22 Multilayer wiring structure 23 Insulating layer 25 Wiring 26 Via 27 Substrate side transistor 28 Semiconductor Devices 40 Underlying semiconductor layer 40A First Conduction Region 40B 2nd conductive area 40C 3rd conductive area 40D 4th conductive area 40E 5th conductive area 40F 6th conductive area 40G 7th conductive area 40K aperture 40Z Element isolation area 41 First transistor 41B Base layer 41C Collector layer 41E Emitter layer 42B First base electrode 42BA Main Section 42BB Contact part 42C First collector electrode 42CC Metal Pattern 42E First emitter electrode 45 Base ballast resistor 46 Base bias circuit 51 Second transistor 51B Base layer 51C Collector layer 51E Emitter layer 52B Second base electrode 52E Second emitter electrode 61 Third transistor 61B Base layer 61C Collector layer 61E Emitter layer 62B Third base electrode 62C 3rd collector electrode 62E Third emitter electrode 71 Diode 71L Diode bottom layer 71U Diode top layer 72U upper electrode 72L lower electrode 75 Wiring 76 Pad 77 Metallic materials 80 Interlayer insulating film 81C 1st collector wire 81E 1st emitter wiring 82C 1st collector pad 82E 1st emitter pad 82W Interconnect Wiring 83C Collector conductor projection 83E First conductor protrusion 84 Solder 86 Interlayer insulating film 87 Protective film 87A aperture 91E 2nd emitter wiring 92E 2nd emitter pad 93E Second conductor protrusion 200 Motherboard 201 Peeling layer 202 Device formation layer 204 Connecting support

Claims

1. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; an element formation layer disposed on the adhesive layer; Equipped with The element formation layer is At least one semiconductor device; an interlayer insulating film disposed on the adhesive layer so as to cover the semiconductor element; Including, the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; the element formation layer further includes a first emitter electrode disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; the first metal region extends to the outside of the element formation layer in a plan view; moreover, a collector conductor protrusion connected to a portion of the first metal region that extends to the outside of the element formation layer;

2. a plurality of the first transistors are arranged, and the first emitter electrode is arranged for each of the plurality of the first transistors; a first emitter wiring disposed between the first emitter electrodes and the first conductor protrusion, the first emitter wiring connecting the first emitter electrodes to each other; 2. The semiconductor device according to claim 1, wherein the first conductor projection is electrically connected to the first emitter wiring.

3. 3. The semiconductor device according to claim 2, wherein the collector layers and the base layers of the first transistors are continuous across the first transistors.

4. The semiconductor device further includes a second transistor disposed on a second metal region of the adhesion layer; the second transistor includes a collector layer electrically connected to the second metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a second emitter electrode disposed on the emitter layer of the second transistor and electrically connected to the emitter layer of the second transistor; a second conductor protrusion disposed on the second emitter electrode, electrically connected to the second emitter electrode, and protruding in a direction away from the substrate; The semiconductor device according to claim 1 , further comprising:

5. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; at least one semiconductor element disposed on the adhesive layer; Equipped with the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; the semiconductor device further includes a third transistor disposed on a third metal region, the third metal region being a metal region of the adhesion layer; the third transistor includes a collector layer electrically connected to the third metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; a third emitter electrode disposed on and electrically connected to the emitter layer of the third transistor; A semiconductor device in which a conductor protrusion connected to the third emitter electrode is not provided.

6. 6. The semiconductor device according to claim 5, further comprising: a third collector electrode that is disposed inside the third metal region and outside the third transistor in a plan view, and is electrically connected to the third metal region.

7. A substrate including a surface layer made of a semiconductor material; an adhesion layer disposed on a surface portion of the substrate, the adhesion layer including a first metal region, a fourth metal region, and an insulating region separating the first metal region and the fourth metal region; a first transistor disposed on the adhesion layer and on the first metal region; a diode disposed on the adhesion layer and on the fourth metal region; at least one semiconductor element disposed on the adhesive layer; Equipped with the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; the diode includes a lower layer made of a semiconductor of a first conductivity type disposed over the fourth metal region, and an upper layer made of a semiconductor of a second conductivity type opposite to the first conductivity type disposed over the lower layer; The semiconductor device further comprises an upper electrode disposed on and electrically connected to the upper layer.

8. 8. The semiconductor device according to claim 7, further comprising: a lower electrode disposed inside the fourth metal region and outside the diode in a plan view, the lower electrode being electrically connected to the fourth metal region.

9. The semiconductor device further includes an underlying semiconductor layer disposed between the adhesion layer and the semiconductor element, the underlying semiconductor layer includes a conductive region that overlaps with a metal region of the adhesive layer in a plan view; 9. The semiconductor device according to claim 5, wherein the conductive region of the underlying semiconductor layer electrically connects the metal region of the adhesive layer that overlaps with the conductive region in a planar view to the semiconductor element on the underlying semiconductor layer.

10. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; at least one semiconductor element disposed on the adhesive layer; Equipped with the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; The semiconductor device further includes an underlying semiconductor layer disposed between the adhesion layer and the semiconductor element, the underlying semiconductor layer includes, in a plan view, a plurality of conductive regions and an element isolation region other than the conductive regions; a collector layer of the first transistor is electrically connected to a metal region of the adhesion layer through a conductive region of the underlying semiconductor layer; the adhesive layer includes an insulating region disposed outside a metal region in a plan view; the underlying semiconductor layer further includes a third conductive region disposed on the insulating region of the adhesion layer; the semiconductor device further includes a third transistor disposed on the third conductive region; the third transistor includes a collector layer electrically connected to the third conductive region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a third emitter electrode disposed on the emitter layer of the third transistor and electrically connected to the emitter layer of the third transistor; a third collector electrode that is disposed inside the third conductive region and outside the third transistor in a plan view and is electrically connected to the third conductive region; A semiconductor device comprising:

11. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; at least one semiconductor element disposed on the adhesive layer; Equipped with the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; The semiconductor device further includes an underlying semiconductor layer disposed between the adhesion layer and the semiconductor element, the underlying semiconductor layer includes, in a plan view, a plurality of conductive regions and an element isolation region other than the conductive regions; a collector layer of the first transistor is electrically connected to a metal region of the adhesion layer through a conductive region of the underlying semiconductor layer; the adhesive layer includes an insulating region disposed outside a metal region in a plan view; the underlying semiconductor layer further includes a fourth conductive region disposed on the insulating region of the adhesion layer; The semiconductor device further includes a diode disposed on the fourth conductive region; the diode includes a lower layer made of a semiconductor of a first conductivity type disposed on the fourth conductive region, and an upper layer made of a semiconductor of a second conductivity type opposite to the first conductivity type disposed on the lower layer, moreover, an upper electrode disposed on and electrically connected to the upper layer; a lower electrode that is disposed inside the fourth conductive region and outside the diode in a plan view and is electrically connected to the fourth conductive region; A semiconductor device comprising:

12. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; at least one semiconductor element disposed on the adhesive layer; Equipped with the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; The semiconductor device further comprises an insulating layer disposed between the surface layer of the substrate and the adhesive layer.

13. A substrate including a surface layer made of a semiconductor material; an adhesive layer disposed on a surface portion of the substrate and including at least one metal region in a plan view; at least one semiconductor element disposed on the adhesive layer; Equipped with the semiconductor device includes a first transistor disposed on a first metal region, the first metal region being a metal region of the adhesion layer; the first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer; moreover, a first emitter electrode disposed on an emitter layer of the first transistor and electrically connected to the emitter layer; a first conductor protrusion disposed on the first emitter electrode, electrically connected to the first emitter electrode, and protruding in a direction away from the substrate; Equipped with a thermal conductivity of a semiconductor material of a surface layer of the substrate is higher than the thermal conductivity of any of a collector layer, a base layer, and an emitter layer of the first transistor; The semiconductor device further comprises a multi-layer wiring structure disposed between a surface layer of the substrate and the adhesive layer.

14. 14. The semiconductor device according to claim 13, wherein the multi-layer wiring structure includes a plurality of wirings and a plurality of vias, and the metal region of the adhesive layer is electrically connected to at least one of the wirings included in the multi-layer wiring structure.

15. Further, at least one substrate-side transistor is formed on a surface layer portion of the substrate, 15. The semiconductor device according to claim 13, wherein the substrate-side transistor is connected to wiring included in the multilayer wiring structure.

16. The surface layer of the substrate is made of silicon, 16. The semiconductor device according to claim 1, wherein a collector layer, a base layer, and an emitter layer of the first transistor are formed of a compound semiconductor.

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