Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of improving avalanche resistance.SOLUTION: In an entire intermediate region 20 between an active region 10 and an edge terminal region 30, a p+ type region 13 is provided between a p type base region 4 and a parallel pn layer 60. The p+ type region 13 is formed simultaneously with p+ type regions 11 and 12 mitigating an electric field applied to a bottom face of a gate trench 7 in the active region 10, and brought into contact with the p+ type regions 11 and 12. The p+ type region 13 includes projections 13a protruding to the side of the parallel pn layer 60 respectively in portions opposed to an n type region 61 and a p type region 62 of the parallel pn layer 60 in a depth direction Z. An n type current diffusion region 3 extends from the active region 10 to the entire intermediate region 20 and exists between the projections 13a of the p+ type region 13 between the p+ type region 13 and the parallel pn layer 60. An impurity concentration of the n type current diffusion region 3 is higher than that of the other portion in the portion of a gate region 22.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, there is known a semiconductor device with a super junction (SJ) structure in which the drift layer is a parallel pn layer in which n-type regions and p-type regions are alternately and repeatedly arranged in a direction parallel to the main surface of the substrate. A trench-filling epitaxial method is known as a method for forming the parallel pn layer, in which a trench (hereinafter referred to as an SJ trench) is formed in an n-type epitaxial layer deposited to a predetermined thickness of the parallel pn layer, leaving a portion that becomes the n-type region of the parallel pn layer, and filling the SJ trench with a p-type epitaxial layer that becomes the p-type region of the parallel pn layer.

[0003] When silicon carbide (SiC) is used as the semiconductor material and the trench-filling epitaxial method is used, the main surface of the semiconductor substrate (semiconductor chip) is the (0001) plane, or the so-called Si plane, and an SJ trench is formed in a stripe shape extending parallel to the <11-20> direction in the epitaxial layer that constitutes the semiconductor substrate. The n-type region and p-type region that constitute the parallel pn layer extend linearly parallel to the <11-20> direction along which the SJ trench extends, and reach the outside of the breakdown voltage structure (the edge (chip edge) side of the semiconductor substrate).

[0004] Fig. 30 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Figs. 31 and 33 are cross-sectional views showing an enlarged middle region of Fig. 30. Fig. 32 is a cross-sectional view showing an enlarged rectangular frame BB of Fig. 31. Fig. 33 shows n - The region where n-type impurities are ion-implanted to form the n-type current diffusion region 103 in the epitaxial layer 143 is shown by hatching. In FIG. 33, in order to clarify the end position of the n-type current diffusion region 103, the n - p-type epitaxial layer 143 formed by ion implantation + The mold regions 111 to 113 are shown only in outline.

[0005] A conventional silicon carbide semiconductor device 150 shown in Fig. 30 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate having a three-layer structure of metal-oxide film-semiconductor) having an SJ structure with a general trench gate structure in an active region 110 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. + The semiconductor device is formed by laminating epitaxial layers 142 to 144 in order on a mold starting substrate 141 .

[0006] The principal surface of the semiconductor substrate 140 on the side of the p-type epitaxial layer 144 is the front surface, and + The n-type drain region 101 + The main surface on the side of the starting substrate 141 is referred to as the back surface. The epitaxial layer 142 is the drift layer 102 that will become the drift region, and includes a parallel pn layer 160. The parallel pn layer 160 is formed by a trench-filling epitaxial method, and has an SJ structure in which n-type regions 161 and p-type regions 162 are alternately and repeatedly arranged in a first direction X parallel to the front surface of the semiconductor substrate 140. Reference numeral 102a denotes a portion of the drift layer 102 that does not have the SJ structure.

[0007] The active region 110 is provided in the center (chip center) of the semiconductor substrate 140. - The n-type epitaxial layer 143 includes an n-type current spreading region 103 that is a current spreading layer (CSL) for reducing the spreading resistance of carriers, and a p-type current spreading region 104 that is a current spreading layer (CSL) for reducing the electric field applied to the bottom surface of the gate trench 107. + The n-type current diffusion region 103 and the p-type current diffusion region 114 are selectively provided. + The mold regions 111 and 112 are diffusion regions formed by ion implantation.

[0008] The active region 110 is surrounded by an edge termination region 130 with an intermediate region 120 interposed therebetween. A breakdown voltage structure such as a junction termination extension (JTE) structure 132 is disposed in the edge termination region 130. FIG. 30 shows a cross-sectional view of a JTE structure 132 in which multiple p-type regions are connected together as a single p - The p-type epitaxial layer 144 is shown as an edge termination region 130 by etching, forming a step 131 on the front surface of the semiconductor substrate 140.

[0009] The front surface of the semiconductor substrate 140 is such that the edge termination region 130 portion (hereinafter referred to as the second surface) 140b is larger than the active region 110 side portion (hereinafter referred to as the first surface) 140a, with the step 131 as the boundary. + The edge termination region 130 is recessed toward the type drain region 101. At a portion 140c (mesa edge of step 131: hereinafter referred to as the third surface) that connects the first surface 140a and the second surface 140b on the front surface of the semiconductor substrate 140, the active region 110 and the intermediate region 120 between the active region 110 and the edge termination region 130 are isolated from the edge termination region 130.

[0010] In the edge termination region 130, the second surface 140b of the front surface of the semiconductor substrate 140 has n - The n-type epitaxial layer 143 is exposed. - A plurality of p-type regions (p - The p-type regions constituting the JTE structure 132 are diffusion regions formed by ion implantation, and + The p-type region 113 is electrically connected to the p-type base region 104 .

[0011] The p-type base region 104 is a portion of the p-type epitaxial layer 144 that remains after the formation of the step 131. The p-type base region 104 extends from the active region 110 outward (toward the chip end) to reach the third surface 140c of the front surface of the semiconductor substrate 140, and is provided over the entire intermediate region 120.+ The type region 113 has an n - The inside of the p-type epitaxial layer 143 + The diffusion region is formed by ion implantation simultaneously with the type region 112 , and is provided between the parallel pn layer 160 and the p-type base region 104 and surrounds the periphery of the active region 110 .

[0012] p + The n-type region 113 is adjacent to the n-type region 161 and the p-type region 162 of the parallel pn layer 160 and the p-type base region 104 in the depth direction Z. + The n-type region 113 extends inward (toward the center of the chip) to reach the active region 110, and the n-type current spreading region 103 and the p-type + It is in contact with the mold regions 111 and 112. + The mold region 113 extends with a uniform thickness over the entire intermediate region 120, and reaches the third surface 140c of the front surface of the semiconductor substrate 140 (FIG. 30). "Uniform thickness" means that the thickness is the same within a range including tolerances due to process variations.

[0013] In the inner portion (hereinafter, referred to as the peripheral contact region) 121 of the intermediate region 120, the source electrode 115 extends from the active region 110. + A contact portion (electrical contact portion: hereinafter referred to as peripheral contact portion) 121a is formed with the p-type peripheral contact region 121b. When the MOSFET is turned off, minority carriers (holes) in the drift layer 102 in the edge termination region 130 are discharged to the source electrode 115 via the p-type base region 104 and the peripheral contact portion 121a.

[0014] The peripheral contact region 121 is a region between the active region 110 and an inner peripheral end of a gate runner (not shown) disposed in a gate region 122 (described later). An n-type current diffusion region 103 extends from the active region 110 over the entire peripheral contact region 121. The n-type current diffusion region 103 is formed so as to overlap the p-type region 113, and + The n-type region 113 is at the same depth as the p-type region 113 or is at a depth lower than the p-type region 113. + Deep on the side of the p-type drain region 101+ It exists with a very small thickness between the n-type region 113 and the n-type region 161 of the parallel pn layer 160 (FIG. 33).

[0015] In a portion (hereinafter referred to as a gate region) 122 outside the intermediate region 120, a gate runner 122a made of a polysilicon (poly-Si) layer is provided on a field oxide film 136. In the gate region 122, a contact (electrical contact portion) is formed between the gate electrode 109 extending from the active region 110 and the gate runner 122a. Reference numerals 114, 117, and 135 denote an interlayer insulating film, a drain electrode, and a passivation film, respectively. The gate runner 122a and the field oxide film 136 are omitted from FIGS. 31 to 33.

[0016] As a conventional semiconductor device with an SJ structure, a device has been proposed in which a p-type resurf region is selectively provided only in the surface region of the n-type region of the parallel pn layer so as not to overlap the p-type region of the parallel pn layer outside the active region (see, for example, Patent Document 1 below). In Patent Document 1 below, the p-type region of the parallel pn layer and the p-type resurf region are formed to overlap (overlap), which prevents the impurity concentration in the p-type region of the parallel pn layer from becoming high, and prevents deviation of depletion conditions due to the overlap.

[0017] Also, as another conventional semiconductor device with an SJ structure, a device has been proposed in which an n-type surface region with a predetermined dose is formed in the surface region of the end (side) of a semiconductor substrate along the slope of the end of the semiconductor substrate (see, for example, Patent Document 2 below). In Patent Document 2 below, the n-type surface region at the end of the semiconductor substrate suppresses the spread of the depletion layer at the end of the semiconductor substrate, thereby suppressing the occurrence of avalanche breakdown outside the active region, so that the breakdown voltage is determined not by the end of the semiconductor substrate but by the critical electric field strength at the interface between the drift layer and the drain region in the active region. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] JP 2010-040973 A [Patent Document 2] JP 2007-208075 A Summary of the Invention [Problem to be solved by the invention]

[0019] However, as a result of extensive research by the inventors, it has been found that in the conventional silicon carbide semiconductor device 150 (see Figs. 30 to 33), the following occurs: When the device is turned off, an impact ion phenomenon occurs in the parallel pn layer 160 of the intermediate region 120, causing avalanche breakdown (see Fig. 23). As a result, a sharply increased hole current (hereinafter referred to as avalanche current) flows through the p + Through the type region 113, + When the electrons are discharged from the peripheral contact region 121b to the source electrode 115, + The metal particles are concentrated in the mold region 113 and the peripheral contact portion 121a (see FIG. 25).

[0020] p in the middle region 120 + Avalanche current concentrates in mold region 113 and peripheral contact portion 121a, causing silicon carbide semiconductor device 150 to break down outside active region 110. This causes the avalanche resistance of intermediate region 120 and edge termination region 130 to be smaller than the avalanche resistance of active region 110. This causes breakdown due to surge current or surge voltage to depend on the capabilities of intermediate region 120 and edge termination region 130, and the current capability of active region 110 cannot be maximized.

[0021] SUMMARY OF THE PRESENT DISCLOSURE ... In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a silicon carbide semiconductor device capable of improving the avalanche resistance. [Means for solving the problem]

[0022] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide, from an active region to a termination region surrounding the periphery of the active region, in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged in a first direction parallel to a first main surface of the semiconductor substrate. The first main surface of the semiconductor substrate has a first surface which is a portion excluding the termination region, a second surface which is a portion of the termination region, and a step formed by recessing the second surface toward the second main surface of the semiconductor substrate. A first semiconductor region of a second conductivity type is provided between the first surface of the semiconductor substrate and the parallel pn layer, extending from the active region to an intermediate region between the active region and the termination region to reach the step.

[0023] A second semiconductor region of a first conductivity type is provided between the first semiconductor region and the parallel pn layer in the active region and in contact with the first semiconductor region and the parallel pn layer. A third semiconductor region of a first conductivity type is selectively provided between the first surface of the semiconductor substrate and the first semiconductor region in the active region. A trench penetrates the third semiconductor region and the first semiconductor region to reach the second semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. A first high concentration region of a second conductivity type is provided between the bottom surface of the trench and the parallel pn layer, facing the bottom surface of the trench in the depth direction. The first high concentration region has a higher impurity concentration than the first semiconductor region. A second high concentration region of a second conductivity type is provided between the first semiconductor region and the parallel pn layer in the active region, in contact with the first semiconductor region and away from the trench and the first high concentration region. The second high concentration region has a higher impurity concentration than the first semiconductor region.

[0024] Between the first semiconductor region and the parallel pn layer in the intermediate region, a third high concentration region of a second conductivity type is provided in contact with the first semiconductor region. The third high concentration region is electrically connected to the first high concentration region and the second high concentration region. The third high concentration region surrounds the periphery of the active region. The third high concentration region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of a second conductivity type constituting a voltage withstanding structure is selectively provided between the second surface of the semiconductor substrate and the parallel pn layer. The fourth semiconductor region surrounds the periphery of the active region via the intermediate region and is electrically connected to the first semiconductor region via the third high concentration region. A first electrode is electrically connected to the third semiconductor region and the first semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0025] The intermediate region has a first intermediate region where an electrical contact between the first electrode and the first semiconductor region is formed, and a second intermediate region between the first intermediate region and the termination region. The third high concentration region has a protrusion protruding toward the parallel pn layer at a portion facing the first conductivity type region and the second conductivity type region of the parallel pn layer in the depth direction. The second semiconductor region extends from the active region to the intermediate region and reaches the step, and exists between the protrusions of the third high concentration region between the third high concentration region and the parallel pn layer, and is adjacent to the first conductivity type region of the parallel pn layer in the depth direction. The impurity concentration of the second semiconductor region is higher in the second intermediate region than in other portions.

[0026] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the impurity concentration of the second semiconductor region is 1.3 to 1.7 times higher in the second intermediate region than in other portions.

[0027] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the convex portions of the third high concentration region are provided in portions facing respectively the first conductivity type region and the second conductivity type region of the parallel p-n layer in the depth direction.

[0028] Moreover, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the convex portions of the third high concentration region are provided in multiple portions in a depth direction facing each of the first conductivity type regions of the parallel p-n layers.

[0029] In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type region and the second conductivity type region of the parallel p-n layer each extend linearly in a second direction that is parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, and the convex portion of the third high concentration region extends linearly in the second direction.

[0030] In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type region and the second conductivity type region of the parallel p-n layer each extend linearly in a second direction that is parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, and the protrusions of the third high concentration region are scattered in the second direction.

[0031] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a gate runner made of a polysilicon layer is provided on the first main surface of the semiconductor substrate in the second intermediate region via an insulating layer, and an electrical contact between the gate electrode and the gate runner is formed in the second intermediate region.

[0032] According to the above-mentioned invention, the electric field strength distribution in the intermediate region on the front surface side of the semiconductor substrate of the parallel pn layer can be made substantially the same as that in the active region, and the electric field strength in the active region can be made greater than that in the intermediate region, thereby facilitating avalanche breakdown in the active region. Effect of the Invention

[0033] Advantageous Effects of Invention The silicon carbide semiconductor device according to the present invention has an effect of improving avalanche resistance. [Brief description of the drawings]

[0034] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device in accordance with a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] FIG. 3 is an enlarged cross-sectional view showing a part of FIG. 2. [Figure 4] FIG. 3 is an explanatory diagram showing an enlarged view of a part of FIG. 2. [Diagram 5] 5 is an enlarged cross-sectional view showing the inside of a rectangular frame B in FIG. 4. [Figure 6] FIG. 3 is an enlarged cross-sectional view showing a part of FIG. 2. [Figure 7] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 8] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 9] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 10] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 11] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 12] 5 is a cross-sectional view showing another example of a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 13] 5 is a cross-sectional view showing another example of a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 14]13 is a plan view showing a layout of a silicon carbide semiconductor device according to a second embodiment, as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 15] 13 is a plan view showing a layout of a silicon carbide semiconductor device according to a second embodiment, as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 16] 11 is a distribution diagram showing a simulation result of the electric field intensity in the depth direction in Example 1. FIG. [Figure 17] FIG. 13 is a distribution diagram showing a simulation result of electric field strength in the depth direction in a conventional example. [Figure 18] 11 is a distribution diagram showing a simulation result of the electric field strength in the first direction in the first embodiment. FIG. [Figure 19] 19 is an enlarged view showing the inside of a rectangular frame C1 in FIG. 18. [Figure 20] 19 is an enlarged view showing the inside of a rectangular frame C2 in FIG. 18. [Figure 21] FIG. 13 is a distribution diagram showing a simulation result of the electric field strength in the first direction in the conventional example. [Figure 22] FIG. 13 is a distribution diagram showing a simulation result of carrier density during avalanche breakdown in Example 2. [Diagram 23] FIG. 13 is a distribution diagram showing a simulation result of carrier density during avalanche breakdown in a conventional example. [Figure 24] FIG. 13 is a distribution diagram showing a simulation result of the amount of hole current during avalanche breakdown in Example 2. [Diagram 25] FIG. 13 is a distribution diagram showing a simulation result of the amount of hole current at the time of avalanche breakdown in a conventional example. [Figure 26] FIG. 13 is a distribution diagram showing a simulation result of hole current density in the vicinity of the peripheral contact portion of Example 2. [Figure 27] 11 is a distribution diagram showing an impurity concentration in the vicinity of the peripheral contact portion in Example 2. FIG. [Figure 28] FIG. 13 is a distribution diagram showing an impurity concentration in the vicinity of a peripheral contact portion in a conventional example. [Figure 29] FIG. 11 is a characteristic diagram showing a simulation result of the voltage-current characteristic of the second embodiment. [Diagram 30]FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. [Diagram 31] 31 is an enlarged cross-sectional view of the middle region of FIG. 30. FIG. [Diagram 32] 32 is an enlarged cross-sectional view showing the inside of a rectangular frame BB in FIG. 31. [Diagram 33] 31 is an enlarged cross-sectional view of the middle region of FIG. 30. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0036] (Embodiment 1) The structure of a silicon carbide semiconductor device according to the first embodiment will be described. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface (first main surface) side of a semiconductor substrate. In Fig. 1, the inner periphery of a thick rectangular frame showing a gate runner 22a is the boundary between an outer periphery contact region (first intermediate region) 21 and a gate region (second intermediate region) 22. Fig. 2 is a cross-sectional view showing a cross-sectional structure taken along the cutting line A-A' in Fig. 1. Fig. 2 shows a region from near the boundary between an active region 10 and an intermediate region 20 to an end (chip end) of a semiconductor substrate 40.

[0037] 3 and 6 are cross-sectional views showing an enlarged portion of FIG. 2. FIG. 4 is an explanatory diagram showing an enlarged portion of FIG. 2. FIG. 5 is a cross-sectional view showing an enlarged portion of a rectangular frame B in FIG. 4. FIG. 3 shows one unit cell out of a plurality of unit cells (constituent units of an element) arranged in the active region 10, but all the unit cells arranged in the active region 10 have the same structure. FIG. 4 shows the p + A part of the type region 13 is shown. + The mold region 13 has the same configuration throughout the intermediate region 20 .

[0038] The upper diagram of FIG. 4 shows the p + 4 is a plan view showing the layout of the mold region 13 as viewed from the front surface side of the semiconductor substrate 40. The lower diagram of FIG. + FIG. 1 is a cross-sectional view showing the cross-sectional structure of the mold region 13. + The planar layout (upper part of FIG. 4) and the cross-sectional structure (lower part of FIG. 4) of the mold region 13 are the same throughout the intermediate region 20. - The region into which n-type impurities are ion-implanted to form the n-type current diffusion region 3 in the type epitaxial layer 43 is indicated by hatching (the same applies to FIGS. 10 to 13).

[0039] In FIG. 6, in order to clarify the end position of the n-type current diffusion region 3 shown by hatching, - The n-type current diffusion region 3 and the p-type epitaxial layer 43 are formed by ion implantation. + Among the regions 11 to 13, p + The p-type regions 11 to 13 are shown only in outline, and the p-type regions 11 to 13 are shown in outline. + 4 to 6, the gate runner 22a, the gate metal wiring layer 22b, and the field oxide film 36 are omitted (the same applies to FIGS. 16 to 18, 22, 24, and 27).

[0040] Silicon carbide semiconductor device 50 according to the first embodiment shown in Figures 1 and 2 includes an active region 10, an intermediate region 20, and an edge termination region 30 in a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and is a vertical MOSFET with an SJ structure and a trench gate structure in which drift layer 2 serves as a parallel pn layer 60 from active region 10 to edge termination region 30. As shown in Figure 1, active region 10 is located in the center of semiconductor substrate 40 (chip center). Active region 10 is a region through which a main current flows when the MOSFET is in an on-state.

[0041] The intermediate region 20 is a region between the active region 10 and the edge termination region 30, and is adjacent to the active region 10 and surrounds the periphery of the active region 10. The edge termination region 30 is a region between the intermediate region 20 and the end of the semiconductor substrate 40, and surrounds the periphery of the active region 10 via the intermediate region 20. The edge termination region 30 has a function of maintaining a breakdown voltage by mitigating the electric field of the drift layer 2 on the front surface side of the semiconductor substrate 40 in the active region 10 and the intermediate region 20. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the element does not malfunction or break down.

[0042] In edge termination region 30, a breakdown voltage structure such as a junction termination extension (JTE) structure 32 or a field limiting ring (FLR) is disposed on the front surface side of semiconductor substrate 40. Here, an example will be described in which a JTE structure 32 (see FIG. 2) is disposed on the front surface side of semiconductor substrate 40 in edge termination region 30. This breakdown voltage structure reduces electric field concentration outside active region 10, and element breakdown does not occur until a predetermined voltage is applied.

[0043] 2, in the active region 10, a trench gate structure is provided on the front surface side of a semiconductor substrate 40. The trench gate structure includes a p-type base region (first semiconductor region) 4, a n + type source region (third semiconductor region) 5, p ++The semiconductor substrate 40 is made of silicon carbide. + On the front surface of a starting substrate 41, epitaxial layers 42 to 44 which become the drift layer 2, the n-type current diffusion region (second semiconductor region) 3 and the p-type base region 4 are deposited in this order.

[0044] The principal surface of the semiconductor substrate 40 on the side of the p-type epitaxial layer 44 is the front surface, and + The main surface (n + The back surface of the starting substrate 41 is the back surface (second main surface). The crystal plane orientation of the front surface of the semiconductor substrate 40 is, for example, the (0001) plane. + The starting substrate 41 is n + The gate trench 7 penetrates the p-type epitaxial layer 44 from the front surface of the semiconductor substrate 40 in the depth direction Z to form an n-type - The gate insulating layer 44 extends into the type epitaxial layer 43 and in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 (a second direction Y, which will be described later).

[0045] The p-type epitaxial layer 44 in the edge termination region 30 is removed by etching, and a step 31 is formed on the front surface of the semiconductor substrate 40. The front surface of the semiconductor substrate 40 is more etched at the edge termination region 30 portion (second surface) 40b than at the active region 10 side portion (first surface) 40a, with the step 31 as a boundary. + It is recessed towards the type drain region 1. The active region 10 and intermediate region 20 are isolated from the edge termination region 30 at a portion (third surface) 40c of the front surface of the semiconductor substrate 40 that connects the first surface 40a and the second surface 40b.

[0046] A gate electrode 9 is provided inside the gate trench 7 via a gate insulating film 8. The p-type base region 4, + Type source region 5 and p ++The p-type contact regions 6 are selectively provided between adjacent gate trenches 7, and extend linearly in the second direction Y, which is the same direction as the extension of the gate trenches 7. The p-type base region 4 is formed by forming the n-type epitaxial layer 44 in a portion of the p-type epitaxial layer 44 that remains after the step 31 on the front surface of the semiconductor substrate 40 is formed. + Type source region 5 and p ++ This is the portion excluding the mold contact region 6.

[0047] The p-type base region 4 extends from the active region 10 outward (toward the chip end) to reach the third surface 40c of the front surface of the semiconductor substrate 40, and is provided throughout the intermediate region 20. + Type source region 5 and p ++ The n-type contact region 6 is provided between the front surface of the semiconductor substrate 40 and the p-type base region 4, and in contact with the p-type base region 4. + Type source region 5 and p ++ The type contact region 6 is exposed on a first surface 40a on the front surface of the semiconductor substrate 40, and contacts the source electrode (first electrode) 15 through a contact hole in the interlayer insulating film .

[0048] n + The source region 5 faces the gate electrode 9 via the gate insulating film 8 on the side wall of the gate trench 7. ++ The contact region 6 is an n + The p-type source region 5 is disposed at a position farther from the gate trench 7 than the p-type base region 4. An epitaxial layer 42 is provided between the p-type base region 4 and the rear surface of the semiconductor substrate 40. The epitaxial layer 42 is a drift layer 2 that becomes a drift region, and includes a parallel pn layer 60. The parallel pn layer 60 and the n + The portion 2a between the starting substrate 41 and the n-type drift region may be a normal n-type drift region that does not have an SJ structure.

[0049] The parallel pn layer 60 is an epitaxial layer with an SJ structure in which n-type regions (first conductivity type regions) 61 and p-type regions (second conductivity type regions) 62 are alternately and repeatedly arranged in a first direction X parallel to the front surface of the semiconductor substrate 40. The parallel pn layer 60 is formed, for example, by forming an SJ trench penetrating the n-type epitaxial layer in the depth direction Z in an n-type epitaxial layer that becomes the n-type region 61 formed by one-stage (one-time) epitaxial growth using a trench-filling epitaxial method, and then filling the SJ trench with a p-type epitaxial layer that becomes the p-type region 62.

[0050] The n-type region 61 and the p-type region 62 of the parallel p-n layer 60 each extend linearly in a second direction Y that is parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. The second direction Y is, for example, <11-20>. The adjacent n-type region 61 and the p-type region 62 are generally charge-balanced. An n-type region 61a is disposed on the outermost side of the parallel p-n layer 60 along the chip edge. The outermost n-type region 61a of the parallel p-n layer 60 surrounds the periphery of the central portion of the semiconductor substrate 40 and connects all the n-type regions 61 of the parallel p-n layer 60.

[0051] In the active region 10, between the p-type base region 4 and the drift layer 2, an n-type current diffusion region 3 and a p + The n-type regions (first and second high concentration regions) 11 and 12 are selectively provided. + The type regions 11 and 12 are n - The n-type current diffusion region 3 is a diffusion region formed by ion implantation inside the p-type epitaxial layer 43. The n-type current diffusion region 3 extends outward from the active region 10 between the p-type base region 4 and the drift layer 2, reaching the third surface 40c on the front surface of the semiconductor substrate 40, and is provided throughout the entire intermediate region 20 (see FIG. 6).

[0052] The n-type current diffusion region 3 is a so-called current diffusion layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is disposed between adjacent gate trenches 7 in the active region 10 and adjacent to the gate trench 7. The n-type current diffusion region 3 is located n-type closer to the gate trench 7 than the gate trench 7.+ The n-type current spreading region 3 extends deep into the gate trench 7 and the p-type drain region 1 in the active region 10. + Type region 11 and p + The p-type region 12 is adjacent to the p-type base region 4 and the n-type region 61 of the parallel pn layer 60 in the depth direction Z.

[0053] The n-type current diffusion region 3 extends outward from the active region 10 to reach the third surface 40c of the front surface of the semiconductor substrate 40. Thus, the n-type current diffusion region 3 is provided throughout the active region 10 and the intermediate region 20. In the intermediate region 20, the n-type current diffusion region 3 is p + A p-type region 13 is provided between the parallel pn layer 60 and, as will be described later, + The third high concentration region 13 is located between the protrusions 13a, and the p + The n-type region 13 is adjacent to the n-type region 61 of the parallel pn layer 60 .

[0054] The n-type current spreading region 3 is a p + p in the type regions 11, 12 and the intermediate region 20 + The protrusion 13a of the mold region 13 is + The p-type drain region 1 reaches a deep position. + The n-type current diffusion region 3 shown by hatching in FIG. + The portion overlapping with the mold regions 11 to 13 is n - These are the portions that become the p-type regions 11-13 by ion implantation of p-type impurities for forming the p-type regions 11-13 inside the type epitaxial layer 43.

[0055] The impurity concentration of the n-type current diffusion region 3 is higher in the gate region 22 described below than in other portions (the active region 10 and the peripheral contact region 21 described below), and is preferably about 1.3 to 1.7 times higher in the gate region 22 than in other portions. The higher the impurity concentration in the gate region 22 of the n-type current diffusion region 3, the thicker the effective thickness of the drift region can be in the intermediate region 20 than in the active region 10. This allows the electric field strength in the intermediate region 20 to be relatively small.

[0056] p + The mold regions 11 and 12 have the function of reducing the electric field applied to the bottom surface of the gate trench 7. + The n-type region 11 faces the bottom surface of the gate trench 7 and the n-type region 61 of the parallel pn layer 60 in the depth direction Z. + The n-type region 11 is located closer to the front surface of the semiconductor substrate 40 than the interface between the p-type base region 4 and the n-type current diffusion region 3. + The p-type region 62 of the parallel pn layer 60 is disposed at a deep position on the side of the p-type drain region 1 and is separated from the p-type base region 4. + The type region 11 may be in contact with the n-type region 61 of the parallel pn layer 60 in the depth direction Z.

[0057] p + The p-type region 12 is disposed between the adjacent gate trenches 7. + The gate trench 7 is provided apart from the mold region 11. + The p-type region 12 contacts the p-type base region 4 and the p-type region 62 of the parallel pn layer 60 in the depth direction Z. The interlayer insulating film 14 covers the entire front surface of the semiconductor substrate 40, except for the contact portion of the active region 10 and a peripheral contact portion 21a, which will be described later. The contact portion of the active region 10 is connected to the source electrode 15 and the n-type region 62 of the parallel pn layer 60. + Type source region 5 and p ++ This is an ohmic contact portion with the type contact region 6 .

[0058] The intermediate region 20 is located outside the center of the outermost gate trench 7 in the first direction X and n +The region is located outside the end of the p-type source region 5 and extends to the step 31. The source electrode 15 extends from the active region 10 to a portion (peripheral contact region) 21 inside the intermediate region 20 (toward the center of the chip). + Mold peripheral contact region 21b(p + When the p-type peripheral contact region 21b is not provided, an ohmic contact portion (electrical contact portion: hereinafter referred to as peripheral contact portion) 21a with the p-type base region 4) is formed.

[0059] The peripheral contact region 21 is a portion between the active region 10 and an inner peripheral end of a gate runner 22a disposed in a gate region 22 described later. The peripheral contact portion 21a is formed in a contact hole 14a penetrating an insulating layer (interlayer insulating film 14, etc.) described later that covers the front surface of the semiconductor substrate 40 in the intermediate region 20 and the edge termination region 30 in the depth direction Z. + The p-type peripheral contact region 21b is selectively provided between the first surface 40a on the front surface of the semiconductor substrate 40 and the p-type base region 4 in the peripheral contact region 21.

[0060] When the MOSFET is off, minority carriers (holes) generated in drift layer 2 in edge termination region 30 are discharged through p-type base region 4 and peripheral contact 21a to source electrode 15. The front surface of semiconductor substrate 40 in intermediate region 20 and edge termination region 30 (portions of the front surface of semiconductor substrate 40 outside peripheral contact 21a) is covered with an insulating layer in which field oxide film 36 and interlayer insulating film 14 are laminated in this order.

[0061] In a portion (gate region) 22 of the intermediate region 20 outside the peripheral contact region 21, a gate runner 22a made of a polysilicon (poly-Si) layer is provided on the field oxide film 36. The gate runner 22a is covered with an interlayer insulating film 14. A gate metal wiring layer 22b is provided on the gate runner 22a via a contact hole in the interlayer insulating film 14. The gate runner 22a and the gate metal wiring layer 22b are electrically connected to the gate pad 16 (see FIG. 1).

[0062] The gate region 22 surrounds the active region 10 via the peripheral contact region 21. In the gate region 22, a gate electrode 9 extends from the active region 10, and a contact portion (electrical contact portion: not shown) between the gate runner 22a and the gate electrode 9 is formed. The gate runner 22a extends along the inner periphery of the gate region 22 and surrounds the active region 10. The gate metal wiring layer 22b extends along the gate runner 22a and surrounds the active region 10.

[0063] In addition, over the entire intermediate region 20, between the p-type base region 4 and the parallel pn layer 60 (drift layer 2), + A mold area 13 is provided. + The type region 13 has an n - The inside of the p-type epitaxial layer 43 + The diffusion region is formed by ion implantation simultaneously with the mold regions 11 and 12. + The mold region 13 surrounds the active region 10. + The p-type region 13 extends inward to the active region 10. + It is in contact with and electrically connected to the mold regions 11 and 12 .

[0064] p + The p-type region 13 extends outward to a third surface 40c of the front surface of the semiconductor substrate 40 and contacts the innermost p-type region of the JTE structure 32, which will be described later. + The entire surface of the p-type region 13 on the p-type base region 4 side is in contact with the p-type base region 4. + The type region 13 has protrusions 13a protruding toward the parallel pn layer 60 at portions facing the n-type region 61 and the p-type region 62 of the parallel pn layer 60 in the depth direction Z. + The thickness of the mold region 13 is thinner in the portions between the protrusions 13a than in the portions of the protrusions 13a (see the lower diagram of FIG. 4 and FIG. 5).

[0065] p +The number of protrusions 13a of the type region 13 is the same as the number of n-type regions 61 and p-type regions 62 of the parallel pn layer 60 in the intermediate region 20, and they are spaced apart at a predetermined interval in the first direction X. + The protrusions 13a of the type region 13 extend in a stripe shape in the second direction Y, which is the same direction as the extension of the n-type region 61 and the p-type region 62 of the parallel pn layer 60 (see the upper diagram in FIG. 4). + 1 shows a layout of a protrusion 13a of the type region 13 facing an n-type region 61 of the parallel pn layer 60 in the depth direction Z, and the n-type region 61 and p-type region 62 of the parallel pn layer 60.

[0066] p + The protrusion 13a of the n-type region 13 facing the n-type region 61 in the depth direction Z is in contact with the n-type region 61 or faces the n-type region 61 in the depth direction Z via the n-type current diffusion region 3. + A protrusion 13a of the n-type region 13 facing the n-type region 61 in the depth direction Z is disposed apart from the p-type region 62. + The protrusion 13a of the p-type region 13 facing the p-type region 62 in the depth direction Z is in contact with the p-type region 62. + Between the protrusions 13a of the type region 13, the n-type current diffusion region 3 is present adjacent to the n-type region 61 in the depth direction Z.

[0067] p + The n-type current diffusion region 3 between the protruding portions 13a of the n-type region 13 reduces the substantial thickness of the drift region of the intermediate region 20 (the drift layer 2 and + The total thickness t1 (FIG. 5) of n-type current diffusion region 3 between protrusions 13a of type region 13 is thicker than the substantial thickness t101 (FIG. 32) of the drift region (drift layer 102) of intermediate region 120 in the conventional structure. Therefore, compared with the conventional structure, the substantial thickness t1 of the drift region of intermediate region 20 approaches the substantial thickness (the total thickness of drift layer 2 and n-type current diffusion region 3) of the drift region of active region 10.

[0068] As a result, on the front surface side of the parallel pn layer 60 relative to the semiconductor substrate 40, the electric field strength distribution in the intermediate region 20 becomes substantially the same as the electric field strength distribution in the active region 10 (see FIGS. 16, 18 to 20). As described above, the impurity concentration of the n-type current diffusion region 3 is relatively high in the gate region 22 portion, thereby making the electric field strength distributions of the active region 10 and the intermediate region 20 substantially the same, and therefore the electric field strength in the active region 10 can be made greater than the electric field strength in the intermediate region 20.

[0069] In the edge termination region 30, the second surface 40b of the front surface of the semiconductor substrate 40 has n - The n-type epitaxial layer 43 is exposed. - A plurality of p-type regions constituting a JTE structure 32 are selectively provided inside the type epitaxial layer 43. The JTE structure 32 has a plurality of p-type regions with different impurity concentrations arranged adjacent to each other in a concentric circle shape surrounding the active region 10 such that the p-type regions with lower impurity concentrations are arranged from the inside to the outside.

[0070] The multiple p-type regions constituting the JTE structure 32 are - The p-type epitaxial layer 43 is a diffusion region formed by ion implantation and exposed on the second surface 40b of the front surface of the semiconductor substrate 40. The p-type regions constituting the JTE structure 32 are arranged in a direction Z such that the n-type epitaxial layer 43 is a diffusion region. - The p-type epitaxial layer 43 is formed on the first surface 40c of the semiconductor substrate 40, and the p-type base region 4 and the p-type region 62 are formed on the second surface 40c of the semiconductor substrate 40. + The mold area 13 is exposed.

[0071] The multiple p-type regions constituting the JTE structure 32 are p-type regions near the third surface 40c of the front surface of the semiconductor substrate 40. + 2, the p-type regions of the JTE structure 32 are electrically connected to the p-type base region 4 through the p-type region 13. -The fourth semiconductor region is shown as a type region (fourth semiconductor region) 33. Being exposed to the second and third faces 40b, 40c of the front surface of the semiconductor substrate 40 means that the fourth semiconductor region is provided in a surface region of the second and third faces 40b, 40c of the front surface of the semiconductor substrate 40 and in contact with the interlayer insulating film 14 on the second and third faces 40b, 40c of the front surface of the semiconductor substrate 40.

[0072] In addition, in the surface region of the second surface 40b of the front surface of the semiconductor substrate 40, there is provided a n + A die stopper region 34 is selectively provided. The JTE structure 32 and the n-type semiconductor substrate 40 are disposed on a second surface 40b of the front surface of the semiconductor substrate 40. + Between the mold stopper region 34, n - The n-type epitaxial layer 43 is exposed. + The mold stopper region 34 is exposed at the second surface 40b of the front surface of the semiconductor substrate 40 and at the edge of the semiconductor substrate 40. + The type stopper region 34 may face the parallel pn layer 60 in the depth direction Z.

[0073] The second and third faces 40b and 40c of the front surface of the semiconductor substrate 40 are covered with an insulating layer in which a field oxide film and an interlayer insulating film 14 are laminated in this order, as described above. The passivation film 35 covers the entire front surface of the semiconductor substrate 40 to protect the front surface of the semiconductor substrate 40. The portion of the source electrode 15 exposed from the opening of the passivation film 35 becomes a source pad. The back surface (n + A drain electrode (second electrode) 17 is provided on the entire back surface of the starting mold substrate 41.

[0074] Next, a manufacturing method of silicon carbide semiconductor device 50 according to the first embodiment will be described with reference to Figs. 7 to 11. Figs. 7 to 11 are cross-sectional views showing a state during manufacturing of the silicon carbide semiconductor device according to the first embodiment. Figs. 12 and 13 are cross-sectional views showing another example of a state during manufacturing of the silicon carbide semiconductor device according to the first embodiment. Figs. 7 to 9 show only active region 10. Figs. 10 to 13 show intermediate region 20.

[0075] First, as shown in Figure 7, + n-type drain region 1 + A starting substrate 41 is prepared. + The starting substrate 41 may have a crystal structure of, for example, a four-layer hexagonal crystal structure of silicon carbide (4H-SiC), and the front surface may be a (0001) surface, i.e., a so-called Si surface. + On the front surface of a starting mold substrate 41, an n-type epitaxial layer 42 which becomes the drift layer 2 is epitaxially grown (formed).

[0076] Next, for example, by photolithography and etching, an etching mask (not shown) made of, for example, an oxide film or the like, having openings corresponding to regions where the p-type regions 62 of the parallel pn layer 60 are to be formed, is formed on the surface of the epitaxial layer 42. Next, the epitaxial layer 42 is, for example, dry-etched using this etching mask to form trenches (SJ trenches) 63 extending in a stripe shape in the second direction Y.

[0077] The portions of the epitaxial layer 42 remaining between the adjacent SJ trenches 63 become the n-type regions 61 of the parallel pn layer 60. + The portion on the starting substrate 41 side is a normal n-type drift region (parallel pn layer 60 and n + This becomes the portion 2a) between the mold starting substrate 41. Then, the etching mask used for forming the SJ trench 63 is removed.

[0078] Prior to the formation of the epitaxial layer 42, + Another n-type epitaxial layer to become an n-type buffer region (not shown) may be epitaxially grown on the front surface of the starting substrate 41. In this case, an SJ trench 63 may be formed that penetrates the epitaxial layer 42 epitaxially grown on the other n-type epitaxial layer to become the n-type buffer region in the depth direction Z and reaches the n-type buffer region.

[0079] Next, a p-type epitaxial layer is epitaxially grown (formed) to fill the inside of the SJ trench 63. Next, excess p-type epitaxial layer on the surface of the epitaxial layer 42 is removed to leave the p-type epitaxial layer that will become the p-type region 62 of the parallel p-n layer 60 only inside the SJ trench 63. Through the steps up to this point, the epitaxial layer 42 including the parallel p-n layer 60 that will become the drift layer 2 is formed.

[0080] n + The parallel pn layer 60 may be formed by forming a p-type epitaxial layer 42 on a starting substrate 41, forming an SJ trench 63 penetrating the epitaxial layer 42 in the depth direction Z to leave a portion that will become a p-type region 62, and filling the SJ trench 63 with an n-type epitaxial layer that will become an n-type region 61. + The entire epitaxial layer 42 is made into the parallel pn layer 60 so that no p-type region remains between the starting substrate 41 and the parallel pn layer 60 .

[0081] Instead of the trench filling epitaxial method, the parallel pn layer 60 may be formed by a multi-stage epitaxial method. In the multi-stage epitaxial method, the n-type epitaxial layer that becomes the n-type region 61 is gradually thickened by multiple stages of epitaxial growth until it reaches a predetermined thickness, and ion implantation for selectively forming the p-type region 62 (or the n-type region 61 and the p-type region 62) is repeated for each stage of epitaxial growth.

[0082] Next, on the parallel pn layer 60, - Next, an n-type epitaxial layer 43 is epitaxially grown (formed) in the active region 10 by photolithography and ion implantation of p-type impurities. - The surface region of the p-type epitaxial layer 43 is + The mold regions 11 and 12a are selectively formed. + Type region 11 and p + The mold regions 12a and 12b are alternately and repeatedly arranged in the first direction X (see FIG. 2).

[0083] Also, p+ At the same time as the formation of the type regions 11 and 12a, n - The surface region of the p-type epitaxial layer 43 is + The protruding portion 13a (see FIG. 5) of the mold region 13 is p + Selectively form a mold region. + The protruding portion 13a of the mold region 13 is p + The type regions are disposed at positions facing the n-type region 61 and the p-type region 62 of the parallel pn layer 60 in the depth direction Z, and are spaced apart at a predetermined interval in the first direction X.

[0084] Next, photolithography and ion implantation of n-type impurities are used to create n - An n-type region 3a is formed in the surface region of the p-type epitaxial layer 43. The n-type region 3a is formed in the entire active region 10 and intermediate region 20 (see FIG. 10). The n-type region 3a is + Between the mold regions 11 and 12a and the intermediate region 20 + The n-type region 3a and the p-type region 3b are formed between the protruding portions 13a of the p-type region 13. + The order of forming the mold regions 11, 12a, and 13 (13a) may be reversed.

[0085] Next, as shown in FIG. - The thickness of the p-type epitaxial layer 43 is then increased. Next, the n-type epitaxial layer 43 is formed in the active region 10 by photolithography and ion implantation of p-type impurities. - The thickened portion 43a of the epitaxial layer 43 is p + The mold region 12b is selectively formed, and p + Type regions 12a and p + The mold region 12b is connected to p + A mold region 12 is formed.

[0086] Also, p + At the same time as the formation of the type region 12b, the n - The thickened portion 43a of the epitaxial layer 43 is p + This intermediate region 20 forms the remaining portion of the mold region 13. -The p-type epitaxial layer 43 is formed in the entire area of ​​the thickened portion 43a. + In type region 13, n - The p-type epitaxial layer 43 is already formed inside the + All the portions that will become the protruding portions 13a of the mold region 13 are connected together (see FIG. 5).

[0087] Next, photolithography and ion implantation of n-type impurities are used to create n - An n-type region 3b is formed in a thickened portion 43a of the epitaxial layer 43, and the n-type regions 3a and 3b adjacent to each other in the depth direction Z are connected to form an n-type current spreading region 3. The n-type region 3b is formed in the entire active region 10 and intermediate region 20 (see FIG. 10). In FIG. 10, reference numeral 71 denotes ion implantation for forming the n-type regions 3a and 3b.

[0088] Next, n - An ion implantation mask 72 having an opening in the gate region 22 of the intermediate region 20 is formed on the surface of the n-type epitaxial layer 43. Next, using the ion implantation mask 72, n-type impurities are again ion-implanted 73 into the gate region 22 of the n-type current diffusion region 3, thereby making the impurity concentration of the n-type current diffusion region 3 higher in the gate region 22 than in other portions (the active region 10 and the peripheral contact region 21) (see FIG. 11).

[0089] By setting the dose of this ion implantation 73 to, for example, about 0.3 to 0.7 times the dose of ion implantation 71, the impurity concentration in the gate region 22 of the n-type current diffusion region 3 can be made to be the suitable impurity concentration described above (an impurity concentration that is about 1.3 to 1.7 times the impurity concentration in the active region 10 and peripheral contact region 21 of the n-type current diffusion region 3).

[0090] The formation of the ion implantation mask 72 and the ion implantation 73 may be performed each time the n-type regions 3a and 3b are formed. Therefore, the ion implantation 73 for increasing the impurity concentration in the gate region 22 of the n-type region 3a and the p +It is possible to interchange the order of forming the type regions 12b and 13, forming the n-type region 3b, and performing the ion implantation 73 for increasing the impurity concentration in the portion of the n-type region 3b that is adjacent to the gate region 22.

[0091] Alternatively, after forming the n-type regions 3a, 3b only in the active region 10 and the peripheral contact region 21 of the intermediate region 20 (see FIG. 12), the gate region 22 of the n-type regions 3a, 3b may be formed with the above-mentioned suitable impurity concentration of the gate region 22 of the n-type current diffusion region 3 by a single ion implantation 77 (see FIG. 13). That is, the dose of the ion implantation 77 may be set to, for example, about 1.3 to 1.7 times the dose of the ion implantation 71.

[0092] 12 and 13, formation of an ion implantation mask 74 and ion implantation 75 for forming n-type regions 3a, 3b only in active region 10 and peripheral contact region 21 may be performed each time n-type regions 3a, 3b are formed. Formation of an ion implantation mask 76 and ion implantation 77 for forming portions of gate region 22 of n-type regions 3a, 3b may be performed each time n-type regions 3a, 3b are formed.

[0093] Next, as shown in Figure 9, - On the n-type epitaxial layer 43, a p-type epitaxial layer 44 that will become the p-type base region 4 is epitaxially grown. + On the front surface of the starting substrate 41, an epitaxial layer 42, n - A semiconductor substrate (semiconductor wafer) 40 is fabricated in which a n-type epitaxial layer 43 and a p-type epitaxial layer 44 are laminated in this order, and the parallel pn layer 60 is included in the epitaxial layer 42 that will become the drift layer 2.

[0094] Next, the portion of p-type epitaxial layer 44 in edge termination region 30 is removed by etching to form a step 31 on the front surface of semiconductor substrate 40, the step 31 being lower in edge termination region 30 (second surface 40b) than in the portion on the active region 10 side (first surface 40a) (see FIG. 2). - The epitaxial layer 43 is exposed.

[0095] The portion (third surface 40c) between the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40 may form an obtuse angle with the first and second surfaces 40a and 40b, for example. + The etching that forms the step 31 exposes the n-type region 13. - A portion of the type epitaxial layer 43 that is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 may be slightly removed.

[0096] Next, a set of photolithography and ion implantation steps is repeated under different conditions to obtain n + Type source region 5, p ++ Type contact region 6, p + The p-type peripheral contact region 21b, the p-type region (p - type region 33), and n + The die stopper regions 34 are selectively formed. + Type source region 5, p ++ Type contact region 6 and p + The outer peripheral contact regions 21b are formed in the surface region of the p-type epitaxial layer 44, respectively.

[0097] The p-type epitaxial layer 44 has an n + Type source region 5, p ++ Type contact region 6 and p + The portion excluding the peripheral contact region 21b becomes the p-type base region 4. The p-type region and the n-type +The die stopper region 34 is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 in the edge termination region 30. - The gate electrodes are selectively formed on the surface region of the epitaxial layer 43 .

[0098] Next, a heat treatment (hereinafter, referred to as activation annealing) is performed to activate the impurities ion-implanted into the epitaxial layers 43 and 44. Next, in the active region 10, n + The p-type current diffusion region 3 penetrates the p-type source region 5 and the p-type base region 4. + A gate trench 7 is formed so as to reach the mold region 11. Next, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7.

[0099] Next, the polysilicon layer deposited on the front surface of the semiconductor substrate 40 is etched back so as to fill the inside of the gate trench 7, leaving a portion that will become the gate electrode 9 inside the gate trench 7. A field oxide film (not shown) is formed on the front surface of the semiconductor substrate 40 in the intermediate region 20 and the edge termination region 30. A gate runner 22a (see FIGS. 1 and 2) made of a polysilicon layer is formed on the field oxide film in the intermediate region 20.

[0100] Next, an interlayer insulating film 14 is formed over the entire front surface of the semiconductor substrate 40. Next, surface electrodes (source electrode 15, gate pad 16 (see FIG. 1), gate metal wiring layer 22b (see FIGS. 1 and 2), and drain electrode 17) are formed on both sides of the semiconductor substrate 40 by a general method. All of the gate electrodes 9 are electrically connected to the gate pad 16 via the gate runner 22a and the gate metal wiring layer 22b.

[0101] Next, the front surface of the semiconductor substrate 40, excluding a part of the source electrode 15 (a part to become a source pad), the gate pad 16, and the gate metal wiring layer 22b, is covered and protected with a passivation film 35. Thereafter, the semiconductor wafer (semiconductor substrate 40) is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 50 shown in FIGS.

[0102] As described above, according to the first embodiment, the p-type base region is provided between the parallel pn layer and the p-type base region in the intermediate region. + By forming a protrusion in the type region that protrudes toward the parallel pn layer, the electric field distribution in the intermediate region is made substantially the same as that in the active region on the front surface side of the semiconductor substrate of the parallel pn layer. In addition, an n-type current diffusion region is provided in the entire active region and intermediate region, and the impurity concentration of the n-type current diffusion region is made higher in the gate region of the intermediate region than in other portions (the active region and the peripheral contact region of the intermediate region).

[0103] This allows the electric field strength in the active region to be greater than that in the intermediate region, making avalanche breakdown more likely in the active region. Avalanche breakdown in the active region allows hole current (avalanche current) to flow throughout the entire active region, making it possible to reduce the hole current density in the peripheral contact region and suppress current concentration in the peripheral contact region. This improves the avalanche resistance in the intermediate region, thereby improving the avalanche resistance of the entire silicon carbide semiconductor device.

[0104] (Embodiment 2) Next, a structure of a silicon carbide semiconductor device according to a second embodiment will be described. Figures 14 and 15 are plan views showing a layout of the silicon carbide semiconductor device according to the second embodiment as viewed from the front surface side of the semiconductor substrate. Silicon carbide semiconductor devices 80 and 80' according to the second embodiment have p + The layout of protrusions 81, 81' of mold region 13 differs from that of silicon carbide semiconductor device 50 according to the first embodiment (see the upper diagram in FIG. 4).

[0105] In silicon carbide semiconductor device 80 according to the second embodiment shown in FIG. + The type region 13 has protrusions 81 that protrude toward the parallel pn layer 60 at portions facing the n-type region 61 and the p-type region 62 of the parallel pn layer 60 in the depth direction Z. + As in the first embodiment, the protrusions 81 of the type region 13 are arranged in stripes extending in the second direction Y, which is the same direction as the n-type region 61 and the p-type region 62 of the parallel pn layer 60.

[0106] p + The protrusion 81 of the n-type region 13 facing the n-type region 61 in the depth direction Z is p + A plurality of protrusions 81 (two in FIG. 14 ) are disposed at a distance from each other between adjacent protrusions 81 of n-type region 13 facing p-type region 62 in the depth direction Z. + The linear projections 81 of the mold region 13 face each other. + The number of protrusions 81 in the type region 13 is greater than the number of n-type regions 61 and p-type regions 62 in the parallel pn layer 60 in the intermediate region 20 .

[0107] In a silicon carbide semiconductor device 80′ according to the second embodiment shown in FIG. + The type region 13 has protrusions 81' protruding toward the parallel pn layer 60 at portions facing the n-type region 61 and the p-type region 62 of the parallel pn layer 60 in the depth direction Z. + The protrusions 81' of the mold region 13 facing the n-type region 61 in the depth direction Z have, for example, a substantially rectangular planar shape and are arranged in a matrix at predetermined intervals in the second direction Y.

[0108] A silicon carbide semiconductor device 80' according to the second embodiment shown in Fig. 15 may be applied to a silicon carbide semiconductor device 80 according to the second embodiment shown in Fig. 14, and a plurality of protrusions facing each of the n-type regions 61 in the depth direction Z of the parallel p-n layer 60 may be scattered in the second direction Y. That is, a plurality of protrusions may be arranged in a matrix shape facing each of the n-type regions 61 in the depth direction Z of the parallel p-n layer 60.

[0109] p + The protrusions 81, 81′ of the p-type region 13 facing the p-type region 62 in the depth direction Z are not shown in the figure. + A protrusion 81 of the p-type region 13 facing one p-type region 62 in the depth direction Z extends linearly in the second direction Y, similar to the first embodiment. + A protrusion 81' of the mold region 13 facing one p-type region 62 in the depth direction Z extends linearly in the second direction Y, similar to the first embodiment.

[0110] The method for manufacturing silicon carbide semiconductor device 80, 80′ according to the second embodiment is the same as the method for manufacturing silicon carbide semiconductor device 50 according to the first embodiment, except that p + The ion implantation mask pattern used for the ion implantation to form the convex portions 81, 81' of the mold region 13 may be changed.

[0111] As described above, according to the second embodiment, the p-type base region is provided between the parallel pn layer and the p-type base region in the intermediate region. + The p-type region (p-type base region electrically connects the p-type region of the JTE structure) + Even when the layout (stripes or matrix) of the protrusions of the n-type region of the parallel pn layer facing the n-type region in the depth direction is changed in various ways, the same effects as those of the first embodiment can be obtained.

[0112] According to the second embodiment, the p-type base region is provided between the parallel pn layer and the p-type base region in the intermediate region. + By providing multiple protrusions in the type region facing one of the n-type regions of the parallel pn layer in the depth direction, the ratio of the n-type current diffusion region between the parallel pn layer and the p-type base region in the intermediate region can be increased. This makes the effective thickness of the drift region in the intermediate region thicker and the electric field strength in the active region higher than in the intermediate region, making avalanche breakdown easier in the active region.

[0113] Example 1 The electric field strength in intermediate region 20 of silicon carbide semiconductor device 50 (see FIGS. 1 to 6) according to the first embodiment was examined. FIGS. 16 and 17 are distribution diagrams showing simulation results of the electric field strength in the depth direction for Example 1 and the conventional example, respectively. FIGS. 18 and 21 are distribution diagrams showing simulation results of the electric field strength in the first direction for Example 1 and the conventional example, respectively. FIG. 19 is an enlarged view showing the inside of rectangular frame C1 in FIG. 18. FIG. 20 is an enlarged view showing the inside of rectangular frame C2 in FIG. 18.

[0114] For active region 10 and intermediate region 20 of silicon carbide semiconductor device 50 according to the above-described first embodiment (hereinafter referred to as Example 1), the electric field strength distribution in depth direction Z is shown in FIG. 16, and the electric field strength distribution in first direction X is shown in FIGS. 18 to 20. + In order to obtain an electric field strength distribution obtained by the protrusion 13a provided at the interface between the type region 13 and the drift region, the impurity concentration of the n-type current diffusion region 3 is made the same throughout the active region 10 and the intermediate region 20 (the peripheral contact region 21 and the gate region 22).

[0115] For comparison, for a conventional silicon carbide semiconductor device 150 (hereinafter referred to as the conventional example: see Figs. 30 to 33), the electric field strength distribution in the depth direction Z of active region 110 and intermediate region 120 is shown in Fig. 17, and the electric field strength distribution in the first direction X of intermediate region 120 is shown in Fig. 21. The electric field strength distribution in the first direction X of active region 110 of the conventional example is the same as the electric field strength distribution in the first direction X of active region 10 of Example 1, and is shown with the reference numerals in Fig. 19 in the 100s. The conventional example differs from Example 2 in the following two points.

[0116] The first difference is that +The second difference is that the interface between the drift region and the n-type region 113 is a flat surface parallel to the front surface of the semiconductor substrate 140. The second difference is that the n-type current spreading region 103 is provided only in the active region 110 and the peripheral contact region 121 of the intermediate region 120, and is not provided in the gate region 122 of the intermediate region 120. The impurity concentration of the n-type current spreading region 103 is the same throughout the active region 110 and the peripheral contact region 121 of the intermediate region 120.

[0117] In the conventional example, it was confirmed that the electric field strength distribution of the intermediate region 120 on the front surface side of the parallel pn layer 160 relative to the active region 110 in both the depth direction Z and the first direction X differs from that of the active region 110, and the electric field strength is greater in the intermediate region 120 than in the active region 110 (FIGS. 17, 19, and 21). On the other hand, in Example 1, it was confirmed that the electric field strength distribution of the intermediate region 20 on the front surface side of the parallel pn layer 60 relative to the semiconductor substrate 40 is substantially the same as that of the active region 10 in both the depth direction Z and the first direction X (FIGS. 16, 18 to 20).

[0118] Although the electric field distribution in the second direction Y is not shown, in the first embodiment, on the front surface side of the semiconductor substrate 40 of the parallel pn layer 60, the electric field distribution in the intermediate region 20 is also substantially the same as the electric field distribution in the active region 10 in the second direction Y. + It was confirmed that by forming the convex portion 13a in the mold region 13, the electric field strength distribution in the intermediate region 20 on the front surface side of the semiconductor substrate 40 of the parallel pn layer 60 can be made substantially the same as the electric field strength distribution in the active region 10.

[0119] Example 2 The amount of minority carrier (hole) current in intermediate region 20 during avalanche breakdown in silicon carbide semiconductor device 50 (see FIGS. 1 to 6) according to the first embodiment was examined. Figures 22 and 23 are distribution diagrams showing simulation results of carrier density during avalanche breakdown (when impact ion phenomenon occurs) in Example 2 and the conventional example, respectively. Figures 24 and 25 are distribution diagrams showing simulation results of hole current during avalanche breakdown in Example 2 and the conventional example, respectively.

[0120] 22 and 24 show the carrier density distribution and the hole current amount distribution during avalanche breakdown in silicon carbide semiconductor device 50 according to the above-mentioned first embodiment (hereinafter referred to as Example 2), respectively. Example 2 differs from Example 1 in that the impurity concentration of n-type current diffusion region 3 is 1.5 times higher in gate region 22 than in active region 10 and peripheral contact region 21. For comparison, FIGS. 23 and 25 show the carrier density distribution and the hole current amount distribution during avalanche breakdown in the above-mentioned conventional example, respectively.

[0121] In the conventional example, the increase in carrier density due to the impact ion phenomenon is greater in the intermediate region 120 than in the active region 110, and avalanche breakdown occurs in the gate region 122 (FIG. 23). This avalanche breakdown causes a sudden increase in hole current (avalanche current) in the gate region 122, and a large amount of hole current flows into the p + Through the type region 113, + The p-type peripheral contact region 121b is discharged to the source electrode 115. + It was confirmed that the hole current was concentrated in the mold region 113 and the peripheral contact portion 121a (FIG. 25).

[0122] On the other hand, in Example 2, it was confirmed that the increase in carrier density due to the impact ion phenomenon was larger in the active region 10 than in the intermediate region 20, and that avalanche breakdown was more likely to occur in the active region 10 (FIG. 22). It was confirmed that the hole current (avalanche current) increased rapidly mainly in the active region 10 due to the avalanche breakdown, and the hole current was dispersed to the contact portion of the active region 10 and the peripheral contact portion 21a of the intermediate region 20 and discharged to the source electrode 15, thereby suppressing the concentration of the hole current in the peripheral contact portion 21a of the intermediate region 20 (FIG. 24).

[0123] The reason why Example 2 is prone to avalanche breakdown in the active region 10 is as follows. Since the impurity concentration of the n-type current diffusion region 3 is relatively high in the gate region 22, the effective thickness of the drift region is thicker in the intermediate region 20 than in the active region 10, and the electric field strength in the intermediate region 20 can be made relatively small. In addition, since the electric field strength distributions in the active region 10 and the intermediate region 20 are almost the same (see FIGS. 16, 18 to 20), the electric field strength in the active region 10 can be made greater than the electric field strength in the intermediate region 20.

[0124] Furthermore, it was confirmed that in both Example 2 and the conventional example, the avalanche breakdown was suppressed at the outer ends D1, D101 (the outer ends of the outermost p-type regions constituting the JTE structure 32) of the JTE structures 32, 132 by using the SJ structure (the drift layer 2 is the parallel pn layer 60). The inventors have also confirmed that it is sufficient for the SJ structure to face the JTE structure 32 in the depth direction Z, and that the above results of Example 2 (FIGS. 22 and 24) can be obtained even if the SJ structure is not provided up to the end of the semiconductor substrate 40.

[0125] FIG. 26 shows hole current density distributions near the peripheral contact portions 21a, 121a of Example 2 and the conventional example. FIG. 26 is a distribution diagram showing a simulation result of hole current density near the peripheral contact portion of Example 2. FIGS. 27 and 28 are distribution diagrams showing impurity concentrations near the peripheral contact portions of Example 2 and the conventional example, respectively. The horizontal axis of FIGS. 26 to 28 is the distance in the first direction X, and indicates the same position in the first direction X. The vertical axis of FIG. 26 is hole current density. The vertical axis of FIGS. 27 and 28 is the distance (depth) in the depth direction Z.

[0126] 26, it was confirmed that in Example 2, the hole current density in the peripheral contact portion 21a can be reduced compared to the conventional example. In this way, by causing avalanche breakdown in the active region 10 during off-state and causing a large amount of hole current (avalanche current) to flow mainly in the active region 10, the hole current density in the peripheral contact portion 21a can be reduced and the avalanche resistance in the intermediate region 20 can be improved. This makes it possible to improve the avalanche resistance of the entire Example 2.

[0127] Moreover, the breakdown voltage (static breakdown voltage) of Example 2 was verified. Voltage-current characteristics of Example 2 and the conventional example are shown in FIG. 29. FIG. 29 is a characteristic diagram showing a simulation result of the voltage-current characteristic of Example 2. The horizontal axis of FIG. 29 is the drain-source voltage Vd, and the vertical axis is the drain-source current Id. From the results shown in FIG. 29, it was confirmed that Example 2 can obtain a breakdown voltage comparable to that of the conventional example due to the charge balance of the SJ structure. Therefore, Example 2 can improve the avalanche breakdown voltage (dynamic breakdown voltage) while maintaining the breakdown voltage.

[0128] Although not shown, it has been confirmed by the present inventors that by making the impurity concentration of n-type current diffusion region 3 higher in gate region 22 than in other portions (active region 10 and peripheral contact region 21), an effect similar to that of Example 2 can be obtained, and that the effect is particularly high when the impurity concentration in gate region 22 is 1.3 to 1.7 times that of other portions. Also, although not shown, it has been confirmed by the present inventors that the silicon carbide semiconductor devices 80, 80' according to embodiment 2 can also obtain the same effects as those of Examples 1 and 2.

[0129] The present invention is not limited to the above-mentioned embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, in the above-mentioned embodiments, due to misalignment of the ion implantation mask (corresponding to reference numeral 72 in FIG. 11, reference numeral 74 in FIG. 12, and reference numeral 76 in FIG. 13), the impurity concentration may be relatively high not only in the gate region of the n-type current diffusion region, but also in a portion slightly shifted from the gate region toward the outer periphery contact region. In addition, the parallel pn layer and the n + The impurity concentration of a normal n-type drift region that does not have an SJ structure with the starting substrate may be higher than the impurity concentration of the n-type region of the parallel pn layer. The present invention is also valid when the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0130] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful for a power semiconductor device having an SJ structure used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0131] 1n + Type drain region 2. Drift layer 2a Parallel pn layer and n + A conventional n-type drift region with no SJ structure between the starting substrate and the n-type 3 n-type current diffusion region 3a,3b n-type region 4 p-type base region 5n+ Type Source Area 6 p ++ Mold Contact Area 7 Gate trench 8 Gate insulating film 9 Gate electrode 10 Active area 11,12,12a,12b,13p + type area 13a,81,81' p + Convex part of mold area 14 Interlayer insulating film 14a Contact Hole 15 Source electrode 16 Gate Pad 17 Drain electrode 20 Intermediate area 21 Periphery contact area 21a Outer periphery contact part 21b p ++ Mold peripheral contact area 22 Gate Area 22a Gate Runner 22b Gate metal wiring layer 30 Edge Termination Area 31 Step on the front surface of a semiconductor substrate 32 JTE structure 33 JTE Structure p - type area 34n + Mold stopper area 35 Passivation film 36 Field oxide 40 Semiconductor Substrate 40a: A portion of the front surface of the semiconductor substrate on the active region side (first surface) 40b: a portion of the edge termination region of the front surface of the semiconductor substrate (second surface) 40c: A portion (third surface) of the front surface of the semiconductor substrate that connects the first surface and the second surface 41 n + Starting substrate 42 Epitaxial layer 43 n - Type epitaxial layer 43a n -The part where the epitaxial layer is thickened 44 p-type epitaxial layer 50,80,80' Silicon carbide semiconductor device 60 parallel pn layers 61, 61a n-type region of parallel pn layer 62 p-type region of parallel pn layer 63 SJ Trench 71, 73, 75, 77 Ion implantation 72, 74, 76 Ion implantation mask t1 Thickness of the drift region X: Parallel to the front surface of the semiconductor substrate (first direction) Y: A direction (second direction) that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. a semiconductor substrate made of silicon carbide; a parallel pn layer provided within the semiconductor substrate from an active region to a termination region surrounding the periphery of the active region, the parallel pn layer including first conductivity type regions and second conductivity type regions alternately arranged in a first direction parallel to a first main surface of the semiconductor substrate; a first surface that is a portion of a first main surface of the semiconductor substrate excluding the termination region; a step formed by recessing a second surface, which is a portion of the termination region of the first main surface of the semiconductor substrate, toward the second main surface of the semiconductor substrate; a first semiconductor region of a second conductivity type provided between the first surface of the semiconductor substrate and the parallel pn layer, the first semiconductor region extending from the active region to an intermediate region between the active region and the termination region and reaching the step; a second semiconductor region of a first conductivity type provided between the first semiconductor region and the parallel pn layer in the active region and in contact with the first semiconductor region and the parallel pn layer; a third semiconductor region of a first conductivity type selectively provided between the first surface of the semiconductor substrate and the first semiconductor region in the active region; a trench penetrating the third semiconductor region and the first semiconductor region to reach the second semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a first high concentration region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region, the first high concentration region being provided between a bottom surface of the trench and the parallel pn layer and facing the bottom surface of the trench in a depth direction; a second high concentration region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region, the second high concentration region being in contact with the first semiconductor region between the first semiconductor region and the parallel pn layer in the active region and being spaced apart from the trench and the first high concentration region; a third high concentration region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region, the third high concentration region being provided in contact with the first semiconductor region between the first semiconductor region and the parallel pn layer in the intermediate region, electrically connected to the first high concentration region and the second high concentration region, and surrounding the active region; a fourth semiconductor region of a second conductivity type that constitutes a voltage withstanding structure, the fourth semiconductor region being selectively provided between the second surface of the semiconductor substrate and the parallel pn layer, surrounding the periphery of the active region via the intermediate region, and electrically connected to the first semiconductor region via the third high concentration region; a first electrode electrically connected to the third semiconductor region and the first semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the intermediate region includes a first intermediate region in which an electrical contact portion between the first electrode and the first semiconductor region is formed, and a second intermediate region between the first intermediate region and the termination region; the third high concentration region has protrusions protruding toward the parallel pn layer at portions facing the first conductivity type region and the second conductivity type region of the parallel pn layer in a depth direction, the second semiconductor region extends from the active region to the intermediate region to reach the step, is present between the third heavily doped region and the parallel pn layer and between the protruding portions of the third heavily doped region, and is adjacent to the first conductivity type region of the parallel pn layer in a depth direction; 2. A silicon carbide semiconductor device, comprising: a first intermediate region having a first impurity concentration higher than that of the second intermediate region;

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of said second semiconductor region is 1.3 to 1.7 times higher in said second intermediate region than in other portions.

3. 3. The silicon carbide semiconductor device according to claim 1, wherein the convex portions of the third high concentration region are provided in portions facing the first conductivity type region and the second conductivity type region of the parallel p-n layer in a depth direction, respectively.

4. 3. The silicon carbide semiconductor device according to claim 1, wherein the convex portion of the third high concentration region is provided in a plurality of portions in a depth direction of each of the parallel pn layers facing the first conductivity type region.

5. the first conductivity type region and the second conductivity type region of the parallel pn layer each extend linearly in a second direction that is parallel to a first main surface of the semiconductor substrate and perpendicular to the first direction; 5. The silicon carbide semiconductor device according to claim 1, wherein said convex portion of said third high concentration region extends linearly in said second direction.

6. the first conductivity type region and the second conductivity type region of the parallel pn layer each extend linearly in a second direction that is parallel to a first main surface of the semiconductor substrate and perpendicular to the first direction; 5. The silicon carbide semiconductor device according to claim 1, wherein the protrusions of the third high concentration region are scattered in the second direction.

7. a gate runner made of a polysilicon layer is provided on the first main surface of the semiconductor substrate in the second intermediate region via an insulating layer; 7. The silicon carbide semiconductor device according to claim 1, wherein an electrical contact between the gate electrode and the gate runner is formed in the second intermediate region.

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